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Lab 4

This lab document outlines objectives to design and analyze combinational logic circuits such as multiplexers, demultiplexers, and adders using Karnaugh maps and Boolean algebra. It provides procedures to build half-adder, full-adder, and 4-to-1 multiplexer circuits using AND, OR, XOR gates and verify their functions through truth tables and output testing. In conclusion, the implementation of these combinational logic circuits proved successful and showed their versatility and practical utility as fundamental building blocks in digital systems.

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96 views8 pages

Lab 4

This lab document outlines objectives to design and analyze combinational logic circuits such as multiplexers, demultiplexers, and adders using Karnaugh maps and Boolean algebra. It provides procedures to build half-adder, full-adder, and 4-to-1 multiplexer circuits using AND, OR, XOR gates and verify their functions through truth tables and output testing. In conclusion, the implementation of these combinational logic circuits proved successful and showed their versatility and practical utility as fundamental building blocks in digital systems.

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Lab#4

Introduction to Combinational Design


Frarh ali dodeen
202110809
Computer Engineering
Dr. Dima Al-Badawi .
15-11-2023
Introduction :

Logic circuits for digital systems can generally be classified into two categories. One is combinational

logic circuits, the other is sequential logic circuits. A combinational logic circuit consists of logic gates

whose outputs at any time are determined directly from the present combination of inputs without

regard to previous inputs. In other words, the combinational logic circuits do not have the ability to

memorize their past. On the other hand, a sequential logic circuit consists of not only logic gates but also

memory elements. Therefore, the outputs of sequential logic circuits depend not only on the present

values of the inputs but also on the input's previous values. In other words, the outputs of a sequential

logic circuit are functions of its present inputs and the previous state of its memory elements. Sequential

logic circuits will be covered in the coming labs.

Objectives:

Combinational logic is a very important part of digital systems. This lab is designed to enable students to

design and analyze combinational logic circuits. Some basic, commonly used logic circuits, such as

multiplexer (MUX), demultiplexer (DEMUX), and adder, are introduced. Students are required to use

Karnaugh map and Boolean algebra techniques to simplify the given Boolean functions prior to

implementing them. Students are also expected to have experience with gate delay and effect of fan-out

on the speed of digital circuits.


Required :

 AND gates

 OR gates

 NOR gates

 XOR gates

Part 1: Use the exclusive-OR circuit and an AND gate


to build a half-adder and draw its truth table to verify its
function.
Procedure :
Connect inputs A and B using AND and OR gates.
A B X Y
0 0 0 0
0 1 1 0
1 0 1 0
1 1 1 1

Part 2: Build a full-adder and draw its truth table to verify


its function
Procedure :
Connect the binary sum inputs (A and B) to an XOR gate
to obtain the partial sum. Connect the inputs (A and B)
and the partial sum to AND gates to derive the
implementation. Input the previous carry (Cin) into a
second XOR gate with the partial sum to obtain the
partial sum with the previous stage. Connect this partial
sum to the previous stage and the partial sum to the OR
gate to get the final posting. This configuration uses
AND gates for logical coupling, XOR gates for binary
addition, and an OR gate to combine the outputs,
achieving full Adder circuit functionality.
A B C X Y
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
Part 3: Construct the circuit of the 4 to 1 MUX shown in
the background section and connect the output Vo to a
LED. Verify its output by setting the select signals S1 and
S0, and then change the four inputs sequentially (one
high, three low) to see which input signal is transferred
to the output.
Procedure :
each data input (I0, I1, I2, I3) is individually connected
to AND gates along with the complemented and non-
complemented control inputs (S0' and S0, S1' and S1).
Each AND gate output is then connected to a common
OR gate, which produces the final selected output
based on the control inputs. This configuration allows
the MUX to choose one of the data inputs based on the
binary value of the control inputs S0 and S1.
S1 S0 V0
0 0 D0
0 1 D1
1 0 D2
1 1 D3
Conclusion :
In conclusion, the implementation of the 4-to-1 MUX,
full-adder, and half-adder circuits proved to be
successful and effective. The integration of AND, XOR,
and OR gates allowed for a compact design that
efficiently performs binary addition and multiplexing
operations. This experiment showcased the versatility of
these circuits in handling data inputs, control signals,
and generating accurate outputs. The simplicity and
modularity of the design make it adaptable for various
digital logic applications, underscoring the practical
utility of these fundamental building blocks in digital
circuitry.

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