MAX14866 16-Channel, High-Voltage Analog Switch

without High-Voltage Supply Requirement

General Description Benefits and Features

The MAX14866 is a 16-channel, high-voltage (HV), ●● Flexibility and Ease-of-Design
analog SPST switch primarily intended for HV multiplexing • HV Switches Operate From +5V Supply
in ultrasound applications. Only–Eliminating Dedicated High-Voltage Supplies
The MAX14866 operates from one only low-voltage Eases Probe Compliance To Industry
supply (+5V) and does not require dedicated HV Safety Standards
supplies, resulting in cost-saving and system simplification. • SOI Technology–Latchup Free
Moreover, for in-probe applications, HV supplies do not • Large Analog Input range (up to 210VPKPK)
need to be associated with the MAX14866 in the probe/ • 16 Independent SPST Ensure Flexibility
transducer head, resulting in greater safety and easier Supporting All Possible MUX Combinations
compliance with safety regulations. • Switches Can Be Controlled Either Individually
The MAX14866 features best-in-class performance in or Globally (Bank Selection)
terms of bandwidth (up to 50MHz), charge injection (<100pC), • 30MHz SPI Interface for Individually Programming
and linear transmit input range (up to 210VPKPK). The the Status of the Switches
low-signal switch RDSON is typically about 7Ω around • SET and CLR CMOS for global control of the
0V and remains flat in the entire input range ensuring switches (Bank Selection or Relay Replacements
extremely good linearity. Applications)
• Extended Digital Logic Input Range From 1.8V to 5V
The latchup-free SOI (Silicon-on-Insulator) technology
and the wide analog range results in extremely high ●● High Level Of Integration and Density for
robustness during undershoots and overshoots that Space-Saving Applications
occur in ultrasound systems due to the resonant nature • 16 Channels Linear SPST switches
of the load. • < 1.9mm2/channel footprint (WLP)
The status of the switches can be individually controlled ●● High Performance:
through a high-speed SPI interface (up to 30MHz). Daisy- • Low RON (7Ω typ) Ensures Low Insertion Loss
chain architecture is supported. • RON Flatness in the Entire Input Range Ensures
Excellent Performances In Harmonic Imaging
Alternatively, switches can also be controlled with global
• Low Charge Injection <100pC.
control signal (SET and CLR) for bank selections or relay
• Wide Bandwidth of Operation (Up to 50MHz)
replacement applications.
• Low On Input Capacitance (33pF)
The MAX14866 is offered in two different packages: Low Off Input Capacitance (7.7pF)
wafer-level packages (WLPs) and TQFNs. The 110- • Excellent Off Isolation (-75dB at 5MHz)
bump WLP size is only 5.53 x 5.47mm, resulting in less Excellent Crosstalk Performances (-62dB at 5MHz)
than 1.9mm2/channel footprint and allowing for very high
levels of integration, which is especially beneficial for
in-probe applications.
The size of the TQFN package is an industry standard Ordering Information appears at end of data sheet.
48-pin, 7mm x 7mm package.

Applications
●● Medical Ultrasound Imaging
●● Relays replacements
●● NDT
●● Printers

19-100068; Rev 1; 4/18

MAX14866 16-Channel, High-Voltage Analog Switch
without High-Voltage Supply Requirement

Absolute Maximum Ratings

VCC to GND............................................................-0.3V to 5.6V TQFN Continuous Power Dissipation
VDD to GND............................................................-0.3V to 5.6V (Single Layer Board, TA = +70°C,
COMx to GND, x = 0..15..................................... -110V to +110V derate 27.8mW/°C above +70°C.)................ 0mW to 2222mW
NOx to GND, x = 0..15........................................ -110V to +110V TQFN Continuous Power Dissipation
COMx to NOx, x = 0..15...................................... -110V to +110V (Multilayer Board, TA = +70°C,
SDIN to GND...........................................................-0.3V to 5.6V derate 40 mW/°C above +70°C.)................. 0mW to 3200mW
SDOUT to GND ...........................................-0.3V to VDD + 0.3V WLP Continuous Power Dissipation
LE to GND ..............................................................-0.3V to 5.6V (Multilayer Board, TA = +70°C,
CLK to GND ...........................................................-0.3V to 5.6V derate 37mW/°C above +70°C.) ................. 0mW to 2960mW
CLR to GND ...........................................................-0.3V to 5.6V Operating Temperature Range .................................0°C to 85°C
SET to GND ...........................................................-0.3V to 5.6V Junction Temperature .................................................... +150°C
Storage Temperature Range ............................ -65°C to +150°C
Soldering Temperature (reflow)

Package Thermal Characteristics (Note 1)

110-Bump WLP 48-Pin TQFN
Junction-to-Ambient Thermal Resistance (θJA)......26.93°C/W Junction-to-Ambient Thermal Resistance (θJA)...........25°C/W
Junction-to-Case Thermal Resistance (θJC)...................... N/A Junction-to-Case Thermal Resistance (θJC)..................1°C/W

Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.

Electrical Characteristics
(VCC = 5V ±5%, VDD = 1.7V to 5.5V. Typical values are VDD = +2.5V, VCC = 5V, TA = +25°C. Limits are 100% tested at TA = +85°C
and are guaranteed by design in the entire temperature range )

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

POWER SUPPLIES
VDD Logic Supply Voltage VDD 1.7 5.5 V
VDD Static Current IDDS 1 5 µA
VDD = +5V, fCLK = 5MHz,
VDD Dynamic Current IDD 300 µA
fDIN = 2.5MHz, CDOUT = 15pF
All switches remain on or off,
VCC Supply Static Current ICCS 240 425 µA
COM_= NO_= GND
VCC Supply Dynamic Current ICC All Channel Switching, f = 50kHz 5.2 8.5 mA
VCC Supply Voltage Range VCC 4.75 5 5.25 V
LOGIC LEVELS
Logic-Input Low Voltage VIL 0.33 x VDD V
Logic-Input High Voltage VIH 0.66 x VDD V
Logic-Output Low Voltage VOL ISINK = 1mA 0.2 V
Logic-Output High Voltage VOH ISOURCE = 1mA VDD - 0.2 V
Logic-Input Capacitance CIN 5 pF

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MAX14866 16-Channel, High-Voltage Analog Switch
without High-Voltage Supply Requirement

Electrical Characteristics (continued)

(VCC = 5V ±5%, VDD = 1.7V to 5.5V. Typical values are VDD = +2.5V, VCC = 5V, TA = +25°C. Limits are 100% tested at TA = +85°C
and are guaranteed by design in the entire temperature range )

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Logic-Input Leakage IIN CLK, DIN pins -1 +1 µA
LEB Pullup Resitor RPU 70 100 KΩ
CLR, SET Pulldown Resistor RPDW 70 100 KΩ
SWITCH CHARACTERISTICS
Analog Dynamic Signal Range VSW_ AC operation only, f > 500kHz -105 +105 V
Small Signal On-Resistance RONS V(NO) = 0V, I(COM) = 5mA 7 13 Ω
Small Signal On-Resistance
DRONS 3 std, VNO_ = 0V, ICOM_ = 5mA 3 %
Matching
AC measured, 100Ω Resistive
load NO and GND. Transmit
bipolar low frequency pulse
Switch Symmetry Symm ±80V, f = 0.5MHz Compare ±1 %
positive and negative output level
on NO Symmetry = [VOP - VON]/
[0.5 x (VOP + VON)]

IPEAK V(NO) = GND, V(COM) HV pulse

Analog Switch Peak Current 2.7 A
100ns duration
COM to GND Leakage Current
ICOMOFF V(COM) = ±100mV -1 +1 uA
Switch OFF
COM to GND Equivalent
RCOMON V(COM) = 100mV 60 82 104 KΩ
Resistor. Switch ON
NO to GND Equivalent
RNOOFF V(NO) = 100mV 35 52 65 KΩ
Resistor. Switch OFF
NO to GND Equivalent Resistor
RNOON V(NO) = 100mV 60 82 104 KΩ
Switch ON
Switch-Off DC Offset COM Pin VOFF1 Ref. Test Circuit R = 100KΩ -5 +6 mV
Switch-Off DC Offset NO Pin VOFF2 Ref. Test Circuit R = 100KΩ -5 +6 mV
Switch-On DC Offset VOFF3 Ref. Test Circuit R = 100KΩ -5 +9 mV
SWITCH DYNAMIC CHARACTERISITICS
Ref. Test Circuit. VCOM_ = +1V,
RL = 50Ω, from switch ON digital
Turn-On Time tON 4 μs
command to 90% of the transition
completed

Ref. Test Circuit VCOM_ = +1V,

RL = 50Ω from switch OFF digital
Turn-Off Time tOFF 4 μs
command to 90% of the transition
completed
Off-Isolation in Transmission
VISOTX Ref. Test Circuit -75 dB
(TX)

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MAX14866 16-Channel, High-Voltage Analog Switch
without High-Voltage Supply Requirement

Electrical Characteristics (continued)

(VCC = 5V ±5%, VDD = 1.7V to 5.5V. Typical values are VDD = +2.5V, VCC = 5V, TA = +25°C. Limits are 100% tested at TA = +85°C
and are guaranteed by design in the entire temperature range )

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Ref. Test Circuit. ZL = 50Ω -80
Off-Isolation in Reception (RX) VISORX dB
Ref. Test Circuit. ZL = 1kΩ//15pF -60
Ref Test Circuit. RX and TX with
Crosstalk VCT -62 dB
switches open or closed
SW_ Off-Capacitance
CSW_(OFF) f = 5MHz, 100mVPK on NO pin 7.7 pF
Small-Signal - NO Pin
SW_ On-Capacitance
CSW_ (ON) f = 5MHz, 100mVPK 33 pF
Small-Signal
SW_Off-Capacitance
CSW_(OFF) f = 5MHz, 100mVPK on COM pin 11 pF
Small-Signal - COM Pin
SW_ Off-Capacitance
CSW_(OFF) f = 5MHz, 100VPK on COM pin 11 pF
Large-Signal - COM Pin
SW_ On-Capacitance
CSW_ (ON) f = 5MHz, 100VPK 16 pF
Large-Signal
Charge Injection QCH Ref. Test Circuit <100 pC
Output Voltage Spike VSPK Ref. Test Circuit 65 mVpkpk
Large-signal Analog Bandwidth CLOAD = 200pF, 60V amplitude
fBW_L >50 MHz
(-3dB) sinusoidal burst, 1% duty cycle
Small-signal Analog Bandwidth CLOAD = 200pF, 100mV
fBW_S 80 MHz
(-3dB) amplitude sinusoidal signal
TIMING CHARACTERISTICS
fOUT = 5MHz, Transmit
amplitude 200VPKPK square wave
2nd Harmonic Distortion HV THD2 -45 dBc
(20 cycles), NO Load:
100Ω // 100pF

fOUT_ = 1MHz - 5MHz, Transmit

amplitude 200VPKPK, 2 cycles.
Strength ratio of the strongest
Pulse Cancellation 1
PC1 spurious signal of the sum -40 dBc
Fundamental
function in the f0 ± f0/2 bandwidth
to the fundamental signal.
NO Load: 100Ω // 100pF

fOUT_ = 1MHz - 5MHz, Transmit

Amplitude 200VPKPK, 2 cycles.
Strength ratio of the strongest
Pulse Cancellation 2 Second spurious signal of the sum dBc
PC2 -40
Harmonic function in the 2 x f0 ± f0/2
bandwidth to the fundamental
signal. NO Load: 100Ω // 100pF

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MAX14866 16-Channel, High-Voltage Analog Switch
without High-Voltage Supply Requirement

Electrical Characteristics (continued)

(VCC = 5V ±5%, VDD = 1.7V to 5.5V. Typical values are VDD = +2.5V, VCC = 5V, TA = +25°C. Limits are 100% tested at TA = +85°C
and are guaranteed by design in the entire temperature range )

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

TIMING CHARACTERISTICS/SPI TIMINGS
CLK Frequency fCLK 30 MHz
DIN to CLK Setup Time tDS 3 ns
DIN to CLK Hold Time tDH 3 ns
CLK to LE Setup Time tCS 3 ns
LE Low Pulse Width tWL 5 ns
CLR High Pulse Width tWC 115 ns
SET High Pulse Width tWS 115 ns
CLK Rise and Fall Times tR, tF 50 ns
VDD from 2.5V - 5% to 5V + 5%,
5 20
CDOUT = 15pF
CLK to DOUT Delay tDO ns
VDD = +1.8V ± 5%,
5 30
CDOUT = 15pF

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MAX14866 16-Channel, High-Voltage Analog Switch
without High-Voltage Supply Requirement

Typical Operating Characteristics

VDD = 3V, VCC = 5V, TA = 25°C, unless otherwise noted.

IDD SUPPLY CURRENT IDD SUPPLY CURRENT ICC SUPPLY CURRENT

vs. VDD SUPPLY VOLTAGE vs. CLOCK FREQUENCY vs. TEMPERATURE
toc01 toc02 toc03
3 1600 240
ALL CHANNELS ON
1400 238

236
1200
IDD SUPPLY CURRENT (µA)

IDD SUPPLY CURRENT (µA)

234

ICC SUPPLY CURRENT (µA)

2
1000
VDD = 5V 232

800 230

600 228
1
VDD = 2.5V 226
400
224
200
222

0 0 220
1.5 2.5 3.5 4.5 5.5 0 10 20 30 0 10 20 30 40 50 60 70 80
VDD SUPPLY VOLTAGE (V) CLOCK FREQUENCY(MHz) TEMPERATURE (°C)

IDD SUPPLY CURRENT ICC SUPPLY CURRENT

vs. TEMPERATURE vs. CLR FREQUENCY
toc04 toc05
5.00 5.5

4.50 5.0
4.5
4.00
ICC SUPPLY CURRENT (mA)

4.0
3.50
IDD SUPPLY CURRENT (µA)

3.5
3.00
3.0
2.50
2.5
2.00 2.0
1.50 1.5

1.00 1.0

0.50 0.5
0.0
0.00 0 10 20 30 40 50
0 10 20 30 40 50 60 70 80
CLR FREQUENCY (kHz)
TEMPERATURE (°C)

TURN-ON, TURN-OFF TIMES TRANSMIT OFF-ISOLATION

vs. TEMPERATURE vs. FREQUENCY
toc06 toc07
3 -50

2.9
-60
TURN-ON/TURN-OFF TIMES (µs)

2.8

2.7 -70
OFF-ISOLATION (dB)

2.6 TURN ON -80

2.5
-90
2.4

2.3 -100
TURN OFF
2.2
-110
2.1

2 -120
0 20 40 60 80 0.1 1 10
TEMPERATURE (°C) FREQUENCY (MHz)

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MAX14866 16-Channel, High-Voltage Analog Switch
without High-Voltage Supply Requirement

Typical Operating Characteristics (continued)

VDD = 3V, VCC = 5V, TA = 25°C, unless otherwise noted.

RECEIVE OFF-ISOLATION TRANSMIT CROSSTALK

vs. FREQUENCY vs. FREQUENCY
toc08 toc09
-50 -40

-60 -50

-70 -60
OFF-ISOLATION (dB)

CROSSTALK (dB)
-80 -70

-90 -80

-100 -90

-110 -100

-120 -110
0.1 1 10 0.1 1 10
FREQUENCY (MHz) FREQUENCY (MHz)

RECEIVE CROSSTALK
vs. FREQUENCY VOLTAGE SPIKE
toc10 toc11
-40 0.07

0.06 TURN-ON
-50
0.05
-60
0.04
NO VOLTAGE (V)
CROSSTALK (dB)

-70 TURN-OFF
0.03

-80 0.02

0.01
-90
0
-100
-0.01
-110
-0.02

-120 -0.03
0.1 1 10 0 2 4 6
FREQUENCY (MHz) TIME (µs)

2ND HARMONIC DISTORTION PULSE CANCELLATION

toc12 toc13
40 20
OUT WAVE
30 10

0
20
HARMONIC (dB)

HARMONIC(dB)

-10
10
-20
0
-30
-10
-40

-20 -50
RESIDUE

-30 -60
0 5 10 15 20 0 5 10 15 20
FREQUENCY (MHz) FREQUENCY (MHz)

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MAX14866 16-Channel, High-Voltage Analog Switch
without High-Voltage Supply Requirement

Pin Configurations

TOP VIEW

COM 12
COM 13

COM 11
COM 15

COM 14

NO13
NO15

NO14

NO12

NO11
GND

GND
36 35 34 33 32 31 30 29 28 27 26 25

GND 37 24 COM10

LE 38 23 NO10

DOUT 39 22 COM9

VDD 40 21 NO9

GND 41 20 COM8
MAX14866
GND 42 19 NO8

VCC 43 18 NO7

DIN 44 17 COM 7

CLK 45 16 NO6

SET 46 15 COM 6

CLR 47 + 14 NO5

GND 48 13 COM 5

1 2 3 4 5 6 7 8 9 10 11 12
COM 0

NO0

COM 1

NO1

COM 2

NO2

COM 3

NO3

COM 4

NO4
GND

GND

TQFN
(7mm x 7mm )
TOP VIEW
(BUMP SIDE DOWN)
1 2 3 4 5 6 7 8 9 10 11

A
COM 1 NO2 NO3 NO4

B
COM 0 NO1 COM 3 COM 5 NO5
C
SET NO0 COM 2 COM 4 NO6 COM 6

D
CLK CLR COM 7
E
VCC VCC DIN GND GND GND GND NO7

F
GND GND GND GND GND GND GND NO8

G
VDD LE COM 8
H
DOUT NO15 COM 13 COM 11 NO9 COM 9
J
COM 15 NO14 COM 12 COM 10 NO10
K
COM 14 NO13 NO12 NO11

0.31mm 0.5mm

UNNAMED PINS ARE INTERNALLY NOT CONNECTED

WLP

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MAX14866 16-Channel, High-Voltage Analog Switch
without High-Voltage Supply Requirement

Pin Description
PIN
NAME FUNCTION
MAX14866 WLP MAX14866 TQFN
B2 1 COM0 Analog Switch 0 - Terminal
C3 2 NO0 Analog Switch 0 - Terminal
A3 3 COM1 Analog Switch 1 - Terminal
B4 4 NO1 Analog Switch 1 - Terminal
C5 5 COM2 Analog Switch 2 - Terminal
A5 6 NO2 Analog Switch 2 - Terminal
B6 7 COM3 Analog Switch 3 - Terminal
A7 8 NO3 Analog Switch 3 - Terminal
E4–E7 9 GND Ground
F1–F7 10 GND Ground
C7 11 COM4 Analog Switch 4 - Terminal
A9 12 NO4 Analog Switch 4 - Terminal
B8 13 COM5 Analog Switch 5 - Terminal
B10 14 NO5 Analog Switch 5 - Terminal
C11 15 COM6 Analog Switch 6 - Terminal
C9 16 NO6 Analog Switch 6 - Terminal
D10 17 COM7 Analog Switch 7 - Terminal
E11 18 NO7 Analog Switch 7 - Terminal
F9 19 NO8 Analog Switch 8 - Terminal
G10 20 COM8 Analog Switch 8 - Terminal
H9 21 NO9 Analog Switch 9 - Terminal
H11 22 COM9 Analog Switch 9 - Terminal
J10 23 NO10 Analog Switch 10 - Terminal
J8 24 COM10 Analog Switch 10 - Terminal
K9 25 NO11 Analog Switch 11 - Terminal
H7 26 COM11 Analog Switch 11 - Terminal
27 GND Ground
28 GND Ground
K7 29 NO12 Analog Switch 12 - Terminal
J6 30 COM12 Analog Switch 12 - Terminal
K5 31 NO13 Analog Switch 13 - Terminal
H5 32 COM13 Analog Switch 13 - Terminal
J4 33 NO14 Analog Switch 14 - Terminal

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MAX14866 16-Channel, High-Voltage Analog Switch
without High-Voltage Supply Requirement

Pin Description (continued)

PIN
NAME FUNCTION
MAX14866 WLP MAX14866 TQFN
K3 34 COM14 Analog Switch 14 - Terminal
H3 35 NO15 Analog Switch 15 - Terminal
J2 36 COM15 Analog Switch 15 - Terminal
37 GND Ground
G2 38 LE CMOS Digital Logic Input. Active-Low Latch Enable Input
H1 39 DOUT CMOS Digital Logic Output - SPI Data Output
Positive LV supply input for digital I/O (from 1.7V to 5.5V).
G1 40 VDD
Bypass VDD to GND with a 0.1µF or greater ceramic capacitor
41 GND Ground
42 GND Ground
Positive LV Supply Input (+5V). Bypass VCC to GND
E1, E2 43 VCC
with a 0.1µF or greater ceramic capacitor
E3 44 DIN CMOS Digital Logic Input - SPI Data Input
D1 45 CLK CMOS Digital Logic Input - SPI Clock Input
C1 46 SET CMOS Digital Logic Input - Asynchrounous Set Input
D2 47 CLR CMOS Digital Logic Input - Asynchronous Clear Input
48 GND Ground
― EP Exposed PAD (Thermal PAD). Connet EP to GND

A1, A2, A4, A6, A8,

A10, A11, B1, B3, B5,
B7,B9,B11, C2, C4, C6,
C8, C10, D3-D9, D11,
E8-E10, F8, F10, F11, ― N.C. Not internally connected
G3-G9, G11, H2, H4,
H6, H8, H10, J1, J3, J5,
J7, J9, J11, K1, K2, K4,
K6, K8, K10, K11

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MAX14866 16-Channel, High-Voltage Analog Switch
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Functional (or Block) Diagram

VDD VCC

SET

CLR
COM0
Analog
LATCH DRIVER switch

NO0
Rbleed
DIN

CLK
SPI MAX14866
SHIFT
REGISTER

DOUT

COM15
Analog
LATCH DRIVER switch

GND NO15
Rbleed

LE

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MAX14866 16-Channel, High-Voltage Analog Switch
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Detailed Description Analog Switches

The MAX14866 is a 16-channel, high-voltage (HV), The MAX14866 can transmit undistorted analog signals
Analog SPST switch primarily intended for HV multiplexing up to 210VP-P. For reliable operation, the maximum drop
in ultrasound applications. between input and output of the switch (pins COM and
The MAX14866 operates from one only low voltage supply NO) must be less than 110V (refer to the absolute maximum
(+5V) and does not require dedicated HV supplies resulting rating in the Electrical Characteristics table)
in cost saving and system simplification. Moreover, for It is required that the input signal is set at GND prior to HV
in-probe applications, HV supplies do not need to be transmission. The minimum guaranteed transmit frequency
associated with the MAX14866 in the probe/transducer is 500KHz. The switch is not symmetrical. Transducer
head, resulting in greater safety and easier compliance to elements must be connected to pin named NOx (x =
safety regulations. 0..15) while the transmit/receive front end circuits must be
The MAX14866 features best-in-class performances in connected to the pin named COMx (x = 0..15). Refer to
terms of bandwidth (up to 50MHz), charge injection (<100pC) the Typical Application Circuit for further details.
and linear transmit input range (up to 210VPKPK). The low Voltage Supply
signal switch RDSON is typically about 7Ω around 0V and The MAX14866 operates from a low voltage supply
remains flat in the entire input range ensuring extremely VCC = +5V ±5%, and a logic supply VDD (from +1.7V to
good linearity. +5.5V). In particular, if the logic high level of the control
The latch-up free SOI (Silicon-on-Insulator) technology and input signals (SPI, CLR, SET) is +5V, the two supply
the wide analog range results in extremely high robustness voltage inputs VDD and VCC can be connected together
during undershoots and overshoots which occur in and the part can operate from one single +5V supply.
ultrasound systems due to the resonant nature of the load. Local bypassing on supply voltage inputs is required
The status of the switches can be individually controlled (C > 100nF).
through a high speed SPI interface (up to 30MHz). Daisy-
chain architecture is supported. Bleed Resistors
The MAX14866 features integrated bleed resistors. Bleed
Alternatively, switches can also be controlled with global
resistors are intended to fully discharge the transducers
control signal (SET and CLR) for bank selections or relay
and eliminate any voltage built up. The bleed resistor
replacement applications.
values depends on the status of the switch. Refer to the
The MAX14866 is offered in two different packages: Electrical Characteristics table and to Figure 1 for further
wafer-level package (WLP) and Thin-QFN (TQFN). The details.
110-Bump WLP size is only 5.53 x 5.47mm, resulting in
less than 1.9mm2/channel footprint and allowing for very Heading RST
high levels of integration which is beneficial especially for The MAX14866 Equivalent Electrical Circuit is shown
in-probe applications. in Figure 1 under different conditions depending on the
The size of the TQFN package is an industry standard status of the switch (on/off) and on the level of the signal
48-pin 7mm x 7mm package. (small-signal/large-signal).

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MAX14866 16-Channel, High-Voltage Analog Switch
without High-Voltage Supply Requirement

COM 7Ω NO COM 7Ω NO

33pF 80KΩ 16pF 80KΩ

Small signal equivalent circuit Large signal equivalent circuit

Switch ON Switch ON
Vsig = 100mVPK Vsig = 100VPK

COM NO COM NO

11pF 50KΩ 7.7pF 80kΩ 16pF 30Ω Note 1

Small signal equivalent circuit Large signal equivalent circuit

Switch OFF Switch OFF
Vsig = 100mVPK Vsig = 100VPK

Figure 1. Electrical Equivalent Circuit

Note 3: The large-signal NO equivalent input impedance (30Ω typical) is shown for completeness only. It is intended that the High
Voltage excitation signals are applied to terminal COM only so that no any HV transmit burst will hit terminal NO whenever
the switch is programmed off.
Note 4: Resistances and capacitances values are typical.

Transmit Operations: High-Voltage Bursts offsets during CW operation results in signal degradation
(Voltage Amplitude Greater Than 20VPK) and can affect the device reliability. In particular, unipolar
The MAX14866 is capable of transmitting long High CW operation is not supported.
Voltage Bipolar Bursts (from 40VPKPK to 210VPKPK) with Serial Interface
excellent linearity and stability. When transmitting Bipolar
The MAX14866 is controlled by a serial interface with
HV bursts (amplitude greater than 20VPK) the device is
a 16-bit serial shift register and transparent latch. Each
not sensitive to the DC content of the signal.
of the 16 data bits controls a single analog switch
In particular, the MAX14866 supports long burst excita- (see Table 1). Data on DIN is clocked with the most sig-
tion modes like the ones commonly used in Elastography. nificant bit (MSB) first into the shift register on the rising
The user must ensure that the total dissipated power can edge of CLK. Data is clocked out of the shift register onto
be handled by the package. DOUT on the rising edge of CLK. DOUT reflects the sta-
Unipolar transmission is supported up to 100Vpk-to-pk tus of DIN, delayed by 16 clock cycles (see Figure 2 and
only. Figure 3).
For reliability reasons, it is requested that both the switch Changing the switch status (from on to off or vice-
input and output (COM and NO pins) are set at ground versa) during the transmission of the analog signal is not
before the transmission is initiated. permitted and can result in reliability issues. The user must
ensure that the analog input is kept quiet at GND before
Transmit Operations: Continuous Wave any SPI programming session and during the entire settling
Bipolar Continuous Wave Operation (CW) is supported time of the switches (TON, TOFF). Similarly the user must
for transmit voltages less than 20VPKPK (amplitude less ensure that the analog input is quiet at GND before assert-
than 10V). It is required that the DC content (offset) of ing either the CLR or the SET signal and during the entire
the CW transmit waveform is less than ±1V. Larger DC settling time of the switches (TON, TOFF).

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MAX14866 16-Channel, High-Voltage Analog Switch
without High-Voltage Supply Requirement

Table 1. SPI Programming and Logic Table

DATA BITS CONTROL BITS FUNCTION
D0
D1 D2 D3 D4 D5 D6 D7 LE CLR SET SW0 SW1 SW2 SW3 SW4 SW5 SW6 SW7
(LSB)
L L L L OFF
H L L L ON
L L L L OFF
H L L L ON
L L L L OFF
H L L L ON
L L L L OFF
H L L L ON
L L L L OFF
H L L L ON
L L L L OFF
H L L L ON
L L L L OFF
H L L L ON
L L L L OFF
H L L L ON
X X X X X X X X H L L
X X X X X X X X X H X OFF OFF OFF OFF OFF OFF OFF OFF
X X X X X X X X X L H ON ON ON ON ON ON ON ON
DATA BITS CONTROL BITS FUNCTION
D15
D8 D9 D10 D11 D12 D13 D14 LE CLR SET SW8 SW9 SW10 SW11 SW12 SW13 SW14 SW15
(MSB)
L L L L OFF
H L L L ON
L L L L OFF
H L L L ON
L L L L OFF
H L L L ON
L L L L OFF
H L L L ON
L L L L OFF
H L L L ON
L L L L OFF
H L L L ON

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MAX14866 16-Channel, High-Voltage Analog Switch
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Table 1. SPI Programming and Logic Table (continued)

DATA BITS CONTROL BITS FUNCTION
D15
D8 D9 D10 D11 D12 D13 D14 LE CLR SET SW8 SW9 SW10 SW11 SW12 SW13 SW14 SW15
(MSB)
L L L L OFF
H L L L ON
L L L L OFF
H L L L ON
X X X X X X X X H L L HOLD PREVIOUS STATE
X X X X X X X X X H X OFF OFF OFF OFF OFF OFF OFF OFF
X X X X X X X X X L H ON ON ON ON ON ON ON ON

Note 5: TNote 5: The 16 switches operate independently.

Note 6: Serial data is clocked in on the rising edge of CLK.
Note 7: The switches go to a state retaining their present condition on the rising edge of LE. When LE is low, the shift register data
flows through the latch.
Note 8: DOUT is the data output pin of the 16 bits shift register. It always reflects the status of DIN delayed by 16 clock cycles.
Note 9: Shift register clocking has no effect on the switch states if LE is high.
Note 10: The CLR input overrides all other inputs.

SPI Programming Inhibition During Transmit CLR description

The MAX14866 cannot be programmed during the The MAX14866 features a latch clear input. Drive CLR
transmission of HV bursts. The device features a transmit logic-high to reset the contents of the latch to zero and
detector circuit. If a transmit input signal greater than ±2V open all switches. CLR does not affect the contents of
is detected, any SPI programming is inhibited for 4.5µs the data shift register. Pulse LE logic-low to reload the
max. During such an interval any attempts of programming contents of the shift register into the latch.
the part via the SPI is ignored and the previous device
SET description
status is hold. This function prevents faults caused by
false programming of the logic due to the large switching The MAX14866 features a latch set input. Drive SET
noise occurring during HV transmit. logic-high to set the contents of the latch to logic-high
and close all switches. SET does not affect the contents
LE description of the data shift register. Pulse LE logic-low to reload the
Drive LE logic-low to change the contents of the latch and contents of the shift register into the latch. CLR is
update the state of the high-voltage switches (Figure 3). dominant with respect to SET.
Drive LE logic-high to freeze the contents of the latch and
Power-On reset
prevent changes to the switch states. To reduce noise
due to clock feedthrough, drive LE logic-high while data is The MAX14866 features a power-on-reset circuit to
clocked into the shift register. After the data shift register ensure all switches are open at power-on. The internal
is loaded with valid data, pulse LE logic-low to load the 16-bit serial shift register and latch are set to zero on
contents of the shift register into the latch. power-up.

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MAX14866 16-Channel, High-Voltage Analog Switch
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SET

ws

Figure 2. Timings

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MAX14866 16-Channel, High-Voltage Analog Switch
without High-Voltage Supply Requirement

Figure 3. SPI Programming

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MAX14866 16-Channel, High-Voltage Analog Switch
without High-Voltage Supply Requirement

Test Circuits 1

+1V

COM
COM COM

NO NO

NO

MAX14866 MAX14866

VCC VCC

DC OFFSET ON/OFF tON/tOFF TEST CIRCUIT

0.3
COM NO

NO COM

Z Z
MAX14866 MAX14866

VCC
VCC

RX
TX

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MAX14866 16-Channel, High-Voltage Analog Switch
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Test Circuits 2

0.3
COM COM NO NO

NO NO COM COM

Ω
NC
Ω Ω
NC
Ω
MAX14866 MAX14866

VCC VCC

TX RX
SWITCHES ON OR OFF SWITCHES ON OR OFF

NO NO

1nF Ω
COM COM

MAX14866 Ω MAX14866

VCC VCC

1nF OUTPUT VOLTAGE SPIKE

CHARGE INJECTION

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MAX14866 16-Channel, High-Voltage Analog Switch
without High-Voltage Supply Requirement

Applications Information Banks-Switching Applications

For relay replacement applications or any application
Power Supply
in which the user needs to control the status of all the
The MAX14866 does not require dedicated high-voltage switches simultaneously so that independent control is
supplies; at a minimum, the device operates from a single not needed (bank selection, bi-plane or triplane probes,
LV supply only (VCC = VDD = +5V). multidimensional array etc ..), CLR and SET command
VDD (supply voltage input for CMOS logic input) can be can be used to control the status of all the switches simul-
set at a lower voltage than VCC and can vary from +1.8V taneously. Notice that the CLR logic input is dominant
to +5V depending on the voltage level of CMOS logic with respect to the SET logic input so that CLR = SET
signals. = High corresponds to a Clear command (see Table 1).
Therefore, in these applications, one only control signal is
Logic Inputs required since the the user can toggle the CLR signal only
The MAX14866 digital interface inputs CLK, DIN, LE, while the SET input can be tied to VDD. Whenever the SPI
CLR, SET operate on the VDD logic supply voltage. is not used, connect DIN and CLK to GND and LE to VDD
Daisy Chain and leave DOUT unconnected.
Digital output DOUT is provided to allow the programming Power Sequencing and Bypassing
of multiple MAX14866 devices in daisy-chain configura- The MAX14866 does not require special sequencing of
tion (Figure 4). Connect each DOUT to the DIN of the sub- the VDD, VCC supply voltages. Bypass VDD, VCC to
sequent device in the chain. Connect CLK, LE, CLR, and GND with greater than 0.1µF ceramic capacitor as close
SET inputs of all devices, and drive LE logic-low to update as possible to the device.
all devices simultaneously. Drive CLR high to open all the
switches simultaneously.

U10 U11 U1n

DIN1 DIN DOUT DIN DOUT DIN DOUT

MAX14866 MAX14866 MAX14866

CLK CLK CLK CLK

LE LE LE LE
CLR SET CLR SET CLR SET

SET

CLR

Figure 4. Daisy-Chain Connection

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MAX14866 16-Channel, High-Voltage Analog Switch
without High-Voltage Supply Requirement

Typical Application Circuit

MAINFRAME PROBES

HIGH-VOLTAGE TRANSMIT PROBE SELECTION CABLE TRANSDUCERS

64-128 ch 2-4 probes 1 per ch 2-4 per ch

± 100V max COM1-4 NO1

RELAY PROBE +5V NO2

1 relay/ch/probe A
NO3
SPI
NO4

MAX14866
PROBE (4 SWITCHES ONLY 
B ARE SHOWN)

+V

10mA typ
LOW-VOLTAGE RECEIVE
64-128 ch
PROBE
C
±1V max

HIGH-
VOLTAGE
ISOLATION

-V

Figure 5. Application Diagram

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MAX14866 16-Channel, High-Voltage Analog Switch
without High-Voltage Supply Requirement

Ordering Information Package Information

PART TEMP RANGE PIN-PACKAGE For the latest package outline information and land patterns
(footprints), go to www.maximintegrated.com/packages. Note
110 WLP that a “+”, “#”, or “-” in the package code indicates RoHS status
MAX14866UWZ+ 0°C to 85°C
(5.47mm x 5.53mm) only. Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
48 TQFN
MAX14866UTM+ 0°C to 85°C
(7mm x 7mm)
LAND
PACKAGE PACKAGE OUTLINE
+Denotes a lead (Pb)-free package/RoHS-compliant package PATTERN
TYPE CODE NO.
NO.
Chip Information Refer to
110 Bump
PROCESS: DiCMOS W1105C5+1 21-11001051 Application
WLP
Note 1891
Refer to
48 Pin
T4877+6 90-0130 Application
TQFN
Note 1891

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MAX14866 16-Channel, High-Voltage Analog Switch
without High-Voltage Supply Requirement

Revision History
REVISION REVISION PAGES
DESCRIPTION
NUMBER DATE CHANGED
0 7/17 Initial release —
1 4/18 Updated Pin Description table 10

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.

Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.

Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc. © 2018 Maxim Integrated Products, Inc. │ 23