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ECOAppendix

This document contains procedures for a semi-automated DRC convergence algorithm implementation in TCL script commands. It includes procedures to read and filter a file containing cell information, create a rectangular box from the filtered cell list, split the rectangular box into smaller boxes, check for cells within each smaller box and insert buffer cells if needed. Main calls the procedures to address two specific DRC violations by reading files, creating bounding boxes around violating nets and inserting buffers within the boxes.

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0% found this document useful (0 votes)
65 views15 pages

ECOAppendix

This document contains procedures for a semi-automated DRC convergence algorithm implementation in TCL script commands. It includes procedures to read and filter a file containing cell information, create a rectangular box from the filtered cell list, split the rectangular box into smaller boxes, check for cells within each smaller box and insert buffer cells if needed. Main calls the procedures to address two specific DRC violations by reading files, creating bounding boxes around violating nets and inserting buffers within the boxes.

Uploaded by

manurudin2
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Appendix A Generated Report in Baseline Implementation

Figure A.1 Design Layout Before and After PnR

Figure A.2 Report Design Rules after Synthesis

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Figure A.3 Report Timing Setup after Synthesis

Figure A.4 Report Timing Hold after Synthesis

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Figure A.5 Report Power after Synthesis

Figure A.6 Report Area after Synthesis

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Figure A.7 Report Design Rules after PnR

Figure A.8 Report Timing Setup after PnR

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Figure A.9 Report Timing Hold after PnR

Figure A.10 Report Power after PnR

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Figure A.11 Report Area after PnR

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Appendix B Generated Report in DRC Convergence Algorithm

Figure B.12 Report QoR after Implemented DRC Convergence Algorithm

Figure B.13 Report Timing Setup after Implemented DRC Convergence


Algorithm

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Figure B.14 Report Timing Hold after Implemented DRC Convergence Algorithm

Figure B.15 Report Power after Implemented DRC Convergence Algorithm

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Figure B.16 Report Area after Implemented DRC Convergence Algorithm

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Appendix C Semi-auto DRC Convergence Algorithm Implementation in TCL
Script Commands

###############################################################
## Notes To Use The Semi-Auto DRC Convergence Tcl Script !!! ##
###############################################################
# ICC2 GUI:
# 1. Invoke: icc2_shell -gui
# 2. Open block after "route_opt"
# 3. Open file Report Constraint that generated
# 4. Identify or choose one of the net violating (DRIVER) pin in the
report constraints list.
# 5. Get all load(s) that connected to the driver using command
below:
# "place the command in icc2_shell"
# -> change_selection [get_pins <PIN>] example <PIN> :
cts_inv_575362629/Y !
# -> CTRL T : to zoom in to look the selected pin at GUI.
# 6. Use GUI to get and store the load(s)
# -> Right click on the Pin Selected in GUI > Select Object >
Nets > Cells
# -> use command : get_selection > <directory> /<name file>
# Eg.: get_selection > cell_violate/cts_inv_575362629
# 7. Rewrite/Rename the Filename and Driver Name in the proc main
based on your violation(s)
# 8. You may need to change certain value in certain proc below which
are
# - proc split rect box : value of WIDTH and HEGIHT
# - proc check_cell : the pin name of the load. Eg: "/A"
or "/D" etc
# 9. Source the file in the ICC II synopsys tool
# Eg.-> source scripts/useful_tcl_proc_fix_logical_drc.tcl
# 10. In Proc main : uncomment "route_opt or source" to direct do
route after done insert buffer !
# 11. Now you can RUN the script:
# use command: main
# Don't forget to uncomment the main if want to run directly the
scripts once you SOURCE the script !

############################
## Call the main function ##
############################
# main ;# uncomment when you want to run directly the scripts
# once you source the semi auto script !

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####################################################
## Procedure 1: Read file and filter the contents ##
####################################################

proc read_and_filter_file {filename exclude_driver} {


set file_handle [open $filename r]
set data [read $file_handle]
close $file_handle

# Trim leading/trailing whitespace and braces from the data


string
set trimmed_data [string trim $data " {}"]

# Remove curly braces and split the trimmed_data using spaces as


the delimiter
set cell_list [split [string map {"{" "" "}" ""} $trimmed_data] "
"]

# Filter out the exclude_driver from the cell_list


set filtered_list {}
foreach cell $cell_list {
if {$cell ne $exclude_driver} {
# Remove braces from cell value
set cell_without_braces [string map {"{" "" "}" ""}
$cell]
lappend filtered_list [string trim $cell_without_braces]
puts "filtered_list >> $filtered_list"
}
}

return $filtered_list
}

#######################################################
## Procedure 2: Read file and create rectangular box ##
#######################################################

proc create_rect_box_from_file {filename driver} {

set load [read_and_filter_file $filename $driver]


create_rect_box $driver $load
}

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#########################################
## Procedure 3: Create Rectangular Box ##
#########################################
proc create_rect_box {driver load} {
# Initialize the values of xlow, ylow, xhigh, and yhigh using the
first cell in the list
set first_cell [lindex $driver 0]
set xlow [lindex [get_attr $first_cell origin] 0]
set ylow [lindex [get_attr $first_cell origin] 1]
set xhigh $xlow
set yhigh $ylow

# Loop over each cell in the input list, including the driver
foreach cell $driver {
set c_x [lindex [get_attr $cell origin] 0]
set c_y [lindex [get_attr $cell origin] 1]

# Update the smallest and largest x and y values if necessary


if {$c_x < $xlow} {
set xlow $c_x
}
if {$c_x > $xhigh} {
set xhigh $c_x
}
if {$c_y < $ylow} {
set ylow $c_y
}
if {$c_y > $yhigh} {
set yhigh $c_y
}
}

foreach cell $load {


set c_x [lindex [get_attr $cell origin] 0]
set c_y [lindex [get_attr $cell origin] 1]

# Update the smallest and largest x and y values if necessary


if {$c_x < $xlow} {
set xlow $c_x
}
if {$c_x > $xhigh} {
set xhigh $c_x
}
if {$c_y < $ylow} {
set ylow $c_y
}
if {$c_y > $yhigh} {
set yhigh $c_y
}

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}

# Output the results origin of rectangular box


puts "xlow, ylow: ($xlow, $ylow)"
puts "xhigh, yhigh: ($xhigh, $yhigh)"

# Call the split_rect_box procedure


split_rect_box $xlow $ylow $xhigh $yhigh $driver $load
}

#################################
## Procedure 4: Split Rect Box ##
#################################

proc split_rect_box {xlow ylow xhigh yhigh driver load} {


set rect_count 0
set width 150 ;# Example width "SUBJECT TO CHANGE WIDTH VALUE"
set height 150 ;# Example height "SUBJECT TO CHANGE HEIGHT VALUE"
puts "$width $height"
for {set y $ylow} {$y < $yhigh} {set y [expr {$y+$height}]} {
for {set x $xlow} {$x < $xhigh} {set x [expr {$x+$width}]} {
set rect_xlow $x
set rect_ylow $y
set rect_xhigh [expr {$x + $height}]
set rect_yhigh [expr {$y + $width}]
incr rect_count
puts "Split Rect Box $rect_count >> low:($rect_xlow,
$rect_ylow), high:($rect_xhigh, $rect_yhigh)"
# Pass additional parameters to check_cell if needed
check_cell $rect_xlow $rect_ylow $rect_xhigh $rect_yhigh
$driver $load
}
}
}

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#####################################################################
#Procedure 5: Check Cell(s) inside Split Rect Box & Buffer Insertion#
#####################################################################

proc check_cell {rect_xlow rect_ylow rect_xhigh rect_yhigh driver


load} {
set cell_count 0
set origin_cells [list]
puts "Original driver >> $driver"

foreach cell $load {


set c_x [lindex [get_attr $cell origin] 0]
set c_y [lindex [get_attr $cell origin] 1]

if {$c_x >= $rect_xlow && $c_x <= $rect_xhigh && $c_y >=
$rect_ylow && $c_y <= $rect_yhigh} {
incr cell_count
puts "$c_x $c_y"
lappend cells_in_box $cell
}
}

if {$cell_count == 0} {
puts "No cell inside the split rectangular box of
low:($rect_xlow, $rect_ylow) high:($rect_xhigh, $rect_yhigh)"
} else {
puts "There are $cell_count cell(s) inside the split
rectangular box of low:($rect_xlow, $rect_ylow) high:($rect_xhigh,
$rect_yhigh)"
foreach c $cells_in_box {
puts "Cell(s) in split box >> $c"

# Retrieve the list of pins for the current cell


set cell_pins [get_pins -of_objects [get_cells $c]]
puts "cell_pins $cell_pins"

if {[llength $cell_pins] > 0} {


set stem_pin [lindex $cell_pins 0]
puts "stem_pin $stem_pin"
set stem_cell [get_object_name $stem_pin]
puts "stem_cell $stem_cell"

set object_list "$c/D" ;#Change based The Input Pin


of the load cell.

# Add buffer cells to the origin coordinates found


set new_cell [add_buffer $object_list -no_of_cells 1
-lib_cell */NBUFFX8_HVT]
puts "debug new_cell $new_cell"

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set c_x [lindex [get_attr $c origin] 0]
set c_y [lindex [get_attr $c origin] 1]
set_cell_location -coordinate "$c_x $c_y" $new_cell
legalize_placement -cells [list $new_cell]
puts "Added buffer cell to the cell pin:
$object_list"

} else {
puts "No pins found in the cell."
}
}
}
puts "Done!"
}

###################
## Main function ##
###################
proc main {} {

# Violation 1
set filename "cell_violate/cts_inv_575362629" ; # Replace with
the actual path to your text file
set driver "cts_inv_575362629" ; # Define your driver value
# Read and filter the file contents
create_rect_box_from_file $filename $driver
save_block

# Violation 2
set filename "v/c2.6" ; # Replace with the actual path to your
text file
set driver "cts_inv_465773114" ; # Define your driver value
# Read and filter the file contents
create_rect_box_from_file $filename $driver
save_block

############
##Re-route##
############
#1. Choose either one and uncomment it!
#2. Source: make sure you have the file
#since there are direct commands to generate report !

route_opt
#source scripts/route_after_buf.tcl
}

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