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Tigt, 4 ;7's AZ-1-1 4 ii--4L7J-74?' A
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ELEKTOR AO
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OLD

OiR95[0
6
in°1_
Tg)'°-t.

A selection of some of the

most interesting construction
projects in volume 1 (1975)
of ELEKTOR magazine.
 Book 75 - 001

A selection of some interesting

construction projects, originally
published in ELEKTOR issues
1 to 8.

Elektor Publishers Ltd.

Canterbury
002 - Book 75

The circuits published are for domestic use only. The submission of
designs or articles to Elektor implies permission to the publishers to
alter and translate the text and design, and to use the contents in
other Elektor publications and acitivities. The publishers cannot
guarantee to return any material submitted to them. All drawings,
photographs, printed circuit boards and articles published in Elektor
are copyright and may not be reproduced or imitated in whole or
part without prior written permission of the publishers.
Patent protection may exist in respect of circuits, devices,
components etc. described in this magazine.
The publishers do not accept responsibility for failing to identify
such patent or other protection.
Copyright ©1977 Elektor publishers Ltd - Canterbury.
Printed in the Netherlands
 Book 75 - 003

is an electronics magazine with a difference.

New components, new ideas and new developments
in the field of electronics are used in practical
designs.
This stimulates the professional designer to up -date
his knowledge of electronics; on the other hand,
even the beginning amateur should be able to build
most of the projects.
Ready-made printed circuit boards are available for
many of the designs.

THIS BOOK...
contains a selection of interesting projects
which were originally published in Volume 1
(1975).
We have taken the opportunity to clarify some
points that have given rise to technical queries in
the past. For those who are not yet accustomed to
the Elektor style of writing, we would like to draw
particular attention to pages 18, 19 and 106.
004 - Book 75

ELEKTOR

Editor : W. van der Horst

Deputy editor : P. Holmes
Technical editors : J. Barendrecht
G.H.K. Dam
E. Krempelsauer
G.H. Nachbar
Fr. Scheel
K.S.M. Walraven
Art editor : C. Sinke
Subscriptions : Mrs. A. van Meyel

UK editorial offices, administration and advertising:

6 Stour Street, Canterbury CT 1 2XZ.
Tel. Canterbury (0227) - 54430.
Telex: 965504.
Bank: Midland Bank Ltd Canterbury A/C no. 11014587,
Sorting code 40-16-11, giro: no. 315 4254.

Assistant Manager and Advertising : R.G. Knapp

Editorial : T. Emmens

Many Elektor circuits are accompanied by designs for printed

circuits. For those who do not feel inclined to etch their own prin-
ted circuit boards, a number of these designs are also available as
ready -etched and predrilled boards. These boards can be ordered
from our Canterbury office. Payment, including £ 0.15 p & p, must
be in advance. Delivery time is approximately three weeks.
Bank account number: A/C no. 11014587, sorting code 40-16-11
Midland Bank Ltd., Canterbury.
Example:
tv sound front end 9357 1 30+
1
3 4 56
1. circuit title 4. * = p.c.b.'s with solder mask
3. board number 5. price (in £) inclusive of VAT
6. + = 12.5% VAT; otherwise 8% VAT

versatile digital clock 4414B 1.50

twin led display 4029-2 2.10
coilless receiver for MW and LW 3166 0.90+
austereo 3 -watt amplifier HB11 1.25+
austereo power supply HB12 0.60+
austereo control amplifier HB13 1.65+
austereo disc preamp HB14 0.70+
tup/tun tester 9076* 2.25
tup/tun tester front panel 9076/2A 2.50
tv tennis, main pcb 9029-1A* 4.75
tv tennis, modulator/oscillator 9029-2" 1.15
tv tennis, 5 -volt supply 9218A* 0.90
tv tennis extensions 9363* 5.55
car power supply 1563 1.70
clamant clock, alarm 4015-13 1.55
clamant clock, time signal 4015-16 1.10
clamant clock, striking system 4015-27 1.45
disc preamp 76131 4040A 1.15+
recip-riaa 4039 0.90
stylus balance 9343 0.45+
aerial amplifier 1668 1.25+
miniature amplifier 1486 0.60+
mos clock 5314 clock circuit 1607A 1.80
mos clock display board 1607B 1.30
mos clock timebase 1620 0.90
univeral frequency reference HD4 1.50
edwin amplifier 97-536 1.35+
compressor 6019A 1.60+
car anti -theft alarm 1592 1.85
 Book 75 - 005

versatile digital clock 6 thief suppression in cars . 98

universal display 10 time signal simulator 101
sensitive coil -less afterburner (W. Ferdinand) 101
synchrodyne receiver
for MW and LW 12 fido (A. Seitz) 102

mini hifi 13
tup-tun-dug-dus ... 'data' . 18 'Data section'
Elektor shorthand ... 'data' 18 Elektor services to readers 106
tup-tun tester 20 LED display 107
tv tennis 27 MOS-ICs 108
brake lights for model cars 35 TTL-ICs 109
(R. Zimmer)
opamps 110
supplies for cars 36
transistors 111
clamant clock 38
tup-tun-dug-dus 112
fuse indicator 50
(J.W. van Beek)
disc preamp 50
electronic candle 54
recip-riaa 54
stylus balance 55
tunable aerial amplifier 56
miniature amplifier 61
mos clock 5314 62
improved 7 -segment for
mos clocks 66

universal frequency
reference 67
steam train 68
steam whistle 69
mos clock (2) 71

edwin amplifier 74
tv tennis extensions 80
calendar (W.G. Paans) 90
compressor 94
006 - Book 75 versatile digital clock

ior
ey,ce\\exit
are &Nog here
ior s
the 0531.4

VevestAe &Pa\
cocks,
as tare
as
such they are

can re
dea\
not etc.1\is
be tlseitA.-cwsas vve\\
ca\endars,
trne.output,
irorn
one
per
as

be used

MAO -coded vary og

'One-ch\p' sue,
troe-keepog,hoNever diesvp can
rop\e de 606,
c\ a BCD thatcrock and
has rates
od.eviia\ C's, devces
this
-0V. g\vng repetrton on V C\aroant
extern
standard Severa\forth
uses train outputs day
per
po\se to one are descobed
second c\ock
With th\s .

ca\endar')

Elsewhere in this book there is a design puts of the IC are both '1'. These out- ling were used then the clear input
for a 'one -chip' digital clock, with both puts are connected to the Reset 0 in- would be held low on count 10 during
mains and crystal reference frequencies. puts, so that when the count reaches 6 the second count sequence, and the
Whilst ICs such as the MM5314 are IC5 is reset instantaneously, and the Q output of FF2 could not go high.
excellent for simple timekeeping, they 6 display is never seen.
have certain disadvantages. Since the One pulse per minute is obtained from Provision of 'tick'
output to the display is multiplexed the the 'C' output of IC5, and this is fed It will be noted that IC9 is connected
time output of the clock is not easily through N2 and N1 to IC4, which is differently from the other divide -by -
accessible in a parallel form. This means again connected as a BCD decade coun- 10 counters (IC2, IC4 and IC6). This is
that the clock is unsuitable for driving ter. because a BCD output is required from
time -controlled devices such as alarms, The time -setting circuits around N1 and the other counters. IC9 is connected to
calendars, central heating programming, N2 will be discussed later. give a symmetrical square -wave output,
automatic recording of radio pro- Like IC5, IC3 is connected as a divide - as a convenient simulated 'tick', and this
grammes or other systems. The clock by -6 counter, so that it counts tens of happens to sound better with a
described in this article is based on minutes. 1:1 mark -space ratio.
TTL circuitry and is eminently suitable Counting of the hours is slightly more
for control systems. The time is avail- complicated. Since the clock is a
Time -setting
able as a BCD coded output, and clock 24 hour design, the hours counter (IC2)
pulse trains with rates varying from one must count up to 10 twice, then reset at Three time -setting switches are pro-
a second to one a day are obtainable. 4 on the third count sequence (i.e. when vided. Two to make the clock advance
Many constructors will probably have the hours count reaches 24). Since the at a fast rate, and one to stop the clock.
some of the ICs in their 'junk box'. tens of hours counter only counts to 2 a This is useful because the clock can be
The complete circuit of the clock (ex- counter is made up from two JK flip- set to a particular time, stopped, then
cluding power supply) is given in fig- flops (7473) instead of using a 7490. the stop button can be released exactly
ure 1. The basic operation is quite Resetting is accomplished as follows: on the time signal from radio or tele-
simple. With all the switches in the During the first 0-10 count of IC2 the phone. It is also handy if the clock is
positions shown the clock runs nor- Q outputs of FF1 and FF2 are low. accidentally advanced too far as it saves
mally. The 50 Hz input is rectified by When the 'D' output of IC2 goes low on going all the way 'round the dial'.
D1, clamped to 4.7 V by D2 and then the tenth count the Q output of FF1 Gating for the time -setting is provided
fed into the NAND Schmitt trigger ST I . goes high. At the end of the second by a 7400 (IC7) plus the spare half of
A 50 Hz square wave suitable for driving count sequence the Q output of FF1 the 7413 Schmitt trigger (1/2IC8).
TTL appears at the output of ST1 and is goes low and the Q output of FF2 goes The operation is as follows: when S2 is
fed to IC10 which is connected as a high. The Q output of FF2 and the in the position shown in figure 2a the
divide -by -fivecounter. Asymmetric `C' output of IC2 are connected to the set -reset flipflop N3/N4 is reset, so the
10 Hz pulses are available at the 'D' out- Reset 0 inputs of IC2, so that when IC2 output of N3 is high and the output of
put of IC10. These pulses are fed to reaches 4 in its third count sequence it N4 is low. This means that the output
IC9, which is connected as a divide -by - is reset. However FF2 cannot similarly of ST2 is high. Pulses from output 'C' of
10 counter. A symmetrical 1 Hz square be reset as it has no gating on the clear
wave is available at output 'A' of this input. This difficulty is overcome by
IC. feeding the 'B' output of IC2 to the
The 1 Hz pulses are fed to IC6, which is clear input of FF2 via C 1 and R3. On
connected as a BCD decade counter. count 4 of IC2 the 'B' output goes low,
This counts seconds from 0 to 10 and feeding a momentary reset pulse to
the BCD output may be decoded for FF2. Of course this occurs at count 8
display using a 7447. The 'D' output of also, and during the first and second
count sequences. However, it is only Figure 1. Circuit diagram of the clock. The
IC6 produces one pulse every ten sec- printed circuit board does not include the dis-
onds, and this is fed to IC5, which is during the third count sequence that the play and its associated decoder/drivers.
connected as a divide -by -6 counter. This Q output of FF1 is high anyway, so
counts tens of seconds from 0 to 6. these earlier reset pulses do not matter, Figure 2a. Logic levels at NAND gates for
When the tens of seconds count reaches since the flipflop is reset already. normal timekeeping.
6 (i.e. the seconds display changes from The capacitive coupling (Cl, R3) is
59 to 60) the BCD output of IC5 is necessary to ensure that only a short Figure 2b. Logic levels at NAND gates for
0110, that is to say the 'B' and 'C' out- reset pulse is provided. If direct coup- time -setting.
versatile digital clock Book 75 - 007

0
LI LI
TJF4i zd,1,-1
-- _L
r5 -F,1 7,2 711,91- 91- T416T2FI1T l4 ;F,F,1,-81- 9 1-
I---
5 -r -r-.1 7:F1:T 91-
f 9 a n c 9 a b i ,1 e
IS
aa 6[4 e
7447 7447 7447 7447 7447 /447

C B 1,1 B A B A 0 BA
6
_21-

12 2

0 A BDIN C R A BD, t P A Bi

IC2 IC3 IC4 IC 5 IC6

7490 7490 A,ry 3" 7490 A'' 7490 /490
FFI =
91. 9,6"921 80161801 ! '96'9121 '1316"0, I
1/2 7473
C5

ICI

9
S
0 0
FF2 = 5V
clock 0
10
50 Hz '110 Hz
1/2 74731' N3

7066 78
1/2 IC8
11
ST2 N4
I/2 7413
1 A
DUS
BDIN
IC10
7490 -6' BDIN
AINI
IC9
7490
IC7
Ni ... N4 = 4x 1/4 7400
Stop
® 5V 89121
6
.912/ .0111 891,/
71 PI 3
I/21C8 74414-1
1/2 7413 0, Hours
DUS c
DI
RI 0, Minutes
6 ... 8 V - 410 ST 1 * see text
50H,
C4V7

2a IC4 ICS
S1 0 0

50 Hz d so 10 Hz 1 Hz
-0- -0- N1 N2 N3
ST1 IC10

IC6
IC9
1/21C8
ST2
1/2 7413
1

IC7
Ni ... N4 = 4x 1/4 7400
Stop
S3
74414 -2 A
0
C4
* see text 1100n

2b
IC4
SI

50 Hz d' `c, 10 Hz 1 Hz
-Cr -C1- N1 N2 N3
ST1 IC10
S2

IC9 IC6
1/2 IC8
ST2 N4
1/2 7413
0
IC7
N1 ... N4 = 4x 1/4 7400
Stop
S3
74414-2B
0
C4
* see text 100 n
008 - Book 75 versatile digital clock

3 7,1
6

A O
220µ
4V
D3
/T4 s

BD 240
B20 C2200

TUN

C5 R7
1k

2200µ
16V TUN 31.5
R

5V
7
D4
10p 4V7
16V

rn

C2 C3 C4 Cl C8

100n 100n T 470p

6.3 \i

74417-3 0
Parts list Semiconductors:
ICI = 7473
Resistors: Capacitors: IC2 ...106,1C9,1C10 = 7490 Switches:
RI,R2 = 470 12 C1,C2,C3,C4 = 100 n IC7 = 7400 51 = Single -pole, 2 -way
R3 = 1 k C5 = 10 n IC8 = 7413 S2 = Single -pole, 2 -way, push-button
R4 = 47 S2 D1,D3 = DUS operated
D2 = Zener 4V7 S3 = Single -pole on -off
versatile digital clock Book 75 - 009

IC5 are thus transferred through N2 and Table 2

Ni. When S2 is changed over (figure 2b)
the flipflop is set. The output of N3 is Parts list Clock FF1 FF2 LED
low and the output of N4 is high. The Pulse dis-
output of N2 therefore goes high. 1 Hz Resistors: Num- In- Out- In- Outputs play
or 10 Hz pulses (depending on position R1,R2 = 3k9 ber put put put
of Si) are now transferred through ST2 R3 = 6k8 J1 Q1 J2 Q2 02
R4 = 470 E2 114) 1121 17) 19) an
and Ni to the input of IC4. The clock R5 = 10012 con- BCD con- BCD
will therefore count at the rate of one R6 = 18012 nec- Code nec- Code
minute per second or 10 minutes per R7 = 1 k ted A ted B
second. As an alternative to the 10 Hz R8,R9,R10 = 1.5 5-2 to to
rate, 50 Hz pulses may be used. This P1 = 1 k, preset Q2 01
rate is useful only for setting the hours
rapidly. Capacitors: 1 0 0 0 1 0
The flipflop is necessary to suppress C1,C2 = 100 n 1

C3,C4 = 1 n 1 1 1 0 1
contact bounce on S2. The flipflop is 2
1

C5 = 2200 A/16 V
set (or reset) when the switch initially C6 = 220 /2/4 V 0 0 0 1 0 2
makes contact on being changed over. C7 = 10 µ/16 V 3
Subsequent switch bounce will not C8 = 470 µ/6.3 V 1 0 0 0 1 0
affect the state of the flipflop.
When S3 is changed over the 1 Hz drive Semiconductors:
is disconnected from IC6 so the clock B1 = Bridge rectifier, e.g. B20C2200 Table 1. BCD code.
stops. The position of S3 during time - D1 = omitted
setting with S2 is unimportant. D2,D3 = DUS Table 2. Truth table for IC1 (7473 connected
D4 = zener 4.7 V, 400 mW as 1:3 divider).
T1 = TUP
Power Supply T2,T3,T5 = TUN Figure 3. Circuit of 5-V stabilised power sup-
The clock requires a supply of about T4 = BD240 or equ.
ply -
1 A at 5 V. As transient interference on
the mains supply could interfere with Sundries: Figure 4. Printed circuit and component lay-
the timekeeping of the clock a stable, F1 = 2 A delay -action fuse out of the clock.
Tr1 = transformer, 8 V/2 A
well -filtered mains supply is essential.
The circuit of figure 3 is recommended, Figure 5. Printed circuit and component lay-
as this can deliver up to 2 A and is well out of the 5-V stabilised power supply.
stabilised. The 50 Hz drive for the clock
can be derived from either side of the
transformer secondary winding.

Construction
The p.c. board and layout for the clock
are given in figure 4, and the assembly
requires little comment. The BCD out-
puts of the counters are brought out to
the edge of the board. Display decoding
is not provided on the board. Suitable
decoder and display boards are the
`Universal Display' (see following
pages). If zero suppression on the
tens of hours display is required pin 5 of
the 7447 should be grounded.
The layout and p.c. board of the power
supply are given in figure 5. The output
voltage of the supply should be set to

9
5 V before connecting to the clock.
For 60 Hz operation, see the following
page.
Eno,
-
For use with crystal time base, see
`Universal time base'. 1-
o--111°.---2

11-40 -1 R T I.
0-1 RC 1-- TTTT
IN-{ .8 1"---0
11,---4 R6 .1--
Table 1 INPUTS
COUNT
D C BA
0 0 0 0 0 40.'
C '*" E
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1

4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1

8 1 0 0 0
9 1 0 0 1
5
010 - Book 75 universal display

universal display It is frequently necessary to have

available a numeric display for
many projects such as frequency
counters, digital voltmeters etc. It is a tedious and untidy business to
build up such displays on matrix board, so Elektor have designed a
universal display which should satisfy the requirements of most
enthusiasts. The display may be used with seven -segment LED indicators.

The universal display is modular in con- The soldering iron must have an ex- Figure 1. The display format produced by the
struction and its basic form consists of a tremely fine tip and soldering must be 7447 decoder.
board to accomodate two displays and done extremely quickly to avoid peeling
their associated decoders. The system the fine track from the board. The Figure 2. The improved presentation of the
digits 6 and 9 as used in the universal display.
may be extended to any number of boards available from Elektor employ
digits and decade counter/latch boards plated- through holes, so that it is Figure 3. The circuit used with the 7447 to
may also be added. unnecessary to solder to component achieve the improved 6 and 9 display.
The universal display uses the popular leads on both sides of the board. Simply
7447 decoder. The display format of this solder on the opposite side of the board Figure 4. Circuit of the LED version of the
decoder is given in figure 1. However, to that on which the component is universal display. Note that the decimal point
for digits 6 and 9 the improved format mounted. 14
series resistor has a higher value than the
described in Elektor 2, p. 258 , is em- segment resistors to achieve the same luminous
ployed. This is shown in figure 2. The intensity.
basic configuration of the decoder with Figures 5 and 6. The p.c. board and layout for
the additional transistors is shown in f/7/b
the LED display. The track shown in feint in
figure 3 and the complete circuit of a /c
the component layouts is the side of the
display module for use with LED displays board on which the components are mounted,
is given in figure 4. i.e. the components are mounted directly on
top of the track shown. Figure 5 shows the
components on the back of the board, and
Construction
Double -sided boards are employed in
11,111110 figure 6 shows the display side. (EPS4029-2).

the construction of the display module

and it may be seen from figures 5 and 6
that components are mounted on both
sides of the board. It should be em-
phasised here that great care is required 6
7INN40791
in the assembly of these boards due to
the degree of miniaturisation involved.

versatile 60 Hz operation

dotal The versatile digital clock can be used

in countries that use 60 Hz mains by
making a few simple modifications.
°look First: break the circuit path on
p.c.b. between pin 11 of IC10 and pin
the
1 of IC9.
Then: connect a jumper wire between
pin 8 of IC10 and pin 1 of IC9.
Finally, use a 7492 for IC10.
universal display Book 75 - 011

4
5V

L2F B Ll

14

R4 R9 R8 R5 R6
R151R121 R18 R13 R14 R17 R16
R20 ci 01 C; ci C; 03 a; 01 01

, 10 12
131 14 9 10 111 12
A F G E D C A F G D C B

IC 2 C1
8
GND 7447 0 16
7447 O 16

A A
7 2 6
T2
R2 R11

J 2k 2
J ZEN
OOo
TUN TUN ABC D TUN

4029 4

2 Components list for figure 4:

Resistors:
R1,R2,R10,R11 = 2k2
R3 to R9, R12 to R18 = 180 E2

Semiconductors:
4029 2
T1 to T4 = TUN
IC1,1C2 = 7447
L1,L2 =e.g. H.P.5082-7730 or
7750, Opcoa SLA 1, T.I.
Til 302, Data Lit DL 707.

6
r
0 L2 LI

:is oti)
IL5 61 49
012 - Book 75 sensitive coil -less synchrodyne receiver for MW and LW

This little receiver tunes the medium to the amplifier stage with T4, via the
and long wave -ranges. It operates with- full -wave 'detector' with DI and D2.
out any coils by employing a synchron- The output level is sufficiently high for
ised oscillator. driving most amplifiers.
When the oscillator is barely able to A short aerial, such as a piece of wire, is
maintain oscillations, it will synchronise enough to provide quite reasonable
to an incoming signal frequency close to reception. If a good aerial is to be used,
its free -running value. The amplitude of PI can be inserted to prevent over-
the oscillation follows, more or less driving by too strong a signal.
linearly, the modulation of the
sensitive incoming signal. The circuit can
synchronise itself to a signal of some
coil -less tens of microvolts, so that its effective
sensitivity is very high.
synchrodyne P4 sets the level of oscillation; the
stereo -ganged pair P2 and P3 form the
receiver for `tuning' control. Since this stereo -
potentiometer covers a very wide range
it may be necessary to add a 'fine'
MW and LW control consisting of a low -value stereo -
potentiometer in series (typically 1 k or
500 ohm).
The modulated oscillator signal is passed

9...12V®

R2 54 R7 R12 514

220n
C61F
56 p 56p 10µ
100p 16V
Cl
C4 C51111_
BF254
100µ T2 F°1
16 V ci2 AF
C2
10U TUN
6,3,y T4

51 R6 R9
I CO
i

D2

R13 10p
P1
47k T -47k 10n 6,3V 515

P5
Thin __log C10

3166

R4 I -. R7 1---0 410-C-1 II -0 AF. Rtt

A1--
D1
ft -.--4 512 I.
411,---t_i314
0-4 A 2 1-1, 0111-0
ci -±11- - 1
C12

T1 R10 1-110C10A

11-1 R3 I". .--f R8 1--

0--1 R 5 1--0 56

EPS 31771
mini hifi Book 75 - 013

ammo lido
In contrast to the now -prevalent
'multiwatt' systems currently on
the market, a design is de-
scribed for a Hi-Fi stereophonic
amplifier of modest specification
for the price -conscious
constructor. The system is built
from several units that are
matched to one another, but this
does not preclude their use with
other equipment.

The block diagram of figure 1 shows how supply provides the H.T. for all three RIAA feedback network R18, R19, C15
the units are connected together to form stages of the amplifier. and C16 connected from the collector
a complete stereo amplifier. The disc of T5 to the emitter of T4. DC feedback
preamplifier is required only with a The disc preamplifier and biasing of T4 is provided by R15.
magnetic cartridge. It is followed by the The disc preamplifier, the circuit of The disc preamplifier board should
control amplifier which incorporates which is given in figure 2 (one channel preferably be mounted inside the turn-
balance, volume and tone controls. This only shown), incorporates equalisation, table itself as otherwise the capacitance
stage will accept inputs from high level to correct the output of a magnetic of the screened lead between the car-
sources such as radio and tape. cartridge according to the RIAA play- tridge and the disc preamplifier can form
The control amplifier drives the power back curve, and also amplifies the signal a resonant circuit with the self-
amplifier which will provide up to 3 watts to a level sufficient to drive the control inductance of the cartridge. If this
per channel; this is sufficient for the amplifier. It consists of a two -stage resonance lies within the audio spectrum
average living room. A regulated power voltage amplifier, T4 and T5, with the it may cause a peak in the frequency

1
L
PP
0_40._t__
magnetic disc control power
cartridge preamplifier amplifier amplifier
R R
No BP

power
supply

Figure 1. An economical Hi-Fi stereo amplifier

built of four units. Each unit may also be used
in conjunction with other equipment.

Figure 2. The circuit of the disc preamplifier.

It is designed for use with magnetic cartridges
and incorporates RI AA correction.
014 - Book 75 mini hifi

3 4
HB1317-7
FY C18

ft22 R23 -.4 .23 j- r-{.22

ID
CIl

1[1

0
0 00
5
C7

12...24V
F35
39n
O 1k
bass P4
T2 R11
R2
R24 100k
lin C8
-r
CI T1 TUP
_ 251-1
R7 16V T3
C12
balance R E91[1
10k TUN oopt 25 P
P5 lin 5°mve 16V p
16V 16V
R8 TUN
C2470µ
=pm 6V 4 2
C5 100k C6 R12
R24 lin C10
P1 5k
R3
1k
lin log laU In
2n2 treble
0 0 12°5°V11 me P3 2n2
T
HB13
0

response. Of course some cartridge the control amplifier by means of P1. Figure 3. The layout of the p.c. board for the
manufacturers quote a recommended P1 is also used to match the gains of the disc preamplifier shows the symmetrical
arrangement of the two channels.
load capacitance and if this is so their two channels so that channel balance is (EPS HB14).
recommendations should be adhered to. correct with the balance control central.
Another good reason for mounting the With P1 set to 1 k the input sensitivity Figure 4. The component layout for the disc
disc preamplifier inside the turntable is when used with the 12 volt version of preamplifier board of figure 3.
to keep it away from the hum fields of amplifier is about 150 mV for 3 watts
the amplifier's mains transformer. Turn- into 4 f2. Figure 5. The circuit of one channel of the
table motors usually have much less P2 is the volume control and this is control amplifier.
stray field then the average mains trans- followed by a standard `Baxandall' tone Figure 6. The printed circuit for the control
former! control circuit which gives a range of amplifier. (EPS HB13).
The printed circuit board for the disc ±-12 dB on both bass and treble. The
preamplifier is given in figure 3 and the balance potentiometer P5 completes the Figure 7. The component layout of the control
associated component layout in figure 4. controls. C10 is a high -frequency bypass amplifier.
It can be seen that the layout for the capacitor to avoid instability. The
two channels is symmetrical. p.c. board and component layout of the
control amplifier are given in figures 6
and 7.
The control amplifier
The circuit of one channel of the control
amplifier is given in figure 5. T1 and T2 The power amplifier
form a voltage amplifier with a high In the circuit of figure 8 Ti and T2 form
input impedance and a low output im- a direct -coupled voltage amplifier which
pedance. Two versions of the power controls the bias of the quasi -
amplifier are described in the following complementary driver/output stage T3,
section; a 12 -volt version, to give 3 watts T5 and T4, T6. R7 and R8 are chosen
into 4 E2 and a 17 -volt version, to give so that the output devices are either just
3 watts into 8 E2. Since the output biased on or just cut off depending on
voltage of the amplifier for 3 watts into the gain of the devices used. C3, C5 and
4 E2 is 3.5 V RMS, whereas for an 8 E2 R3 help to maintain stability. The input
load it is 4.9 V RMS, the 17 -volt version sensitivity of the amplifier is about
of the power amplifier requires a larger 400 mV for 12 volt operation with a
input signal, since its gain is fixed. This 4 E2 load, and 600 mV for 17 volt
is accomplished by varying the gain of operation with an 8 si load. The gain
mini hifi Book 75 - 015

Parts list for figures 2 and 4: Parts list for figures 5 and 7:

Resistors: Resistors: Semiconductors:

R15 = 47 k R1 = 2M7 T1,T3 = TUN
R16 = 1k5 R2 = 4M7 T2 = TUP
R17 = 18 k R3,R4,R5,R12 = 1 k
R18 = 12 k R6,R9,R13 = 4k7 Miscellaneous:
R19 = 120 k R7 = 39 k P1 = preset potentiometer 1 k lin.
R20 = 2k7 R8 = 5k6 P2 = potentiometer 4k7 log. stereo
R21 = 10 k R10 = 47 k P3,P4 = potentiometer 100 k lin. stereo
R22 = 4k7 R11 = 220 k P5 = potentiometer 10 k lin.
R23 = 100 k R14 = 100 k
R24 = 470
Capacitors:
C13 = 1µ,6V Capacitors:
C14 = 100 p, 25 V C1 = 1 bt, 6 V tantalum
C15 = 27 n C2 = 470 p, 6 V
C16 = 6n8 C3 = p, 16 V
C17 = 50 µ, 6 V C4 = 100 p, 25 V
C18= 1 1..1,16V C5,C6 = 2n2
C7 = 39 n
Semiconductors: C8,C9,C12 = 25 /.2, 16 V
T4 = BC 109 C10 = 1 n
T5 = TUN C11 = 50 p, 6 V

16164114-t_ell!glifi
el

7 I1LP II

ITIT 0-1
H813.1

0.--4 R13' 0-4 R

0 0i I
R 11

0-* R10' tl C3 n

0 11---4 R12
R4'

lC
016 - Book 75 mini hifi

Figure 8. The output amplifier, which will

8 deliver 3 watts into 4 E2 with a 12 volt supply
12...17V and 3 watts into 852 with a 17 volt supply.
The different values for R12 and C4 are given
C6 147n in the table.
8
Figure 9. The printed circuit for the power
amplifier is also symmetrical. It may be cut
R3
4k7
in half for mono applications if desired.

1
Figure 10. Component layout for the power
amplifier p.c. board. (EPS HB11).
2N1613
C4 Figure 11. The circuit of the simple stabilised
supply. The values of R1 and Z1 depend on
;1700µ the supply voltage required.
-{ 4k7 16V

D2 DUS Figure 12. Board and component layout for

R10
C1
R
47,, the power supply. (EPS HB12).
0-1 2112
T4

T6
-r
16V TUP 2N1613 LS
42
C3 C2
V
R R12 cr,
R11
10o 1O0µ co
16V

HB 1

Parts list for figures 8 and 10:

Resistors:
R1,R2 = 100 k
R3,R5 = 4k7
R4 = 470 E2
R6 = 33 E2
R7,R8 = 56 E2
R9,R10 = 0,2 12
R11 = 1 k
R12 = see table

Capacitors:
C1=2,2µ,16V
10 re C2= 100/2,16 V
C3=10 n
C4 = see table
C5,C6 = 47 n
.311. RS

°-.{
RIO
H. Rtt
0 Semiconductors:
T1,T3 = TUN
C1 R4
1-0
T2,T4 = TUP
T5,T6 = 2N1613
R12 D1,D2 = DUS
2 TO5 heatsinks for T5 and T6
1+1

0 -A DI 02 12V 17V
Rt7
R8
R12 680 E2 1k
. 3$ .31$ C4 4700 II 2200
RIO
LS 452 852

R1
}- I

atit 3111
1)
mini hifi Book 75 - 017

may be increased by reducing R4 but this

is not recommended as instability may
occur and in any case the overall gain of
the system may be altered by adjusting
P1 on the control amplifier board. The
printed circuit for the power amplifier
is given in figure 9 and the component
layout in figure 10.

Supply
The regulated power supply is very
simple, as can be seen from figure 11.
T1 and T2 form a Darlington pair acting
as a compound emitter -follower with
a reference voltage provided by Zl. Zl
is chosen as a 13 or 18 volt zener for a
12 or 17 volt supply respectively. Since
T2 dissipates only a small amount of Transformer:
Tr1 = 2 A sec. see table
power a heatsink is not required. Parts list for figures 11 and 12:
Figure 12 shows the board and com- Miscellaneous:
ponent layout of the power supply. G = B40C2200 40 V 2.2 A bridge rec.
The component values for both versions or 4 x 1N4001
are given in the table of figure 11. Resistor: Z1 = zener diode, 250 mW, see table
R1 = see table N = neon
Layout R2 = 100 k S = switch on/off
The following layout precautions should Capacitors:
be noted when assembling the completed C1 = 2200 bi, 25 V 12V 17V
board onto a chassis: C2 = 100 µ, 25 V R1 270 2 680 E2
1. Loudspeaker common must be con- Z1 13V 18V
nected directly to the power supply Semiconductors:
T2 TUN BC 107
common and should be kept well T1 = 2N3055
away from the boards. T2 = see table Tr 12 V^ 18 V
2. Separate leads must be run from the
supply to the supply points on each
board.
3. Outputs of any board should be kept
well away from inputs of other boards
(except of course where the output of
a stage is connected to the input of
the succeeding stage).
4. Care should be taken to avoid earth
loops. Each section of the amplifier
should have only one connection to
supply common.
N
018 - Book 75 tup-tun-dug-dus

Table 3 lists a number of possibilities for

use as TUP, while table 4 gives equival-
ents for DUG and DUS.
A further group of better quality tran-
sistors are the BC107 - BC108 - BC109
(NPN) and BC177 - BC178 - BC179

tup-tun-du
(PNP) families. The minimum specifica-
tions are listed in table 5, while table 6
gives a list of equivalents. As will be
obvious from the specifications, the
main differences between the types are

dus
that the BC107/BC177 are higher volt-
Wherever possible in Elektor age types (Vceo = 45 volts) and the
circuits, transistors and diodes are BC 109/BC179 are low -noise. If these
simply marked 'TUP', 'TUN', differences are not important in a par-
ticular circuit, the various types are
'DUG' or 'DUS'. This indicates interchangeable.
that a large group of similar devices The code letters A, B or C after the type
can be used without detriment to number on these transistors denote
the performance of the circuit. various current amplification factors.
For the A -types this is from 125 to 260,
for the B -types it is 240 to 500 and for
the C -types 450 to 900. A BC109C is
therefore not a direct equivalent for a
As far as possible, the circuits in Elektor DUS = Diode, Universal Silicon. BC109B, for instance, although in many
are designed so that they can be built TUP, TUN, DUG and DUS have to meet practical circuits it will make little or no
with standard components that most certain minimum specifications - they difference.
retailers will have in stock. are not just 'any old transistor' or 'any When using the equivalent types BC167,
It is well-known that there are many old germanium diode'. . . .The minimum -168,-169, BC257, -258, -259 or BC467,
general purpose diodes and low fre- specifications are listed in tables la and -468, -469 it should be noted that the
quency transistors with different type 1 b. It is always possible, of course, to use base, emitter and collector leads are in
numbers but very similar technical a transistor with better specifications a different order (see table 6).
specifications. The difference between than those listed!
the various types is often little more
than their shape. This family of semi-
conductors is referred to in the various Specifications and equivalents
articles by the following abbreviations: A number of transistor types that meet
TUP = T ransistor, Universal PNP, the TUN specifications are listed in
TUN = Transistor, Universal NPN, table 2. This list is, of course, incomplete
DUG = Diode, Universal Germanium, - there are many more possible types.

4700 µF, and could have been written

as 4m7 - but never is.
Capacitance value 10 n: this is 10 nF,
elektor shorthand and is also sometimes written (but
not in elektor!) as 10,000 pF or
From various enquiries it has become clear that some of our readers feel 0.01 µF; or even as 10 kpF (10 kilo-
pico-Farad), which is a horrible con-
that they have been plunged in at the deep end. Elektor's 'shorthand' fusion of symbols. In the same way
style of symbols and conventions seems to have led to some confusion, one sometimes finds µµF (micro -
in spite of our efforts to the contrary, so some further explanation seems micro -Farad) instead of pF.
to be called for.
Semiconductor type numbers
Very often, a large number of equivalent
types for one integrated circuit exist
with different type numbers. On closer
Furthermore, the symbols E2 (ohm) and examination, a group of digits are often
Resistor and capacitor codes found to be identical, but they are pre -
When giving the values of resistors and F (farad) are usually omitted, since it is or suffixed with letters and digits which
capacitors, decimal points and large normal practice to state resistance values
in ohms and capacitance values in farads. denote the manufacturer. As an example,
numbers of zeros are avoided as far as a popular op -amp is variously denoted
possible. To this end, extensive use is Finally, the decimal point is usually re-
placed by one of the abbreviations (p, n, as µA741, LM741, L741, MC1741,
made of the international abbreviations: MIC741, RM741, SN72741 or ZLD741,
. .) listed above (This has also been
p (pico-) = 10-12= one millionth of .
to name a few. To cut through this
one millionth; accepted practice for some years).
confusion, this IC is referred to in elektor
n (nano-) = 10-9 one thousandth A few examples may serve to clarify all as a '741' - which means that we
of one millionth; this: couldn't care less who makes it, provided
µ (micro-) = 10-6 = one millionth; Resistance value 2k7: this is 2.7 kE2, or it meets the specifications.. .
m (milli-) = 10-3 = one thousandth; 2700 E2.
10° = unity; Resistance value 470: this is 470 E2.
k (kilo-) = 103 = one thousand Resistance value 3M9: this is 3.9 ME2, or
times; 3,900,000 f2.
M (mega-) = 106 = one million Capacitance value 4p7: this is 4.7 pF, or
times; 0.000 000 000 004 7 F . . .
G (giga-) = 109 = one thousand Capacitance value 100 µ: this is 100 µF.
million times; Capacitance value 4700 µ: this is
tup-tun-dug-dus Book 75 - 019

TUP TUP
TUB 111111
DUB
DUG
our
Table 6. Various equivMents for the BC107,
type Uceo Ic hfe Ptot fT -108,. .families. The data are those given by
.

min. max min. the Pro -Electron standard; individual manu-

max max
facturers will sometimes give better specifi-
TUN NPN 20V 100 mA 100 100 mW 100 MHz cations for their own products.
TUP PNP 20 V 100 mA 100 100 mW 100 MHz
NPN PNP Case Remarks
Table la. Minimum specifications for TUP and
TUN. BC 107 BC 177 C

Table lb. Minimum specifications for DUS and BC 108 BC 178 B

DUG. BC 109 BC179

Ptot CO
BC 147 BC 157 Pmax =
type UR IF IR
BC 148 BC 158 250 mW
max max max max max A

BC 149 BC 159
DUS Si 25 V 100 mA 1 pA 250 mW 5 pF
DUG Ge 20 V 35 mA 100 pA 250 mW 10 pF BC 207 BC 204
BC 208 BC 205 111,,
BC 209 BC 206
c

Table 4. Various diodes that meet the DUS or BC 237 BC 307

Table 2. Various transistor types that meet the
TUN specifications. DUG specifications. BC 238 BC 308 HIS
BC 239 BC 309

TUN DUS DUG BC 317 BC 320

BC 384 BA 127 BA 318 OA 85 BC 318 BC 321 SI icmg0=mA
BC 107 BC 208
BC 407 BA 217 BAX 13 OA 91 BC 319 BC 322
BC 108 BC 209
BC 109 BC 237 BC 408 BA 218 BAY 61 OA 95 BC 347 BC 350
BC 147 BC 238 BC 409 BA 221 1 N914 AA 116 BC 348 BC 351 4/
BC 148 BC 239 BC 413 BA 222 1 N4148 BC 349 BC 352
BC 149 BC 317 BC 414 BA 317
BC 407 BC 417 Pmax =
BC 171 BC 318 BC 547
BC 408 BC 418 250 mW
BC 172 BC 319 BC 548
BC 409 BC 419
BC 173 BC 347 BC 549 Table 5. Minimum specifications for the
BC 182 BC 348 BC 582 BC 547 BC 557 Pmax =
BC107, -108, -109 and BC177, -178, -179
BC 183 BC 349 BC 583 families (according to the Pro -Electron BC 548 BC 558 IN 500 mW
BC 184 BC 382 BC 584 standard). Note that the BC179 does not BC 549 BC 559
BC 383 necessarily meet the TUP specification
II Ia
BC 207 BC 167 BC 257 169/259
(lc,max = 50 mA).
BC 168 BC 258 icmax =
BC 169 BC 259 50 mA
NPN PNP

Table 3. Various transistor types that meet the

TUP specifications.
BC 107
BC 108
BC 177
BC 178
BC 171
BC 172
BC 173
BC 251
BC 252
BC 253
ii 251 .

low noise
.. 253

BC 109 BC 179
BC 182 BC 212 Icmax =
TUP Vceo 45 V 45 V BC 183 BC 213 . 200 mA
BC 157 BC 253 BC 352 max 20 V 25 V BC 184 BC 214
BC 158 BC 261 BC 415 26V 20V
BC 582 BC 512 Icmax -
BC 177 BC 262 BC 416 Vebo 6V 5V BC 583 BC 513 844 200 mA
BC 178 BC 263 BC 417 5V 5V
max BC 584 BC 514
BC 204 BC 307 BC 418 5V 5V
BC 205 BC 308 BC 419 BC 414 BC 416 low noise
BC 206 BC 309 BC 512 lc 100 mA 100 mA BC 414 BC 416 ai
BC 212 BC 320 BC 513 max 100 mA 100 mA BC 414 BC 416
BC 213 BC 321 BC 514 100 mA 50 mA
low noise
BC 214 BC 322 BC 557 Ptot. 300 mW 300 mW Ci]
BC 413 BC 415
BC 251 BC 350 BC 558 300 mW 300 mW
max BC 413 BC 415
BC 252 BC 351 BC 559 300 mW 300 mW
BC 382
150 MHz 130 MHz
fT
150 MHz 130 MHz
BC 383 al
mm. BC 384
150 MHz 130 MHz
BC 437 -: Pmax =

IMP ::
F 10 dB 10 dB BC 438 220 mW
10 dB 10 dB BC 439
max
4 dB 4 dB
BC 467 Pmax =
220 mW
1111111 The letters after the type number
BC 468
BC 469
h V

11116 denote the current gain:

A: a' (j3, hfe) = 125-260
BC 261
BC 262 -
low noise

DUG B:
C:
a'
a'
= 240-500
= 450-900.
BC 263
020 - Book 75 tup-tun tester

which has been divided into three sec-

tions to avoid confusion. Transistors T5

tup tun
and T6 in figure 2a form an astable
multivibrator which runs at about 2 kHz.
T2 and T3 form another multivibrator
which runs at a much lower speed, about
2 Hz, and turns the 'fast' (2 kHz) oscil-

tester
lator on and off through transistor T4,
which also supplies a 2 Hz switching
waveform, via connection 'Q', to the dis-
play section T7 ... T9 and LEDs 'A' and
`B' (figure 2c). A similar 2 Hz switching
waveform, in antiphase to the one which
appears at 'Q', is supplied to the display
This tester gives an instant check of the 'general health' of a transistor, as section by T 1 via `P'. As will be seen
well as its compliance with the minimum TUP or TUN specification, by later, these switching waveforms are
needed to enable an unambiguous display
the very simple procedure of plugging it into test sockets and interpreting to be obtained from two LEDs only.
the messages from two light -emitting diodes. It is also possible to check An optional third LED (shown in the
diodes for excessive capacity or leakage. circuit as LED 'C') can be connected in
series with the 680 SZ resistor R9 be-
tween 'Q' and supply negative. This will
give a partial test of the tester itself by
blinking in step with the slow oscillator
The principle of operation is simple and mittent 2 kHz square wave is fed in anti - if this is functioning.
no preliminary calibration is needed - phase to the bases of each of the two 2 kHz square waves of equal amplitude
only the use of transistors and diodes transistors. Figure 1 shows a block dia- and opposite polarity are produced inter-
known to be 'good' and resistors within gram of the arrangement, from which a mittently at the collectors of T5 and T6.
the specified tolerance. lot of information about the semi- These two points, which drive the whole
An astable multivibrator generates a conductor under test can be deduced of the test circuitry, are marked 'X' and
square wave at a frequency of about from the 'behaviour', voltage -wise, of `Y' respectively. When the fast oscillator
2 kHz, and this oscillation is turned on the junction between the two semi- is turned off, T5 is cut off and its
and off by another multivibrator at conductors. This information can be collector ('X') is at its higher potential.
about 2 Hz. The collector -emitter path displayed with the aid of only two light - The left-hand half of figure 2b is the
of the transistor under test (or the emitting diodes (LEDs). section in which PNP-transistors are
anode -cathode path of the diode) is tested. It has been shown that 2 kHz
connected in series with another transis- Circuit Description square waves of equal amplitude and
tor across the supply rails, and the inter- Figure 2 shows the complete circuit, opposite polarity are being injected
intermittently at 'X' and 'Y'.
Display
Assume that a (good) PNP transistor is
plugged in at the test point TA in fig-
ure 2b. When the fast oscillator is off,
`X' is positive and 'Y' is negative. (The
terms 'positive' and 'negative' are used
to denote the higher and lower potentials
taken up by various points in the circuit).
Both the transistor T10 and the transis-
tor TA under test are therefore cut off,
and the connection joining the collectors
of T I 0 and TA is floating. The diode D10
does not pass any current and the
Darlington pair T11 and T12 is cut off.
Figures 2b and 2c show that the collector
of T12 is one of the points connected
to the base of T9 (point A). When T12
is cut off, 'A' is positive and T9 is there-
fore also cut off. LED 'B', which is in
the collector lead of T9, is therefore off,
and the collector of T9 is negative.
To find what LED 'A' is doing, the
other switching waveforms, derived from
the slow oscillator via `P' and 'Q', must
now be examined. To switch the fast
oscillator off, 'Q' must be negative;
therefore `P' is positive. T7 is connected
to `P', so T7 can conduct if its base re-
ceives a positive drive from the collector
of T9 via R19.
In the situation now under consider -
ation, however, the collector of T9 is
negative and T7 does not pass current.
T8 is also returned to the negative rail
through LED 'A', but 'Q' is negative so
LED 'A' stays off.
Recapping at this stage; with a good
tup-tun tester Book 75 - 021

transistor and when the fast oscillator

is turned off, both LEDs are off.
It has been seen that the three points
which determine the LED display are
`A', `P' and `Qe. The basic relationship is
as follows:
1. When `P' is positive (i.e. the fast oscil-
lator is turned off), LED 'A' will
light up if the base of NPN transis-
tor T7 is driven positively from the
collector of T9.
2. When 'Q' is positive (Le. the fast
oscillator is turned on), LED 'A' will
light up if the base of PNP transis-
tor T8 is driven negatively from the
collector of T9.
3. LED 'B' lights up when the collector
of T9 is positive, irrespective of
whether `P' or 'Q' is positive. 2
4. When 'A' is negative, the collector of 20...24V
910 R15
T9 is positive. 4

,
6 R11
50mA
These relationships can be combined BC
177A C3
in a kind of truth table which will help
in predicting the display for transis-
C. II-.
5n6
A
tors or diodes in different states of 4/17/2 5V
C4
I
health. They are also summarised, in a
D2 R12
H
5n6
slightly different form, in figure 3a + b. 15
gr. LE
C
FAST 'A' LED LED BC237B BC237B BC237B BC237B

OSCILLATOR SWINGS A B
TURNED
L® ©0
Off positive Off Off
Off negative On On 0I
R38200 24J
On positive On Off R32 936 R37

On negative Off On ]930

T15 B
What happens during the bursts when BC
the fast oscillator is turned on? 0 925
17 7A R39

`X' and 'Y' are being swung alternately

positive and negative with opposite po-
larities at 2 kHz. When 'X' swings positive
BC239C BC 179C T14© 0
and 'Y' swings negative, the same reason- O -0
R34 R40

ing which was applied to the situation

when the fast oscillator is turned off will -re BC
237B
BC237B
indicate that 'A' swings positive and T13

012
LED 'B' is off. In this case, however, the -931 R33 R35
fast oscillator is turned on (`Q' is there- D13

fore positive) and LED 'A' lights up.

When 'X' swings negative and 'Y' swings 0
positive, it will be seen from figure 2b L_ _ J
that both T10 and the transistor under
test in TA are turned on. The emitter of
TA is directly connected to supply 0
20...24V
positive, while the emitter of T10 is con-
nected to supply negative through the D1 ...D 13 = DUS 617

470 S2 resistor R28. Ifthe current

gain of TA is high enough, the potential 918 -924 C
47k
at the collector of TA will move positive- BC177A
BC 237B
ly, D10 will conduct and the base of T11 919
47k

will also move positively. (This will be 916

6802 I- 4700
R20

discussed in more detail later.) The

emitter of T12, the other transistor in LED
A VI B
LED 6

the Darlington pair, is held by R30 and 0

R31 at half the supply rail potential, so 9076-2
T12 is turned on; its collector potential
(point 'A') swings negative and, as can
be seen from the table, LED '13' lights Figure 1. Block diagram of the arrangement The full display cycle for a 'good' tran-
up and LED 'A' is off. for testing a PNP transistor. For clarity, the sistor is that both LEDs blink on and off
So the LED display while the fast oscil- breakdown voltage test and the complemen- together (figure 3c). It will be seen later
tary test for an NPN transistor have been that this display occurs only with a
lator is turned on and the transistor is a omitted.
`good' one is that 'A' and 'B' each come transistor which is good according to all
on during alternate half -cycles of the Figure 2. Complete circuit of the TUP/TUN
the criteria that are tested in socket TA.
2 kHz oscillation. Both LEDs therefore tester. Block A is the collector section, B con -
appear to be on during each 2 kHz burst, tains the test bridges for NPN and PNP transis- Transistor with low current gain
and it has already been seen that both tors and C shows the breakdown voltage testing
are off while the fast oscillation is turned and display sections. (a')
off. When the fast oscillator is turned off,
022 - Book 75 tup-tun tester

`X' swings positive and 'Y' swings nega- 18 x 106 both being off. When the fast oscillator
tive, so both T10 and the transistor under 70 µA comes on and swings 'X' negatively and
270 x 103
test in TA are cut off. Their commoned (the base -emitter resistance can be dis- `Y' positively, both transistors are turned
collectors are floating, and by the same regarded in this context). on, but if TA has high collector -to -base
sequence of events as described for a It has been mentioned that T10 acts as a (Ccb) and/or collector -to -emitter (Cce)
good transistor, the voltage at the col- current source attempting to stabilise the capacitance, its response is delayed. The
lector of T9 is low and LED 'B' is off. It collector current through both transis- voltage rise at its collector is slowed
can be deduced from the table that this tors at 7.4 mA, which corresponds to a down as these capacitances discharge,
combination of switching voltages leads current gain of something over 100 for but the voltage will probably level off at
to LED 'A' also being off. the transistor under test. If TA cannot its 'final' value before the end of the
When the fast oscillator comes on and produce this current, T6 bottoms and period in which TA is turned on, and
swings 'X' and negative and positive the voltage at the connected collectors when this happens LED '13' comes on
respectively, T10 and TA are both turned of TA and T10 becomes too low for T11 while LED 'A' stays off (figure 3e).
on. The potential at the base of T10 is and T12 to be turned on (figure 3d). So When, however, TA and T10 are once
therefore determined by the potentio- the potential at 'A' remains positive and more turned off by the swings at 'X' and
meter R15 (figure la), R26 and R27, i.e. LED 'B' stays off. The table will show the capacitances can recharge only
33 that LED 'A' comes on. through the Darlington pair T11 and T12
20x - 4.2 V. When the fast oscillator swings to its (which has, by definition, a high input
4.7 + 120 + 33
other polarity (i.e. 'X' swings positive impedance) and through the 10 MS2 re-
The base -emitter voltage drop in T10 will and 'Y' swings negative) the linked col- sistor R29. The drop in potential at the
be about 0.7 V, so the voltage at the lectors of TA and TIO revert to the float- collector of TA, as the capacitances
emitter of T 1 0 cannot rise above ing condition, so that the Darlington recharge, is slower than it would be with
4.2 V - 0.7 V = 3.5 V. T 10 is therefore pair T11 and T12 remains non-conduc- a normal transistor, and if the capaci-
acting as a current source, its collector tive and 'A' positive. LED 'B' therefore tances are too large the potential will not
current being stabilised at the value stays off and LED 'A' stays on. fall far enough to turn T11 off (and
determined by this latter voltage and the Summarising: the LED display with a therefore LED 'A' on and LED '13' off)
emitter resistor R28, i.e. transistor of low current gain is that before the time when TA and T 10 are
LED 'A' blinks and LED '13' stays on. turned on once again. So LED 13' will
3.5 x 1000 stay on, and LED 'A' off, throughout
mA ,=,- 7.4 mA
470 Transistor with high capacitances each period when the fast oscillator is
As the emitter of TA is directly con- When the fast oscillator is turned off, turned on.
nected to the positive supply rail, its the situation is the same as in both the With slightly smaller capacitances,
base current is determined by the voltage cases already examined: T10 and the LED 'A' may come on dimly if the slow
(about 19 V) between 'X' and the posi- transistor under test are both cut off, recharge of excess capacitance only
tive rail, and by R25, i.e. and this leads to LED 'A' and LED 'B' allows this LED to turn on for a small

3 DISPLAY

a. Fast oscillator On/Off

potential at®
On Off

b. Display mode, depending 20Vi

on potential at D10 WA 0 7//, B a .//. ViA a r//.8 (X %/.
anode
10V
OV
A ():-,\\ B s\\ ,\ A B
A B
c. Good transistor
_ _____ - -
, (11,- A BO

---1
d. a < 100
__r714"_ -r-%___ _. --'4
Acc_7..

B. A B
el. Capacitances, Ccb or
- - --
Cce, much too high -,-4
AO BO-- AO BO

e2. Capacitances, Ccb or

Cce, just too high
AO BC) AO BO
\ I /,,,,
f. Leakage > 1 µA

s0:-
1 f() ,0:
- A-
O -13-057 A 0.1-

g. Base -emitter short

I_

' A0,- B.
j ------ -- -1
A BO- --
-')C)
Figure 3. Summary of LED displays, based
on the waveforms at the collector of the
transistor under test.

h. Collector -base or
collector -emitter short;
or PNP/NPN revorsed
t_
Tha 1
-;,711-"-?---- AO, BC)7,=-`
' -a
, -0-. -
, I
Figure 4. Transistor testing chart, showing what
the various displays signify. This chart is
derived from figure 3.
i. Leak + low a'
AG-, Bo- 07- 1
O.
/I
- -,
/ I
Figure 5. Transistor (or diode) breakdown test
s cp, chart.
- = on _ =(appears to be)on
\/ Figure 6. The conduction test for diodes, in
= off = blinks the 'PNly test socket, is shown in figure 6A.
The leakage test for diodes is shown in
9076 3
figure 6B.
O = blinks dimly

Figure 7. Tests to test the tester.

tup-tun tester Book 75 - 023

4 DISPLAY MEANING
DISPLAY MEANING
LEDA LED B
LEDA LED B

_f()- Good transistor

.CD
._
- Conducts satisfactorily
/
,..fik a. PNP/NPN reversed b. Leak > 1 µA
Air
/ - .-- c. C -B short d. C -E short Not conducting, i.e. open circuit or
-IP III connections reversed

,\rik a. a' < 100

--A, III b. B -E short e
Key to display as for figure.4. b
c
TA
9076.6A

-:() C -B or C -E capacitance > 20p

b
\ ,\ DISPLAY MEANING
I....
.- .4 Leak > 10µA + very low a' + large Ccb
or Cce LEDA LED B

(11
0 -,4 Ccb or Cce 7.---, 20p
Blocks satisfactorily

a. Leaks severely
_ b. Shorted
- Cx - - - Leak > 10 µA + a' < 50
/ 1 k
c. Connections reversed
/ \
I

I \ I

Impossible. If this happens something - - - - Leaks

is wrong with the tester. Check the
power supply!
/ I

= On continuously = Blinks
Key to display as for figure 4 9076 - 68
TA

O= Blinks dimly = Off

9076-4
7 TEST APPLIED DISPLAY

5 DISPLAY MEANING
LEDA LED B

1. Nothing plugged into any test socket

LEDA LED B

4 .
-c
,._
2. Base and collector or emitter and collector sockets
shorted in TA or TB.
Good (Breakdown voltage > 20 V) I

\
3. PNP or NPN transistor known to be good, correctly . rik
plugged into TA or TB as applicable
.ck -:\1(14

-... . -
Fail (or connections reversed)
4. As previous test, but with a 22 p capacitor connected 0
from collector to base or emitter

NPN PNP
Tc
5. Emitter and base leads of a PNP or NPN transistor
known to be good connected to the collector and
emitter sockets of Tc or TD, whichever is appropriate,
i.e. reverse -diode check of breakdown voltage testing
section
-4
.,`

't
..1 i
'O' --
Diode
Key to display as for figure 4
Key to display as for figure 4. 9076-5 9076 7

part of each fast -oscillator cycle. emitter, this will flow through D10 and off. When the fast oscillator is turned
Summarising again: the display for high R29 to the negative rail even when 'X' is on and the display transistors are
capacitance is that LED `13' blinks on positive and both TA and T10 are sup- switched through `P' and 'Q', LED 13'
and off while LED 'A' remains off or posed to be cut off. This leakage current stays on but LED 'A' goes out (figure 3f).
blinks dimly. develops a voltage across the 10 MS2 re- So with a transistor having a leakage
sistor R29, and therefore raises the current of 1 µA or more, LED 'B' stays
potential at the base of T11, on and LED 'A' flashes.
Transistor with high leakage
A transistor with high leakage current It will be recalled that the emitter of T12 Transistor with base and collector
tends to behave, from the tester's point is held at half the supply voltage (i.e. at or emitter and collector short-
of view, as though it were turned on all about 10 volts) by the potentio-
the time. In all the cases examined so far, meter R30 and R31. So if the leakage circuited
no collector current flows in the transis- current is a little more than 1 µA, it will A transistor with one of these faults
tor under test while the fast oscillator build up a voltage sufficient to turn on `looks like' one with high leakage (only
is turned off. If, however, there is a T11 and T12 and thus light up LED `A' more so). A current can flow from the
leakage current between collector and and LED 'B' while the fast oscillator is positive rail through the emitter -base
024 - Book 75 tup-tun tester

8 PNP and NPN transistors

The foregoing descriptions apply to
PNP transistors. They also hold good,
mutatis mutandis, for NPN transistors
A O plugged into test socket TB, which ap-
C6 1000P pears on the right-hand side of figure 2b.
D14... D17
T 25V
The functions performed by T 10, T11
and T12 and associated components for
PNP transistors are performed by T13,
T14 and T15 and associated components
20...24V 100 mA
for NPN transistors. In this case, how-
--,pc 237
ever, the transistors T13 and T14 which
B pass on a voltage drop at the anode of
0 D1 1 are not a Darlington pair but a
complementary PNP-NPN-pair.
If a transistor is plugged into the wrong
C 10p
test socket (PNP into an NPN socket or
25V
vice versa), the base -to -collector path be-
D18=20...22V
0 comes equivalent to a forward -connected
diode, and the display is the same as for
a transistor with a base -collector short.
20...24V 100mA IC 1 The transistor will not be damaged, and
it is clearly a good thing, when one
C 0 shows up unexpectedly as 'faulty', to
check whether it has been plugged into
the wrong holes!
10p

Breakdown Voltage Test

The sockets for this test are Tc and TD,
0 shown in figure 2c. The effective break-
IC1=µ A 78M18HC
9076 8
down test voltage is about 20 V, and if a
breakdown current flows the voltage
at 'A' is pulled down continuously,
resulting in LED 'A' blinking and
junction and the base -collector short in Figure 8. Alternative power supply arrange- LED '13' staying on throughout the
TA (or directly through the emitter - ments, depending on the components one can cycle. For a transistor which passes this
collector short), through D10, and obtain.
test, LED 'A' blinks and LED '13' stays
through the 10 M&2 -resistor R29. It has off all the time (figure 5).
Figure 9. The p.c.b. and component layout
been shown that a leakage current as low for the TUP/TUN tester. Three alternative
as 1µA can turn on T11 and T12 and layouts are given, corresponding to the three
therefore make LED '13' light up and power supply arrangements. Diode Tests
LED 'A' go out while the fast oscillator By plugging the anode and cathode leads
is on. When the fast oscillator is off, of a diode into the emitter and collector
LED 'A' lights up and 'B' stays on. So the sockets of the PNP test points (or the
display with base and collector or emitter other way round with the NPN test
and collector short-circuited is that points) it can be tested for forward con-
LED '13' stays on all the time, and duction, leakage and breakdown voltage.
LED 'A' blinks on and off (figure 3h). When the fast oscillator is off, the
junction of the diode cathode and the
Transistor with base and emitter collector of T10 will be held positive
by the conduction of the diode, and if
short-circuited the conduction is good enough, this
When the base and emitter are short - junction will remain positive when T10
circuited, no 'normal' base current can is turned on (through 'Y') by the fast
flow, and therefore there is no collector oscillator. When T10 is turned off the
current. So the transistor 'looks like' one junction will still be positive. This leads
with zero a', and the LED display is the collector current (if any) in TA and pull to a display cycle in which LED 'A'
same: i.e. LED 'A' blinks and LED '13' down the potential of the commoned blinks and LED 'B' stays on continuous-
stays off (figure 3g). collectors, whereupon LED 'A' comes ly (figure 6).
on and LED 'B' goes off. This alternate When the diode is non -conducting, open -
Combined leak and low current lighting up of LED 'A' and LED 'B' is at circuited or connected the wrong way
the speed of the fast oscillator, and both round, the junction of T10 collector
gain or combined leak and base - LEDs stay on while the fast oscillator is and the cathode (or anode) will remain
emitter short turned off, so we have a display cycle negative throughout the oscillator cycle,
While the fast oscillator is off, the display in which both LEDs appear to be on giving a LED display in which 'A' blinks
isthe same as for a leaky transistor: continuously (figure 3i). and 'B' remains off. When a diode is
both LED 'A' and LED 'B' are on. deliberately connected the wrong way
When the fast oscillator is on and round, this display gives an indication
is turning TA and TIO off, the leakage cur- Other combinations of Faults (if the diode is a good one) that it is
rent holds the collectors of TA and TIO It would not be a very profitable blocking properly in the reverse direc-
high enough in potential to turn on Tll, exercise to list the LED displays with all tion. If a diode is short-circuited or is
resulting in LED 'A' being off and possible combinations of faults, but it leaking severely, it will give the same
LED 'B' being on. When the fast oscil- can be said that only a transistor which display, when plugged in the wrong way
lator turns TA and T I 0 on, the low is 'sound in wind and limb' according to round, as a good diode connected the
current gain of TA allows T 10 to 'over- all the test criteria will give the 'good correct way round. It is just possible,
come' both the leakage current and the transistor' display in both test sockets. however, that it is a good diode plugged
tup-tun tester Book 75 - 025

-41.4
t
17j
,"..
777T. *TTI.
f',,,1
DA

--f
4I -- - -FR72 -0

642_4 _1 -4,

_ 14
- \

Stabilised supply with discrete corn-

ponents
Tr = 20 V/100 mA C6= 10µ135 V
R41 = 1 k T16 = BC237B
C5 = 100 p/35 V D18 = 20 V Zener
Parts list
Resistors:
R1,R7,R24,R30,R31,R34 = 10 k
R2,R3,R6,R8 = 22 k
R4,R5 = 220 k
R9 (if used1,R16,R21 = 680 S2
R10,R11,R14,R15= 4k7
R12,R13,R32,R33 = 100 k
R17 = 2k7
R18,R19= 47 k
R22 = 1 k
R25,R40 = 270 k
R26 = 120 k
R27, R38 = 33 k
R28,R37,R20 = 470 E2
R29,R36 = 10 M
R23, R35 = 1 M
R39 = 120 k
R40 = 270 k

Capacitors:
C1,C2 = 4117
C3,C4 = 5n6

Semiconductors:
T1,T4,T8,T9,T15 = BC307B or equ.
T2,T3,T5,T6,T7,T10,T12,T13,T16 =
_ i --410

BC237B or equ.
T11 = BC239C or equ.
T14 = BC179C or equ. Unstabilised supply Stabilised supply with IC
D1 ... D17 = BAX13, BY126, BY127, Tr = 18 V/100 mA Tr = 20 V/100 mA
1 N4002, or other general-purpose C6 = 1000 µ/25 V C5= 100µ135 V
silicon diodes C6 = 10 p/35 V
2 x LEDs IC = µA78M18HC or equ.
026 - Book 75 tup-tun tester

the connections will be correct. This

facilitates the mounting of the board
flush under the top panel, without the
other components getting in the way.
ELEK TOR TU P/TUN TESTER As it is not possible to give meaningful
voltage or current test values for individ-
ual transistors, which might help to local-
ise mistakes or faults, the construction
1
NPN SS PNP 2
should be checked very carefully. Even
if one does not intend to use the optional
LED 'C', one of the LEDs which will
ultimately serve as 'A' or 'B' can be
`borrowed' at the constructional stage
,a ;4 GOOD TRANSISTOR to serve temporarily as 'C' and thus give
a check whether the slow oscillator (T2
-, ,, -
b. zrinP; k
c CB or CE -.
and T3) and also T4 is working. The
actual value of the 'nominally 680 S2 re-
a' < 100
1 --,
a
b BE - t sistor in series with 'C' is not critical. If
-. the temporary 'C' is seen to blink at
-4 CCB> 20 pF
CCE
about the right rate, test number 1 of
1

lc° > 10 µA, a' < 100

figure 7 will show whether T8 is also
- O --,a Ccb
{Cce > 20 pF
working. Test number 2 will show
whether T7, T9, T11 and T12 are work-
,
-0- -0'1 { c1°<>5010trA
ing if the short is put into test socket TA,
and T7, T9, T13 and T14 with the short
2(115)1 o in test socket TB.
o To check the complete PNP and NPN

ee,..
43
3
-CI

',
,/

--, ,-
Vcemax > 20 V

Voernax < 20 V
testing sections, including the breakdown
voltage test, one will need spare PNP
and NPN transistors known to be sound,
,

in addition to those used in building the

tester. Only a transistor with normal

:41
..
"
-11 ,:o 1-144 ?
current gain, or with a particular com-
bination of faults, can produce a display
in which LED '13' blinks.
Once the two good transistors have been
seen to give the display for test number 3
of figure 7, the more refined test num-
ber 4, which simulates the effect of
NPN
®4 PNP excessive capacitance, can be applied. A
22 pF capacitor should be enough to
EPS 9076-2 make LED 'A' black out altogether, but
it may be of interest to experiment with
different lower capacitor values to find
9076 10 what value of capacitor is just low enough
to allow the waveform at the junction
of TA and T10 to extend below the
Figure 10. Front panel design for the tester. fast oscillator and point 'A', which is critical level (about 10 V) and cause
This panel is available via the Elektor print common to the main testing circuits and LED 'A' to blink dimly, as shown in
service, with black lettering on an aluminium - to the breakdown voltage testing circuit. figure 3e2.
coloured background, as a self-adhesive label. The relationship between the potential The emitter -base junction of a transistor
at the anode of D10 and the potential forms a diode with a reverse breakdown
at 'A' when the main PNP testing section voltage of about 5 V, so one of the tran-
in the correct way round, i.e. that one is in use is that a high potential at the sistors used in the foregoing checks can
has mistakenly connected it this way anode of D10 produces a low potential also be used to check the breakdown
instead of reversing the connections. So at 'A' and vice versa. Figures 4, 5 and 6 voltage testing section (figure 7; num-
it is important to make tests in both summarise the meanings of the possible ber 5). One must make sure that it is
polarities if ambiguities are to be LED indications for various tests. Fig- connected the right (or is it the wrong?)
avoided. ure 4 is, of course, derived from figure 3. way round.
If a diode which leaks moderately is The front panel design (figure 10) sum-
plugged in the wrong way round, the marises all three figures. Power Supplies
leakage current may be enough to hold Three different possibilities are offered
the anode of D10 positive while T10 for a mains power supply unit (figure 8):
is turned off, but not while T10 is Construction and testing a simple unstabilised unit, a stabilised
turned on. This will give a display in Unless one has access to an independent unit with the stabilisation circuit built
which both LEDs appear to be on con- means of testing the transistors and up from three discrete components, or a
tinuously - the same as for a transistor diodes, these should be ones which carry stabilised unit using an IC. The unstabil-
which is both leaky and low in current the manufacturers' warranty. Resistors ised unit uses a transformer with an 18 V
gain. should have 5% tolerance. secondary - which may sometimes be
Figure 9 shows the p.c. board and the difficult to obtain - and a 1000 p capaci-
General component layout for the complete tor. If either of the stabilisation circuits
Figure 3 summarises the LED indications tester (with the exception of the mains is used, the capacitor can be much
when the fast oscillator is on or off, and transformer). It should be noted that smaller. The 20 V transformer used in
for different potentials at the anode of the emitter and collector connections to these circuits should be more readily
D10 in the main PNP testing section. the test sockets appear to be inter- obtainable.
The difference between this figure and changed, but when the sockets are The transistor or IC should have a heat -
table 1 is that the table is based on the mounted on the copper side of the board sink.
tv tennis Book 75 - 027

The popularity of television tennis

games has prompted Elektor to
produce a design that can easily be
built by the home constructor for
a modest cost. Although several

tw ten
designs have previously appeared

os
on the market, it was felt that
there was a need for a simple
circuit using a minimum of compo-
nents.

In order to keep costs down the TV

tennis circuit generates the most basic
`picture' possible, i.e. two 'bats' and a
`ball'. The ball is 'served' from one side
of the screen or the other and the
players move their bats up and down
the screen to intercept the path of the
ball. If the ball strikes a bat it is re-
FJ11131 turned, otherwise it leaves the side of
14(YIN
i!"1.31
Or 4. the screen and a 'new ball' must be
served. Should the ball reach the upper
or lower edge of the screen during its
traverse across the screen it will 're-
bound'. The upper and lower bound-
aries are, however, not displayed on the
screen.
The output of the TV tennis game is
used to modulate a VHF oscillator so
that the game may be plugged direct
into the aerial socket of a television.

Principle of operation
For those not familiar with TV a brief
resume of the principles involved may
prove helpful. A TV picture is, of course,
generated by an electron beam scanning
across the phosphor -coated face of a
cathode-ray tube in a zig-zag
fashion from top to bottom.
At the end of each horizontal
line the beam flies back to
the left hand edge of the
screen and starts the next line
slightly lower down the
screen. Each complete scan
(frame) of the picture con-
sists of either 405 or 625
lines, depending on the trans-
mission standard. To reduce
the bandwidth required to
transmit the video infor-
mation a complete frame is
not transmitted in a single
scanning of the picture, but is
made up of two 'fields' con-
taining half the number of
lines in a frame. These two
fields are interlaced with each
other to make up a complete
frame. Fields are transmitted
at a 50 Hz rate, therefore frames are
transmitted at half that rate,
i.e. 25 frames per second.
The video waveform
In order to build up a picture on the
screen the brightness of the trace must
be modulated by varying the electron
028 - Book 75 tv tennis

beam current. This is controlled by the also have a longer duration to dis- Block Diagram
amplitude of the video waveform. So tinguish them from line sync. pulses. The operation of the circuit is best
that the scanning of the electron beam From the foregoing some of the require- understood with the aid of a block
in the TV set is in synchronism with the ments for the circuit become apparent. diagram (figure 1). Sync. pulses from
received signal in order to build up the Firstly, the circuit must contain oscil- the field and line oscillators are mixed
picture correctly, field sync. pulses are lators capable of generating field and in the video mixer and then fed to the
transmitted (at the end of each field) sync. pulses at the appropriate fre- modulator. They are also used to con-
and line sync. pulses are transmitted quencies (50 Hz and 15625 Hz re- trol the timing of the other waveforms.
(at the end of each line). spectively). Secondly, circuitry for
To distinguish sync. pulses from video generating the bat and ball waveforms, All the video waveforms are generated
information, sync. pulses are negative - and for controlling the movement of using monostable multivibrators and as
going and confined to a voltage below these, is required. Fortunately, since we the generation of the 'bats' is simplest
that required for zero beam current are concerned only with white bats and this will be considered first. The left-
(black level). Video information oc- ball on a black background the only hand player's horizontal bat generator
cupies a range of voltages above black modulation required is peak white level 105 is triggered continuously from the
level up to the voltage required to or black level, so analogue circuitry is line sync oscillator. A presettable trigger
saturate the TV tube phosphor (peak not needed to produce these waveforms, delay is incorporated so that the pulse
white level). Circuitry in the TV dis- and digital logic circuits can be used to appears a little time after the line sync
tinguishes between sync. pulses and generate the rectangular pulses necess- pulse._ This ensures that the bat appears
video information. Field sync. pulses ary. some way in from the left hand edge of

video
mixer
CA
video output

field line
sync. sync.
IC9
oscil- oscil-
lator lator

horizontal

trigger IC1
delay

inte-
FF1
ball cip grator
ball
signal
delay I C2

preset vertical

horizontal

delay IC3

player
control
(right) right bat
bat
signal
delay IC4 (r)

preset vertical inte-

FF2
grator
horizontal
9029 -1

delay IC5

player
control
(left) left bat
bat
signal
delay IC6 (I)

vertical
tv tennis Book 75 - 029

the screen. The right-hand player's

horizontal generator IC3 incorporates a 2a
longer delay so that this bat appears line
sync. Qic3
near the right-hand edge of the screen.
Since the triggering occurs after every
line sync pulse the result would be a ver- Qicl
tical band of white the full height of the
screen. This is where the vertical bat gen-
erator (IC6 left, IC4 right) comes in. field
sync
_J Qic5
This monostable is triggered from the
field sync pulses via a delay which is
continuously variable by the player.
This determines the vertical position of
the bat. The delayed pulse from the ver-
tical bat generator gates the pulses from
the horizontal oscillator so that they are
only allowed through for the duration 0
of this pulse. The result is thus a verti-
cal bar on the screen whose vertical
position can be varied by the player and
P
Qic4 Qic2 Qics 9029-2a

2b 4v ball bat

black level 1.4v

711L3111M1TT Thuiiinilll immumu ITTIRMITUTITIT
line sync field sync
Ov pulses pulse
9029-2b

whose height (length of the bat) is Figure 1. Block diagram of TV Tennis game to travel to the right. If the ball does
determined by the duration of the ver- (excluding modulator/oscillator). not strike a bat it will leave the side of
tical pulse. The same applies for both the screen and will not return until it is
the left- and right-hand bats. Figure 2a. The horizontal and vertical wave- `served', since the state of the flip-flop is
forms are gated together as shown to produce
The ball is generated in a similar manner the bat and ball display. not changed and the integrator output
with two monostables (IC1 and IC2). will eventually saturate in one direction
However, since the ball is continuously Figure 2b. The complete video waveform as or another. Service will be dealt with in
moving this in effect means that for seen on an oscilloscope. the description of the full circuit.
movement to the right the horizontal
trigger delay is increasing all the time, Travel of the ball in the vertical direc-
and for movement to the left it is de- tion is controlled in a similar fashion,
creasing. but here the change of direction occurs
at the upper and lower boundaries. The
For downwards movement the vertical lower border of the picture corresponds
trigger delay is increasing, while for up- with the leading (negative -going) edge of
wards movement it is decreasing. Of the field sync pulse, so change of direc-
course it is necessary to reverse the tion at this boundary is accomplished
direction of ball travel when the ball by gating the ball signal with the field
strikes a bat or the upper and lower sync pulse in N5. To change ball direc-
boundaries. This part of the circuit tion at the top of the picture a
operates as follows: monostable (IC9) is triggered by the
trailing edge of the field sync pulse. The
the horizontal ball pulse generator output pulse of the monostable is gated
(IC1) is triggered via a delay by the line with the 'ball' signal to reset FF1. A
sync pulses. The delay, and therefore timing diagram showing how the various
the horizontal position of the ball on pulses are gated together to produce the
the screen, is controlled by the output bat and ball outputs is given in figure 2,
of an integrator, which is fed with a together with the general appearance of
d.c. voltage and therefore generates a the complete waveform as seen on an
ramp which varies the trigger delay oscilloscope.
linearly. The slope of the ramp (positive -
or negative -going) and hence the direc-
tion of ball travel is determined by Complete Circuit
the state of flip-flop FF2. If FF2 is The complete circuit is given in figure 3.
initially reset the ball will travel to the Field sync pulses are produced by the
right. However, should the 'ball' out- circuitry in box A, which consists of an
put and the right-hand tat' output astable multivibrator driving a
both be high at the same time (i.e. the monostable to produce pulses of the
ball strikes the right hand bat) then the correct length. Box B contains similar
output of N7 goes low, resetting FF2 circuitry, but operating at a much
and reversing the horizontal direction. higher frequency, to produce line sync
When the ball strikes the left-hand bat pulses. The Q outputs of these
then the output of N8 goes low, re- monostables (to produce the negative -
setting the flip-flop and causing the ball going sync pulses) are fed via D3 and D4
030 - Book 75 tv tennis

5V

_Air see text and figure 3A. R5.11

B
11 ND.
1- I 03
°"
-
"C ,C8
74121 74121
r7 0
NT NT,

L_
L_
012

846

1C1
T N
74121

uN

00
ball

IC1 ... IC9 = 9 x 74121

ICIO = N1 N4 = 1 x 7400
IC11 = N5 ... N8 = 1 x 7400 IC 2
IC12 = N9 ... N11 = %x 7402 /4121
IC13 = FF1, FF2 = 1 x 7474
IF UN
DOS

D1 ... D14= DUS ,1N41481 L

T1 ... T12 = TUN ,BC10881
T13 =AF 239

(7)
IC3
74121 at 1132

849
Of
DUS
-II UN

FF2
right
0 4k 7
T12
T R50

II
TUN

11_4
/4121 C32 I R51 R52

0 47y
DU, 7 UN
, o

/4121
0
UN

left
* 9029
TUN

L= 4 turns 1 mm Cu 0 8 mm

NJJ

- see text
r 7e
LS
O
IIIN

90292
tv tennis Book 75 - 031

Figure 3. The complete circuit of the TV

tennis game. The modulator/oscillator
circuit is shown inset at the bottom right-
hand corner.

Figure 3a. Suggested modification to derive

field sync pulses from the mains for mains
only versions of the game. This should give a
more stable picture than the free -running
field oscillator, so it is highly recommended
wherever possible.

Figure 4. Circuit of the mains power supply

for TV Tennis.

to the junction of R58 and R59. This plied via R21 from P7). However, since
Parts list for figures 3, 5 and 7
portion of the circuitry fuctions as the the voltage across C15 is still 3 V then
video mixer. Black level occurs when the base of T5 must be negative. T5
Resistors: the Q outputs of IC7 and IC8 are both therefore turns off. C15 now charges
R1,R2,R39,R43,R55 = 4k7 high and the bat and ball inputs to D11, via R22 until the voltage on the base of
R3,R4,R47 = 33 k D12 and D13 are all low. The voltage at T5 reaches about 0.7 V when T5 turns
R5*,R9 = 10 k NTC the junction of R58 and R59 is then on and the collector voltage goes low,
R6*,R10 = 820 s2 solely determined by the value of these triggering the monostable.
R7,R11 = 5k6 resistors and is about 1.35 V. When a It is evident that the trigger delay is
R8,R12 = 18 k sync pulse occurs then the junction of dependent on the time taken to charge
R13,R16,R17,R20,R21,R24,R25, these two resistors is held down to C15 after T5 has been turned off, which
R28,R29,R32,R33,R36,R56, about 1 V via D3 or D4. When bat or is in turn dependent upon the voltage
R59 = 10 k
R14,R18,R22,R26,R30,R34,R40,
ball signals occur the inputs to D11, applied to the cathode of D7 from P7.
R44,R57 = 100 k D12 or D13 go high, so the potential The trigger delay may thus be varied by
R15,R19,R23,R27,R31,R35,R53 = 2k2 at the junction of R58 and R59 a d.c. voltage, in the case of the bats
R37,R41,R48,R52 = 2k7 becomes about 4 V. derived from the various poten-
R38,R42 = 1052 If the unit is to be used for mains only tiometers, and in the case of the ball
R45 = 1 k8 operation the astable in box A can be from the emitters of T11 and T12.
R46,R49,R54 = 1 k dispensed with and field sync pulses In the case of the ball, as explained
R50 = 12 k may be derived from the 50 Hz mains
R51 = 47052
earlier, the trigger delay in both hori-
by the modification shown in figure 3a. zontal and vertical directions is continu-
R58 = 27 k
P1 *,P2 = 4k7 lin. preset
P1, R5, R6, C1 and C2 are omitted; the ously varied to achieve motion of the
P3,P6 = 47 k lin. sync pulses are fed in at the original ball. Horizontal movement of the ball is
P4,P5,P7,P8 = 100 k lin. preset connection to the positive side of Cl on controlled by FF2 and the integrator
the board, and the track between this constructed around T12. When FF2 is
Capacitors: point and the output of N2 (pin 6 of preset the Q output is high and C32
C1 *,C2* = 4/27, 10 V IC10) must be broken. charges via P9 and R50. The potential
C3 = 22 n The sync pulses are buffered by emitter on the emitter of T12 therefore rises.
C4,C8,C11,C14,C17,C20,C23,Cx =100 n followers T1 and T2 to avoid loading This is applied to R13, thus continu-
C5,C6 = 15 n
C7 = 390 p
the monostables excessively. The ously increasing the trigger delay and
C9,C15,C21 = 1n5 buffered sync pulses are then fed via the making the ball move to the right. When
C10,C16,C22 = 180 p trigger delays to the appropriate FF2 is cleared (reset) then C32 dis-
C12,C18,C24,C26,C27,C28,C29 = 470 n monostables which generate the hori- charges via P9 and R50. The voltage on
C13 = 68 n zontal and vertical components of the the emitter of T12 falls, thus decreasing
C19,C25,C30 = 220 n bat and ball waveforms. The (rigger the trigger delay and making the ball
C31,C32 = 47 10 V delay circuits are all identical in prin- move to the left. The rate of charge or
C33 = 3n3 ciple and merely vary in component discharge of C32, hence the speed of the
C34 = 1012/6.3 V values. The trigger delay for IC3 oper- ball, is determined by the setting of P9.
C35 = 3p3
C36 = 4 .. . 20 p trimmer
ates as follows: normally T5 is turned Vertical ball movement is controlled in
C37,C38 = 47 p
on by base current through R23. Its a similar manner by FF1 and T11. Note
collector voltage (and hence the A in- that in this circuit the AND -gates shown
Semiconductors: puts of IC3) is low. The cathode of D7 in the block diagram have been replaced
T1 ... T12 = BC547B, BC107, 2N3904 is held at a few volts positive by the by NOR -gates connected to the Q out-
T13 = AF239 voltage via R21 from P7 (max. 2.5 V), puts of the monostables. This is of
D1 ... D14 = 1N4148 and since T2 is turned off the anode of course exactly equivalent to AND -gates
1C1 ... IC9 = 74121 D7 is at 0 V. C15 thus has a voltage connected to the Q outputs (De
IC10,1C11 = 7400 across it equal to the voltage on the Morgan's theorem).
IC12 = 7402 cathode of D7 minus the base -emitter The horizontal bat trigger delays are
IC13 = 7474 voltage of T5. On the leading edge of preset,by P7 for the right-hand player,
the line sync pulse T2 turns on, forward and by P4 for the left-hand player. This
Sundries:
L = 4 wdg. 1 mm cp Cu, cp 8 mm
biassing D7. C15 thus charges until the allows the position of the bats to be
HF Tr = 60 E2 + 240 ft impedance
voltage across it is adjusted to a few cm away from the
converter (see text) 5 V - VbeT2 - VD7 - VbeT5 = 3 V sides of the screen. The vertical position
approximately. On the trailing edge of of the bats is continuously adjustable,
* see text the sync pulse T2 turns off. The voltage by P6 for the right-hand player and P3
on the cathode of D7 therefore reverts for the left-hand player. P5 and P8 are
to its initial value (the potential sup- presets used to adjust the bat position
032 - Book 75 tv tennis

Figure 5. Printed circuit board and com-

ponent layout for the modulator/oscillator
circuit.
Figure 6. Printed circuit for the TV Tennis
game.

Figure 7. Component layout for the main

board. Note that the indications T3 and T4
are transposed!

so that P6 and P3 are effective over the

full height of the screen.

Service of the ball

It is evident that if the state of FF2 is
not reversed by a coincidence between
the ball and one of the bat signals then
the voltage at the emitter of T12 will
continue to rise or fall as C32 either
charges or discharges, until it reaches
either zero volts or supply minus the
base -emitter voltage of T12. The ball
will then disappear off one side of the
screen or the other and will not return.
For this reason (as well as for the rules
of the game) it is necessary to 'serve' the
ball when this has occurred.
Ideally the ball should emanate from
the bat of the player who is serving.
However, in practice this is difficult to
achieve as it means that at the instant possible to make the ball service depen- 4 -pole switch Si is closed. This
of service the vertical ball trigger delay dent upon the bat position at the time produces several results. Firstly points X
must be matched to the vertical bat of service, though not coincident with and Z are connected to ground via R38.
trigger delay. Since the delay circuits are it. This clears FF1 and presets FF2 so that
independent component tolerances will Service is accomplished as follows: when the ball is served it will travel up-
make this unlikely. It is, however, for a service by the left-hand player the wards and to the right.
tv tennis Book 75 - 033

so the ball travels in direction

7 determined by the states of FF1 and
a

FF2 (i.e. up and to the right).

rin Service by the right-hand player oper-
ates, so to speak the same way but
backwards, i.e. pushing S2 grounds
point X so that the ball still travels up-
wards. However, point Y is grounded so
that the ball travels to the left, and
point U is grounded to discharge C32 so
that it starts from the right. The verti-
cal starting position is determined by
the emitter potential of T10.
Modulator and oscillator
The only part of the circuit which
remains to be described is the modu-
lator/oscillator which converts the video
output at point A into a VHF signal suit-
able for feeding direct into a television
aerial socket. This part of the circuit is
[I 10--f R shown inset in figure 3. An AF239
forms the basis of the oscillator circuit
which is tuned to the required fre-
quency by the coil L and C36/C37. The
output may be fed direct into an unbal-
anced 50 - 75 1-2 coaxial cable termin-
ating in a normal TV coax plug, or if the
TV has continental type 240 - 300
twin feeder input then the output must
4110-1 fl 58 1,--40
be fed through an inverse balun trans-
--{R kill former before feeding into the 300 52
41-1 r.17.
-{ mse feeder.
40_4 A* 1-1,
:t Power Supply
A power supply which is absolutely free
from mains ripple is absolutely essential
for the TV Tennis game. The reason
for this is fairly obvious. Any mains
ripple will cause a variation in the input
--f F4 4 5 1--- .1F, voltages to the trigger delay circuits, and
hence in the trigger delays. This pro-
duces distortion of the picture as the
trigger delay varies down the screen
height.
------ - -
The 5 V power supply shown in figure 4
is strongly recommended. It uses an
L129. However an LM309 can be used
and is recommended when the

e .
*41
additional TV tennis circuits are going
to be added. This power supply is short-
circuit protected. If another supply is to
be used it must also be short-circuit
. proof, since when both 'serve' bottons
00 are pressed simultaneously R42 and
--{ R..
zo -40.--"4 .46 1----
7 R38 are connected across the supply -
SO o * the current consumption then becomes
"-{ A 501 -4a -H,14 1 more than 1 A.
T It has been found that some fixed volt-
[117,-* ---1[1
age stabilisers actually supply approxi-
---{ R52 R48 mately 4.8 volts. The consequence may
be that practically the entire field
1111-....-1 R41 1---41
remains white. The circuit of figure 4A
shows how this can be remedied by
0-4 R raising the voltage.

4a
L129
7805
Point U (R51) is connected to positive bat control). The voltage on C31 is thus LM309k
5,5 V
supply, thus charging C32 rapidly and constrained to slightly above the emitter
holding the ball off the left-hand side of voltage of T9, thus determining the ver- 1N4002
the screen. Point T (cathode of D14) is tical position from which the ball will 9029-4a
connected to the emitter of T9, whose start. When the switch is released the
base is fed via R39 from P3 (left-hand constraints on C31 and C32 are released
034 - Book 75 tv tennis

To minimise power dissipation within Figure 7A. Shows where to connect the line
the IC it is recommended that a trans- sync pulses from the power supply board.
former with a 6.3 V RMS secondary volt-
age be used. This will give a DC input to Figure 8. Printed circuit board and com-
Parts list for figures 4 and 8 ponent layout for the power supply.
the IC of about 9 V. The bridge rectifier
is made up of 4 1 -amp diodes such as Resistors.
1N4001. Note that C3 should be a R1 ,R2 = 470 SZ
tantalum type to reduce output noise
and any tendency to R.F. instability. Capacitors:
Components D1, D2, RI and R2 C1 = 2200 /2/16 V
correspond with figure 3a. C2,C4 = 100 n
C3 = 10 ,u/6 V (tantalum)

Construction and adjustment Semiconductors:

D1 = DUS
The p.c. board and component layout D2 = 4.7 V zener
for the VHF oscillator are given in B = Bridge rectifier, or 4 x 1 N4001
figure 5, for the main board in figures 6 IC1 = L129, LM309 (5 V/1 A)
and 7, and for the power supply in
figure 8. Note that there are several Sundries:
indications on the main board that Transformer, 6.3 V (r.m.s.)
concern future extensions. At this stage secondary
these can be disregarded; the wire links
shown dotted are all needed for the
basic game.
Slider potentiometers are used for the
bat controls as these give easier control
than rotary types and are sufficiently
robust for domestic use. The oscillator
is mounted on a separate board as it
must be housed in a completely
screened box to avoid radiated inter-
ference and to minimise pickup of other
transmissions. A small diecast or pressed
aluminium box with a lid is suitable.
The main board housing should also be
a metal box. Having checked that the
circuit is correct and that the power
supply is giving the correct voltage
before connecting it to the unit, power
can then be applied and the output of
the VHF oscillator plugged into a TV
set. Due to the harmonics generated
extending into the hundreds of MHz
the unit will function on both VHF and
UHF although we do not advise using
the circuit on 405 lines VHF, as this
calls for extensive modifications to the
line sync and horizontal bat and ball
position circuits.

Alignment, step 1:
Initially all the potentiometers should
be set at the middle of their travel. If an
oscilloscope is available the waveform
at point A can be checked, if not, then
proceed as follows. For UHF operation
the TV set should be tuned to the low
end of the UHF band. By adjusting the
TV tuning and C36 it should be possible
to tune in the signal. At first the picture
will be rather chaotic as the field and
line sync oscillators are not running at
the correct frequency.

Alignment, step 2:
By adjusting P I it should be possible to
obtain vertical lock, i.e. the picture will
stop 'rolling'. Of course with mains field
sync there is no adjustment and if lock
is not obtained it will be necessary to
adjust the frame hold control on the
TV set. It may be found that, due to the
tolerances of C I and C2 it is not poss-
ible to obtain the correct field sync
frequency. The oscillator may run at
25 Hz, in which case the picture will
tv tennis brake lights for model cars Book 75 - 035

lock but will jitter considerably. In this positive supply rail. For this reason it R. Zimmer
case Cl and C2 should be reduced to is advisable to run completely separ-
2p2. It may be found that a black bar ate wires from the supply electrolytic
appears in the centre of the screen. This (in the power supply shown in
is because the field sync oscillator is figure 4, this is C3) to each of these
running at 100 Hz, and P1 should be ICs. The simplest way to do this is
adjusted until normal lock is obtained. to unsolder the positive supply pins
Having obtained vertical lock the (pin 14, in each case), bend the pins
picture will probably consist of a up from the board and solder the
random pattern of white dashes.
Alignment, step 3.
P2 can now be adjusted until the two
wires on to them in mid-air. The
positive supply ends of the de -
coupling capacitors (C8, Cx and Cx)
are also unsoldered from the board
brake
bats appear on the screen. If the line
sync oscillator is tuned to a multiple
of the line frequency then four bats
may appear.
and connected via 1 S2 resistors to
pin 14 of the corresponding ICs.
the negative supply to IC10 (pin 7)
could also do with some additional
lights
Alignment, step 4.
Having obtained the correct number of
decoupling. A 100 pH micro -choke
in series with this connection is
sufficient. The easiest way to mount
this is to unsolder all seven pins on
for
bats the horizontal positions of the left -
and right-hand bats may be adjusted by
P4 and P7 respectively.
that side of the IC and bend it up so
that these pins are in mid-air (pins 1
to 6 are no longer used after the
model
mains sync has been incorporated).
The choke is then mounted between
the original hole for pin 7 and pin 7
itself.
cars
if the frame sync is derived from the
mains as recommended, there is a
wire link in the connection between
pins 1 and 2 of IC10 and pin 5 of
IC7 (figures 3A and 7A). If a 2.2 mH
choke is used in place of this link,
some further improvement of picture This circuit performs two functions.
quality can result. when the supply voltage to the motor
of the model car cuts out, the car will not
in some cases, the ball signals inter- stop abruptly but will continue over some
Alignment, step 5: fere with the other signals - causing time two LED's
The final adjustment is to the range of a dent in the vertical boundaries that will light up and function as brake lights.
the vertical bat controls. With the moves up and down with the ball, for Thus a very realistic effect is obtained.
slider controls set to the centre of instance. To prevent this, two 1 kS2 The circuit is extremely simple. As long
their travel P5 and P8 are adjusted so resistors can be added in series with as the car is under power, there is a
that the bats are halfway down the the inputs of N9 (pins 2 and 3 of voltage across the motor (M), the polarity
screen. It should now be possible to IC12). On the board, these resistors of which is indicated in the diagram.
traverse the bats over the entire screen can be mounted in place of the Capacitor C1 and (via diode D) also C2
height, and some further slight read- original wire links between pin 2 of
IC12 and pin 1 of IC2 and between are now charged.
justment of P5 and P8 may be necess- When the voltage cuts out, C1 discharges
ary to achieve this. pin 3 of IC12 and pin of IC1 re-
1

spectively.
The unit is now ready for use and it - sometimes a minor improvement of
should be possible to serve a ball from the picture can be obtained by
either side of the screen by pressing adding small resistors (1 . .. 2.2 SZ)
the appropriate service button. Due to in series with the decoupling capaci-
the simple nature of the circuit it may tors C4, C8, C11, C14, C17, C20,
be found that pressing the service C23 and Cx. The improvement de-
button causes slight picture jitter, but pends on how `lossy' the capacitors
this should not prove inconvenient in were in the first place.
practice. The next item to receive attention is the
ball speed. With the existing circuit it is
Trouble -shooting impossible to obtain exactly the same
Some readers have encountered prob- ball speed in both directions. This is not
lems involving vertical distortion of the so important in the vertical direction,
picture. This can be caused by poorly but different ball speeds in the horizon-
adjusted horizontal synchronisation, so tal direction give one player an unfair across M and C2 discharges via the two
a word of advice will not be out of advantage. Adjustment to equalize ball LED's, resistor R, and motor M. If
place: first of all re -read the adjustment speeds in the left -right, right -left, and braking is the result of a short-circuit of
instructions given. up -down, down -up directions may be the supply voltage, both capacitors dis-
Carefully check all wiring and other provided by a 4k7 preset in series with charge via the short-circuit connection;
connections, then set all pre-set poten- R46, and a similar one in series with in that case the LED's burn somewhat
tiometers to mid position and carry out R49. brighter. The value of resistor R can be
the alignment procedure as described. One other thing: calculated with the following simple
If this does not cure the problem, some To cope with the additional load formula:
further 'brute force' expedients are imposed by future extension circuits, 12 - 2. VLED
required: the output capability of the emitter R
- the three ICs in the synchronisation follower buffers T 1 and T2 can be I LED
circuits (IC7, IC8 and IC10) are sen- improved by changing the values of R1 Usually a value of about 560 12 will be
sitive to interference pulses on the and R2 to 1 k and R3 and R4 to 3k3. suitable.
036 - Book 75 supplies for cars

supplies for
cars In order to function effectively, electronic equipment used in cars must
have an appropriate power supply, which in addition to providing a
regulated voltage from the battery supply, must also suppress inter-
ference appearing on the battery voltage from the car electrical systems.

Two power supplies will be described; will then not provide stabilization of current through this zener diode.T4 is a
a simple zener stabilizer with built-in the supply voltage, but only interference constant -current load for the collector
suppression, for low -power circuits such suppression. This would be quite ad- of T6, which drives the Darlington -
as instruments (electronic tachometer equate for COSMOS IC's, which are connected transistors T8 and T9. Current
etc.) up to about 170 mA and a high - fairly tolerant of supply voltage vari- limiting is provided by T1 and T2. When
power stabilized supply, for powering ations. the current through R4 is such that the
such things as portable cassette re- The difference between battery voltage voltage drop across it exceeds the base -
corders, up to about 2 A. and output voltage is dropped across R 1. emitter voltage of T1, this transistor
In the example given, for a 6 V battery turns on, which turns on T2, pulling
Low -power circuit R1 would be 8.2 ohm % W, and for a down the collector of T6 and reducing
Figures 1 and 2 show the low -power 12 V battery 47 ohm 2 W. the drive to T8. The maximum output
circuit configuration for negative- and C2 should be a low -inductance type current required determines the value
positive -earth cars respectively. L I and such as ceramic and DI can be any diode of R4:
D1 provide high -frequency decoupling. that will carry 200 mA. 0.5
LI may be wound on a wire -ended R4 - (E2)
cylindrical ferrite core, with a diameter High -Power Circuit 'max
of about 10 mm, using 45 turns of This circuit (figure 3) is designed to
0.5 mm enamelled copper wire provide a stable, interference -free supply L1 is wound from 45 turns of 1.0 mm
(25 SWG). Zener diode Z1 stabilizes the for cassette recorders, audio amplifiers copper wire (19 SWG) on a ferrite core
output voltage at 5.6 V, which is suit- and other equipment. Car radios gener- and thus provides interference sup-
able for TTL circuitry, but 5.1 V or ally have their own inbuilt suppression pression due to its high inductance. P I
4.7 V types would also do, as they are circuits. will adjust the output between about
within the supply voltage limits for TTL. The circuit is a simple feedback stabil- 5.6 V and 12 V, although the higher
Other voltages may, of course, be used izer. T5 and T6 form a differential figure can only be obtained when the
for different equipment. amplifier with a constant -current (12 V) car battery is fully charged and in
If a supply voltage is required that is emitter load (T7). This compares a good condition, so that the supply
almost equal to the available battery portion of the output voltage at the voltage is around 14 V, since some
voltage, then R1 and the zener diode slider of P1 with a reference voltage voltage must be dropped across the series
may be omitted. Of course, the circuit provided by D6. T3 provides a constant regulator transistor and R4.
A printed circuit layout for this supply
is given in figure 4. The connections
battery + stabilized
shown encircled in figure 3 are shown
Li D1
on the board layout. The circuit of
6...12V 0. 5.6V figure 3 is for use with negative earth
1N4001
core 10 mm Z1
C2
cars, but may be modified for positive
45 turns 1

earth simply by reversing all diodes and

0.5 mm
5,6V
1W
000µ
16V
0.111
electrolytic capacitors and replacing
transistors by their complementary
* see text 1587-1 equivalents.
If higher output currents are required,
an external transistor (e.g. MJ3055) can
be added. The connections to this tran-
sistor (T10) are shown dotted in figure 4;
battery - stabilized it should be mounted on an adequate
6.. 14 Li

1N4001
5.6V heatsink, with mica washers for isolation.
If this transistor is not required, the
core 10 mm 0 Z1
C2 connections 5 and 6 on the pcb must be
45 turns
0.5mm0 5.6V 1000µ 0.1µ
bridged.
1W
16V To avoid deterioration of the board in
the car due to humidity and dirt it is
* see text 1587-2 best to encapsulate the circuit (once it
has been tested) in epoxy resin or
silicone rubber.
supplies for cars Book 75 - 037

3
battery + 0
00
R4
L

0 0.2210

core 10 mm
45 turns D2
1.0 mm R2 R
0 D3
TUP

T3 4
DI

TUP TUP
BY126
C5
T
TO (56 12V 2A)
PI 10k47"
Itn
R
D6
2x
5.6V
250 TUN
mW 47n

TUN

TUN D4
C2 Cl
RIO
- J C3
25V
woo l./
25 V
D5
D2 D5=1N4148 0
0 47iTOOOP T 1587-4 0
battery -

Parts list for figures 3 and 4:

Resistors:
R1 = 1 k
R 2 = 470 1-2
R4 = 0.22 S2*
R5 = 27 k
R6 = 68 S2
R7 = 180 1-2
R8,R11 =100 S2
R9 = 2k7
R10 = 15 k
P1 = 10 k, preset

Capacitors:
Cl ,C3 = 1000 4/25 V
C2,C4,C5 = 47 n

Semiconductors:
T1,T3,T4 = TUP
T2,T5,T6,T7 = TUN
T8 = BC107 or equ.
T9 = BD 131 or equ.
(T10 = MJ3055 or equ.*
D1 = BY 126
D2 ... D5 = 1N4148
D6 = 5.6 V/250 mW zener

Coil:
L1 = 45 turns of 1.0 mm enamelled
copper wire on 10 mm ferrite
former.

* see text

Figures 1 and 2. Simple zener stabilized

supply with high -frequency suppression. Fig-
ure 1 is for negative earth and 2 is for positive
earth.

Figure 3. A high -power regulated supply for

car electronics. The output voltage may be
adjusted from 5.6 V to 12 V and the circuit
will supply 2 A continuously.

Figure 4. P.c. board and component layout

for the circuit of figure 3.
038 - Book 75 clamant clock

Any horologist who keeps a digital The main attribute lacking in a digital clock is produced by the balance wheel
clock in the same room as conven- clock is the comforting tick which as- (or pendulum) and escapement, the tick
sures us that the thing is actually going. and tock sounds having different pitch.
tional clocks cannot but feel sad How many man-hours have been wasted The pitch of the sounds and the rep-
to see it sitting there, mute and waiting for the elusive change of that etition frequency obviously depend on
reproachful amongst its more last digit? 'Well I'm sure its been stuck the physical construction of the clock.
vociferous brothers, its only sound at that time for more than a minute A grandfather clock will have a deeper,
the feeble humming of the mains now.' more leisurely tick than a travelling
A clock with a seconds display or flash- alarm.
transformer. In this article we Electronic simulation of the sound is
ing colon alleviates these problems, but
look at various ways of providing the hypnotic effect of such devices fortunately relatively simple. The
the digital clock with a voice, so has been known to send people to sleep. waveform of the ticking is a damped res-
that it can draw our attention to No such problem exists with a tick,
the fact that it is keeping time far which informs us that the clock is work-
ing without actually looking at it. Figure 1. Gyrator circuit to simulate tick-tock
more accurately than any mere of a clock.
mechanical clock.
The tick-tock circuit Figure 2. P.C. board and component layout
(These units can be added to the The tick-tock sound of a conventional for gyrator circuit.
versatile digital clock described
elsewhere in this book)
Di 6V

R1 R4 R6 R9
I4 0
DUS
9
T1 T2

C6
TUN
UP R7
R2
9 T6 I 1-40
100n
C2
T3
TUN

TUN
C3

oocp)
1n8
T5 R11
C4

6n8
O
C5

10011
10V
R3 R5 R8 ci TUN R10
=is D2
(1,
4n7
DUS
4015 1
clamant clock Book 75 - 039

onance similar to a percussion instru-

ment. A suitable circuit is therefore the
gyrator used in the Elektor Minidrum
2
(february 1975). This circuit (with the
component values modified for this
application) is given in figure 1. Suitable
1 Hz trigger pulses may be obtained
from the clock circuit by taking an out-
put from the counter preceding, the
!jhrill I II IL 8441t6.
seconds counter (either side of S3 in
the versatile digital clock). The pulses
must be TTL compatible (5 V ampli-
tude) and have a 1 mark -space ratio,

4: Itie
1 :

otherwise the ticking will

unbalanced. The pulses are fed into the
base of T3 through C3 to trigger the
sound
qmil ILgT&D4
gyrator, whilst T5 switches C2 in and
out of circuit to alter the relative
frequency of the tick and tock. - 1
_J
r
Components list for figure 1 r GYRATOR
Resistors:
C6 C4
R1 R9,R11 = 6k8 mem
awe
R1

R10 = 1k5
R9

Capacitors: flt

C1 =4n7
C2 = 1n8
C3 = 1 n
C4 = 6n8
C5 = 100 pt/10 V R5

C6 = 100 n 02

"IIIIL
C5

Semiconductors:
T1,T3,T5,T6 = TUN
cG Ia J

T2,T4 = TUP ,68, I

D1,D2 = DUS
040 - Book 75 clamant clock

The frequency of the sounds may be

adjusted to suit personal taste by exper-
imenting with the values of Cl, C2 and
C4. Since C3 and the input impedance
of the trigger input differentiate the
trigger pulse, changing the value of C3
will affect the 'crispness' of the sound.

P.C. Board
A suitable printed circuit board already
exists for the Minidrum gyrator, and the
board and component layout (modified
for use with clock) are given in figure 2.

Alarm Clock
One clock noise in popular demand by
readers (though perhaps not first thing
in the morning) is an alarm. It is a
simple matter to add an alarm to a digi-
tal clock (but unfortunately not so
simple if the display is multiplexed).
The alarm control circuit given in figure
4 minute -counter units of hours tens of hours 4 is suitable for TTL clocks with parallel
outputs (i.e. where the BCD outputs of
the hours and minutes counters are
fTl r1 r available continuously and are not
Rscn 89121 Roil) R012) R9(1) 8912) ROW R0(2) clear IC 3 clear strobed). It was felt that an alarm set-
7490
IC3
AIN 7490
IC 2
1/2 7473 clock 1/2 7473 ting accuracy of one minute was not
:6 :10 :2 :2 necessary, so the smallest step provided
A BCD ABCD T, FF1 FF 2
in this circuit is 10 minutes.
_
The circuit operates as follows:
the portion of the circuit inside the
dotted box is the alarm. The rest is the
existing clock circuitry. The BCD out-
puts of the hours and tens of minutes
counters are decoded to decimal by the
7442's. No decoding of the tens of
hours is required as the truth table for
this counter (table 1) shows. Outputs A
and B are never both '1' at the same
time. The desired alarm time is selected
_ _ _ _ _ _ _ 0-0-0 by single -pole switches S1 - S3. When
1 the required time is reached three of the
A B C D A B C
0 610020 inputs of the four -input NAND gate go
7442 7442
3300
S3
high. This allows the alarm signal con-
nected to the fourth input to pass
2 3 4 5 6 89
2 3 4 5 1

through the gate.

The possibilities for the actual alarm sig-
0 nal generator are endless. The simplest
solution would be a fixed frequency os-
S2
S1
cillator such as an astable multivibrator.
There are however more interesting
possibilities. The voltage -controlled
multivibrator of figure 5 can be made to
play a tune by connecting differing
alarm signal voltages sequentially to the control in-
alarm system
generator put. For a control voltage range of
2-5 V the frequency range covered is
4015 4 about 3 octaves. There are various
methods of driving the oscillator. A
simple circuit is shown in figure 6. This
consists of a 7490 connected as a BCD
decade counter, with its outputs con-
nected to the VCO via presets. As the

Table I

HOURS A A B 8
0 0 1 0 1

10 1 0 0 1

20 0 1 1 0
clamant clock Book 75 - 041

Figure 3. Photograph of the completed board

that makes the tick-tock sound. 8 1Hz T
0 1 1

Figure 4. Circuit of an alarm control system. R9111 89121

O 48011) 8012)

Figure 5. A voltage -controlled oscillator VCO 7490

that may be used to generate a tuneful alarm 8D1N

signal. A

Figure 6. Using the existing seconds counter r- -

in the clock to produce a varying voltage for
1

15/6
the VCO. Since the outputs interact it is diffi-
7404
cult to tune this circuit to play a particular
melody.

Figure 7. This circuit may be used to make

the VCO play a tune. Ten independent
sequential outputs are produced, so each pre- --1
set can be used to tune one note in the se- I

quence.

7400
Figure 8. Extension of the circuit of figure 7 L7400
to a 20 -note sequence.

Table I. Output of an arbitrary tens of hours

counter as in figure 4. 7442 B 7442 A

0 1 2 3 4 5 6 7 8

I I 1 I
1 3, 5, 91 111 131 151 17, 9 41 6 81 101 14 16, 18 5V
DUS.... DUS

47k 47k 47k 4

n

1 1 1 1 1 1 1 1 1 1 1 1 1. 1 1 OVc
4015 8

output states of the counter change so means that each note in the sequence equal time span is required for each
will the output voltage to the VCO. Of can be tuned independently. note then the clock pulse waveform
course the outputs change in a binary This ten -note sequence can easily be ex- must have a 1 : 1 mark -space ratio. The
sequence so more than one output can tended to twenty notes by the circuit of 7490 in all these cases can be the
be high at one time. figure 8. In this circuit two decoders are existing seconds counter (IC6) in the
Since the outputs interact it is difficult driven by the 7490 and are switched in clock.
to set this circuit to play a particular and out by the 1 Hz clock pulses to the Another variation on the alarm theme
tune. In addition the 1 Hz clock pulses counter. Thus, during the half -period can be obtained by a circuit which
are also fed in via R2 increasing the per- when the clock pulse is '0' the outputs changes the rhythm of the tone se-
mutations still further. of the 7490 are switched through the quence, making it less monotonous.
If one requires a circuit which can be set transfer gates (7400) to decoder A. The Such a circuit is given in figure 9. The
to play a particular tune then figure 7 is other transfer gates are disabled by the dividers I to III are again part of the
more suitable. Here the outputs of the `0' on their commoned inputs, so their existing clock circuit (IC9, IC6 and IC5).
7490 are decoded with a 7442 to give outputs are all '1'. This is an invalid in- The operation of the circuit is as fol-
ten independent outputs. These outputs put code for the 7442 so all its outputs lows:
go low in sequence as the counter goes are high. During the '1' half period of counter II controls the pitch of the volt-
through its cycle. All other outputs are the clock pulse the reverse situation age controlled multivibrator as in the
high, reverse -biassing their respective occurs. Decoder B is enabled,whilst A is circuit of figure 6, except that no ad-
diodes, so no current flows through disabled. Decoder A thus controls the justment is provided for. The time at
their respective presets. Only the preset even notes 0, 2, 4, in the sequence, . . . which the alarm sounds is again deter-
connected to the output which is low whilst decoder B controls the odd notes mined by the alarm control circuit, as
forms a potential divider with R 1. This 1, 3, 5, . . Of course in this case, if an
. . in figure 4. The rhythm variation is
042 - Book 75 clamant clock

9
Ii
R0(1) R0(2)
I
8911) R9(2) 1Hz
Rom) 8012) 8911) 89121 01Hz 911) 8912) ROM) 8012)
AIN AIN
7490 7490 7490
10Hz I :10 II :6
0 Boos
:10
BD N BD N
B2 C2 D2 A2 A3 133 C3 D3 A4 4 C4

11 minutes
O

5V
18k TT 74 00

N2

N5 D 0

alarm control
signal
circuit
generator
as figure 4
N4
40 5 9

provided by gating the C output of Figure 9. Circuit for generating an alarm sig- minutes counter are thus at '0', so T2 to
counter I with the A output of counter nal with variable pitch and rhythm. T4 are turned off. The alarm tone is
III, and the B output of counter I with applied to the base of T 1 via R1 and
the B output of counter III. This has the Figure 10. Timing diagram for the circuit of switches this transistor on and off
figure 9, showing the tone sequences for the
following effects. Starting at a point in four possible states of A4 and B4.
causing a signal from the loudspeaker.
the timing cycle where counter III has Since there is a 390 12 resistor (R2) in
just reset, A4 and B4 are both '0'. The series with it the tone is not very loud.
Figure 11. Circuit to gradually increase the
outputs of Ni and N2 are thus high so volume of the alarm signal if the sleeper does
After 1 minute the A output of the
(assuming it is time for the alarm to go not awaken immediately. counter goes to '1', switching on T2 and
off and the outputs of N3 and N4 are thus connecting R3 in parallel with R2.
high) the tone sequence controlled by Figure 12. A complete alarm circuit incorpor- The tone thus becomes louder. After
counter III can pass through N5. After ating the ideas of the previous circuits. 2 minutes output B becomes '1' while A
10 seconds output A4 goes high and the becomes '0'. R4, which is smaller than
pulses from output C2 switch the out- R3, is paralleled with R2, so the tone
put of N2 between '0' and '1'. The tone becomes louder still. After 3 minutes
from the output of N5 is thus switched outputs A and B are '1', and after
on and off at a 2.5 Hz rate. After 20 4 minutes output C becomes '1', by
seconds output B4 goes to '1' whilst which time the tone is quite loud.
output A4 goes to '0'. The output of Output D is not connected to this sys-
N2 is thus high whilst via Ni output tem. If the sleeper has not awoken after
B2 switches the tone on and off at a 8 minutes output D will become '1' and
5 Hz rate. After 30 seconds output
can be connected to set off a small
A4 again goes to '1' while B4 remains explosive charge underneath the bed. A
at '1'. Outputs B2 and C2 therefore of counter I. This means that the 7490 less drastic cure for the deep sleeper is
both affect the tone output. When (which consists of a divide -by -2 and a to connect an additional transistor to
either of these outputs is high the tone output D with a 56 fl resistor in series
divide -by -five counter in the same with its emitter.
is off, and when both of them are low package) must be connected with the
the tone is on. The complete circuit of an alarm system
divide -by -2 after the divide -by -5, as is given in figure 12. Everything within
A timing diagram for these events is shown in figure 9. If an existing clock the dotted box is the alarm circuit,
,shown in figure 10. The top two wave- circuit is used this counter may be whilst everything outside is the existing
forms are the outputs B2 and C2 during connected as a BCD decade counter clock circuitry. This differs slightly
a 1 second interval of the sequence (this (i.e. with the divide -by -5 after the from the circuits discussed in that a
repeats every second). The other 4 divide -by -2). Some slight modification HEX -inverter replaces the five -input
waveforms are the tone outputs that may therefore be necessary. NAND -gate in the alarm control circuit.
occur for the four possible states of A4 This has open -collector outputs, so the
and B4. Volume Control outputs may be joined to perform a
The audible effect is thus as follows: In order not to awaken the sleeper too wired -OR function. In this circuit the
an uninterrupted tone sequence for 10 harshly it is a simple matter to arrange a additional transistor T9 is shown con-
seconds, then a further 10 second in- volume control so that the alarm tone nected to output D5 for the extra loud
terval of tone bursts and silence as in starts at a low level and gradually be- alarm signal. A suitable printed circuit
figure 10d, then 10 seconds as figure comes louder and louder until it is board and component layout for this
10e and finally 10 seconds as in figure switched off. This is achieved by the alarm are given in figure 13.
10f, after which the sequence repeats. circuit of figure 11. The counter shown The IC numbers shown in brackets in
Of course, during each ten second is the minutes counter (i.e. the one that figure 12 correspond to those in the
period the frequency of the tone is drives the minutes display). Since the versatile digital clock.
being varied by the outputs of counter alarm can only be set in units of ten
II. minutes, the alarm will sound when the
It should be noted that for all these tens of minutes have just changed to the Time Signal Generator
alarm circuits a symmetrical 1 Hz required number and the minutes coun- Provision of a 'six pips' time signal
squarewave is required from the output ter is reset. Outputs A to C of the every hour is a relatively simple matter
C") 0 D3301:17:13313DOD:170177333 0
... W (1) OD ,..1 0) N) -. CD
in
b -F173 7,* II II
(0 -.4 0) ( -4* -53 -53 '53
i
N) 11 11 0 11 ...I ..b
74:
,) -...
II Ca) -a -+...... C) -+ NJ ,u Oa o'
C...) cn
IQ co Co 11
c.
-. 0 II ,, A_CO 01 A_GO
C) 0) CD C) fl II

rt0 rl0 n.) W 4=.

x- 11
.4

u) (i) (/) cr)

(...) N) -* FN.) -, ci- cia0-
--
,,,,-
ii ii il 74'
o = It i ID i
r -l LA CA
() -I
g. CC 5..
5 (05CCI CD CO ...i,
0) 0r..)(10
r. li 45
3 cv cr, co .....-1 ii
or -o -o -a 0 -I
z- o o o
0 co C
cD CD i o- ro"
t C
e.,
co c..) 80) w 11 z
0 390 S-2,

tv
C
i' to <ID Cf)

C)
z- --ci-
cp n, .--fiso
' 62.
.c
um
3
CO E cn

co
t.. , .-FTE-21
CD c:,cl.
0- co
-a
-1390 S-2 I

7 x 7490 1 min.
- - 5V
10 min. 1 hour r F= 7,17j - 113
1 sec. 10 sec. 10 5 80117 R072) IC 3 ROW 80127 IC2 2
0
IC10 IC9 IC 6 IC4 AIN 2
A A, AIN N AIN AIN
: 10 : 10 STOP
10/: 5' 10 :6 : 10 :6 FF 1 008k FF 2
BDIN BD,N . BD N BD, BD1N
61 C1 62 C2 A3 83 C3 44 B4 C4 04 A5 85 C5 D 6 B6 C6 D A7 B7 C7 8 A8 8 88 LS
8E2 IW
_1 I 1
L._
10 hours 20 hours -
X spare A7 B7 C7 D7 8
-1
Ain A3 B3 C3 D3 A4 B4 65 C5 D5 A6 B6 C6D6 L19 S
390$2 I
tB2 -o02 0 0- 0-- 0 0 0A 0 0 -- 0 0--0--0--0
R1 82 3'-- R4- 85 D5
5V =I= R17
DiAiik
LTuN 560 }- -.
R6
18k TITT T5

15 14 13 13 12
B C D A B C D
R16
D3 .. D6 = DUG TUN 120E2
IC2=7442 IC3=7442
R7 9 810 0 2 3 4 5 0 1 2 3 4 56 7
2 815
11 21 3 4 5 6 2 3 4 5 6 7 9 10
D7 08 TUN
1800}-
12
7
11 2 345 0 12 3 4 5 67 89
oo 00 00 0 00
10
0 0 0 2 R14
TUN 390E2
SI S2
S3
-,0mmwme 0-
S1

S2c0)

S30 R13
2x TUN 2x TUN II . . 16 = 7405 = 101
TUN
4 015 -12_1
L
044 - Book 75 clamant clock

o23
o
oS°,

2
od
ov
8 o
ot3

C.

o
131---.
C F117
C
0-"I R18

0
rho

6-1 he

I-.
Pi }---411

and a suitable circuit is given in fig- 59 minutes 55 seconds. When this time Figure 13. P.C. board and component layout
ures 14 (block diagram) and 15. The is reached the inputs of gate 1 will all be for the circuit of figure 12.
portion of the circuit outside the dotted high, so the output will be low. At any Figure 14. Block diagram of a time -signal gen-
box in figure 15 is the existing seconds other time at least one input must be erator.
counter in the clock (IC6). The circuit low, so the output will be high. Nor-
works in the following manner: mally therefore, the Q output of IC2 is Figure 15. Complete circuit of the time -signal
the inputs of gate 1 are connected to low, so the output of IC4b is high generator.
the outputs of the tens of minutes, blocking the oscillator IC4a (which will
minutes, tens of seconds and seconds be dealt with later), whilst the Q output
counters corresponding to the time is high, holding the 6 counter IC3 in

14 Tens of
minutes oscillator
counter

minutes
counter

gate 2 Ls
gate 1 Fliptlop amplifier 8S-2

Tens of
minutes
counter
`mk

seconds 6 counter Differen-

counter tiator

0 4015 14
1 Hz pulses
clamant clock Book 75 - 045

15 1

5V1
9

10
0
8 IC4a
1/2 12_4.
7413
R
IC31Aci
Co gate 1 T3
C2

6V
Ao gate 2 T2
IC 4 6
Do IC4b 36 R5
a 2k2
4 1/2
1 IC1 Ckclear IC2 7413
2 9
12
clock Q
IC51A U
Co 5

IC1 = 7430
6
IC4a,IC4b = 7413
R0111 A0121
0 14 = +Vb
7492 0 7 = GND
I1 BoiN IC3

IC2 = 1/2 7473

A c 0 4 = +Vb
IC 6 0 11 = GND
7490 R2

IC3 = 7492
0 5 = -i-Vb
C1
R3 0 10 = GND
o-
470n see text
1 Hz pulses TUN

L 4015 15
Components list for figure 15
Resistors: Capacitors:
R1 = 220 k C1 = 470 n I C's:
R2,R5 = 2k2 C2 = 1 bt, 6 V IC1 = 7430
R3,R4,R6 = 1 k IC2 = 7473
R7 = 100 1-2 Transistors: IC3 = 7492
P1,P2 = 1 k T1 ... T4 = TUN IC4 = 7413

the reset condition. On the negative - onds until it is time for the next signal. OUTPUTS
going edge of the incoming seconds The circuit thus produces six pips every COUNT
pulse at 59 minutes 55 seconds the out- hour, starting with the first pip at
59 minutes 55 seconds and terminating 0 0 0 0
put of the seconds counter will assume
the condition '5', i.e. outputs A and C with a pip exactly on the hour. Of 0 0 1

high. The output of gate 1 will go low, course, this circuit produces pips of 2 0 0
clearing IC2 so that the Q output goes equal length, whereas the last pip of a
3 0 0
low and the Q output goes high. radio time signal is longer than the pre-
IC3 may now count the incoming sec- ceding five. An alternative circuit, which 4 0
onds pulses. However, due to the propa- produces this type of signal, is de- 5 0
gation delays through the seconds scribed elsewhere in this book. 0
0 0 0
counter, IC1 and IC2, it will not count
on the abovementioned negative -going
Oscillator and Amplifier Table II. Truth table for the 7492 connected
edge, as this has already disappeared be-
fore the counter is enabled. However, The oscillator is a simple single time as a divide -by -6 counter.
the negative -going pulse is differentiated
by C 1 and R3 (neglecting R1 and the
base resistance of T1), and turns off T1
for about 100 ms. This takes pin 1 of
IC4 high, and since pins 4 and 5 are
already held high by the Q output of
IC2 the oscillator will be gated through
it providing a 1 kHz tone burst of
100 ms duration.
On each negative -going edge of the five
subsequent second pulses IC3 will count
and the oscillator will provide a 100 ms
tone burst. On the fifth pulse the D out-
put of IC3 will go high, and on the sixth
pulse the D output goes low, clocking
IC2, so that its Q output goes high and
its Q output goes low. This disables the
oscillator and holds the counter (IC3) in
a reset condition so that it can count no
further seconds pulses. This condition
obtains for a further 59 minutes 55 sec-
046 - Book 75 clamant clock

charge and discharge C2 between these

points, which is of course dependent on
the time constant P1C2. The oscillator
frequency can therefore be varied by P 1.
With C2 = 1 µ and P1 set to 330 12 the
frequency will be about 1 kHz. Altering
P1 also changes the mark -space ratio of
the waveform, but this is unimportant
in this application.
The other gate in IC4 is used to gate the
oscillator output into the amplifier,
consisting of T2 to T3. This is a simple
switching amplifier, as only square waves
are being dealt with. In the quiescent
state only T2 is turned on so the current
drawn is only about 7 mA.

P.C. Board
The track pattern and component lay-
out of a board suitable for the time -
signal circuit is given in figure 16. Note
that R4 (shown dotted in figure 15) is a
precaution against power supply ripple
appearing at the loudspeaker output.
Depending on the power supply it may
or may not be necessary.

Chiming and striking systems

In a conventional chiming clock there
are two systems. A chime, which plays
a tune just before the hour, and a
striking system, which sounds a bell a
number of times equal to the number of
hours. In more sophisticated clocks the
chime may also play a portion of its
tune at the quarter-, half- and three-
quarter -hour marks. In simpler clocks
the chime may be absent altogether.
It is difficult to convincingly imitate
bells and chimes electronically, so in
this article two types of system are
described, a fully electronic system
constant multivibrator based on the low and C2 will discharge through P1 driving a loudspeaker, and a hybrid
7413 which is a dual 4 -input NAND until it falls below the threshold, when electromechanical system suitable for
Schmitt Trigger. Assuming the output the output will go high again. Because driving a normal electric door chime.
of IC4a is initially high then C2 will of hysteresis the negative -going The circuit of a simple electronic chime
charge through P1 until the voltage threshold is below the positive -going is given in figure 17.
across it reaches the threshold of the threshold, so the frequency of the oscil- It operates as follows:
Schmitt trigger. The output will then go lator is determined by the time taken to every hour the tens of minutes counter
in the clock produces a negative -going
pulse that changes the state of the hours
17 5V counter, and hence the hour display. In
the circuit of figure 17 this is used to
R7
CCM trigger a monostable with a period of
about 4 seconds. The Q output of this
monostable is connected to one of the
R8 reset inputs of a 7493 divide -by -
T1
4700 16 counter, so that when the Q output
of the monostable goes low the counter
P1 Cl R21 R3 R4 R5
is enabled and counts pulses from the
R6
o TUN clock seconds counter, which are fed
4 1-
Al
+ B R C
100µ
10V
R/C
ITT T B C D
C2.

I-
II
27_4,70
into the A input. T1 and T3 form a
voltage -controlled oscillator, and as the
output states of the 7493 change so
IC1 = 74121 IC2 = 7493 does the voltage applied to the base of
T 1, thus altering the frequency of the
111- A2

0
GND 0 80111 R0(2) AIN GND see text [/\ LS
oscillator.
The oscillator will thus produce a se-
quence of notes until the monostable
inhibit 4 015 17
resets, and when the seconds pulse input
-Cr (which is also connected to the other
lhour pulse from seconds pulses reset input of the 7493) goes high then
10 minute counter o/p C the counter will reset. T2, which is
IC3
driven by the Q outputs of the mono -
stable, switches the power supply to the
clamant clock Book 75 - 047

Figure 16. Board and component layout for

the time -signal generator. 18
BD! N
Figure 17. Circuit of a simple electronic output C
chime. from 10 min. counter
o IC1 =
Figure 18. A striking system suitable for r

7492
driving an electric bell or chime. P1 must be
110111
adjusted to give a monostable period time
greater than 1 second but less then 2 seconds. hours reset
0 80121
Figure 19. By gating the 3 output of the ten- 8
10
minute counter and using it to drive the
chime the clock will strike on the half-hours Sout
as well as the hours. o

ED
B

Figure 20. A suitable drive circuit to switch 1 Hz BDIN

the chime. There are two inputs, one from °

the striking circuit and one from the half hour LNG- 7486 7401
I/2
gating of figure 19. 7440 1N IC2 -
7492
Figure 21. If the drive circuit is used with a ROM)
9

D.C. bell then the relay may be omitted and

an additional transistor connected as shown Inhibit
Ro(2)
will switch the bell.

3 13 12

Al A E
/2 1C4 =
20 clock
IC3 = 74121 clear
see text 1.2 s
1/2 7473
R/C

10
Cl
ri
5V
loop
6v T. 4015 18 0

VCO, thus disabling it when the chime quired information an auxiliary divide -
has finished. P1 can be used to vary the 19 by -12 counter (IC1) is used. This has
length of the monostable pulse and from 10 min. the advantage that (coded) outputs from
hence the number of notes in the chime counter 0 - 11 are available directly from a single
sequence. Altering C2 will change the a 'ou t counter, whereas deriving these outputs
frequency range of the VCO - the from the hour and ten-hour counters in
larger C2 the lower the frequency. As a 4015-19 the clock would require additional
final point, if a faster chime rate is gating. It should be noted that, whereas
required then the 7493 may be driven the clock counts hours 1-12 the counter
by 10 Hz pulses instead of 1 Hz pulses. counts 0-11. This is no disadvantage as
there are still 12 output states for the
Striking the hours striking system.
A circuit for striking the hours is shown Every hour on the hour monostable IC3
in figure 18. The basic idea is that the is triggered by the output of the ten-
output of the hours counter is com- minute counter. The Q output of this
pared with the output of a second coun- monostable is used to clear flip-flop
ter which is driven by 1 Hz pulses. IC4, thus allowing 1 Hz pulses from the
Every hour on the hour 1 Hz pulses are seconds counter through Ni. IC2 now
gated into this counter until its count counts the 1 Hz pulses. Exclusive -OR
equals the output count of the hours gates N2 - N5 are used to compare each
counter. The number of 1 Hz pulses bit of the hours count with each bit of
required to achieve this state is thus the output of IC2. When each bit is
equal to the number of hours and these equal the outputs of N2 - N5 are all low
pulses may be used to drive a chime or so the commoned outputs of N6 - N9
bell. go high. On the next pulse to IC2 the
The circuit operates in the following outputs of the two counters become
manner: instead of using the hours different and the commoned outputs of
counter in the clock to provide the re - N6 - N9 go low again, thus clocking IC4.
048 - Book 75 clamant clock

Figure 22. Circuit of a complete striking sys-

tem. P1 must be adjusted to give a mono -
stable period time greater than 2 but less than
4 seconds.

Figure 23. Printed circuit board and compo-

nent layout for the striking system of
figure 22.

The Q output of IC4 goes high, resetting to the count of IC1 plus 1, which is of used to drive the chime or bell.
IC2, while the Q output goes low, course the number of hours since IC1 is To ensure that counter ICI is in
blocking N1 so that no more 1 Hz always one digit behind the counters in synchronism with the clock hours coun-
pulses can be counted. The number of the clock. The pulses can therefore be ters, and thus prevent the wrong hour
pulses allowed through Ni is thus equal taken from the output of Ni and be from being struck, it is necessary to

22
Output C BDIN
11
from 10 min.
counter
O AIN B

1C3 Pin 8 IC2 =

7492 8 4
Roll) 9
16
hours reset
610121
O
IC2 pins 2 and 3*
10
100n
S3 C 1_1
1Hz
5V
9

5(l
11

BDIN
1D6 11 13

clock
1/3 IC1 = 7410 GND
4
7486 7401
1/2 IC6 5
AIN IC4 IC5
= 7473 IC3 =
8
clear 7492
6O
Roll)

7 8012)

1/3 IC1 = 7410

17. 13 12

Al A2 GND Q

IC7 =
0 clear clock a
*see text 74121
2.5 sec. IC6 =
C R/C 1/2 7473
r C1
1 14 9

47kP1

100 µ
6

bell
6V T ® 5V
100n C2
P2
4C>:8V
Cr3i
47k depending
100P i0µ on relay
10 6V 11 14 9
16V
C IR/C
IC 3 fromlOminute 3
D1
pins 9 and 12 counter IC8 =
4 74121 11 Re: 6V
A 2
DUS TUN C5
B GND ma x.100 mA
STOArsi 1/3 IC1 = 7410 7
D2
DUS 00n

4015 22
clamant clock Book 75 - 049

stable and hence the time for which the

bell coil is energised. It should be ad-
justed so that the bell will just strike
reliably, to minimise the energised time
and hence the dissipation in the coil.
If a normal ding-dong type of door
chime is used it may be a good idea to
remove one of the tubular or bar res-
onators so that the chime produces only
a single stroke. In the larger tubular
type of chime the tubes are usually
suspended on cord or wire and are
easily removed. The smaller types of
chime usually employ metal bar res-
onators which are suspended from
rubber mounts. These can also be
removed quite easily.
The circuit of a complete striking
system is given in figure 22. It embodies
the ideas of figure 18 together with the
half-hour striking circuit of figure 19.
The only difference is that the spare
half of IC6 is utilised and the striking
ter in the clock, as in figure 19. The out- occurs at a Y. Hz rate. If this is thought
reset IC1 to zero at the change from 12 to be too leisurely then the seconds
to 1 o' clock in a 12 hour system, or at put of this NAND -gate can then be used input can be connected direct to pin 4
the transition from 12 to 13 hours or 00 to trigger the bell, which will then strike
every half-hour.
of IC1. A printed circuit board and
to 01 hours when used with a 24 -hour component layout for this circuit are
clock. A suitable drive circuit for the bell is given in figure 23.
given in figure 20. It consists of a mono -
Striking the half-hour stable multivibrator driving a transistor The connections to the 'versatile clock'
As a small refinement it is possible to which switches a relay. This enables the are shown in brackets in figure 22. Note
make the clock strike once on the half- circuit to be wired into the household that two hours reset lines are required,
hour. As the half-hour corresponds to A.C. doorbell circuit. If a separate so the connection between pin 6 and 7
an output of 3 or binary 0011 on the (D.C.) bell or chime is used it is possible of IC2 in figure 23 must be broken,
tens of minutes counter this can easily to drive it directly with a transistor and after which these two pins are pairwise
be derived by NANDing together the A dispense with the relay, as in figure 21. connected to pins 2 and 3 of IC2 in the
and B outputs of the ten-minute coun- P1 adjusts the pulse length of the mono - clock.

23
S

go
 fuse indicator disc preamp
050 - Book 75

J.W. van Beek

DISC

fuse
pre= A preamplifier -equaliser for
magnetic pickup cartridges has to
meet quite exacting requirements.
Values for gain, noise level and maximum input voltage which will
guarantee trouble -free operation under all conditions are not so easy to
achieve. The well-known two -transistor configuration, operating from a
12 .. . 18 V supply, invariably falls short on gain and overdrive -margin -

indicator unless it is designed for a low nominal output voltage (about 30 mV).
An alternative approach is to make use of a good integrated amplifier.
The design about to be described, which meets all the requirements,
employs a SN 76131. An almost identical I.C. is the µA 739.

To make optimum use of the possi- Figure 1. The desired closed -loop gain curve
In this circuit, the neon indicator lamp follows the IEC (RIAA) disc equalisation
shows whether or not the power is on bilities for groove -modulation, gramo-
characteristic, with a mid -band gain (1 KHz)
and whether or not the fuse is blown. phone records are cut with low audio of 40 dB (heavy line). The open -loop gain
As long as the power is on and the fuse frequencies attenuated and high audio must be at least 20 dB greater; the SN 76131,
is intact, the neon lamp will draw frequencies boosted (with respect to with the chosen lag compensation, provides
current through the fuse, D2 and the 1 kHz). To simplify playback equalis- this with a margin of about 10 dB (upper
built-in series resistor. It will burn ation, a single weighting curve has dashed curve).
brightly to indicate that all is well. been standardised throughout the
If the fuse is blown, however, current world - the IEC disc -cutting character- Figure 2. The heavy line is an estimated
can only flow through D1 and R 1. This istic. (This curve originated as the RIAA contour for the highest voltage delivered to
standard: Record Industry Association the preamplifier by a high -output dynamic
current will charge Cl until the ignition cartridge. The preamplifier cannot be over-
voltage of the neon lamp is reached. The of America).
The disc -cutting engineer arranges for a driven by the highest input voltage; the upper
lamp will light up. It will now draw dashed line is the overdrive threshold for the
`0 dB standard (reference)level' in the disc -preamplifier with SN 76131. This clears
extinction voltage is reached, where- taped programme to produce a stylus the maximum -input contour by approximately
upon the lamp will go out again. tip -velocity about 14 dB below the 'safe' 10 dB.
Cl recharges through R 1, and the cycle drive -level, to provide headroom for
repeats. The result is that the neon instantaneous signal peaks. 0 dB standard Figure 3. The maximum RMS output level
lamp will flash continuously as long as level (corresponding roughly to the produced by the preamp when used with a
the power is on. average level in loud passages) is typi- high -output cartridge follows the thick con-
The only critical points in this circuit cally 39 mm/sec tip peak velocity at tour. The dashed line indicates the maximum
1 kHz. Standard level on carrier -channel output capability. The safety margin is here
are the resistors. The value of R1 must once again about 10 dB.
be so large that current flowing through discs (CD4 and UD4) is lower, about
this resistor into the neon lamp is 22 mm/s.
insufficient to keep it ignited. On the Experience indicates that wide -band
other hand, the built-in resistor should cartridges suitable for carrier discs
be small enough to discharge C 1 fairly deliver 70 . . 140 µV for each mm/sec
.

rapidly but not so small that the lamp of tip velocity. The usual 'hifi' cartridges
will 'burn out' when fed directly deliver about 6 dB more. (Note that
through D2 (actually, a neon lamp sensitivityspecifications are usually
doesn't burn out - it can progressively given in RMS millivolts per peak centi-
darken as the electrode material metre per second). So the input to the
`migrates' to the inside of the glass preamplifier at standard level 1 KHz will
envelope). be about 1 . . 10 mV peak.
.

H What are the consequences of all this for

the preamplifier?
Suppose it is the intention that the
output voltage at standard level be about
100 mV RMS with the lowest -output
cartridge. The closed -loop gain must
therefore be 100 at 1 KHz. Now allow
20 dB of extra gain for IEC equalisation
at the lowest frequencies, not including
20 dB of negative feedback (which
should reasonably be maintained at the
end'). This tots up to an open -loop
gain of at least 80 dB! Ten thousand
times. That seems to eliminate the two -
transistor configuration.
The SN 76131 integrated circuit, with
the chosen lag compensation, has a
typical open -loop response according to
the upper dashed curve in figure 1. The
disc preamp Book 75 - 051

lower dashed curve indicates the mini-

mum requirement (80 dB at the low
dB
90 -------,, end, reducing as the closed -loop gain
- i.e. the bold line in figure 1 - falls
NN1
1 according to the IEC curve). The con-
80
clusion is that there is about 10 dB of
. ti
open -loop gain to spare at all fre-
quencies, which will accomodate IC -
70
tolerances etc.

\1 1
Overdriving the input
60

\
N
1 To find the maximum input voltage
%
N which can occur, one must start with
1 %
1 the highest -output cartridge. This will
50 1 %
deliver, as shown earlier, about
5. . 10 mV peak at standard level.
.

40
N The maximum level encountered on the
%
-.-...111144N4441444.11416114.414404%44444sssx_.-
=open loop gain of SN76131 disc is nominally +14 dB relative to
µA 739C) with lag compensation. standard level. This indicates a nominal
30
N maximum input voltage of 25 . . 50 mV.
.
- - - -= minimum required open loop gain.
(At 1 KHz of course). It is clearly
= closed loop gain including IEC advisable to regard this figure, with due
(R IAA) equalisation respect, as nominal. One might encoun-
20 (output 0dB ref = 100mV with
cartridge 0.5mV/cm/s) ter a cartridge with still higher output
1 50 200 500 2 OK 20 50 100K or some disc manufacturer may fully
exploit tracing -compensation, to cut a
4040 1

clean signal at more than +14 dB . . .

2 The absolute limit. (set by 'slope -over-
load' at the inner radius of LP discs) is
dB
presently about 350 mm/s (+18 dB) -
1 30
but a 33 disc also has outer grooves and
.. 90 they can be cut at a level 6 dB higher.
20 50
This means that in theory the
maximum output level for the highest
28
output cartridge is about 200 mV! With
6 the circuit arrangement given, the
9
SN 76131 will accept 80 mV at the
input (thick dashed line in figure 2).
0
4411110A11 5 The same figure can be used to estimate
AOFF 28
the effect of amplifier noise. The wide -
= max. input voltage lab . 80mV) for band noise level, referred to the
- 10 preamp with SN76131 (or 1.6
SN 76131 input, is 2 µV (RMS). This is
pA739C)
= max. output of high -output
0.9 -68 dB in the figure (0 dB = 5 mV
cartridge 12.5mV/cm/s) RMS). For the least sensitive cartridge,
20
= IEC (R IAA) equalisation
0,5
this noise level is -54 dB relative to
asymptotes (0dB = 22mm/s at standard level for CD -4 or UD-4 discs.
1 kHz)
= wideband input noise level equiv. Assuming maximum signal level to be
- 60 spy
(20./ or - 68dB) +14 dB the overall S/N ratio is (for this
2,8PV worst case) 68 dB. Manufacturers esti-
- 70 1.69v mate that the S/N ratio possible with a
10 20 50 00 200 500 1K 2 5 10K 20 50 00K first-rate LP pressing is about 70 dB.
4040-2 Conclusion: pass.
Figure 2 can be used once more to
3 determine the hum -level requirements.
dB
The IEC bass -lift now aggravates matters:
to achieve a hum level 60 dB below
ImV standard level, with a fairly high -output
9000
cartridge (5 mV RMS at 1 KHz), it
60 5000 becomes necessary to keep the hum
2800 voltage at the input below 1 pV! This
can be achieved, in general, by providing
50 1600
good screening for the input circuit and
900 for the preamplifier itself (signal -return
500
inside the cable -screen, the latter bonded
40
to signal -earth at the amplifier end
280 only), and by properly smoothing
30 160
(preferably regulating) the DC supply.
The sensitivity of the SN 76131 to
90
interference on the DC supply rail is
20 50 quoted - under operating conditions
- -- = max. output voltage SN76131 or rather different to the above - as
pA739C1; abt. 7 V RMS
for V' = 30 V and RL = 10 k
50 µV/V. (i.e. 50 µV apparent input for
= max. estimated Vo, with high - each volt of supply disturbance). To
output cartridge achieve the 1 µV hum level just men-
tioned means keeping supply ripple
below 20 mV. A simple active circuit
_f
4040-3 will readily meet this requirement;
052 - Book 75 disc preamp

simple smoothing of a 'raw' DC supply voltage swing at the output can be as Figure 4. The pinning of the IC's SN 76131,
high as 2.5 V RMS (7 V p -p). TBA 231, TCA 590C, pA 739C and LM 1303
would probably be inadequate or too (figure 4a) is identical. The internal circuit
expensive (or both!). The clipping level for the SN 76131 diagram (figure 4b) however only applies to
depends on the supply voltage and on the SN 76131.
the load impedance. The case of V+ = 30
Clipping at the output and RL = 10 K, where the IC can deliver Figure 5. The circuit diagram of the equaliser -
The requirement that the input circuit about 7 V RMS, is shown dashed in preamplifier. An integrated voltage regulator,
is not overdriven will not by itself figure 3. This reserve should take care of when required, can be connected between the
guarantee that the amplifier as a whole all eventualities. If one considers a brink - points A and B (see text).
operates within limits. The output of -disaster capability of 3 V RMS, then
the combinations 18 V/5 K, 14 V/10 K Figure 6. PC board and component layouts
circuit can still 'run out of voltage or for the equaliser -preamplifier. All external
current swing. and even V+ = 12 (at RL = 50 K) are in
connections are made to one edge of the PC
Taking the combination of a sensitive car- order. Even under these conditions, board, so that it can be used as plug-in
tridge and the maximum disc modulation current clipping due to the load of the module in a complete control amplifier.
likely to be encountered, one can esti- feedback network on the output (at the
mate the highest level of output signal highest audio frequencies) and slew -rate Figure 7. Illustration of the preamplifier board
that the preamplifier will have to limiting (due to the early open -loop as plug-in module.
deliver. This can be done by combining rolloff) are not expected to occur.
the closed -loop gain characteristic
(figure 1, thick line) with the maximum
cartridge output contour (thick line in Integrated circuit
figure 2). The result is shown in figure 3 The circuit was designed around the
(thick line). The conclusion is that the specified SN 76131 by Texas Instru-

5 TO 39
(B)
T
30V 24V O IU

10 16mA Parts list to figure 5.

IN (C)
Resistors:
C17
lop \GND R1,1314 = 100 k
C4 1,3 8 40V C11
R2,1313 = 1 M
4n7 4n7 78M24 HC
R3,R11 =10
12)
C5 10
C12 R4,R12 = 1k2
86 R9
4n7 4n7 R8,R10 = 270 k
3 MEI ECM 12
R6,R9 = 150 k
C9 C14
C2 4µ7/25V C7
R7 = 56 k
0,47P 0,471.1 13
IC la IC lb R8 = 470 k

R2 R13 Capacitors:
C1,C18 = 680 p
C2,C8,C10,C14 = 40, 25 V
C3,C13 = 2n7
R C8 C4,C8,C11,C12 = 4n7
R4 4P7 10 4p, R12
25V
R5
25 V
C7,Cg = 0.47 m
lop
16V C16 = 0.1
4040-5 ® Semiconductors:
12) IC1 = SN 76131,mA 739C,
0 TBA 231
'Cr
R IC S N 76131. µA739,TBA 231
disc preamp Book 75 - 053

(and the TBA 231) is given in figure 4b.

Except for the output transistor, the
µA 739C is identical. Table 1 lists the
most important characteristics of the
device. The TCA 590C has an additional
class B output stage, while the LM 1303
circuit dispenses with the stabilising
diodes and with the current sinks for
the second long -tail pairs.

The external circuit

Figure 5 gives the complete circuit dia-
gram of the equaliser -preamplifier. The
open -loop response is set up by C4/C5/R3
and Cii/C12/Rii; it follows the appro-
priate dashed curve in figure 1. The IEC
correction networks are R1/R2/R4/Ci/C3
and R12/R13/R14/C13/C1s. R5 and R10
take care of the DC biassing. With the
values given, the correction obtained
using 5% components is within 1 dB of
the IEC (RIAA) standard.
The input blocking capacitors C7 and
C9 should not be replaced by larger
values or by electrolytics. This could
lead to undesirable switch -on phenomena
Table 1. The most important specifications of Table 2. Main specifications of the disc pre- (`plop' or even momentary oscillation).
the SN 76131 and pA 739C. amplifier described here. The values given will not affect the bass
response (which is 1 dB down at 20 Hz).
V+ max. 36 V It has already been pointed out that the
Vin max. ±5V
Voltage gain, 1 KHz 40 dB
supply ripple must be well filtered.
Ptot max. 500 mW
Equalisation IEC ± 1 dB
A typical regulated supply will meet
Vout swing 1 . .. 26 V" Max. input (RMS) 80 mV the requirements, but a 'raw' supply
Open loop gain typ 18000 followed by resistor -electrolytic filter
Max. output (RMS) 7V
Open loop gain min 6500* will usually cause too much hum. In this
Input noise level 21./V
Zin typ. 150 KS2*
S/N ratio 55 .. 70 dB* case one can use an IC voltage regulator
Zin min. 37 KS2"
Zout (1 KHz) 5 K17*
Crosstalk (1 KHz) -80 dB which will deliver 24 .. . 30 V at 15 mA
-140 dB* T.H.D. <0.1% (or more), e.g. the Fairchild
Crosstalk (10 KHz)
* see text The printed circuit board (figure 6) has
* These values apply for V+ = 30 V;
RL = 50 KS2
a position for this regulator. If such a
device is not to be used, the points A
and B should be bridged.
ments. According to the maker's data the LM 1303 by National Semiconduc- To simplify assembly, all external con-
sheets, the Fairchild µA 739C and the tors. This last device has lower specifi- nections have been placed at one edge
SGS TBA 231 are almost identical and cations for gain, noise and drive level - of the PC board, using standard grid -
should perform well in the circuit. The it will probably work acceptably in the spacing. This means that it is possible
three IC's are pin compatible (see preamplifier, but we have not checked to mount the disc preamplifier as a plug-
figure 4a). Two other IC's with the same this. in module on a suitably designed
pinning are the Philips TCA 590 C and The internal circuit of the SN 76131 control amplifier board (figure 7).
Table 2, in conclusion, summarises the
most important specifications of the
equaliser -preamplifier for disc records.
Lit.: Texas Instruments data sheets for
SN 76131.
14
054 - Book 75 electronic candle recip-riaa

electronic recip-
candle riaa
The starting point for design of this electronic candle was a desire to The performance of bought or
reduce the fire risk associated with the Christmas season, at the same self -built preamplifiers for
time providing a candle which would not burn up so quickly. Naturally, magnetic pickup cartridges is
the electronic candle can be lit with a match (but a pocket torch will do invariably not sufficiently well
the job too!); it can be blown out or 'nipped out' with the fingers. known. This is mainly due to the

Carrying out measurement on a disc -

preamplifier involves two specific, nor-
mally time-consuming complications.
First of all, one cannot straightforwardly
check the frequency response; carrying
out such a check on the dynamic pre-
amplifier requires a point -by -point com-
parison of the meter reading with a
voltage -frequency table.
This brings us to the second complica-
tion. A correct test of the nominal or
maximum available output voltage as a
function of frequency is only obtained
when the input voltage follows the
weighting curve used during cutting
(figure 1). The simple and direct solution
The circuit is very simple. In the con- heat current is passed through the NTC-
dition 'candle out' no current flows in resistor (R2) via P1. This trimmer has to
Tl and T2 is saturated. A certain pre - be adjusted so that the candle is just not
`self -igniting'. Strong illumination of the
2 LDR (R1) will cause T1 to conduct.
The circuit is arranged so that even
bright room lighting will not cause
things to happen - a burning match
held close to the LDR will however do
the trick nicely.
When Tl starts to conduct, the current
through T2 is reduced until ultimately
this transistor cuts off. T3 will mean-
time start to conduct, lighting the
candle flame. As T3 approaches satu-
ration an extra heating current flows via
D1 into the NTC, causing this to drop
in resistance value. If the match is held
long enough in position - it should
almost burn down to the fingers - the
circuit will hold in the 'candle lit'
condition.
The candle can be blown out if one
blows long and hard enough on the NTC.
The ultra -slow triggering action of
starting up is now reversed and the Performance characteristics of the
lamp -current falls away to zero - the weighting network. Noise and distortion
Figure 1. Circuit diagram for the 'electronic flame goes out. It is also possible to levels will in practice be those of the
candle'. P1 is adjusted so that the lamp just `nip out' the candle by cooling the NTC LF oscillator in use.
does not light up spontaneously. The candle between two fingers. The prototype
is 'lit' by holding a match (or a torch) close to Maximum amplitude
the LDR, and 'put out' by blowing on the
candle used a miniature NTC having a error with 1%
NTC.
resistance at room temperature of about components ± 0,2 dB
150 ohm.
Maximum amplitude
Figure 2. A sketch of one possible construc- If desired, one can replace the zener- error with 5%
tion method. The candle is made from a piece diode D2 by 5 series -connected DUS components ± 0.9 dB
of PVC electric -wiring conduit. universal diodes.
recip-riaa stylus balance Book 75 - 055

the calibration accuracy depends on the

position of the pivots, and any sharp
edges (such as deep scratches) can

Stylus
work involved in accurately affect the freedom of movement.
measuring the amplitude response The calibration depends on the mass per
(R IAA or I EC curve), overdrive unit area of the material, of course; the
margin, distortion, signal-to-noise scale shown is accurate for the boards
supplied by the Elektor p.c. board
ratio and hum level. The weighting
network described here greatly
simplifies the above -mentioned
measurements. Despite its
balance
Correct setting of stylus tracking
service (EPS 9343).

How to use it
The balance is placed on the turntable
simplicity, using only five force is of utmost importance - so that it pivots on the round heads of
components, it will deliver a certainly for modern 'feather- the tacks (see photo). The stylus is now
measurement signal that is within weight' cartridges. The gauge that gently lowered onto the balance, and by
0.2 dB of the standard R IAA is built in to many modern record sliding it up or down along the open
track between the calibration marks
cutting -curve. This should make it players is not always reliable, so a (rotate the turntable a fraction) the
just about the smallest professional double-check by means of a position can be found where the whole
test instrument ever described . . . separate balance is often advisable. set-up is in equilibrium. The tracking
force can now be read off.
For the highest degree of accuracy it is
advisable to set the anti -skating corn -
to both problems should now be obvi-
ous: insert a weighting network having
the amplitude -frequency response of fig-
ure 1 between the constant -voltage oscil-
lator and the preamplifier under test.
A suitable network is shown in figure 2.
N
Figure 1. The I EC/R IAA weighting curve used
during disc cutting. The 'recip-R IAA' network
also produces this curve.

Figure 2. Circuit diagram of the network.

C2 can be made up by parallel connection of
twice 1.5 nF (or 2.2 nF plus 820 pF).

Figure 3. PC board and component layout

for the network (EPS 4039).

3 The 'ideal' tracking force for most

modern cartridges is somewhere in the
0.75 . . 3 gram range.
.
- 0,75

Most manufacturers specify the mini-

mum and maximum permissable tracking - -1.0
force for their cartridges. In practice,
the best value usually proves to be just
under the specified maximum. It is
---2.0
1.5
perhaps worthy of note that the danger
of damage to the record is greater if the
tracking force is too low than if it is too
high - within moderation, of course! As
a rule of thumb, the maximum for dy-
- - 2.5
- 3.0
4.0
5.0

namic cartridges with an elliptical stylus

is about 1.5 g, whereas the maximum
with a spherical stylus will be about 3 g.
From the above it will be obvious that a
useful measuring range for a stylus
balance would be 0.75 . . 4 grams.
.

The p.s.b.
The simplest type of measuring instru-
ment for tracking force is a balance -
and it can also be one of the most
accurate types.
Signal-to-noise ratio 80 ... 120 dB An easy way of making such a balance
is to use epoxy printed circuit board
Distortion (with film
resistors) below noise
material. Computer aided design has
resulted in the end product shown in
Oscillator output figure 1: the printed stylus balance or ELEK TOR 9343
voltage for routine
p .s.b .
testing (0 dB
± 3.5 mV at 1 kHz) 100 mV
Round -headed furniture tacks, rivets or
the like can be used as pivots. These are pensation at '0', and to level the record-
Oscillator output pushed through the holes until the heads player. The latter is always a good idea,
voltage for overdrive anyway, in the interest of minimum
test (+26 dB) 2V
lie flush against the back of the board.
Due care should be taken at this stage: wow. N
 tunable aerial amplifier

056 - Book 75

tunatab mrkil
cim
The aerial amplifier
'for
described in this article is
characterized, among
(1-2 dB), a voltage gain of 10-20
dB,
noise level
other things, by its low (146-76 MHz).
and a wide tuning range it is relatively
FM -aerial amplifier, although
It is designed for use as an lication as a TV aerial amplifier.
simple to modify it for app
tunable aerial amplifier Book 75 - 057

variable aerial
stabilized
supply h.f. choke
14 ... 26 V -
560p
coax C1 tunable
cable amplifier

+ tuning -voltage

R2

1668 1

Aerial amplifiers can be divided roughly Figure 1. With simple means the coax cable the necessary design data, we get
into two categories: wideband and can be used for the signal-, the supply- and something like table 1.
tuned. The main advantage of wideband the tuning voltages.
Table 1. common source common gate
types is, of course, to be found in the input specified by the usually de -
fact that a frequency spectrum of sev- impedances manufacturer; viates no
eral decades can be amplified without can be any- more than
anything having to be switched over or thing between 20% from
readjusted. On the other hand, there are 1 and 20 k 1/S
some drawbacks that count all the more at 100 MHz
if the amplifier is expected to provide output specified by the manufacturer
maximum improvement in reception impedance and is usually of the same order
quality. as the input impedance at
common source
Using wideband amplifiers entails the
following drawbacks: feedback 1-10 p very low;
capacitance usually
1. Cross modulation soon occurs be- 0.1-0.01 p
cause the total amplitude offered can
be fairly large. Furthermore, the The drawback of the common -gate
entire amplified spectrum is fed to amplifier is that its maximum gain is
the receiver and this is another likely less than that of the common -source
cause of cross modulation. circuit. On the other hand, however,
2. In most cases it is impossible to By connecting a 12 V regulator diode in the common -gate amplifier has greater
design a wideband amplifier for mini- series with the supply voltage, the reliability and stability. A secondary
mum noise contribution. This is be- tuning voltage is 12 V lower than the advantage is that the difference in
cause the cable impedance (usually supply voltage. If the variable stabilized matching for minimum noise or maxi-
60 S2) is not the optimum value for supply is now adjusted from 14 to 26 V, mum gain is much less than for the
the amplifier. In addition, it is almost the supply voltage for the amplifier common -source circuit, and is in some
impossible to compensate fully for remains 12 V, and a tuning voltage of 2 cases even negligible. Radio reception
parasitic capacitances. to 14 V becomes available. requires matching to minimum noise,
Comparison of the noise contributions It goes without saying that the variable TV reception requires matching to
of TV tuners and of wideband ampli- supply must have a very low hum and maximum power gain to eliminate cable
fiers shows that both are usually of the noise level to avoid amplitude and phase reflection (picture `ghosts').
same order of magnitude for the UHF modulation via the varicaps. Therefore
band. In the VHF -TV and the FM bands, a large electrolytic capacitor is placed in The circuit (figure 2)
the tuner often has an even lower noise parallel with D2.
The circuit consumes about 100 mA, To obtain a wide matching range, the
figure than the wideband amplifier. If circuit is designed around discrete coils.
the wideband amplifier gives better but offers the advantage that the ampli-
fier always is at a higher temperature This also offers greater freedom as
reception, this is due mainly to the fact regards using other types of FET. Often
that when the amplifier is placed than ambient, so that water conden- mistakes are made as regards the quality
between the aerial and the cable, the sation and the resulting corrosion are
avoided. factor of such home-made coils; in this
cable losses become far less important. case a Q -factor of 100 or more can
easily be achieved.
Tunable amplifier Design possibilities for tunable Although the diagram shows the ampli-
A drawback of a tunable amplifier is amplifiers fier with asymmetrical input and out-
that an extra cable is usually needed for A FET-amplifier can be based on two put, it can easily be adapted for appli-
the tuning voltage. By means of a simple main circuits, to wit: the common -gate cation with symmetrical aerials by
circuit, however, (figure 1) it is possible and the common -source amplifiers. providing LI and L3 with coupling
to use a tunable amplifier without an Since the amplifier is tuned, the input windings. To eliminate the problem of
extra cable. The stabilized power supply and output capacitances of the semi- the (wide) tolerance in the pinch -off
provides the sum of the supply voltage conductors usually present no problems. voltage, the gates are connected to a
and the tuning voltage, and within the Not so, however, the feedback capaci- positive voltage so that each of the
amplifier the 12 V supply is obtained by tance, because this may give rise to FETs draws about 10 mA. For a 12 V
stabilization with a voltage regulator instability. Another important quantity supply voltage, the gate -drain voltage is
diode. is the input impedance. If we tabulate about 6 V, and for most types of FET
058 - Book 75 tunable aerial amplifier

this produces the minimum noise contri- load the circuit heavily, which also re- Figure 2. Although the supply voltage in the
bution. The only limitation to using duces the effect of the FET output diagram is 13 V, the amplifier can be con-
impedance. For the case where Qo = 00, nected to any supply voltage between 10 and
certain FETs is the slope, which should 20 V. At about 13 V the noise contribution
be greater than 4 mA/V. A larger and the output impedance of the FETs is lowest.
number of types meet this requirement, is 00, the gain is given by (figure 3):
as shown in table 2. Figure 3. This simplified diagram serves for
Table 2. db noise contri- Av = n2/n1 S1 (n3/n4)2 a rough calculation of the gain.
type minimum slope bution (typ) at n4 /n3 (ns /n6)2
mA/V 100 MHz n6/ns Zc = Figure 4. The drawing shows how the coils
should be wound.
E300 4,5 1.5
E310 10 1.5
n2 -n3 -n,
ninen6 SiZc ( 1) Figure 5. The method for coil mounting
U1994E 4,5 1.5
shown here saves considerable time. Overall
2N4416 4 1.2
performance does not suffer, but the appear-
2N5397 6 1.8 ance is not so neat.
U310 10 1.5 If we take
E304 4,5 1.7 Zc = 50 n2/n1 = 1.2
SD201
(mos) 13 1.5 n3/n4 = 2.5 ns/n6- 5

The fact that the circuits possess a high - (1) becomes:

Q -factor does not necessarily imply that Av = 750S1 (2)
the amplifier is a narrow -band type. The
circuits are damped by the input and From the above formulae it appears that
output impedances of the FETs. Sup- the gain is directly proportional to the
pose the no-load Q -factor is 100. The slope of the first stage. This is only true,
resonance impedance then found at if the ideal condition (Qo = 00 and
100 MHz is: infinitely high output impedances) is
Z = Qw1_, = 15 k.
sufficiently approached, and that is the
case here if S2 is at least 4 mA/V.
The efficiency of a circuit is given by: It is logical, therefore, to use for T2 a
cheap FET that meets this requirement,
Qo - QL such as the U 1994 E or the E 300.
=
Qo Measurements where T 1 = T2 = E 300
where Qo and QL represent the quality indeed showed a voltage gain of 3. When
factor under no-load and load con- a type E 310 was used for Ti
ditions, respectively. (S = 10 mA/V), the gain increased to
So for a high efficiency it is necessary to about 8.
To investigate the effect of T2 on the
gain, first a type E 310 was used, with
the result that the gain increased to 10.
Since the primary function of an aerial
amplifier is to improve the signal-to-
Note: noise ratio at the amplifier input, it is
The FETs mentioned here are supplied by the
following manufacturers: pointless to measure the bandwidth at
Siliconix E300, E310, U310, E304;
:
the 3 dB points. It is better to quote
Teledyne : U1994E, 2N4416, 2N5397; the bandwidth in which the noise con-
Signetics : SD201. tribution may deteriorate a certain

2
clo
50...75 s-2
C6
Ll
Ii C2
II-
560p
T7
560p
50.750 T1
II
0 D3

BB105
560p

R2
--I 5605
L2
C5

560p
E300
L3
C9

560p
E300
D1 D2
V
05
C1 04
2x R6 0 C7
BA191 560p

BB105
760P 560p B105

C11I 06 (312 V
47µ 5V6
250... 300 0 6V R7 R8

tuning
voltage
410-0
1668 2
tunable aerial amplifier Book 75 - 059

amount, say 0.5 or 1 dB. If this stan- K 3/12/100. Several other types of coil The wire should preferably be silver-
dard is used, the bandwidth of the formers might be suitable as well, if the plated copper wire with a diameter of
amplifier is about 3 MHz at 100 MHz, diameter is about % in (6 mm). The 1.2 mm. The spacing between the turns
but this could not be measured exactly ferrite core has to be a VHF -type! The is0.8 mm and is obtained simply by
because the elektor laboratories are not winding data are given in table 3. winding a so-called 'blind wire' of a
equipped with the (extremely) expens- diameter equal to the spacing, i.e.
ive equipment needed to take accurate coil tap with respect to total number 0.8 mm, together with the coil wire.
noise measurements. + or -Vb of turns Once the coil has been mounted, this
The ratio n2/ni given in the example Ll aerial 50/75E22 blind wire is, of course, removed unless
above, and which is lower than might be 240/300E24 the 240/300 S2 connections are to be
expected, was determined empirically (coupling winding) 5 used. In that case the blind wire is
for a minimum noise contribution, and source 2.5 0.8 mm enamelled copper wire, and
this adaption proved to be the most L2 source 2 5 after mounting of the coil, this blind
favourable one for both the E 300 and L3 output 50/75521 wire is wound off again until the above
E 310. If the coils are made of silver- 240/300E22 5
number of turns is left.
plated copper wire, it is quite a simple (coupling coil) As the coupling coils must be placed at
matter to determine the best tap.
Mounting, construction and
adjustment
An important requirement is that all
connections must be as short as poss-
ible. Photograph 1 gives a clear picture
of the mounting. The FETs should have
much shorter connecting leads than
shown in the photograph (about 6 mm);
long leads have distinctly unfavourable
effects on stability and the signal-to-
noise ratio; this was being verified when
this photograph was taken.
All capacitors, except for C11, are of
the low -loss ceramic disc type. Current
types of Schottky diodes can be used
for D1 and D2, and types BB105A,
BB105B and BBIO5G are suitable for
D3 to D5. The coils are wound on
Kaschke coil formers type KH 5/22,
7-560-8A, with a ferrite core, type
060 - Book 75 tunable aerial amplifier

7 Figure 6. To obtain the tuning voltage for the

amplifier from a tuner with a high -impedance
tuning voltage, such as tap presets for
6 0
instance, an emitter follower is required. If a BC 109C tuning voltage
low -impedance tuner voltage is used, the
tuning voltage for the amplifier can be tuning voltage
- EMI
for the aerial

10µ
amplifier
obtained directly via the 47 k adjustment for the tuner P1
potentiometer. r
Figure 7. Layout of the printed circuit board. 1668 6
(EPS 1668).
Figure 8. Component layout on the PC board
in figure 7. Parts list
resistors:
R1 ,R3,R5,R7,R8 = 10 k
R2,R6 = 560 It
R4 = 1 k
capacitors:
C1 ... C10 = 560 p ceramic disc.
C11 = 47 µ, 6 V
semiconductors:
D6 = 5V6 regulator diode
other semiconductors: see text!
the 'cold end', winding back takes place
from the coil end that is connected to If further adjustment is needed, then
the varicap. This is illustrated in fig- repeat the whole procedure until it is
ure 4. Soldering the wires to the former not.
pins is a time consuming job, particu-
larly for the wire diameter quoted here. Results and application in the 2 m
If more value is set upon efficient amateur band
mounting than on appearances, the coils
are mounted directly in the circuit, as The sensitivity of FM tuners can be
shown in figure 5. The coil formers will limited by:
fit only after clipping, as can be seen in 1. the signal-to-noise ratio at the input,
and
this figure. In this case the coils are 2. insufficient amplification of the
wound on a drill with a slightly smaller intermediate frequency.
diameter (about 0.1 mm) than the outer Most factory -made receivers are de-
diameter of the coil former. signed so that a combination of these
If the receiver used is not tuned by two factors is operative. Although it is
means of varicap diodes, the aerial difficult to give an exact rule for the
amplifier should be adjusted as follows. improvement obtained by using the
0 U Set the ferrite cores half way in the amplifier, it may be expected that the
-110}-
formers. Tune the receiver to a weak sensitivity of the receiver will improve
station with a frequency of about by about a factor of 3 for the same
95 MHz and adjust the tuning voltage signal-to-noise ratio. If still greater
- the voltage applied to the varicap amplification is required, the amplifiers
P-~-1AI 1
diodes - to obtain a maximum output. can be cascaded. An amplification
~I Tune L2 and L3 to increase the output factor of more than 10, however, will
R2 H 0- R3 still further or to obtain a maximum;
adjust L 1 to reduce the noise of the
usually give rise to cross modulation in
the receiver; the same amplification can
41-11-7.
received signal to a minimum. If the also be obtained by means of one ampli-
varicap diodes are three matched diodes, fier equipped with FETs that have a
the aerial amplifier will now track steep slope. The coils described can be
R5-' correctly over the range 76 to 146 MHz. used in the two -meter band, but the
If the receiver is tuned by means of varicaps must then be replaced by
-11- varicap diodes, the voltage that controls ceramic trimmers of 1-9 pF. The band-
them can also be used to control the width is more than sufficient to cover
to- -f R,
diodes in the aerial amplifier. However, the entire band.
to prevent overloading the receiver, the
voltage should be applied to the diodes Conclusions
in the aerial amplifier through an The aerial amplifier discussed in this
emitter follower as shown in figure 6. article is suitable for many applications
The tuning procedure now is as de- and has such a low noise figure that it
scribed above, except that a weak will improve reception in all cases.
station with a frequency of about Apart from the 76-146 MHz range, the
88 MHz should be used and P1 is set to amplifier, with modified coils, can also
give a maximum tuning voltage. Next be used to great advantage in the fol-
R
turn the receiver to a weak station at lowing bands:
100 MHz, and again adjust P1 to obtain 14, 21 and 28 MHz amateur band,
a maximum output. Tune the receiver channel 2-4 TV, channel 5-12 TV, and
to 88 MHz and readjust the three cores perhaps the UHF band.
TG to obtain a maximum output (L2, L3)
0 with the least noise (L1). Tune the 14
7 receiver back to 100 MHz and check
that no further adjustment is required;
the aerial amplifier should now track
correctly over the band 76 to 146 MHz.
miniature amplifier Book 75 - 061

\\rn\ted \Oen
vg\th fecof
cost-consc\ous fro
constructorvery a s'op\e
younger to be 0I'vt icy( operate pickup
For the\t \s necessary
ctivts 1.0s c\rcu\tvv\11
oi a cry outstand-

OVII*6t6 ionds "Ole

6v output \s not
des\g\grequernents. the
-the 0\1.
these to aropOy

tit% u0s be usedhea phones. and re\iab\e.

60
can or
arop\\i\er and \t \s s\rope
payer\I battery \oudspeaker but
a 4 .5 a sroa\\ or qua\\ty
to drWe
\ts po\Ner
\ng ior

The input and driver stages T 1 and T2

operate as voltage amplifiers. The out- 4,5 V
put stage, T3 and T4, operates in class B
to achieve long battery life. D.C. feed- R5
back is provided by means of R3 and
T3
A.C. feedback by means of R3, R4 and
C2. This defines the gain, stabilises the 2,95

operating point and increases the input ol CO TUN

impedance. R6

The biassing of Ti is critical and the

values for R1 and R2 must be adhered
DUS
R3
1
2.25
to. Should the circuit fail to operate cor- 22k

rectly the D.C. conditions may be Ti

D2
7

checked at the base of T3 and T4 and C3

the junction of R6 and R7. - log 470 TUP DUS 100p

If 25 ohm loudspeakers are difficult to 4
1,55
10V

obtain, then 8 or 15 ohm types may be T2

TUP
used instead. In that case R6 and R7 LS
should be replaced by wire links. C2
2552

As can be seen from figure 2 the p.c. TUN

board is extremely miniature and
finding space in the record player cabi-
0 710"iov
0
net should be no problem. To improve Input impedance Zi >600 k 1486
loudspeaker efficiency the loudspeaker Input sensitivity vi = 200 mV (r.m.s.)
1

cabinet should be as large as possible. Output power (with 25 E2) P = 50 mW.

Parts list. R6 = 2.2 E2 Semiconductors:

R7 = 2.2 12 T1,T4 = TUP
Resistors: P1 = 2M2 log T2,T
D1,D32 TUNDus
= 2M2
R2 = 820 Capacitors:
Figure 1. The very simple amplifier circuit. R9 = 22 C1 = 470 Sundries:
R4 - 1 k C2 = io p/10 V Torch battery 4.5 V
Figure 2. Layout of match -box size printed - R5=47052 C3 = 100 00 Loudspeaker 25 E2
circuit board.
062 - Book 75 mos clock 5314

mos dock 5514 The 'brain' in the digital clock described in this article is the clock -IC
MM5314, which needs only a few external components. The time of day
is indicated by seven -segment Ga-As displays, which are now offered at
quite agreeable prices. Another attractive feature is that if no seconds
reading is included in the design, a considerable saving can be made,
whilst seconds indication can always be added at a later stage.

The clock -IC Pulses to drive the counter are obtained counter readings are scanned quickly
The clock integrated circuit type from half cycles of the mains supply. in successive order and are fed in the
The pulse shaper at the input of the same order to an output memory
MM5314 is designed to indicate the
time in hours, minutes and seconds with counter changes the sine -waves into (ROM), which for this IC is pro-
the aid of seven -segment displays. In square waves by means of a Schmitt grammed for seven -segment displays.
contrast to the MM5313 it has no BCD trigger. This trigger has a hysteresis of At the same time that the counters
output. Consequently, it is smaller about 5 V. Depending on the logic state are read, each corresponding display
(DIL 24 pins), has a simpler construc- at pin 11 of the IC, the pulse signal is receives the supply voltage via the
tion, and, what is perhaps even more divided by 50 or 60, so that a signal of drive logic of the block marked 'Digit
important, is a lot cheaper. However, 1 Hz becomes available for the next Enable'. This means that, with this
as appears from the circuit diagram of divider. In the next three stages of the clock, the counters can be read 1 out of
the MM5314 (figure 1), all the com- counter the pulse signal is divided into 4 if a four -digit display is used, or 1 out
ponents needed for building a clock are minutes and 12 or 24 hours, depending of 6 for a six -digit display; the logic
available. on the cycle chosen, and determined by state of pin 24 determines the display
The IC receives its clock pulse from the the logic state of pin 10. mode. If, for instance, the one -second
mains, and can be used for 50 Hz or Via the gates of the individual stages of counter is read, the one -second display
60 Hz drive. The supply voltage may the counter the clock can be set cor- receives supply voltage via 'Digit Enable',
vary from 8 V to 17 V and need not be rectly. If pin 14 of the IC is at '0', the and the reading of this decade becomes
stabilized. If not connected, all drive clock will run at the rate of 1 minute visible. Corresponding segments of each
inputs are at '1' level because resistors per second. If pin 15 is at '0', the hours display are interconnected, but only the
are incorporated which connect them to will run at the rate of 1 hour per second. particular segments of a display that
the plus pole of the supply voltage. When pin 13 is at '0', the clock is receive a voltage will light up. In spite
As regards the clock design, the IC stopped. If a 12 -hour cycle is chosen, of the fact that series drive is used,
offers the choice of various possibilities the leading zero is suppressed by a visual read-out remains constant, pro-
that depend only on a certain logic state special circuit in the IC. vided the multiplex frequency is higher
of the drive input concerned. Counter read-out and display drive are than about 100 Hz. In the MM5314 the
It is possible, for instance, to choose be- achieved with a multiplex technique. multiplex frequency can be chosen up
tween a 24 -hour and a 12 -hour cycle. The multiplexer senses the various to 60 kHz. If the read-out is suppressed
With the 12 -hour cycle the leading zero counter positions successively in the via pin 1 (`strobe') of the IC, the clock
indication is automatically suppressed, rhythm of a multiplex frequency, and will continue to run normally. Thanks
which saves a lot of power. If in ad- passes the value found to a decoder, and to this feature it is quite easy to build
dition no seconds reading is required, from there to an output memory (ROM - an emergency supply.
two seven -segment displays and two Read Only Memory). The multiplex fre-
transistors can be omitted, which gives quency can be varied by means of a The circuit
a considerable saving. By means of the simple RC network connected to pin 23. The complete circuit in figure 3 shows
input 'strobe', read-out can be sup- The multiplex oscillator is followed by that apart from the MM5314 only few
pressed, and there are, of course, control a divider that, depending on the logic components are needed to build a com-
inputs for retarding or advancing the state of pin 24, produces four- or six - plete clock, Perhaps somewhat un-
clock. The clock can also be stopped for digit drive pulses (with or without usually, the circuit description starts
correct time setting. The table gives all seconds, respectively). Using the multi- with the supply, because it is from there
possible settings of the control inputs. plex technique implies that the displays that the counter pulses are derived.
Figure 2a shows a top view of the pins are not driven in parallel, but in series. Since the supply voltage for the IC need
of the MM5314 integrated circuit. Parallel drive means that all counter not be stabilized, the source has been
positions can be read out simul- kept as simple as possible. The d.c.
taneously. To that end the counter supply voltage may be anything be-
Operation reading of each decade is, at a certain tween 8 V and 17 V.
In the overall circuit of the IC two main moment, fed to a memory correspond- The half cycles of the 50 Hz mains are
sections can be distinguished: ing to each decade. The information fed to the pulse input via a decoupling
a. the counter with corresponding cir- thus stored drives the displays of the network R22/C3. This input is pro-
cuits counter readings via a decoder. This tected against overloading by means of
b. the circuits for decoding and driving happens simultaneously for all decades; diode Dl.
the displays (surrounded by the hence the term parallel drive. Multiplex The RC network (R23/C4), connected
dashed line in figure 1). technique, however, means that all to pin 23 of the IC, determines the
mos clock 5314 Book 75 - 063

Figure 1. Block diagram of the MM5314 inte- multiplex frequency which, for the
grated circuit. From this it is clear that the Table
given values, is about 10 kHz, Because
entire clock, except the supply and drive for the integrated circuit cannot provide
the displays, is incorporated in this IC. function state* pin
sufficient current to drive the seven - stop '0' 13
Figure 2a. The pins of the IC seen from the segment display simple buffer stages are slow adjustment '0' 14
top. required. These use normal TUN's and quick adjustment '0' 15
are connected between pins 3 to 9 and mains frequency 50 Hz '1' 11
mains frequency 60 Hz '0' 11
Figure 2b. Pin details of the Opcoa red GaP the display segments. The collector 12 -hour cycle '0' 10
seven -segment display type SLA1. With most resistors provide current limiting for the 24 -hour cycle '1' 10
other types of seven -segment displays separate segments, so their values determine the with seconds 24
anodes are also connected to pins 3 and 9; luminous intensity of the displays. The without seconds .1' 24
hence, an extra connection is needed between minimum permissible value for these strobe '0' 1

these pins and pin 14.

resistors is 330 S2 (+Vb = 17 V), in
practice 470 S2 gave satisfactory results
for all supply voltages. A lower value
produced no noticeable increase in
luminous intensity, so that in fact only
the life of the display is then unnecess-
arily shortened.
Buffer transistors, acting as switches, are
also connected between the 'Digit - *) An unconnected input is at state '1' be-
cause within the IC these inputs are connec-
Enable' outputs and the anodes of the ted to the plus of the supply voltage via
displays. These switches connect the resistors.

50 Hz in 50/60 Hz gate divider gate divider divider 12/24 h select

gate 0
0 16-- puts select II III 11
shaper

r-
stop o
zero
slow o 4
extinction
fast o 15 at 12 h.
50/60 Hz 11

select

cr
02
o multiplexer: seconds, minutes, hours

4/6 Digit
select /\ got
8o f
Toe
MPX MPX MPX Progr.
0 decoder 6 od
oscillator divider decoder ROM
MPX 5 oc
frequency 4
network ob
3 oa

1 o Strobe

19 oht
20
he
21
o mint
Digit 22
Enable o mine

18 o se

1607 1

2 Strobe 1 4/6 Digit sel.

a 2 multiplex -frequency b
a 3 mine
b CI mint a-1 14- Anodes
f -2 13 -b
c 5 20 he 0.625
out 3 12
out d 6 MM 5314 ht 1
4 11-9
7
(top view)
e 18 se 5 10 -c
st DP -6 9
17
e -7 8 -d
g 50/60 Hz in(pulse)
1607 2b
12/24 h sel. ea fast
50/60 Hz sel. 14 slow

+8... 17 V 13 stop
V
1607 2a
064 - Book 75 mos clock 5314

second-, minute- and hour displays to

the supply voltage at the correct mo-
ment. The switching transistors used
here are TUPs.
The circuit is mounted on two printed
circuit boards: one for the displays, and
one for the actual clock circuit with
mains supply.

Printed circuit boards

Figure 4 shows the printed circuit board,
and figure 5 the component layout for
the mains -fed clock circuit. The boards
are quite small, so that the whole unit
can be housed in a small attractive
cabinet. So much space has been re-
served on the board for the supply
transformer and electrolytic capacitor
C2 that, if necessary, fairly large types
can be used. All terminals and controls
(50/60 Hz selection, strobe, etc.) are
placed in a row on one side of the board,
directly opposite the terminals they are
connected to on the display board,
which is shown in figure 6. This display

3
Parts list

Resistors: Capacitors: Various: Semiconductors:

R1 ... R7 = 10 k C1 = 5n6 Tr = mains trafo, 8 ... 12V/250 mA IC = MM5314
R8 ... Ri4 = 100 k R2 = 220Oµ/25 V S1 ... S3 = miniature push-button, ... T7 = TUN
R15 R21 = 470 E2 C3= 10n SPST T8 = TUP
= 100 k C4 = 22 n IC -socket (24 pin DI L) D1 = DUS
R22,1323
C5 = 47 n B = bridge rectifier
C2
B300500, BY 164 etc.
= Opcoa SLA 1, Monsanto
-10
2200...2500µ
Displays
MAN 1, MAN 7 and
25V MAN 10, Hewlett Packard
BY164
5082-7730, Litronix Data
ti B=B300500
Lit 707
se
8 12V-1300,14 BS h min mineO
0
R22
C3
T8 19 1-10 T11 112 T13

10n

C
TUP TUP TUP TUP TUP TUP
47n

21 22 17 18
2 12 20
SB GND + Vb 10 10 minutes 10 seconds
0 hours 4/6 Digit.
strobe 4
Select.
D1 50/60 Hz
16
50/60 Hz Select.
IC= MM 5314
C4
DUS 12/24 h.
n Select.
23 frequency
stop slow fast
13 14 15
a b' d' f'
R2 816 R R1 R18
I R5 R20
0
_L 7

O 0 a a
1=1 2 1=153
D 0

3- TUN TUN R10 TUNI Oil TUN R12 TUN R14

1607

ht mint mine

b'
c'
d'
6'
f'
mos clock 5314 Book 75 - 065

Figure 3. The total circuit complete with board holds the displays and small push and two transistors can be saved. In this
mains supply. If instead of TUNs, quality buttons for 'stop', 'slow' and 'fast'. case there is no connection between pin
transistors are used for T1...T7 (e.g. BC107), 24 and earth. Since the board is designed
the resistors R8...R14 can be omitted. for six displays, two more can always be
Displays
Figure 4. The printed circuit board of the
added at a later time without much
The display board (figure 6) is mounted trouble.
clock circuit with mains supply. The pins are behind the front plate of the cabinet. In-
positioned so that only very short connec- stead of the seven -segment LED displays
tions are needed between clock and display used here (the Opcoa SLA1), types
circuit boards. Connection between the boards
MANI MAN7 and MANI 0 of In total (including the seconds) there
Figure 5. Component lay -out for the clock Monsanto, T6302 of Texas, 5082 and are 13 control connections between the
circuit. There is sufficient space for almost 7730 of Hewlett Packard or Data Lit of clock and the display circuit boards.
any type of transformer. Even a 40 V electro- Litronix can be used. Some of these The six pins of Digit Enable (ht, he, mt,
lytic capacitor could be accommodated on even have two LEDs per segment, which me, st, se) are connected to the corre-
the circuit board. gives a greater intensity at a slightly sponding terminals on the display board.
lower current consumption. Unfortu- Furthermore, the terminals a to g of the
nately, there are many displays where clock circuit are connected to the same
not all anodes are connected to pin 14, terminals on the display board. Three
but have separate anodes connected to other connections run to the three small
pins 3 and 9. The pins 3 and 9 (at the push -buttons for setting the clock. One
bottom of the displays concerned) must side of each button is connected to the
then be bent completely inward and supply common.
connected to pin 14. By means of time signals on the radio,
TV, or telephone service, the clock can
With or without seconds be started properly and quite accurately.
If the 'seconds' indication is not used With the buttons 'fast' and 'slow' the
the expense of two displays, two sockets clock is pre-set before the time signal
066 - Book 75 mos clock 5314

Figure 6. The display circuit board. The small

buttons for setting the clock are at the front.

comes, and the button 'stop' is released

the moment the signal sounds. The
front of the cabinet must have openings
for the four or six displays which can be
mounted behind perspex, for instance.

Further developments
In Elektor laboratories the following ad-
ditional units have been developed for
the clock:
- crystal -controlled time base with
only one IC; current consumption
complete with oscillator: about
90 µA.
emergency supply in case the mains
supply fails.
These extensions are discussed else-
where in this book. The points marked
SB, BX and X in figure 3 and in the
component lay -out are for use with
these units. N

The idea is to add an extra stroke at the

top of a six and at the bottom of a nine
(Figures 2 and 3).
The circuit in figure 4 can be used with
improved 7 -segment common -anode displays, as in the MOS-
clock. The points A, D, E and G are
connected to the collectors of the
for MOS-docks corresponding segment -drive transistors
(T1, T4, T5 and T7 in the MOS-clock).
For common -cathode displays the
circuit of figure 5 can be used. N

3 5
1
i
En,
G
A

81
ni
D
'9103-1
DUS

2 4 DUS TUN

DUS

IIMTUP G

9103 5
9103 - 2 DUS
. . . .
A

9103 4
universal frequency reference Book 75 - 067

universal
frequency
reference
rer
This circuit claims nothing in the way of
originality, but is simply a useful,
general-purpose board that can be used
in many frequency and time measuring
applications. It is particularly suitable
for use as a gate pulse generator in fre- 4i)
quency counters.
13
The heart of the system is a 1 MHz 7490. IC5 "10, 40, \
crystal oscillator based on two NAND -
gates. The output of this oscillator is
14
I\ ., 4.12

1,
buffered by a third NAND -gate and the
frequency is then divided down by a
series of 7490 decade counters. These
consist of a divide -by -2 stage followed
by a divide -by -5 stage, which means that
0
7490. IC I
in addition to dividing the reference fre-
quency down to 1 Hz in decades, out-
0 0
puts of 500 kHz down to 5 Hz are also
available. These outputs are particularly
useful where gate pulses for frequency SHz 1004z 671. 100Hz 50014z 17.12 5k Hi 10kHz 40.0e Hz 100kHz 500k Hz Iti11-41

counters are required. For example, the

5 Hz output will provide positive pulses
of 100 ms width, so if the frequency of

HD4

II, I
:I 31 I, 21 31 16 17 21 21 16 17 2F31-117-17 21 31 t I, 21 31, lb 17

0 7490
IC1
11 14
IC2
7490
11 14
IC3
7490
11 14
IC4
7490
11 14
IC5
7490
11 14
IC 6
74 90

BD A BD A BD A BD A BD A BD
12 12
L._11 Let L.]
C, O 0 0 0
100k H, 50k Hz 10kHz 5kHz 1 kHz 500Hz 100Hz 50Hz 10Hz 1Hz

a 10 MHz signal were being measured a The oscillator frequency may be 200 kHz Droitwich transmissions, using
gate pulse this long would let through trimmed to exactly 1 MHz by the Lissajous figures. The trimmer should,
1,000,000 cycles of the signal to the trimmer capacitor. The best method of of course, be adjusted until the
counter, giving a display of 1000000. doing this is to use an oscilloscope to Lissajous figure apparently ceases to
On the other hand, for period measure- compare the 100 kHz output with the rotate.
ments the 1 Hz to 1 MHz outputs are
more useful. For example, when
measuring a one second period,
1,000,000 cycles of the 1 MHz output
can be counted, giving a display of
1000000.
The p.c. board layout is quite compact
and well laid out. The outputs are avail- special terminals
able along the lower edge of the board on the p.c. board
in the diagram. There is one spare
NAND -gate in the package used for the
oscillator, and this may be used as the
gate in frequency counter applications.
The connections to it are brought out at
the top right corner of the board.
068 - Book 75 steam train

steam train Many owners of model railways want their 'world of trains' to be as
realistic as possible. A means of imitating the sound of a real steam train
is, therefore, more than welcome. This article describes a simple method
of building an electronic circuit of few components that will produce the
required sound. To add even more authenticity, the rhythm of the steam
train sound is regulated automatically and is practically proportional to
the speed of the train.

9V Parts list

R
D2
Resistors: R12 = 27 k
R

DUS
R1 = 4k7 R13= 10k
33n 2xDUS
R8
-I 470k
D1
D3
R2 = 1 k R14= 10k
R3 = 330 SZ R15 = 8k2
R10
4410M}1 C6
R4 = 470 S2 R16= 27k
R5 = 4k7 R17 = 390 k
T4 R6 =470 S2 Rig = 270 k
R12 R7 = 10 k R19= 10k
27k Rg = 470 k R20 = 100 k
TUP R9 = 6k8 R21 = 270 k
R10 = 10 M = 4k7 lin.
C9
R11 = 330 k P2 = 10 k, trimmer
R14
2n7
Capacitors: Semiconductors:
C1 = 220 ,U, 15 V T1,T2,T6,T7,T8 = TUN
TUN
T8 instead of P1 C2 = 100 n T3,T4,T5 = TUP
C3 = 8n2 D1,D2,D3 = DUS
C4 = 33 n
GTUN
R18 R20
CE
R21 L C5 = 680 p
270k 100k 11-. 270k
C6 = 2n7
6V
10n 72
50r-nA C7= 10 n
10k Cg = 10 n
Ian
L 1 C9 = 2n7

E PS1473

-11°-

R 17 1.-0
.-.H F--4 MIS

6
steam train steam whistle Book 75 - 069

The circuit
Figure 1 shows the complete circuit dia-
gram. The sound of a real engine is pro-
duced by the regular escape of waste
steam. This hissing sound is produced
electronically by a noise generator. The
rapid increase and slow fading of the
noise as well as its rhythm, is controlled
by an astable multivibrator and a pulse
shaper. The output of the noise gener-
ator T6 is amplified by transistors T7
and T8. The amount of noise, or noise
level, can be adjusted by means of
potentiometer P2. The transistors T 1
and T2 form the astable multivibrator
which produces a square wave.
The rhythm of the steam sound can be Many model railways still run on 'steam'. For greater realism the steam
varied by means of Pl. By coupling the locomotives are nowadays often fitted with an artificial smoke device.
spindle of this potentiometer to the
speed control on the supply transformer They become even more realistic when an imitation steam whistle is also
for the locomotive, the rhythm of the provided.
steam sound is automatically controlled
by the speed of the train. Should this
arrangement be too difficult, the
potentiometer can be replaced by a
light -dependent resistor (LDR); practi-
cally any type of LDR will do. A d5V
R2
suitable lamp is then connected in R1

parallel with the power supply for the C1

train and placed with the LDR in an -II
opaque envelope to ensure that other 0 .033p
C3
'Cl R5

light sources, such as room lighting, 5

have no effect. O.27µ 6

709
The light intensity now depends on the 4 DIL
12
9
C6
speed of the train; this controls the R8

TUN
value of the LDR and this adjusts the 3
C5
6 22p C7
rhythm of the sound to match the speed. 1

To ensure satisfactory control, it may R7

22k
be necessary to try several lamps of C2 C4 C8 1.5V
different wattage. The capacitors C2, C3 0.47p_ 47p
22k

and C4 convert the square wave pro- 15V 15V

duced by the astable multivibrator into

a certain pulse shape. This pulse drives AB 1471-1

transistor T5 quickly into conduction,

but cuts it off again at a much slower
rate. For a short time, transistor T5
then feeds the amplified noise signal to In general, electronic imitation of sounds Figure 1. The circuit diagram of the steam
the output while amplifying it even is not so easily done. Analysis of a whistle. Note the unusual feedback circuit.
more, after which the amplification is specific sound by looking at an oscillo-
reduced slowly. The output signal can scope display, or, better still, with the
be further amplified by means of an aid of a spectrum analyser, will make
external amplifier or radio set. clear just how complicated that sound cuit. A steam whistle produces a tone,
can be. The spectrum analyser is the so that the heart of the circuit must be
The supply clearer, because it displays the various an oscillator. Secondly, a steam whistle
The circuit can be fed from a 9 V bat- frequency components with their relative is blown - which means hiss. The cir-
tery. Figure 2 shows the circuit for a amplitudes. But even given sufficient cuit must therefore also contain a noise
mains supply. information about the composition of a generator. This noise generator must
sound, its electronic imitation is still no modulate the oscillator. Experiment
pushover. An accurate imitation usually will determine which method of modu-
requires a 'truckload' of circuitry. lation is to be used. Assuming that the
An acceptable imitation, however, can brute -force excitation of the original
Figure 1. The electronic steam train circuit. be achieved with less complication. The steam whistle gives rise to strong over-
Figure 2. Circuit diagram for power supply. problem in this case is nonetheless the tones, the oscillator will have to be
same, how to dream up a suitable cir- some kind of multivibrator producing
cuit. Any attempt to seriously calculate a fairly sharp -edged waveform. The
component values is futile, particularly selected square -wave oscillator is a 709 it
when the sound produced is only an a positive feedback arrangement (and in-
approximation to the original. Then cluding the usual compensation).
there is always the consideration that a The noise -generator is a reverse -biassed
spectrum analyser is not normally base -emitter junction of an NPN transis-
readily available, never mind a genuine tor.
working steam whistle! One is forced At the supply voltage of 15 V this
to the conclusion that trial and error junction operates in the breakdown
is the only available approach. region (Zener), producing plenty of
noise. Resistor R1 limits the current to
The circuit protect T 1 . Since the noise is directly
We already know two aspects of the cir- injected into the oscillator feedback
070 - Book 75 steam whistle

path, it causes an irregular frequency - This keying can be done, of course, with A real train usually gives a warning signal
modulation of the square -wave. This a push-button (break contact) - but it just before entering and leaving a tunnel.
irregular jittering of the waveform is much more interesting to let the loco- An LDR positioned under the track will
causes the output to sound piercingly motive switch the whistle on and off. arrange for the model train to auto-
shrill - very like a real steam whistle. This can be achieved with a Light matically do the same. The same applies
The pitch of the note can be varied by Dependent Resistor in two operating to a level -crossing. Here once again an
changing the values of the capacitors. modes. The whistle sounds either when LDR mounted under the track, between
The influence of the noise generator is light falls upon the LDR or when the the sleepers, will greatly add to the
largely determined by R3. Varying R3 LDR is shielded. Figure 2 gives the cir- realism of a model railway.
adjusts the shrillness of the note, but cuits for both modes. When the whistle Sometimes a quite weak shadow is
one must bear mind that it will also is to be started by illumination of the enough to start the circuit. Some
affect the pitch to some extent. LDR, the circuit with T2 is sufficient. If adjustment of the sensitivity is possible
the triggering is to be done by shadowing with R12.
Keying possibilities the LDR, T3 and R13 have to be added. When the ambient light level in the 'play-
to the fact that almost any The board layout in figure 3 enables room' is on the low side, it will be
Due necessary to shine extra light on the
disturbance of the circuit has an influ- either arrangement to be used. In the
first case, a jumper lead is required be- LDR. The same applies to the circuit
ence on the pitch, it is not possible to that whistles upon illumination. To start
key the whistle by electronically tween the base and collector connec-
tions for T3. the circuit it is necessary to distinctly
switching the feedback. The best illuminate the LDR.
approach turned out to be short- The positioning of the LDR is very
circuiting the points A and B. This important. When a shadow is to trigger
disturbs the biassing of the 709, causing the whistle, the illumination under
the oscillation to stop immediately. `silent' conditions has to be very strong.

2
0
R13

O T3

RIO
T2 TUN
01

TUN

R12

B
Figure 2. The optical keying switch for the
steam whistle, which will respond to either whistle sounds whistle sounds
1471- 2

illumination or shading of the LDR. upon illumination upon shielding the LDR

Figure 3. Printed circuit board and layout for

the steam whistle with optical switch.

3 Parts list

Resistors:
R1, R2,R4,138,R10 = 220 k
R3 = 1k8
R5 = 68 k
R6 = 1k5
R7 = 22 k
R9 = 22 k, trimmer
R11 = LDR 03
R12 = 47 k, trimmer
R13 = 150 k

Capacitors:
Cl = 0.033 /I
C2 = 0.47 /I
C3 = 0.27 11

C4= 47 µ/15V
C5 = 470 p
C6 = 22 p
C7 = 500 p, 16 V
C8 = 1 µ, 15 V
C9 = 10 µ, 15 V

Semiconductors:
... T3 = TUN
-tw 0 D1 DUS
IC1 = 709
mos-clock 12) Book 75 - 071

mos - clock The mos-clock described in this book can be extended with a crystal
time base and an emergency supply. These do make the clock a bit
more expensive, but they are at the same time elements changing the
clock into a highly -accurate and universal instrument.
Furthermore, the total extra current consumed by these extensions is

(2) practically negligible. Both the emergency supply and the crystal time -
base are mounted on one printed circuit board.

In recent years especially, the mains Figure 1. With the mos-clock, the displays point is indicated on the clock P.C.
voltage has been liable to cut out draw most of the current. If the clock is board. The transformer secondary volt-
momentarily (or even for quite some provided with a circuit that drives the 'strobe' age on BS is rectified via D1, so that
when the mains cuts out, the emergency capacitor Cl is charged. Then transistor
time!). Depending on the capacitance battery will keep the clock itself running for
of the electrolytic in the power supply, Ti is driven into saturation via resistor
about one day. R 1. The collector voltage of this transis-
the d.c. voltage driving the clock will
have disappeared after about 200 ms. Figure 2. The mos-clock can easily be provided
tor is then so low that transistor T2 is
The clock will then forget what time it with an emergency supply. A 9 -volt battery not driven. Via resistor R4 and push-
is, so that it must be reset. This is in and a series resistance of 120 st will do. button Si the collector of T2 is con-
itself not such an enormous problem, nected to the strobe inppt of the clock -
but a number of brief failures in one IC. This point (SB) is also indicated on
day could be annoying! the clock p.c.b. When transistor T2 is
The emergency supply circuit described off, the strobe input of the clock -IC is
here uses a 9 -volt battery. This provides connected to a relatively high -impedance
an emergency drive for about 20 hours; load so that it 'sees' a '1', causing the
a period within which even the most displays to light up.
serious mains breakdown will have been If, however, the mains voltage cuts out,
repaired. The emergency drive also offers point BS in figure 1 no longer carries
the possibility of moving the clock from a voltage, and Cl discharges so rapidly
one room to another without it stop- that transistor T1 is cut off within
ping. 5 ms. Now the base of T2 is driven via
resistors R2 and R3, so that its collector-
Design
-to -emitter resistance drops to about
200 ohms. As a result point SB becomes
As the clock -IC MM5314 consists of `0' via resistor R4 and the supply for
one monolithic MOS circuit, its current the display circuits is cut off inside the
consumption can be neglected in com- clock -IC.
parison with that of the displays. At
15 V the total current consumption of
the clock is about 250 mA, 240 mA of
which is drawn by the displays. This is
one of the reasons why the clock -IC is
provided with a so-called strobe input
(pin 1 of the IC) which is '1' when the
clock is running normally. If, however,
the strobe input is made '0', the display
is suppressed, and only the divider
circuits and the memory still draw
current.
These circuits still function satisfactorily
at a supply voltage of 7 V.
So for an effective emergency supply
from a small battery it is essential that
as soon as the normal supply cuts out,
the strobe input becomes '0' so that
current consumption drops to about
8 mA. Of course, it must be possible to
switch on the display circuits now and
again on the emergency supply. A circuit
which provides for this is given in
figure 1.
If the mains voltage is available, the
circuit is driven via point BS from
the secondary of the transformer. This
072 - Book 75 mos-clock 121

3 o VDD
VDD

1LT
1

Vss 65536
TO
R1
X-tal 0---11000

0400Hz
VDD
Z3
'Z5
7V
7V
R3
X-tal o__11..
Z4 VDD
(2)
7V
1620 3
VOS

When button Si in figure 1 is depressed, Some specifications of the Intersil IC type ICM 7038 A.
Table 1.
the strobe input of the clock -IC becomes
`1' again and the displays light up. supply voltage 1.6 V ... 4 V (max. 5 V)
Instead of a push button, a single -pole current consumption 60 /IA (Vb = 2.2 V); 130 /IA (Vb = 3.6 V)
output resistance 230 E2 both for p- and n -output
switch can be used for S 1. condition (lo = 3 mA)
minimum oscillator frequency : 0.2 MHz (Vb = 1.6 V)
Practical version maximum oscillator frequency : 10 MHz
For the emergency supply, only a bat- power dissipation 300 mW maximum
tery with a series resistor need be input voltage oscillator Vb
connected across the supply electrolytic case temperature -30° C +125° C maximum
capacitor of the clock proper. Figure 2 ambient temperature -20° C +70° C maximum
shows the relevant detail of the clock output voltage ti Vb at all outputs
output current at Vo = 0 80 mA maximum
supply: the extra battery and the series Vo Vb 18 mA maximum
:
resistor R5 are in parallel with the supply 400 Hz output current
elco. A so-called minipower pack will (Va Vb) 30 mA maximum
do as the battery. The design of the 400 Hz output resistance 200 E2 (1 a = 3 mA)
p.c.b. is based on this type of battery.
Two alternative arrangements are also For this crystal time base use is made
possible. The first is to replace R5 by a of a complementary MOS IC which,
diode, with the anode connected to the besides an oscillator, also comprises the
battery and the cathode connected to dividers necessary for obtaining the
the supply rail. This has the advantage 50 Hz square -wave voltage with which
that the full battery voltage is available
to drive the displays for short periods the clock is driven.
Figure 3 gives a simplified block diagram
on emergency drive. However, it also of this IC, the INTERSIL ICM 7038 A.
means that no 'refresher' current runs Transistors Ti and T2 in figure 3 are a
through the battery when the mains is
on.
part of the crystal oscillator. Two exter-
Perhaps the best arrangement of all is to nal capacitors and the crystal are con-
replace R5 by a diode, as above, and add
nected between points 7 and 8. The
an extra resistor of 100 k in parallel to Figure 3. The intersil IC type ICM 7038 A oscillator is followed by an inverter (I)
comprises a.o. a 16 -stage divider and a crystal which is turn is followed by 16 divider
the diode. This will trickle -charge the oscillator. For the oscillator only the crystal stages. The 16th divider is followed by
battery. and two capacitors need be connected exter- two inverse output stages at which a
In all cases it is advisable to check the nally. The IC is built up from complemen- relatively low -impedance square -wave
battery condition occasionally (by dis- tary MOS-circuits, so that the power dissi-
voltage is available for further pro-
connecting the mains). This is particu- pation is extremely low.
cessing. The divider stages D 1 . . . D 16
larly important when 'dry' batteries are are all binary so that after the 16th
used - they sometimes become very wet Figure 4. The external connections of the
ICM 7038 A. Owing to the COS/MOS proper- divider we have a frequency of:
after a period of time, as many owners it is always advisable to use a base or
of portable radios and torches have dis- ties, f = fo/216 = f0/65536
socket for this IC.
covered to their cost! Here fo is the oscillator frequency and
Figure 5. The complete 50 -Hz reference source f the output frequency behind the 16th
Crystal timebase for the mos-clock. The diodes D2 . D6 are divider.
Although the standby supply will main- for protection and ensure that the supply It is also apparent from figure 3 that all
tain the information in the memory of voltage for the IC cannot rise above about important points are protected by means
3.5 V. T3 is needed because the output of, zener diodes. This does not imply,
the clock in the event of a mains failure, voltage of the IC is too low to drive the
the counting circuits will not operate in however, that the IC can be handled
clock input directly.
the absence of a 50 Hz signal. This is as if it were TTL: due care is always
where the crystal timebase comes in. It recommended. Touehing the connecting
Figure 6. The lay -out of the printed circuit
ensures good timekeeping accuracy board for the circuits of figures 1, 2, and 5.
pins of the IC must be avoided as much
(approx. 10 seconds per month) and as possible, whilst the IC can best be
makes the drive to the clock independent Figure 7. The component arrangement on the mounted on the p.c.b. by means of a
of the mains. printed circuit board of figure 6. socket.
mos-clock (2) Book 75 - 073

The most important specifications of

the ICM 7038 A are given in table 1. 5
The low supply voltage (1.6 4 V) . . .

and the low current consumption (8 18V/0.8mA)

(average 90 btA) are worthy of note.
Figure 4 gives the pin connections of 0 6

the ICM 7038 A. R7

D2, D3, D4,D5, D6= DUS

The circuit
Figure 5 shows the circuit diagram of D2
x.taiV OD
the complete time base.

i
Since the clock supply lies between 8 V D3
(clock board)
and 18 V, a special circuit must be C4 IC1=
provided which ensures that the time 220P
D4 C2 ICM7038A
base IC gets no more than 5 V. The 10V
D5 5...30P
X-tal

simplest solution is shown in figure 5: VSS

the IC is fed via a resistor R6, and an D6 2

electrolytic capacitor (C4) is connected

across the IC. The diodes D2 . . D6 .
1620 5 X-Tal = 3.2768 MHz
ensure that the supply voltage can never parallel resonance
rise above about 3.5 V.
In figure 5 the capacitors C2, C3 and
the crystal are the external components

for the oscillator. The crystal must be circuit to make the output voltage of circuits of figures 1, 2 and 5 can be
of a type that has been ground for IC 1 suitable for clock drive. The collec- mounted. The component arrangement
parallel resonance with an external tor of this transistor is connected to of these circuits is given in figure 7.
parallel capacitance of 12 pF nominal. point X on the clock p.c.b., after which Figure 8 shows a photograph of the
For 50 Hz output reference the crystal resistor R22 (100 k) is removed. board. It can be mounted on the mains
frequency must be 3.2768 MHz. The transformer on the original clock board.
oscillator can be adjusted with capacitor The printed circuit board
C2. Figure 6 shows the lay -out of the
Transistor T3 has been included in the printed circuit board on which the

Parts list for figures 1, 2, 5, and 7.

resistors: capacitors:
R1,R3 = 100 k Cl = 0.1 p
R2,R7 = 27 k C2 = 5 ... 30 p trimmer
R4=10 k C3 = 15 p
R5 = 120 E2 C4 = 220 p, 10 V
R6 = 15 k
R8 = 47 k

semiconductors:
T1,T2,T3 = BC 107 B or equ.
D1 = BAY 61, BA 127
D2,D3,D4,D5,D6 = DUS
IC1 = ICM 7038 A (intersil)

miscellaneous
S1 = push button with break contact
X-tal = 3.2768 MHz crystal; parallel
resonance with external 12 p
8 -pin DI L IC -base for IC1
074 - Book 75 edwin amplifier

0.0\o
40 design
20 \N the
{or a n\gh-qua\\ty
earier .on
\s a de donon an 9opu\ar
"Ch\s based \levy
a010\ev 90ved ernbodssorne
con
has the the
at-n90\er and
\Nn\c ieatoves due
to
cont\nent.lhe
design -Mee
ieedback
unosuat \s 0001 oi
oi negat\ve
the absence

sittitial%
stfuct\on
srna\\
amount
and to n the output
erop\oyed curvet
qu\escent
stage.

The Edwin amplifier is unusual in that it circuit consists of a voltage amplifier, a

embodies two types of output stage in class A driver stage and a class B output
one amplifier. A class A output stage stage. The input stage consists of T1 and
handles the low level signals and also T2 in a Darlington configuration, re-
serves as a driver for a class B stage sulting in a high input impedance. The
which handles the larger outputs. signal passes to the base of T3 via the
The principle of operation is shown in limiting resistor R4. T3 operates as a features
figure 1. T2 and T3 are biased on by voltage amplifier and in its collector
the voltage drop across the diodes D1 - circuit has T4, which is connected as a - output power from
D3. T2 and T3 function as a class A simulated zener diode to provide a 10-40 W depending on
stage at low signal levels supplying constant d.c. bias voltage of about 2 V
current to the load via resistors R. As the across the bases of the driver transis- power supply.
signal is increased the voltage drop across tors T7 and T8. Feedback is applied be- - high efficiency.
these resistors becomes sufficient to tween the output and the junction of
cause T4 and T5 to conduct and the R11 and R12 to provide a high collector - low crossover
class B part of the output stage begins to impedance so that true current drive is distortion.
operate. Crossover distortion is quite achieved. This helps to reduce crossover
low with this type of design. distortion still further so that despite the - short circuit proof.
small amount of overall negative feed- - no quiescent current in
back and the absence of quiescent cur- the output transistors.
The complete circuit rent in the output stage the distortion
As figure 2 shows, the complete amplifier figures are very good. - output transistors and
drivers need not be
matched.
- unconditionally stable.

figures
- Sensitivity:
1 V (RMS).
- Input impedance:
--- 45 k12.
- Distortion:
1 kHz, 30 W: 0.1%,
10 kHz, 30 W: 0.3%.
- Power bandwidth:
20 Hz - 100 kHz.
- S/N ratio:
> 90 dB.
edwin amplifier Book 75 - 075

2
O
42V
RI C71 R
2,6
In 3
R6
680
40
0,2
T3
R2
00µ/50Y
38,5
25tv T7
BD138
T9
BD137
1 10P

R17 2N3055
0.4 BD130
T4
32
T1

T2 R9
R20
BC108 BC108 2W
BC107 R10 BC148
BC148 20
BC171 BC107
BC171 R 21

T6 2W
R15
1100
BY127 C6
BC177 R16 R18
0.4 D1
BC158 25O0µ
/50
18

R11
C3
BD138
1°4/25v
710
0.4 RL

R12 R19
2N3055 Et\
BD130

Figure 1. Basic circuit of an Edwin -type

output stage.

Figure 2. Final circuit of the Edwin amplifier

for output powers up to 40 W.

Figure 3. The power supply.

Figure 4. Graph of available output power

versus transformer secondary voltage for 4 SZ
and 8 5-2 loads.
076 - Book 75 edwin amplifier

The output stage differs from the con-

figuration shown in figure 1 because it
comprises two NPN transistors of the
same type and not a complementary
pair. To maintain symmetrical operation
of the output stage D1 is included across
R18. This simulates the base -emitter
junction which would be present across
R18 if the configuration of figure 1
has been used. The values of R17, R18
and R19 are low (10 12) to reduce cross-
over distortion.
Overall negative feedback is applied from
the output to the emitter of T2. The
inclusion of C3 means, that 100%
d.c. feedback is applied, which stabilises
the d.c. operating point of the output
at around half supply voltage over a wide
range of supply voltages without the
need for adjustment potentiometers.

6
Amplifier gain
Vout
(dB)
V,n
24

22

V,,, = 245 mVRms

20
1 . * 1111 ,
I ,k1

18
R L= 8 1
RL= 4 i2

16
-3dB -3dB /

14

12

r
10
10 20 50 100 200 500 1k 2k 5k 10k 20k 505 00k 200k 500k '''
I
2MHi
.... Frequency(Hz)

Figure 5. Maximum output power versus fre-

7 quency.
Distortion (%)
. . II ITT I I I
Figure 6. Frequency response.
Output power 6 dB below
0,4 maximum
Figure 7. Distortion versus frequency for
output power 6 dB below maximum.
0,3 Figure 8. Distortion versus output power.

0,2

0,1
momPlum

10 20 50 100 200 500 1K 2 5 OK 20 50 100K

- Frequency (Hz)
edwin amplifier Book 75 - 077

8 Distortion (%)
1%

0,9

0,8

0,7
Frequency 1kHz

0,6

0,5

0,4

0,3

0,2

0,1 J
001 0,1 10 100
Output power 13 (w)

The a.c. gain of the amplifier is, of Power supply capacitor is sufficient and that the
course, given by A stabilised power supply is unnecessary RMS secondary voltage of the trans-
with the Edwin amplifier, as its perform- former does not exceed 33 V on load,
AV _ Vout _ Ru9+ R5
otherwise the voltage rating of the tran-
R5 ance will not be significantly improved.
A simple unregulated supply is quite sistors may be exceeded.
It is worth noting the effect of the com- adequate and two suitable circuits are Over the range of supply voltages given
bination R7, C5 on the operation of the given in figure 3. Figure 3a shows a in figure 4 nothing need be changed
amplifier. Some amplifiers, when used supply using a normal full -wave bridge in the amplifier as the operating point
with an unstabilised supply, display rectifier, whilst figure 3b shows a full - is self-adjusting.
ripple on the peaks of the waveform wave rectifier with a centre -tapped trans-
when driven to clipping. This is elimin- former. Performance figures
ated by R7 and C5 as follows. When the The component values and specification The performance figures, as measured on
amplifier is being driven, current flows for supplies suitable for 20, 35 and 40 W the 35 W prototype of the amplifier are
through R7 and the voltage on C5 is versions of the amplifier are given in summarised in table II and displayed
always below the ripple 'troughs' on the table 1. Of course any suitable trans- graphically in figures 5, 6, 7, and 8. As
supply. The drive voltage available from former may be used, there is no need to can be seen they are quite exceptional.
T3 is limited to the voltage on C5 and adhere to the exact voltages specified. Among the outstanding features are the
the output of the amplifier can never Figure 4 gives the output power available large power bandwidth, good signal to
swing into the ripple region of the versus transformer secondary voltage. noise ratio, immunity to transients, low
supply voltage. R7 also limits the current The only points to watch are that the distortion and absolute stability, even
through T3 in the event of an overload. current rating of the transformer is with large capacitive loads.
adequate for the required output power, Figure 9 shows the printed circuit board
Overload protection that the voltage rating of the smoothing and component layout of the amplifier.
The protection circuit is designed to
prevent excessive current peaks from
occurring during signal overloads or
short-circuiting of the output. The pro- Table I
tection circuit consists of transistors T5
and T6. Their base bias is set such that Po max (W) Vt1 ltr max (A) C1 Power
under normal operating conditions the
voltage across R20 and R21 is insuf-
ficient to turn them on. In the event of
(RL = 4 Ohm) RMS figure 3b

Mono
/
figure 3a
/IF working
voltage
supply
no-load
voltage
excessive output current flowing in R20 Mono Stereo Stereo Mono Stereo (V) (V)
or R21, due to a signal overload or a
short-circuited output, the voltage across 42 33 1,1 2,2 4,5 60 46,5
these resistors is sufficient to cause T5
or T6 to conduct. This reduces the drive 35 30 1 2 4 2500 5000 50 42,5
voltage to the output stage and there-
fore limits the output current, thus 21 24 0,8 1,5 3 40 34
protecting the amplifier.
078 - Book 75 edwin amplifier

TIO

-;1

.
-
4S2

,
r -0 0-1 RIO
..
. ---.T6--3-410 2

41±l
R2o

f -Tin
TT

Figure 9. Printed circuit board and component

layout.

Figure 10. Heatsink details for the driver and

Components list for figures 2 and 9 output transistors.

Capacitors:
Cl = 1 p
C2 = 100 p, 50 V
C3= 100,U, 25 V
Resistors:
C4 = 10 p ceramic
= 10 k,Y4 W
C5 = 250 p, 50 V
R2 = 82 k, W C6 = 2500 p, 50 V
R3 = 100 k, % W
C7 = 3n3
R4 = 6k8,1/4 W
R5,R14,R15 = 100, % W
R6,R8 = 680,'/4 W Semiconductors:
R7,R12 = 220,'/4 W T1,T2 = BC 107, BC 171
R9 = 330, 1/4 W T4,T5 = BC 108, BC 148
R10 = 1 k, 1/4 W T3,T8 = BD 138
R11 = 1k5, % W T6= BC 178, BC 158
R13,R16 = 8k2, 14 W T7 = BD 137
R17,R18,R19 = 10,'/4 W T9,T10 = 2N3055, BD 130
R20,R21 = 0.12, 2 W D1 = BY 127
edwin amplifier Book 75 - 079

10

Heatsink for two output

Length transistors

b Height

Width
Cooling fin for
a driver transistor

25mm
Po max. W H L

42Watt approx. approx. approx.

35Watt 100mm 60mm 75mm
21Watt 50mm

The driver transistors are mounted on the Table II

board, with a cooling fin as detailed in
figure 10a. The output transistors are Performance figures of 35 W version
mounted on a separate extruded alu-
minium heatsink, details of which are Maximum output power ' 35 W (4 E2); 20 W (8 D) f = 1 kHz, THD = 1 %
given in figure 10b and the associated 45 W (4 S-2); 27 W (8 S2) THD = 10%
table. Most manufacturers of heatsinks
will have something similar to this in Efficiency >60% 1 = 1 kHz; Po = 35 W
their range.
If resistors R20 and R21 are not readily Load impedance 0 ... 00 (Maximum
obtainable they may be wound from power into 4 S-2)
suitable resistance wire. Alternatively
wire eight 1 S2 0.25 W resistors in parallel, Overload protection Proof against long
there is plenty of space on the board to duration short-circuit
mount them vertically (figure 11).
Maximum capacitive load >100 µF (!)
Concluding remarks
Whilst the Edwin amplifier meets an Sensitivity ---z--% 1 V RMS f= 1 kHz, Po = 35 W
exacting specification this is no reason
to recommend its construction by the Input impedance -,-;_-, 45 k1.2

Hi-Fi enthusiast. There are many other

designs with similar performance. What Distortion Po = 0 ... 30 W
makes the amplifier eminently suitable 0,1% f = 1 kHz
for the amateur is its problem -free con- 0,2% f = 30 Hz
struction and virtual (electrical) inde- 0,3% f = 10 kHz
structibility.
Frequency response 25 Hz ... 1,2 MHz (-3 dB) Vin = 245 mV
40 Hz ... 1,0 MHz (-1 dB)

Power bandwidth > 100 kHz (-3 dB)

Noise rejection 73 dB input open -circuit
93 dB input short-circuit

Signal to noise ratio 95 dB input open -circuit

> 105 dB input short-circuit

Feedback factor ",-z--' 36 dB

Stability unconditional
 tv tennis extensions
080 - Book 75

TV Tennis.
extensions The scope of the TV -tennis game
can be considerably extended.
In its basic form the circuit
provides only the tennis game,
with a display consisting simply
of bats and ball, with no
boundaries or other refinements.
By the addition of a number of
auxiliary circuits, a number of
different games can be played, and
boundaries, automatic scoring and
other effects can be added.
 tv tennis extensions Book 75 - 081

5V

rA

IF
.1-r7
- 3v D4V
-1; ID II

IC 7`
74121
62 0 119

NTC NTQ/ R59

10k I
L J L J

011
XV
A
012

A
013

F13
11

011 D2 -IF
I BOP O.
. 10
913 Pr 11
TUN
105 1- ®
P
W
TUN
74121 X 21
05 c9 9

01 TUN

--0
DUS
4S111
L,4
M °

.1.,* FF1
ball R47

K
n2c-1
IC1 ... IC9 = 9 x 74121 -4 C14

IC10 = N1 ... N4 = 1 x 7400 8 1-9

1006
tp1 TUN
IC11 = N5 ... N8 = 1 x 7400 (29
W2
"
IC12 = N9... N11 =%x 7402
IC13= FF1, FF2 = 1 x 7474
II
74121
0
C31
O R48

4706 TUN
10y
D1 ... D14= DUS 11N41481
T1 ... T12 = TUN (BC10813,
T13 =AF 239

FO -

21

0
13
W3
07 15 74121 12

H II TUN
DUS

L_

right
7--C

T12
R50

TUN

C32 851 852

I
C
0
TUN
;0

0 0
1
= connection point
= break copper track
R29

D9 C21
LA

DUS
-II TUN

L
left

1 25

V R33
5 .0 nr-
-G
W6 L=4 turns 1 mm Cu 8 mm
010 C24
74121

0
DUS TUN

_J 93631 see text

Figure 1. The original circuit of the TV tennis The extensions to the TV tennis game course of the article it will be made
game. The new connection points and the are connected into various points on the clear which connection points are
places where connections will have to be existing board. In some cases the track
broken are shown.
used for the various extensions to the
on the existing board must be broken game.
for connection of the auxiliary circuit.
Figure 1 gives details of these modifi- Automatic opponent
cations to the existing board. In the TV tennis, like may other pastimes, is
082 - Book 75 tv tennis extensions

a game that only two can play. How- the field of play divided into two halves. ball can be seen to rebound from a
ever, for solo practice it is a relatively A vertical centre line will serve as the visible (white) barrier.
simple matter to provide an automatic net for TV tennis, or as the centre line To give horizontal white boundaries at
opponent, who never gets tired and who for a football game, which will be de- the top and bottom of the picture it is
never misses a shot. This is scribed later. A white centre line is necessary to produce a peak white video
accomplished by making the vertical easily achieved by producing a peak signal that lasts for several line periods,
position of the automatic opponent's white video pulse halfway along each and overlaps the start and finish of the
bat always coincide with the position of line sweep. The circuit that performs field sync pulse. The portion of the
the ball. Vertical control of the bat this function consists of a delay circuit video pulse before the field sync pulse
must therefore be disconnected from triggered from the line sync pulses, and produces the lower boundary, and the
the player controls (P3 or P6) and must a monostable to produce the pulse (fig- portion after produces the upper
be connected to the vertical ball pos- ure 4). This is almost identical to the boundary. This is shown in the timing
ition control. To do this the connec- circuits used in the original design for diagram of figure 5. The video pulse is
tions to the sliders of P3 and P6 from the generation of the bats and ball. The again produced by a delay circuit and
R33 and R25 must be broken, giving circuit is triggered from point H (emit- monostable (figure 6), but here the
4 new connection points: ter of T2), and the output is taken to delay is triggered from the leading edge
B : slider P3/C26/R39 the video mixer (point A). The horizon- of the field sync pulse. This entails con-
C : left-hand side R33 tal position of the line may be adjusted necting the input of figure 6 to point I
D : slider P6/C28/R43 by varying the delay with P10. (emitter T1). The output again goes to
E : left-hand end R25 the video mixer.
A new connection is also made to the Vertical boundaries P11 adjusts the delay, and therefore
emitter of T11 (F). An auto/manual In the basic version of the TV tennis the position of the boundaries, while
switch is connected to these points so game the vertical boundaries at the top P12 adjusts the duration of the video
that point C may be switched between and bottom of the picture, from which pulse, and hence the width of the
points B and F, and similarly a switch is the ball rebounds, are invisible. Since boundaries.
introduced between points E, D and F one of the boundaries is derived from As the ball must now rebound from
(figure 3). the field sync pulses and occurs during these new boundaries, the connections
the field blanking interval, the ball may to FF1, which determines vertical ball
Vertical Centre Line disappear from the screen for short direction in the original circuit, must be
It is usual with most ball games to have periods. It is much more pleasing if the somewhat modified. The new connec-

PS C14

0{-6 tQ 03140010 I 03R2414) 03R281.0

aka
0-1M
C22 C23 C11
2,aka "/-4'19 0200
AG

0.18311,, 1.,.. vpi.1.6 .1'47106

*1'30* 60.1R151.000604R19
Q{ P14 ° Cq-R1 io
cm,oiR2,14, o oiLwsio
04427 2 1.° 9 or1-0 G4141 0-44-0 G-+7-*
o clu
C24
1 0 0
040.2. T'°
0

00
a
ir02,5 0{7,210
c4>IR2
01P. 10
1-0 GP' I°
0-0
a

®0 4. 6 9_

0-1Egi, ° °el'0
e---#4-42
0- - - - ---o crei
tv tennis extensions Book 75 - 083

3 4
snanual
L
auto S3 (?60-1 R62 R63 R64
C41

82p
0Lnar:ual T 10

R 5 C001 ext/
130 Re" -
O ° auto S4 Cex, I R65 D16

A IC14 74121
9363-3 DUS
P10 661
10k
C40 L fig. 15

1n5
C42
C39

tions are shown enclosed in the dotted 100k

Ton 017DUS TOn
box in figure 6. Instead of functioning
as a set -reset flip-flop, FF1 is now con-
93634 0
nected in the divide -by -two mode, so 0
15625Hz
every time a pulse reaches its clock
input it changes state. The pulses to
trigger the flip-flop are obtained from
the output of N6, N5 and N6 being
connected to form an AND gate. When
the vertical ball signal (Q output of IC2
5
20 m. sec.
connected to point W) and the Q output
of IC15 are both '1' this indicates a co-
incidence between the ball and the
upper or lower boundary, so the output
-41
'--I---,
/1
1-1

of N6 will become '1' and FF1 will 9363-5

change state, reversing the vertical ball I- .1
delay sec_
direction.
The preset input of FF1 is still con-
nected to point X of the original circuit,

6
P12
0
5V

22k

666- R68 R69`-- R70 C4i

100n

41 9 10
BC) Rex Cext F cl ee>;<tt

671 D18
A
3 1C 15 74121 °
A2 DUS
P1r--100k R67

C 43

0
50 Hz
-- R 72
47011

1
O preset
0
P3
Figure 2. Half-size reproduction of the main D.0 3r/ D clock FF1
7474 _
board and component layout. (Shown full-
size on pages 32 and 33). =1b dear

Figure 3. The automatic opponent is very 5V

simple to add: two single -pole double throw 9363-6 C10
switches are all that is required.
=wire link (on the
Figure 4. The centre line. As in the rest of the p.c.board)

circuit, a combination of pulse delay and

monostable multivibrator is used for this.

Figure 5. Pulse diagram of the horizontal

boundaries. Approximately 18 msec after
each frame sync pulse a 5 msec pulse is
7
produced, which overlaps the next frame sync 64 µsec
pu Ise.

Figure 6. Circuit for producing the horizontal

boundaries. This extension entails modifying
part of the original circuit, as shown in the 1-7/A--1 1 -7Y --m4
lower half of the diagram. IC9 must be
removed from the original board. delay 24 µsec.

Figure 7. Pulse diagram for the vertical

boundaries.
084 - Book 75 tv tennis extensions

but is no longer connected to the out-

put of N5. Instead, a 470 S2 pullup 8
resistor is connected from this point to
the positive supply. The connections to P14
0
5V
the Q output of FF1 (R46/R47) remain
unchanged. 10k

To recap, the modifications to this part -R73 R75- R76 F177

of the circuit are as follows: O C49

Cx

1. tracks connected to the inputs and 4710] 100n

outputs of N5 and N6 are broken. 141 91

Re
10
FR78 - 7:120
2. Pin 2 (point W) of N5 is connected Cex
cRena 3301-2,

to pin 6 (point 2) of IC2. Pin 1 Al

IC16 74121
L36315- DUS_
(point 1) of N5 is connected to pin 6 -100k R74
4
A2
oT16
of IC15 (on new ancillary board). 1n5
Pin 3 (point S) of N5 is connected to D19.4r.
TUN
ALDUS
pins,9 and 10 (point V) of N6. 470n

3. Pin 8 of N6 is connected to pin 3 9363-8 :)

(point P) of FF1. Pins 2 and 6 (M
and K) of FF1 are linked, and pins 1 15625 Hz o
preset
clock
and 4 (N and L) of FF1 are linked FF3
by the 470 C2 resistor. Pin 1 is also
connected to +5 V by joining it to clear
.®
pin 14. 5V
4. IC9 is now redundant and may be yl
removed from the board.
These modifications may be carried out
by means of wire links on the back of
the board.

Left and Right Hand boundaries

A further logical extension to the
TV tennis game is the addition of verti-
cal white bars as boundaries at the left -
and right-hand extremes of the 'court'.
If automatic scoring is to be incorpor-
ated these are essential. When the ball
crosses one of these boundaries this
indicates that a point has been scored,
to trigger a
points counter can easily de derived.
The circuit (figure 8) is almost identical
to that which produces the upper and
lower boundaries, but it is triggered
from the line sync oscillator and pro-
duces a video pulse that overlaps the
line sync pulse, thus giving a white bar
at the left- and right-hand edges of the
picture. wer,

The video pulse width is about 24 µsec. 55k3 14121

7'315 9803/74121
and the timing diagram for this circuit DC F 1319
is given in figure 7. P14 adjusts the pulse '111 lirlfiriff
width, and hence the width of the verti-
cal bars, while P13 adjusts the delay
time, and hence the position of the
boundaries. FF3 is used to control the
sound effects unit which will be de-
scribed later. Pin 2 (point 3) of FF3 is
connected to pin 6 of IC1, which sound of the smash and bounce. The a positive step to the circuit of figure 9,
generates the horizontal ball signal. circuits described here will produce a it sets off a short and gradually decaying
Within the boundaries of the court the variety of sounds that not only create oscillation. The duration of the oscil-
an atmosphere of 'presence' but also lation depends on the value chosen for
Q output of IC16 is high, and point Xis give unmistakable indication when a C66.
normally high, so the output of N13 mark is scored. The active elements of the other signal
holds the D input of FF3 low, and the For this purpose, five different sounds
ball signal cannot trigger it. If, however, generators are COS/MOS NAND gates,
are provided; the pitch and decay time four of which are housed in one IC 4011.
the ball crosses the left- or right-hand of each of them can be varied according
boundary then the Q output of IC16 The feedback controls (P15 . . . P18) are
to personal taste. set so that each circuit is just on the
will be low, so the D input of FF3 will
be high and the flip-flop can be verge of oscillation.
triggered by the horizontal ball signal Circuit Description The sound effect will then be a damped
applied to the clock input (point 3). The circuit diagram of figure 9 shows sinusoidal oscillation with a frequency
This means that the sound unit is the smash and bounce sound generators. determined by the time constants of
activated only when the ball crosses the Four generators use COS-MOS NAND the twin -T feedback network. The dur-
left- or right-hand boundary. gates. The fifth (T17 and T18) is a ation is determined by the value of the
multivibrator; it is unique in that it is coupling capacitors (C53, C57, C61,
synchronous sound not connected to the power supply! C65).
The fun of playing the game cannot be When flip-flop FF3 (see figure 8) Different sound effects are produced for
complete without the excitement of the indicates a mark scored by applying the ball being struck by the right or left
tv tennis extensions Book 75 - 085

Figure 8. Circuit for producing the vertical field, or by adding a 'window' at the number of clock pulses. This means that
boundaries. In this case, no modifications to centre of both vertical boundaries. In the Q output will change state once
the original circuit are required. The extra the latter case the goal line coincides when the ball hits the boundary. This
flip-flop will be used in conjunction with a with the boundary, like in real soccer. signal can be used to clock FF2.
sound effects generator to be described later. Adding FF4 is a major improvement,
Figure 10 shows the required modifi-
cations to the vertical boundaries circuit but it is not yet sufficient to guarantee
Figure 9. Five separate sound effect gener- (IC16): one more mono -stable (IC21) reliable operation. The ball can leave the
ators are used. Four of these simulate the with a trigger delay circuit is sufficient. field through the goal, but it still moves
impact when the ball strikes the bats and the up and down. This means that the ball,
upper and lower boudaries, the fifth sound
The position and width of the goals are
set by P19 and P20 respectively. The even though off the field, will hit the
indicates a mark scored.
signals that determine the vertical goal posts. As soon as it hits the edge of
boundaries and the goals (0 of IC21) the boundary, above or below the goal,
are applied to the video modulator via FF4 will clock FF2 causing the ball to
an AND gate and a diode. re-enter the field. To prevent this, the
The ball must now rebound from the `clear' input of FF4 is connected to the
remaining field boundaries only and not Q output of FF3. This will block the
from the goals. To achieve this, the clock pulses to FF2 after a goal has
Q output of FF2 is connected to its been scored. FF3 is already part of the
D input. This flip-flop, which deter- sound circuit (indicating a goal).
mines the horizontal direction of the The Q output of FF3 must only become
ball movement will now change state logic '1' when the ball enters the goal.
at every clock pulse. Moreover, this output condition must
The most convenient way to acquire the be maintained as long as the ball is 'out'.
clock pulse for FF2 is to AND the ball Starting from the situation when the
signal and the vertical boundary signal. ball is within the field area and the
The combined signal could be applied to Q output of FF3 is logic '0', the oper-
the clock input of FF2. The flip-flop ation of this section of the circuit can
player's bat, or bouncing against the top be explained as follows.
or bottom boundary. A bat hitting the will then receive clock pulses at line fre-
ball is accompanied by a sharp click; a quency during the period that the ball Inside the goal, the Q outputs of both
coincides with the white part of a verti- IC16 and IC21 are '1'. The N14 output
bounce at the top or bottom of the field is, therefore, '0' and the D input of FF3
is more like a thud. cal boundary. If the ball goes into the
goal, no clock pulses will arrive at the is '1'. As soon as the ball enters the goal,
`Out' balls will retain their vertical the clock pulses applied to FF3 coincide
motion and, therefore, continue to hit flip-flop. The direction of the horizon-
tal ball movement will remain un- with this logic '1' condition at the D in-
the upper and lower boundaries. This put. The Q output then becomes logic
would cause a regular bouncing sound changed, causing the ball to leave the
effect. This sound is suppressed by picture. Goal! `P. Since this output is connected to
There is, however, one drawback to this the D29/D28 OR gate, a '1' is applied to
ANDing the Q and Q outputs of FF1 one of the inputs of N14.
with the Q output of FF3. When the method: if the ball has not bounced
back out of the white field boundary The possibility of FF3 changing state is
ball is 'out' the Q output of FF3 is at now determined by the vertical field
logic '0', blocking the AND gates. before the next clock pulse arrives, the
1 he component values shown in the direction of the ball movement will boundary (IC16) and the ball position
diagram are to be taken as an example; change again causing the ball to reverse only. As long as the ball is 'out' the out-
the sounds can be adapted according to indefinitely and fail to re-enter the put state of FF3 will not change. When
taste by altering the capacitor values. field. one of the 'serve' buttons is pushed the
An additional flip-flop (FF4) is used to ball will re-enter the field and the Q out-
The various signals are summed and put of FF3 will change back to logic '0'.
applied to an amplifier. prevent this. Its D input is connected to
the vertical boundary signal; the clock The flip-flop should not become '0'
input is connected to the ball signal. immediately, as otherwise an unwanted
Football The logic state at the Q output of this `goal' sound could be generated. This
An obvious extension of the possibilities flip-flop can only change when the flip- could happen when the ball is served by
discussed earlier is a simple football flop is 'clocked' by the ball signal. The the opponent, so that it has to cross the
game. A field with centre line is already Q output then assumes the logic state at field rapidly to 'appear' from the other
available. All that is required is the ad- the D input - determined by the side. To prevent this, one of the inputs
dition of goal posts. boundary signal. The Q output will not of N13 is connected to point X, which
These posts can be simulated in two change as long as the ball and boundary is at zero voltage as long as one of the
ways, either by erecting them inside the signals coincide - irrespective of the start switches is depressed. This will

9
fig14
FF3 let
IQ FF1) CI FF3 (if) FF1) O (C) FF2) fig 14
100 =%14
14011
Q IC FF2) 0 0 FF3

GND =

1/4 IC20 =1/47408 l 1/4 IC20 =1/47408

R102 110 R 116

C66
)44011 = 1C19

IMO MIN

R96 R92
MEI
C55 csg., C63
C53
D22 ./n on C.' ,0 024

R83 1190
334

8191
DUS
1893
,1,3- !
R10
C1:17
- 06
334 27'
R107
DUS C.
8 58

7- Tao
086 - Book 75 tv tennis extensions

10
P14

1006

R73' R75- R76 -- R77

470p
14 91 10
Cext Rext
Cext 14IC22 ='/7408
A R78 D20
3 IC16 74121
N15) 13300,1 M
A2
P13' -100k R74 C48 T16 DUS
10k
1n5 C46a
5V
C47 019
TUN
470n IDUS 100n
N14 preset

%IC18 = clock FF3 fig.9

15625 Hz
1h7400
clear ° 00
fig.9
5V
00
028

D29 R122 DUS

DUS
A ®
N9-1
preset

-Ciclock FF4
^R117 R119" R120"
C71 D clear

330n
10
Rex, Cext
r--
0
6
81.1 CRZ"t()

IC21 74121 N7-11

P19
^100k
C69
R118
10k
C70 .T19
1470n C72
preset
a -0
027.r 7
clock FF2
470n
DUS TOn clear
100
N8-6
9363-12
50Hz

only work properly if contact X makes There are three ways to get the ball into than an ordinary tennis game, since one
before (or simultaneously with) con- the opponent's side of the field. The must not only hit the ball but also
tacts Y and Z. If this is not the case an first two are holes in the net, one corre- nosition the hole in the net correctly. A
unwanted 'goal' sound will be heard sponding to each bat. As each player novice at the game will quite often send
when serving; points Y or Z must then moves his or her bat up and down, the the ball into his own goal.
be used instead of point X. corresponding hole in the net moves up Adding this extension to the original
and down with it. The trick is to hit the game requires only very few modifi-
Hole -in -the -net ball and then quickly place the hole in cations (see figure 11).
As far as we know, this is an entirely the path of the ball. Three gates are added to the centre line
new game. A more simple version does The third possibility to get the ball ('net') generator. These gates use the
exist, where one player has to send the across is sheer luck . . If the ball hits . vertical `bat' signal to blank the video
ball through a 'hole in the wall'. the net at precisely the right moment, signal for the centre line. As a result, the
The 'hole in the net' game is rather the flip-flop that determines the direc- vertical position and the size of the
more complicated. The field and the tion of the horizontal ball movement holes correspond exactly to those of the
horizontal position of the players are may receive two clock pulses. The ball bats.
the same as in the tennis game. How- will then change direction twice, with An additional flip-flop is required to
ever, it is impossible to play normal the 'net' result that it flies straight over bounce the ball back off the net. The
tennis because the ball bounces back off the centre line. circuit is similar to that used in the foot-
the 'net'. Obviously this game is more difficult ball game for rebounding from the

11 06-1C4
co
% 7 408 = 3/4 IC22

R6 016

1-)
11111.112) MB
DUS
0
Q- IC14

1:)
0
15-106
et"
r-
17
FF4 FF2

0
N9-1
'/2 IC17 ='/2 7474 10
9363 13
tv tennis extensions Book 75 - 087

13 P14

47k

-R73 R75 -- R76 -.- R77 Q IC 6

n4
C49 O
N17
100n
Q IC 14
9 10

8
Rext Cext Rext 7 N16
11

Cex
IC 4
IC16 74121 % IC 22 =3/4 7408
P13 -100k R74
T16
A2
O
1n5
C47

470n
D19.1.
ALDUS
TUN
N15
R78
3 (33012) it 020

DUS
0
Y4 IC 22=
1/4 7408
O g3
15625 Hz S5b
4S5d
5V
P20 D29r
47k
2x DUS
2
R122 D281
--R117 R119 R120 R121 C72
C71 1/21C18=
N14
O
100n 7400
14 1 9 10
BO R ex t C ex t Rex
o S5a
5
A
3 IC21 74121
A2
N13
RI18 T19 4
P 9--100k C70

C69 D27
470n
TUN
r- N7 - 11 0
470n IDUS
5V
10 0,0
0
50Hz position:
12

11
preset 1
12

11
preset

clock FF2
2

3
preset

lock F F 3
5 0
fig.9
O. clock F F4
1 = football
2 = hole -in -the -net
3 = tennis
N9-1
1/27474
clear
1/27474 -
clear
N9 -1 112 7474
clear 6. 0
1/2 171= 13
1/2 IC 17

5V

9363 15

vertical boundaries. FF4 can be used for Figure 10. Additional circuit for 'football'. Figure 13. Combination of the additional cir-
both circuits, provided one or two Part of the vertical boundary is blanked to cuits for hole -in -the -net and football requires
simulate the goal. a selector switch.
switches are added.
There is no gap in the vertical bound- Figure 11. Holes in the net are simulated by Figure 14. The audio amplifier is quite
aries ('goal') for this game, so a mark is partial blanking of the centre line. This only straightforward.
scored when the ball crosses a vertical requires a minor addition to the circuit for
boundary at any point - as in the tennis the centre line.
game. The same sound effects circuit
can therefore be used for both games Figure 12. Circuit addition to control a sound
(figure 12). effect generator.

Combining the three games

The diagram of figure 13 shows that it 14 R132 R131

is relatively simple to design a combined O C77

1k
Cri
1000
O
10..18V
circuit suitable for all three games: fig.9 min.100µ
R123

TV tennis, football and hole -in -the -net. 116 V Zop

25V
For clarity's sake only those sections of T20
the circuit are shown where modifi- BC141
cations are to be carried out. The letters R125

8 -pin
at the various connection points refer to DIL
D
R129

the interface with the original TV tennis C731 7

circuit. 0.0
fig.9
_1p5
74 C75
C74
In the new circuits, 1-2 resistors (Rx) 1
4 IC 23 D31
VDUS
are included in series with the decoup- 11-1-p 2k2
- R130 220µ
R126
ling capacitors for the integrated cir- 100k
25V

cuits. It is recommended to add these R124

resistors to the basic circuit as well; they T21
will improve picture quality.
80
The amplifier SIN BC161
The amplifier design shown in figure 14
is quite straightforward but adequate ®9363-16
for the purpose. The signals from the
sound effects generators (figure 9) are
088 - Book 75 tv tennis extensions

Figure 15. The p.c. board and component lay-

out for all additional circuitry, i.e. the com- 15
bination of figures 4, 6, 9, 13 and 14.
(EPS 9363).

Missing link
We regret that there are a few errors
in the component layout shown in
figure 15.
R 115' between R113 and R116 should
be R115A; `R94' between R98 and
R101 should be R99; 'C44' between
1C16 and R77 should be C49; 'T20'
between 1C21 and C70 should be T19.

amplified to the comfortable level of

about 750 milliwatts.
The volume control (P21) can be a pre-
set. When setting this control, take care
that the amplifier is not overloaded; this
is quite audible, the sounds develop a
nasty twang.

The p.c. board

Combination of the circuits shown in
figures 4, 6, 9, 13 and 14 gives the
total extension circuit. The printed
circuit board for these additions is the
same size as the p.c. board for the
basic game, so that it can be mounted
on top of the latter. All connections are
at one end of the board, so that it can
easily be hinged up should final adjust-
ments to the basic board be required.
The wiring between the two boards
should not be neatly bundled; it is
better to run the wires criss-cross to
reduce crosstalk.

Final adjustments
Few problems are likely to arise if the
basic equipment has been correctly set
up.
With S5 switched to `TV tennis', the
centre line is positioned by adjusting
P10.
The next step is the positioning of the
horizontal boundary. P12 is used to set
the width, PI 1 to set the position. The
vertical boundary can then be adjusted
in the same way, using P14 and P13 for
width and position respectively.
Having carried out these adjustments,
switch S5 to 'hole -in -the -net'. Two holes
should appear in the centre line, one
corresponding to the vertical position of
each bat. There is no adjustment for
this, so if it does not work there must
be a mistake in the wiring . . .

The last video adjustment is the correct

positioning of the goals for 'football'.
Switch S5 to `football'; the height and Resistors:
position of the goals is set by P20 and
P19 respectively. Finally the sound Figure 4: Figure 6:
effects units must be adjusted. All Parts list to figures 4, 6, 9, 13, 14 and
NAND generators must be set on the 15 R60,R62 = 100 k R66,R68 = 100 k
verge of oscillation, by means of R61 ,R64 = 10 k R67 = 10 k
P15 . . . P18. R63 = 2k2 R69 = 2k2
The gain of 1C23 is set with P21 to a R65 = 330 E2 R70 = 4k7
P10 = 100 k (preset) R71 = 330 E2
comfortable level, where there is no R72 = 470 E2
audible distortion.
tv tennis extensions Book 75 - 089

025
S 04111 1-0 cl 0417410 n Figure 13:
R73,R75,R117,R119 = 100 k
0-1112 10a R74,R77,R118 = 10 k
,
CH FPO°
a R76,R120 = 2k2
Cn0 R78 = 330 ,S2,
04113 C D R121 = 5k6
123 WD 0-01-0 e. 6 R1 22 = 470 n
-4
04115 IK°
O 0 13 2 * 127 P13,P19 = 100 k
n 0.1115 ta 01116 1-0
C73 P14,P20 = 47 k
a)
a)
0-14-0
026
n U1 n
n
Ea I n
Figure 14:
R123,R124 = 10 k
R125,R126 = 100 k
0333 R127,R128 = 820 n
to 0 0
R129,R130 = 12 so
ro
R131 = 100 n
R132 = 1 k
OIR 961.0 ISO P21 = 2k2
Rx = 1 52(4x)
04896}0 j W0+1001-0
0410 4 1-0 gn010610 Capacitors:

9 0" Figure 4: Figure 6:

11°310 W141 *It:* ael
0--0 C39 = 470 n C43,C44 = 470 n
a
S. a " C40 = 1n5 C45 = 820 n
33 Sa
to co co
0
0 0 0 C41 = 82 p C46 = 100 n
N ol C42 = 100 n
In
P1 P19
Figure 9:
P11 C50,C53 C58,C61,C62,C65 = 33 n
C51,C52,C59,C60 = 10 n
33
a C63,C64 = 15 n
) C66 = 100µ/10 V
/ C67,C68 = 100 n

0 01
ru g)1 01
I
33
an
.9-
CO
33
0 Figure 13:
C46a,C72 = 100 n
C47,C69,C70 = 470 n
Figure 14:
C73 = 11/5/16 V
C74 = 1 µ
C75 = 220 au/25 V
0 0
0 al)
6 (Z.)
co

0 6 C48 = 1n5 C76 = 220 µ/16 V

A C49 = 1 n C77 = 100 ,u/16 V
01

O Q oti-0 o-3 71
0 0 27 Semiconductors:
0-14-0 04-02 t D19 ID Figure 4:
Sn
"E81 0-f1i9
I no 14 o D15,D16 = DUS
R741-0 Et'l T14 = TUN
0-1119 I-0 wttcH
04R 7 51-0
In IC14 = 74121
0412 0 1.0
C,c3)

TNI4
0-----0 Figure 6:
D17,D18 = DUS
MEE x117 1-0 MIK
-12.5
c>iR x T15 = TUN
ro
IC15 = 74121

PI1 r11
0-0
0-0
111
`10-11-0

Id0 CEO (°t!, )

Figure 9:
D21 . D26 = DUS
.

T17,T18 = TUN
0 0 IC19 = 4011
0 mo-41-o IC20 = 7408
0
04 Pt afo Figure 13:
0
ESEC ca)i
In
D19,D20,D27,D28 = DUS
ru T16,T19 = TUN
ca
+ tir ui 0 IC16,1C21 = 74121
F co

U) -In -0 g., (n (D
ur
r.
i
(n a) t o_ U10101
aim r,
w Lo (1)_0 / IC17 = 7474
IC18 = 7400
01 al . (SI CD

D. 0' RI (1 ti) r?. 100) 0 ' n Cr Di

IC22 = 7408
1 + t t .
t 1 1
*
X33-,Its3 ItJ01?8+ 3 Xr4411) 0 01+ 3 4 g+- -A DOL
0
o i o! o 0: o Figure 14:
D29,D30 = DUS
T20 = BC141
T21 = BC161
R85,R93,R101,R109 = 10 k IC23 = 741
Figure 9: R86,R94,R102,R110,R115a,
R116 = 390 k Mechanical parts:
R79,R87,R95,R103 = 150 k R111 = 470 52
R80,R81,R88,R89,R96,R97,R104, R112,R115= 2k7 Figure 13:
R105 = 68 k R113,R114 = 270 k S5 = rotary switch, 4 -pole 3 -way
R82,R90,R98,R106 = 12 k P11 = 100 k
R83,R91,R99,R107 = 47 k P12 = 22 k
R84,R92,R100,R108 = 27 k P15 ... P18 = 470 k (preset)
090 - Book 75 calendar

W.G. Paans

calendar
Many mechanical and electro-
mechanical clocks and watches are
now provided with date indication.
Addition of a calendar to an elec-
tronic digital clock is a fairly
simple matter, and the circuit
given here gives the month as well
as the date.

As the calendar is an addition to a digi- which case the calendar will not need to tions are, of course, considerably more
tal clock a control signal must be de- be reset until the year 2100, when a complicated due to tile differing num-
rived from the clock to change the date. century correction (omission of leap - ber of days in each month. Since the
This can be derived from the changeover year) becomes necessary. year begins with the first month, and
from 23.59 to 00.00 with a 24 -hour The calendar is simply a logical exten- each month begins with the first day, it
clock, or if used with a 12 -hour clock sion of the hours, minutes and seconds is not possible to use simple decade
the changeover from 11.59 to 12.00 counters in the clock, but counting days counters such as the 7490, which can be
may be used. However, since this occurs and months instead. The resetting func- reset to zero. Instead, presettable
every 12 hours a 2 flip-flop must be counters must be used, so that they can
inserted between clock and calendar to be preset to one at the beginning of the
give a pulse once every 24 hours. year or month. A suitable choice is the
Like all the best calendars, this calendar 74163, which is a four -bit binary
knows whether the last day of the counter with synchronous preset and
month falls on the 28th (February), the clear. Two of these counters make up
30th or the 31st. Those who are worried the days and tens of days counter, and
about the 29th of February can add the as the capacity bf the 74163 is 4 bits,
optional leap year correction circuit, in one of these IC's will suffice for the

2 to day decoder to ten day decoder to month decoder

Aa Ab Ac Ad
a
5V
Ba Bb Bc Bd
5

id 14 16 14113112f 1110 16
16 13 12
a bcdT L
11 10 19 151
a bcd T
91
L 0 a bcd T

IC7 = 74163 A IC8 = 74163 B IC9 = 74163 C

RCA BCD PGND RCA 8 C DPGND C A BC D POND

2 3 4 5 8 1 2 31 41 51 61 7 81 2 3

24 h. clock puls 41 1617

0
from date
setting circuit
Ba

9 Aa
Bb 4
D-
Ba 9

Bb
12
omD 0

1 clock

12
IC6
14 13

clear

r
a 2k2
1. 667 2

Bb IC1 = 7400 = N1 ... N4

0--0-4,
1

Cc 3N19D 4 Ad MD- IC2 = 7403 = N5, N6, N7, N13

IC3 = 7403 = N10, N16, N17
12
IC4 = 7412 = N8, N9, N11
13
IC5 = 7405 =N12, N14, N15, N18, N19, N20
Cb IC6 = 7473
I
Cd IC7, IC8, IC9 = 74163
NW Febr.-load
_J
calendar Book 75 - 091

months counter. The pin configuration connected to positive supply, as are the 31 and December/January similarly. It
of the 74163 is given in figure 1. Points clear inputs of IC8 and IC9. The data is thus possible to indicate the number
to watch with this IC are: inputs of the three counters must have of days required in each month with a
i ) unlike the 7490 it counts on a the correct presetting data hardwired flip-flop whose state is changed each
positive -going edge of the input into them. The day counter is preset to month, the only corrections necessary
waveform. 1 at the beginning of each month, so the being a) additional circuitry to detect
ii) for resetting purposes a logic '0' is A input is connected to positive supply when the month is February, and b) cir-
required. and the B, C and D inputs to ground. cuitry to inhibit the changeover of the
iii) counting may only take place when The tens of days counter is preset to flip-flop at the July/August and
there is a '1' at both the enable in- zero so all the data inputs are grounded. December/January transitions. The flip-
puts P and T. The month counter is preset to 1, like flop is IC6, and the `February detection
iv) when there is a '0' at the load input the day counter. circuit' is contained in the dotted box.
the count function is inhibited. The IC7 receives one pulse every 24 hours This part of the circuit operates as fol-
next positive -going transition of the from the digital clock at pin 2 (clock lows: Assume that the next transition is
clock input transfers information input). This IC is connected so that it from a month with 30 days to one with
from the data inputs to the outputs. normally counts up to 9 before resetting 31 days (say April/May). The Q output
to zero. When the count reaches 9 of IC6 will initially be high. When the
Counter Circuit (binary 1001) the a and d outputs of count of IC7 and IC8 reaches 30, out-
the counter are high, so the output goes puts Ba and Bb of IC8 will go high. This
The circuit of the counter section of the low, taking the synchronous clear input means that all three inputs of N9 are
calendar is given in figure 2. IC7 counts (pin 1) to '0'. On the tenth clock pulse now high so the output is low, taking
the days, IC8 counts tens of days and the counter is reset synchronously to the load inputs of IC7 and IC8 to '0'.
IC9 counts months. The enable inputs zero. This sequence is of course inter- On the next clock pulse IC7 and IC8 are
of all three counters are permanently rupted when the counter is preset to 1 thus preset. The output of N9 also holds
at the beginning of each month. the input of N3 low. The output of N3
While the output of N5 is low this also is thus high, so the clock pulse is
holds pin 9 of N2 low, so its output is allowed through N6 to the clock input
high. The tenth clock pulse which resets of IC9. Immediately IC7 and IC8 are
IC7 can therefore pass through N1 and preset the output of N9 goes high again.
N4 to the clock input of IC8. IC8 there- The output of N12 thus goes low. This
fore counts once every ten clock pulses. is connected to the clock input of IC6
As stated earlier IC7 and IC8 must be so the flip-flop changes state and the
preset at the beginning of each month, Q output goes low.
the count that they reach before this At the end of the next month, since the
Figure 1. Pin configuration of the 74163 used occurs depending on the number of days Q output of IC6 is low the output of N9
in this design. in the preceding month. It is evident must remain high and the transition can-
Figure 2. Basic circuit of the counting section
from table 1 that with two exceptions not take place on day 30. Instead N8
of the calendar.
the number of days in the month alter- takes over, and on day 31, when out-
nates between 31 and 30. The excep- puts Ba and Bb and output Aa are all
Figures 3 and 4. Two alternative decoding tions are February, which has 28 days, `1', then the output of N8 goes low and
circuits for the calendar. August, which has 31 days after July's the sequence repeats. Inhibition of the

3 days units days tens tens months units

Minitrons
a

I4t;1 ;;T121 11110

9 abcd e
9
I.
a741 1311271[1-01 9
1
. -- ---

9 abcde
.1-___-

15 141 7217111101 9
9abcde
7447 7447 7447

DCBA CC BA A

61 21 11 71 6 7
61 21 11 71

r- A
161 151 14
5

12 10,

-a
16 151 14 13 12 11 10 9 13 11 91

a bcdT L a bcd T L
16
13
IC7 = 74163 A 1C8 = 74163 B
3
RCABCDPOND R C AB C DP GN D 10k
51 61 71 21 31 41 51 61 71 81
11 21 31 41 81 11
N5
see fig. 2 100 1 2 41 5

11,12,13,14,15,16 = 7416
N1, N2, N3, N8 = 7400
N5, N6, N7, N4 = 7400 c ob
166 7-3
from IC9
092 - Book 75 calendar

flip-flop changeover during the July/ ure 3 operates as follows: put of Ni allows the data on the c input
August transition is accomplished by when the month count is less than 10 through N7. During months 10 to 12
N11. As July is the 7th month (binary the flip-flop comprising N1/N2 is reset therefore inputs C and D of the 7447
0111) outputs Ca, Cb, and Cc are con- and the output of N1 is low. This means are low, the B input receives data from
nected to the inputs of N11. When these that the data from IC9 (connected to the c output of the counter, while the
are all '1' (during July) the output of inputs a, b, c, d) is allowed through A input continues to receive 'a' data.
N11 is low. This takes the J and K in- N4/15, N5/16 and N6/N8 (data on in- During month 10 ( binary 1010) the
puts of IC6 low, inhibiting the change put a is connected direct to decoder) 7447 receives input code 0000 and thus
of state. N10 performs a similar func- and is decoded into the months (units) the display is 0. During month 11 (bi-
tion during the December/January tran- display. nary 1011) the input of the 7447 is
sition. The inputs of I1 , 12 and 13 are all con- 0001 (display 1) and during month 12
The 'February detection circuit' oper- nected to the output of N2, which is (binary 1100) the input code is 0010
ates as follows: the rather complicated high, so their outputs are low and the and the display 2. During this period the
looking array of gates performs the logic ten month display is '0'. If a leading ten month display is, of course, always
function: zero is not required on the ten month 1. At the end of the year, when the
`February transition' = display then these inverters may be month counter is preset back to 1, the
Cb Ca Cc Cd Bb Ad. omitted. When the month count reaches d input to the decoder goes low. This
Which is to say that the output of N13 10 (binary 1010) the output of N3 goes transition is differentiated by the 10 k
goes low when the month is February low, setting flip-flop N1/N2. The out- and 100 p on the input of N2, pro-
(binary 0010) and the day is 28 (Ad = 1, puts of II , 12 and 13 are now high, while ducing a short negative -going pulse that
Bb = 1). the output of 14 is low, so the ten resets the flip-flop.
The only point left to explain in fig- month display is 1. The month decoding of figure 4 oper-
ure 2 is the presetting of the month The low output of N2 inhibits the data ates on a somewhat different principle.
counter. This is allowed to count up to on the b, c and d inputs from passing Basically, for counts of less than 10 the
12. When the count reaches 12 out- through N4, N5 and N6. The high out - months units are decoded by IC2. For
puts Cc and Cd are high so the output counts from 10 to 12 the months units
of N7 holds the load input low. On the Month Number IC6 Q IC6 J and decoding is transferred from IC2 to IC3,
next clock pulse the counter is syn- of days outputs K inputs while IC2 counts the tens of months.
chronously preset to 1. January 31 0 1 The circuit operates as follows: for
February 28 1 1
month counts below 10 flip-flop N2/N3
Display Decoding March 31 0 1
is reset, so the output of N2 is low. Ti
To provide an intelligible display the April 30 1 1
and T2 are turned off and IC3 is in-
May 31 0
outputs of the three counters must, of June 30 1
1

1
hibited by a '0' on the blanking input
course, be decoded. Two alternative de- July 31 0 0 (pin 4). 1C2 thus decodes the data from
coding circuits are given, and the choice August 31 0 1
the output of the month counter.
is up to the constructor. Since the day September 30 1 1 When month 10 is reached the output
counters have BCD outputs these are October 31 0 1 of N1 goes low, setting the flip-flop and
easily decoded, in both figures 3 and 4, November 30 1 1 blanking 1C2. The display is now driven
using 7447 BCD/seven-segment decoder - December 31 0 0 by Tl and T2, which are turned on,
drivers. Although the circuits shown use Table 1. Number of days in each month and causing a 1 to be displayed. The low
Minitron displays, LED displays may the corresponding states of flip-flop IC6. state on the blanking input of IC3 is re-
equally well be used (with appropriate moved, and this decoder receives data
segment series resistors). Figure 5. Date setting circuit. on its A and B inputs from the a and
As the month counter counts to 12 in c outputs of the counter. Thus for
straight binary decoding is a little more Figure 6. Showing the addition of automatic months 10, 11 and 12 IC3 receives in-
difficult. The month decoding of fig- leap -year correction to the calendar. puts 0000, 0001 and 0010 respectively.

4 days units days tens months units/tens months units

T1

TUN

LI LI
T2

TUN

I- I
.211417.4 10,9
. _
15

f
741
9
13.112F1110
a bcd
9
e fgabcde 15 141 131121171 10
9abcd
15
19abcde
141 13 12 11(10_ 9

41f
IC2 IC3
7447 7447 7447 B 4 7447

DCBA DCBA DCBA DC

61 21 11 71 61 21 11 71
decoder
7

N1
decoder 61 7

A TOOP

1667-4

161 151141 13 10 161 1511411311211111°1 91

a bcdTL
12 101 121 11
151 141 13 91
0 a bcdTL
161 11

0 a bcdT L
1 19
IC1=N1...N3=7400
1
IC2,1C3=7447
IC7 = 74163 A IC8 = 74163 B IC9 = 74163 C

RCABCDPGND RCA B C DPGNo RCA BC D P GND

11 21 31 41 51 61 71 81 21 31
11 21 31 41 51 6171 81 41 9 81 71 81

see fig. 2
L
calendar Book 75 - 093

At the beginning of the new year the

flip-flop is reset in a similar fashion to 5 330 1-2 I 330 cl N1, N2, N4, N5 =
that of figure 3. 3
4 7400
N1 N2
Date Setting 5
N6, N7, N8, N9 =
7400
This is accomplished by the circuit of
figure 5. With SI S2 and S3 in the pos- N3, N10, N11 =
ition shown the three flip-flops com- 7412
prising N4 -N9 are reset. The outputs of
N4, N6 and N8 are thus high. One of
the inputs of N3 is held low by N5 so its
output is high, and both inputs of N11
are low, so its output is high. Two of fast setting
the inputs of NiO are high so the 24 -
hour pulses connected to the other in-
put can pass through Ni 0 and N12 to
the day counter.
If Si is now changed over flip- 4P--{ 5k6
flop N4/N5 is set blocking the 24 -hour
pulses through N10 and allowing a fast 1/4 IC3 ( fig. 2 1
pulse train from the astable multivi- 13 mak 12 12
11

brator N1/N2 through N3 and Ni 2. This single pulse

NIP MID
1

can be used for fast setting of the calen-

dar to some value near the required date. 24 h- pulse
If Si is now reset to its original position --{ 5k6
and S2 is changed over N10 is again
blocked by a '0' on pin 2. Pin 9 of N11 --I 5k6
is now high, so the calendar may be
advanced slowly to the correct date by 9
single pulses through N11, produced by step switch N11
alternately setting and resetting flip- 11

flop N8/N9 with S3. Flip-flop IC6 must,

of course, be set to the correct state for
5k6
the month, according to table 1. 13

In the 'versatile digital clock', a suitable

24 hour pulse is available at pin 8 of 1667.5

IC1 (FF2).

Leap Year Correction

The automatic leap -year correction is
extremely simple, and consists basically
6
of a divide -by -four counter that counts Aa Ab Ac Ad Ba Bb Bc Bd Ca Cb Cc Cd 5V
oo
the years and gives February an extra 5
? o

N7
B
4 NS
day every fourth year. The addition of
the leap -year correction to the calendar 16.

®
15(14113I
a bcd
12 11 10 19 16 15114 13112
abcd T
II 10 al
L 0 abcdTL
16 15114 13 12 11 10 91

circuit is shown in figure 6. The counter IC7 = 74163 A IC8 = 74163 B IC9 = 74163 C

consists of two JK flip-flops (IC10). ABC° Y GND B c D P nno CABCDPGNO

41 51 61
Once a year this counter receives a pulse 2 3 41 5161 7

31'15161"1
2 3 7

from output d of the month counter

IC9. Normally at least one of the Q out-
puts of IC10 will be low and the base of Ba
Bb
T1 will be held down via one of the two 2 N1 9 Aa

diodes connected to these outputs. T1 Ba

Bb
will thus be turned off. During the CC

cd: 01:1).
9
12

fourth year both these outputs are high, clock

removing the constraint on the base of Ca

14
IC6
E

Ti. Ti is now turned on and off on Imp clear

Cc

alternate days by N21, whose input is -

connected to output a of IC7. On odd Ca
1 1 1
days Ti is off, and on even days Ti is
on, holding pin 12 of N13 low. When RI% 4
Bb 3 10
I ICI = 7400 = Ni N4
IC2 = 7403 = N5, N6, N7, N13
.

Cc . MD - MO*
the 28th of February arrives the 'Febru- I

Ad . IC3= 7403= N10, N16, N17,N21

IC4 = 7412 = N8, N9, N11
ary detection circuit' will try to operate, MD- IC5 = 7405 = N12 N14, N15, N18, N19, N20
IC6 = 7473
but since it is an even day Ti is turned Cd
4
co. ID. Febr.load
IC7, IC8, IC9 = 74163

on and the output of N13 remains high.

It will not go low until Ti turns off on ED. 2k2
0 V
the 29th, and on the next clock pulse
the day counters are preset.
IC10 IC10
A = 24 h. clock pulse
Conclusion clock 0
from reset circuit
B = to units -of -days decoder
These circuits should enable the con- C = to tens -of -days decoder
D = to months decoder
structor to add a calendar to most digi- se ,3

tal clocks. The construction and type of 1X7473

4XDUS TUN
displays used are left to the reader's
individual preference, and presumably ,6616
1440.7

will be chosen to match the existing

clock.
094 - Book 75 compressor

0 ocno

They
sbceail

may be found in tape recorders,

intercom systems and baby alarms,
public address systems, disco-
theques and of course broadcast transmitters. A compressor supplements
a manual volume control and allows a system to adjust itself to a wide
range of input signals with little distortion.
The design described here should find a wide range of applications with
the electronics enthusiast.

The aim of compression constant whatever the input. This can- Figure 1. Block diagram of a p.a. system
Where signals with a wide dynamic range not be achieved in practice, but it is including a compressor.
have to be processed it is desirable that possible to limit the output to a narrow
range over a wide range of input signals. Figure 2. A first approach to a transfer
as little distortion as possible should function for a compressor. This is doomed
occur. The designer of, say, a public In a p.a. system (figure 1) a compressor to failure however.
address system may have given much could be included between the micro-
thought to achieving a good distortion phone preomp and the normal volume Figure 3. Black -box representation of a square -
figure, but this is of no avail if the control. The compressor, like death, is law compressor.
system is overloaded by an enthusiastic a great leveller.
speaker shouting into the microphone. Figure 4. a. Voltage -current curve of a fila-
It is of course possible to prevent a ment lamp. The resistance increases with
Compressor Transfer Functions increased current.
circuit from being overloaded by At first sight it would seem to be an b. Compressor using a lamp and a fixed
attenuating the input signal with a admirable aim to control the output resistor.
fixed or manually variable attenuator, signal amplitude with the input signal c. Transfer function of the compressor.
but then in the example above the as in figure 2. This system has an
person who mumbles into his notes Figure 5. a. Voltage -current curve of a VDR.
would certainly not be heard. overall gain of where K is a constant b. Compressor using a VDR and a fixed
This is where a dynamic range com- vi resistor. c. Transfer function of the com
pressor comes in. A compressor is and vi is the input voltage (for an pressor.
basically an attenuator, or variable gain attenuator of course the gain is less than
1). Figure 6. Dynamic characteristics of various
amplifier, which is controlled by the types of compressor in response to a sudden
signal it is attenuating, either directly viK
So Vo = = K. burst of signal.
or by a control voltage derived from the vi
signal. As the signal increases so does The output voltage is therefore constant Figure 7. Block diagram of an active com-
the degree of attenuation, so the com- for all input voltages. This seems admi- pressor using a peak detector to derive a
pressor tries to keep the output signal rable until one considers what happens control voltage which alters the attenuator.

2 3
gain= gain=
vi Vo

6019-2 6019-3
 Book 75 - 095
compressor

when vi is zero. The gain then becomes resistor (VDR) as in figure 5. This has distortion on sustained large signals,
infinite and this idea becomes unnat- a voltage versus current curve which is but will not react sufficiently quickly
tractive. approximately the inverse of that of the to prevent momentary overloads of the
A much better solution is to control the lamp, so it is included in the lower limb equipment, whereas a fast -acting com-
output signal with the output signal, of the attenuator. As the signal is pressor will react in time to prevent
which at first sight may seem odd. increased the resistance of the VDR overload, but will of itself introduce
In figure 3 however it can be seen that decreases so a smaller proportion of the distortion. Here, however, an unusual
signal appears across it. The response aural phenomenon comes to the de-
the gain is .
time of a VDR is quite fast so that it signer's aid. The ear is incapable of
V0
Kvi will follow sudden increases in signal detecting even large amounts of distor-
Therefore vo - amplitude, but unfortunately it can tion in transients, so that if a fast -
vo
2 also follow the signal waveform so that acting compressor is applied to a sudden
Or vo = Kvi instead of compressing the envelope increase in signal it will prevent gross
This is a square -law compressor func- amplitude whilst preserving the wave - overloading of the system whilst the
tion. Of course, other functions may be shape it simply 'rounds off' the signal distortion it introduces will be unno-
achieved, notably logarithmic, where peaks thus introducing distortion. None- ticed. Once the compressor has limited
vo = K log vi. theless, in certain applications where the signal, however, the ear can detect
distortion can be tolerated, such as the distortion it introduces, so on
Practical Compressor Circuits amateur radio transmitters or intercoms, sustained loud passages the slow re-
There are many different kinds of com- it does have its uses. sponse of the lamp -type compressor is
pressor circuit. One of the oldest and It thus appears that the compressor required. In fact what is required is a
simplest circuits makes use of the non- designer is caught between two stools. compressor with a fast attack and slow
linear resistance of an incandescent A slow -acting device will cause little decay characteristic.
lamp, whose resistance increases as the
current through the filament increases.
In figure 4 the resistance of the lamp, 6 Fr -F1 -1 -ITT -11,
which forms the upper limb of the
attenuator, is low at low signal levels so
only a small portion of the signal voltage input waveform
is dropped across it. At higher signal
levels the resistance increases and a
larger proportion of the signal voltage
is dropped across the lamp. The output
signal therefore does not increase as
much as it would with a normal attenu-
ator. The thermal inertia of the lamp
filament means that this circuit cannot
follow the actual signal waveform but slow acting compressor
only the envelope (provided the fre-
quency is not too low) so distortion
produced by the circuit is fairly small.
The thermal inertia of the filament
means, however, that the circuit cannot
respond quickly to sudden increases in distortion due to 'rounding off' of peaks
signal, so that associated circuitry may
be overloaded whilst the lamp resistance r 1'T r -r
is changing. Also the range of this type
of compressor is limited. fast acting compressor
An alternative solution would seem to
be the use of a voltage -dependent

5 V

vi
compressor with fast
attack and slow decay

\I\ 6019-6

Rfixed

7
VDR

input voltage- peak

stage controlled detector
attenuator

R2

T
6019-7
VOUt
6019 5
096 - Book 75 compressor

The characteristics of various types of directly by the signal on which they Figure 8. An LDR used in a voltage -controlled
compressor are given in figure 6. The operate, but for a device with different attenuator. This circuit suffers from slow
triangular waveform was used to show attack and decay time constants it is response due to the inertia of the lamp and
how distortion is caused by a fast - necessary to turn to active circuits. In LDR.
acting compressor. figure 7 the signal passes through the Figure 9. An r.f. carrier type of compressor.
The discussion has so far been confined input stage and into a voltage -controlled The filter eliminates harmonic distortion of
to passive devices that are controlled attenuator. The output voltage is taken the carrier caused by the attenuator and also
eliminates control -voltage noise.

parts list: Figure 10. Voltage -current curve of a diode

and circuit of a simple diode attenuator.
resistors 1/4 Watt: transistors: C12,C13 = 4711., 10V
R1,R4,R10,R12 = 10 k T1,T3 to T9 = BC 109C D1 = zener diode 2,7 V
Figure 11. Balanced type of diode attenuator
R2,R9,R21,R22 = 220 k T2 = BC 179C D2 to D5 = germanium diode
eliminates control -voltage noise which appears
R3 = 4k7 matched pairs AA 119
in common mode.
R5 = 220 E2 D6 to D8 = silicon diode 1N914
R6,R17,R20,R26 = 22 k capacitors: or 1N4148
Figure 12. The circuit of the final compressor
R7 = 1 k = 100 n design.
R8,1315,1316 = 330 k C2,C1 = 1 10 V
R11 = 270 k C3 = 180 p Figure 13. The printed circuit board and
R13,1R14,R25 = 3k3 C4 = 100 ,U, 16 V for Vb = 9 Volt: R18,R1g = 270 E2 component layout of the compressor.
R24 = 47 k C5,C9,C1 0 = 560 n and R23 = 1k8
R27 = 120 k C6 = 100 µ, 4 V for Vb = 12 Volt: R18,R19 = 330 E2
P1 = preset 22 k C7,C8 = 2,2 10 V and R23 = 1k5

9
input voltage
modulator band detector
0- stage
controlled
filter
attenuator

R1

carrier peak
R2 -- detector
oscillator

6019-9

Quiescent D.C. test voltage

measured with 50 k/V meter
Emitter T1 2.4 V
Emitter T2 8.8 V
Collector T2 5V
Collector T3 5.5 V
Emitter T3 3.3 V
Collector T4 and T5 6V
Collector T6 2V

12
0
9...12V R9 R10 R17

BC109 7
C9

BC179 C
R14 C7
BC109 Ca!, T4
1F R21
C13
-- R27 3k3 1-1
R20
560n
220k H

-I I-
C3
lOV 2p 2
10V R22
BC109 C 4
220k 17
R18 R25
180
100n R6 C10
R8
22k 3306
D2 ...D5 = -I 1560n BC109 C
R2
CS. AA119 BC109 C
R19 T6 R24
560n R16 DS
* 47k
BC109C 1N914
22k 0611 N914
R3 C12 P1 R13 C8
C4=MI
0 0-12L,3 _Hi I T9
R23
47p 1009
lOy 292 *
16 V 10V D7I1N914
Toy 912 R26 C11
C6r t DI BC109C
100µ mom
4V 2,7V 10V
T
O * see components list
6019-12
compressor Book 75 - 097

from the output of the attenuator and as otherwise the variations in control to be described was a diode attenuator.
is also fed to a peak detector which voltage with varying signal levels will In its simplest form (figure 10) it suffers
rectifies the signal. The rectified voltage appear as spurious noise at the output. from two disadvantages.
charges up the capacitor C via the One way of achieving this would be by 1. The signal voltage will itself vary the
potential divider consisting of R1 and using a light -dependent resistor (LDR) attenuation as with a VDR thus causing
(R1+ R2 ) as the lower limb of the attenuator, as distortion.
R2 . The time constant is C.
in figure 8. This would be controlled by 2. The control voltage will appear at the
R 1. R2
a lamp driven from the control voltage. output superimposed on the signal thus
The voltage on C increases the attenu- producing spurious noise.
ation of the voltage -controlled attenu- Unfortunately problems arise due to the The first problem may be overcome by
ator as the signal increases. If R1 is small slow response of both the lamp and the making the signal small compared with
C charges up quickly but since the dis- LDR. Another rather elegant solution the control voltage so that it has little
charge path for C is via R2 only, the is to amplitude -modulate the signal onto effect. The second may be prevented by
decay time constant can be made as a carrier and to vary the modulation using a balanced attenuator of four
large as desired so that the voltage on depth by a voltage -controlled amplifier diodes as in figure 11. The signal appears
C will not follow the signal waveform. stage (figure 9). The compressed modu- differentially at the input of the differ-
lated signal is then filtered to remove ential amplifier and is therefore ampli-
The voltage -controlled attenuator control voltage noise and distortion fied. The control voltage, however,
Whilst the derivation of a control voltage (mainly second harmonic) and is then appears in common mode and is there-
from the signal is a relatively simple demodulated, resulting in a 'clean' fore rejected.
matter the design of a suitable voltage - compressed signal. Intermodulation
controlled attenuator is another matter. distortion can still occur, but this can
Ideally the attenuator should be electri- be minimised by proper circuit design. The Final Circuit
cally isolated from the control voltage The design chosen for the final circuit Figure 12 shows the circuit of a simple

13

D1 0

13 1
-11

14
omr,
Lir-6
Di -c2- HPH0 6019
098 - Book 75 thief suppression in cars

Compressor Specification
Input impedance : 180 k
Output impedance : 25 k (do not

thief
load with less
than 100 k)
Gain with P, at
minimum : 60 (max. input

suppression
voltage = 1 V)
Gain with P, at
maximum : 150 (max.
input voltage =
30 mV)

in cars
Maximum (compressed)
output voltage : 500 mV
Maximum distortion
(gain = 60)
a. below compression
threshold : 0,4%
b. at maximum (1 V) Thefts of cars, or accessories and/or other articles in them, are becoming
input : 5% more and more common. By the same token, anti -theft alarms for cars
Maximum control
current through diode are becoming more and more of a necessity . . . .

bridge : 350 µA
Power consumption : 10 mA at 9 V

compressor intended principally for Each year an increasing number of cars

speech applications. The circuit has an are stolen. The majority of them are
input stage with adjustable gain which quickly recovered, but at best they have
is sensitive enough to be driven by a been abandoned on running out of
magnetic microphone. This is followed petrol, and often they are a total write-
by a phase splitter which produces two off, with everything of value removed.
antiphase signals to feed into the Thefts of articles from cars are still
differential stage T4, T5. The com- more common, especially now that ex-
pressed output is taken from the pensive in -car entertainment systems are
collector of T4 which should not be so popular. When compared with the
loaded with anything less than 100 k possible loss of property and/or no -
as this would upset the circuit oper- claims bonus, the cost of installing a bur-
ation. A class B -type stage T7, T8 drives glar alarm is negligible, and two designs
the peak detector D8, C11. The control are presented here, which should cost
voltage appearing on C11 is buffered by about 10 p and £ 10 respectively. Even
the emitter follower T9 and is fed to with an alarm installed, however, do not
the diode bridge D2 D5. D1 is a ignore the simple precautions advised by
threshold control which determines the the police. Lock all valuables in the boot,
point at which compression starts. T6 is and make sure that all doors and win-
simply a constant current source for the dows are securely fastened.
differential pair.
The board and component layout for
the compressor are given in figure 13 A very simple alarm.
and the performance figures in the table. The simplest of the burglar alarms can be
At first sight it may seem that the constructed from components that most
distortion with the compressor oper- enthusiasts will have in their junk box.
ating is rather high but compared with It makes use of the door courtesy light
the distortion when an amplifier is over- switches and the horn relay, and the
loaded it is minimal. only additional components required are
three diodes and a hidden switch to
Applications of the compressor activate and de -activate the alarm. How-
This compressor is sure to find a whole ever, one door of the car is left un-
host of applications. It can be used to protected.
control the recording level in a tape The circuit operates as follows:
recorder to prevent overloading of the Si and S2 are the courtesy light switches.
tape. It can be used in amateur radio When the hidden switch S3 is closed, Figure 1. Circuit of the simplest burglar alarm
installations to achieve the largest opening the door protected by S2 causes consisting of three diodes and a switch. The
possible modulation without over - the horn relay to operate via S3, D2 and door containing S1 is not protected. Ad-
modulating so that maximum range can S2. When the horn relay contacts close ditional door switches should be wired in
parallel with S2, other switches such as boot
be achieved. It can be used in a car the horn sounds and the cathode of D3 and glove compartment between point A' and
radio so that quiet passages may be is grounded via the relay contacts. This earth.
heard above the engine noise without latches the horn relay via S3 and its own
loud passages being unbearable. The contacts. The horn will continue to Figure 2. Block diagram of the sophisticated
range of applications is limited only by sound even if the door is closed, unless alarm.
the ingenuity of the constructor - S3 is opened. The door containing Si is,
remember, a compressor rules the waves of course, not protected, as when Si is Figure 3. Timing diagram of the alarm of
closed D1 is reverse biased and only the figure 2.
(somewhat straighter than they were
originally ! ). interior light operates. Figure 4. Circuit of the sophisticated alarm,
When the alarm is not armed (S3 open), which uses COSMOS IC's.
D2 prevents the interior light from light-
Bibliography: ing when the horn button is pressed and Figure 4a. Alternative method of wiring the
Electronic Engineering, January 1973. D3 prevents the horn from sounding horn and horn relay, for cars with one side of
Radio Elektronika, January 1959. when the interior light is switched on. the horn connected to chassis.
thief suppression in cars Book 75 - 099

Additional courtesy light switches (in the alarm by inserting the ignition key and When S1 is opened Cl begins to dis-
case of a four -door car) may be connected turning it to the first position (without charge through R1 and R2. When
in parallel with S2, and switches to pro- actually switching on the ignition). On the voltage on Cl falls below the
tect glove compartment and other ancil- cars without a steering lock, however, threshold voltage of gate 2 then the
lary equipment may be connected be- it will be necessary to use a separate flip-flop consisting of gates 1 and 2 is set.
tween point 'A' and ground. concealed switch - or a separate lock - This holds the input (pin 13) of gate 4a
This simple alarm will provide a fair de- switch. high, which means that when one of the
gree of protection at little cost, but it A timing diagram of the alarm is given door switches (represented by S2) closes,
should be noted that alarms which sound in figure 3. On removing the ignition the flip-flop consisting of gates 3a and 4a
indefinitely after being triggered are key from the lock the driver has about is set. The alarm is triggered, and even
illegal in some European countries. one -and -a -half minutes to leave the car closing the door (opening S2) will not
and lock the doors. If a door is sub- reset the flip-flop. C2 and C3 were
sequently opened there is a delay previously charged through 6 and D3
A sophisticated alarm. (adjustable from 5 to 15 seconds) to from the output of gate 1 a. 02 and C3
A block diagram of a more sophisticated allow the driver to reset the alarm with now discharge through R5 into the out-
burglar alarm system is given in figure 2. the ignition key. Failing this, the alarm put of gate 4a. C3 may be optionally
In many modern cars with a steering operates and the horn will sound switched in by S3 to increase the delay
lock there is no need to have a con- continuously for 30 seconds. After this before the alarm sounds. With S3 closed
cealed reset switch as a position is there is ten seconds silence, then short the delay is about 15 seconds; with S3
often available on the ignition switch three second blasts with ten seconds open the delay is only 5 seconds. If this
that only opens when the switch is in silence in between until the alarm is facility is not required S3 and C3 may
the 'locked' position. It is thus possible, reset or the door is closed. The complete be omitted and C2 replaced by a capaci-
on entering the car, to de -activate the circuit of the alarm is given in figure 4. tor chosen to give the required delay.

3 door closed

ignition off alarm set door open alarm alarm alarm

silence I silence I alarm set
I 1,Z I
I I .

(11/2min) (5 ... 15s ) (30s) (lbs) I (10s) I 1592 7

(3s) (3s )

4
battery

1A 6A
0
R3
22k
188 113 _1115 R18
D4 D5

X
1011 10011
R9

V
7

TUP

-
10p
R6 16V
2

R11 12

R5
100k

CD4011A
R1
220p
220p D6 16v
16V

D1...D8= DUS
0
100 - Book 75 thief suppression in cars

S4 may be a trembler switch or switch(es) Gates lb and 3b thus form an asymmetric possibility would be to power the alarm
on glove compartment, boot etc., which multivibrator which causes the horn to from a separate battery locked in the
will discharge C2 and C3 rapidly and produce short blasts at 10 second inter- boot. Wiring from the battery to the
trigger the alarm. vals. In addition, each time the horn is alarm should, of course, be direct, not
When C2 and C3 have discharged the switched off a differentiating network via the ignition switch, and the simplest
output of gate 2b goes high. This takes consisting of R8, R9, C4 and CS feeds way is to run cables from the battery
pin 6 of gate 1 b high. Since the other a reset pulse to pin 9 of gate 3a, so that side of the fuse box with in -line fuse
input is held high by R13 the output goes if the doors are closed during the horn holders in them.
low, turning on T1 and T2 and sounding `off' period, the horn will not sound When constructing either of these alarms
the horn. C8 charges through R14 and again and the alarm will be re -set. it should be borne in mind that they
R15 in about 3 seconds, taking pin 13 of The only disadvantage of this alarm cir- may need to be adapted to suit particular
gate 3b high. Meanwhile C6 slowly cuit is that it cannot easily be adapted types of car. For instance, some horn re-
charges through R11 and it is this time for positive earth cars. On the other lays have one end of the coil and the
constant that determines the duration hand, it has the advantage that it is contact commoned, so they would not
of the initial blast of the horn (about insensitive to spurious pulses due to work in the circuit of figure 1. A separate
30 seconds). the high noise immunity of COSMOS. heavy-duty relay (6A contacts) would
When the voltage on C6 exceeds the The circuit will operate over a wide have to be used. This problem does not
threshold voltage of gate 3b the output range of supply voltages without modi- arise with the more sophisticated design,
of this gate goes low, grounding pin 5 of fication (4 to 14 volts), with almost the and a normal horn relay may be used. A
gate lb through C7 and R12. The output same delays. printed circuit board layout is given in
of lb thus goes high and the horn figure 5 for the alarm circuit of figure 4
switches off. C8 now discharges through and this has alternative sets of connec-
D7, R14 and the output of gate lb. C7 Installation of the alarm tions for the relay, as shown in fig-
slowly charges through R13 and R12, To ensure reliable operation the alarm ure 4a, to suit different car wiring. S5 in
and this time constant determines the should be mounted where it cannot be both circuits is the original pushbutton
`off' period of the horn (about 10 sec- disabled by a thief, but not inside the for the horn.
onds). When C7 has charged to the engine compartment, which gets rather
threshold voltage of gate lb the output hot for COSMOS. Wiring should be con-
goes low and the horn again sounds. C8 cealed or made as inconspicuous as Final Remarks
charges through R14 and R15, and this possible, especially wiring into the engine The designs discussed in this article give
time constant determines the subsequent compartment if the car does not have varying degrees of protection at varying
`on' periods of the horn (about 3 sec- a bonnet lock. In this case it is also wise cost. It should be remembered that any
onds). to install an alarm switch in the bonnet protection is better than none - the
After this period the output of 3b goes lid, as otherwise the alarm could be dis- majority of thieves are amateurs and
low, grounding pin 5 of gate lb through abled simply by disconnecting the bat- will be deterred by even the simpler
R12 and C7, and the whole cycle repeats. tery. Another (somewhat expensive) circuit described

O
Components list for
figures 4 and 5.

Resistors: RB }-
R1,R6 = 10 k
R2,R15 = 470 k
R3,R7,R9,R10,R16 = 22 k 40.--1 R9 1-
R4,R5,R8 = 100 k
R11= 180 k RB 1--
R12,R14 = 47 k
R13= 1M5
R17= 1 k
R18 = 4k7

Capacitors:
R 1-110
C1,C6 = 220 A/16 V
C2 = 47 A/16 V
C3= 1O0µ/16 V T.41.
C4 = 10 n
C5 = 100 n
C7,C8 = 10 A/16 V NEM
4 4 .1 4 4 4
Semiconductors:
ICa,ICb = CD4011A
R12 I-. ..-40115)--.
T1 = TUP
T2 = BC140 or equ.
D1 ... D8 = DUS

Figure 5. Board and

component layout for
figure 4.
time signal simulator Book 75 - 101

the logic '1' level only being used for marked by a 'pip' of a length of about
decoding. The code shown in the dia- 1 second.
gram corresponds to the moment 59'55". The tone itself appears at the input of
The period of MF1 monostable is about N4. If the clock is crystal controlled it
6 seconds. During this period mono - may be possible to derive a frequency of
time signal stable MF2 is triggered by a 1 Hz signal
at (C), as shown in the pulse diagram,
around 1 kHz from the divider circuitry
in the clock. Otherwise a simple 1 kHz
its B input being logic '1' (B). The MF2 multivibrator may be used.
simulator monostable period has been set to about
100 millisec, which permits MF2 to be
N

triggered every second. The result is a

signal at (D).
Until the turn of the hour, the minute -
unit mark remains logic '1' (E). Ni

la 1Hz I kHz

0 0
5V

47k 47k

DUS
22µ
DUS 6.3V DUS 500E2 -
16:33TP C

sec.<
units < OA
`"'c
OA0
3'-
Clear2 11
RkA
2K

dear
tens < oC MF1 MF2
10 12
nA 0
units '
7430
a 3 N 4> MF1 = 6 s
MF2 = 100 ms
O
Min<
tens <
0D
0c
0
N1
1y MF1+MF2= 74123
N1...N4 = 7400
9308-1A

This circuit generates a 'six pips' signal inverts this level, causing the signal at
indicating the exact hour. (F) also to be '1'.
At the instant the first 'pip' is to start, At the instant 00'00, N2 by-passes
an eight -input NAND gate, which MF2. This means that MF2 only deter-
receives BCD -coded minute and second mines the length of the first five 'pips'.
marks from a TTL clock, transmits a The length of the sixth 'pip' is deter-
mined by the remainder of the MF1
negative -going edge to MF1 (at A). Each
digit requires not more than two inputs, period (G). The new hour is, thus, afterburner
lb XX: 59:55 XX: 59:56 XX: 59:57 XX: 59:58 XX: 59:59-XX: 00:00 XX: 00:01 W. Ferdinand
I 1 I

When starting a car journey after dark it

is useful to have a device which will
keep the interior lighting on for a while
after the doors have been closed, and so
B make it easier for the occupants to
fasten safety belts and insert the ignition
key. This can be done with the simple
time -switch circuit shown.

12V

1N4001or equ

interior
2 light switch

DUS door
G contact
3231
93 08 -18
102 - Book 75 fido

A. Seitz

fi Fido is a new electronic game in

which an unfortunate dog is called
by four masters at the same time.
The command "Fido come" is given by means of a pushbutton. At each
push on one of the four buttons controlled by each player Fido jumps in
the required direction. However, the four masters and/or mistresses have
one handicap: After one successful command to Fido, the would-be Fido
owner who has given the order has nothing more to say for a certain
time. Then the other players can go on with Fido. If one of the players
succeeds in getting Fido into his kennel, the game is decided: Fido stays
where he is.

Construction and operation by nine lamps arranged in a square. These The game is started by pushing the
Since Fido is clever enough to let him- lamps are located at the intersections of starting button; then all the "kennel"
self be represented by a small incan- 3 x 3 matrix rails. The signals for these flipflops are reset and the two shift
descent lamp, he is not going to suffer rails are driven by two left/right shift registers take up a central position. In
from an otherwise unavoidable nervous registers. The clock pulses to the registers that case the middle lamp is alight.
breakdown. The worst that can happen is are produced by the players pushing one
that after a prolonged fight for mastery of the buttons. Since each player has The left/right shift register
over Fido our doggy will suffer from a four buttons at his disposal, Fido can be Figure 3 shows how a flipflop can be
flat battery. sent in all directions including the kennel turned into a "flipflopflap". The inputs
On the playing board nine lamps are of another player. of each nand are connected to the 'out-
arranged in a square (figure 1). On the The directing signals for left, right, up puts of the other nands. Consequently,
extension of each side there is a lamp and down are coupled into the registers only one output at a time can be low
representing a kennel (so in total four). via the multiplexer. Once in a corner, the ("0"). This "0" -signal produces a high
Furthermore, at each of the corners dog can be made to jump into the kennel output level ("1") at all the other nands;
there are four push buttons with a pilot situated below the corners as seen from these high levels in turn cause the low
lamp to indicate when a player can join the player's position. The register input output level on the first nand. A negative -
the game. The buttons make Fido jump driving the "kennel" flipflop is so con- going pulse on one of the coupling rails
in four directions (away, towards, left or nected that the command for jumping causes all nands connected to this rail to
right with respect to the particular is only followed if the other register, too, change to "1", whereas the nand whose
player). The photograph also shows that is in the proper position. The lamp field output is connected to this rail ensures
the "gaming table" is provided with an is blocked to prevent lamps from lighting that this rail remains "0".
on/off switch, an interval switch (coarse) up after a jump into the kennel. At the If gates with a so-called totem -pole
and an interval control (fine) for setting same time all register outputs are blocked output are used (7400, 7420 and 7430)
the obligatory rest period for the players. so that no more "kennel" flipflops can the outputs must be separated by means
These switches can be calibrated "blood- be driven. of a diode as otherwise none of the
hound/whippet" and "dog-tired ... alert"
respectively.
Furthermore there is a switch to disable
the "rest" lamps and there is also a
starting switch By pushing this button,
Fido takes up his position in the centre
of the field; i.e. the middle lamp is alight.
By pushing one of his buttons, each
player can now try to direct Fido into
his kennel. Once a player has pushed a
button, he is obliged to take a breather
before he can push a button again. The
lamps fitted near the buttons indicate
when the next command can be given.
Each player can give only one command on/off bloodhound/whippet dog-tired alert

at a time. If an impatient player pushes

his button too soon, the penalty is a new
on/off
start of the waiting period. So Fido will
not respond to a command that comes start

fine Interval control

too early. coarse interval control

To make the game a bit more exciting, pilot lamp

the pilot lamps can be switched off, so
that each player must just guess when he
may next give a command.

The block diagram

Fido's position in the field is indicated
 Book 75 - 103
fido

Figure 1. Artist's impression of Fido.

2 command units
Figure 2. The block diagram. The command -
units also comprise the waiting time indication.
The push button "start" resets all "kennel"
flipflops and sets the registers at the central
0 0©
positions, so that the lamp in the center of the @@ 0
field lights up. Multiple connections between
the circuits are indicated by means of broad
arrows.

Figure 3. The development of a multiple

flipflop starting from the fundamental prin- multiplexer
ciple.
a. Two methods of drawing a simple flipflop
b. A 3 -fold flipflop
c. A 5 -fold flipflop.

horizontal vertical

shift start shift

register register
kennel II kennel I

'kennel' kennel'
outputs would change to low (figure 3c). flipflop flipflop
With types with an open collector output
this is not strictly necessary, although
it is recommended to keep the input load
lamp blocking
of the pulse low.
In that case the "0" must, after each
pulse, shift one position to the right,
d'kennel'
left, top or bottom. So we need a 'kennel' '
flipflop
memory which remembers what coupling
rail is carrying a "0" signal before the kennel IV
flipflop
IV III 0
kennel III
pulse, and a circuit that determines
in what direction the shift should take
place.
The memory by C1, (C2, C3, field
figure 4); the direction of shift is deter-
mined by two nands (N3 and N4, N5 and O00
N6, N7 and Ng) which receive their sig-
nals via N1 and N2. When the button is O 00
pushed, say left, this is what happens:
Via N1, connected as an inverter, the
O00
"1" signal is fed to the nands N3, N5 and
N7 via the "left" conductor. At the same
time all the connecting rails are brought
to the "0" level via the diodes D1, D3, 1,150 2
D4 and D5 . As a result, the nand N9,
 104 - Book 75 fido

4 9

"kennel" 11(111)

46 - - -0
"kennel" flipflop
"kennel" IV(I)

0 ---
"kennel" flipflop

0 4,5 V
I::
0,47p
R61 iR10
o, R11

'
R I
D5 left (top)

centre (hor) coupling

ii
C/3
!centre (vert) rails

D6 D7 8 right(bottom)

y N5
C2
r6\ A ei C3 111
start

from matrix line

1

11p ipli ip
"top (right)
R3 I. 4 R5--' C5

. ..
.
2 information inputs

from matrix line

° "bottom" (left)

-1 N4 ... N7, Ng ... = 1/4 7401

I

N1 N3 + Ng = 7420
I LI
Ni + N2 = 1/2 7400

Di D9 = DUS
left (top) o pulse inputs o right (bottom) 1490-

5 Figure 4. Complete "shift register for a zero",

3 -fold, for the matrix line of the horizontal
shift register. The vertical register is of the
same construction (description between
brackets).

pulse outputs Figure 5. Field with waiting time indication

II
Depending on the type of field used, the trigger
4 13
T7 TO
unit is required several times. It serves to sup-
TUP TUP accelerated Id press contact bounce.
T8 T6 6
waiting time
!

A V RIS
Figure 6. Diagram for Fido with nine lamps.
normal 4,56 If the whole is fed from batteries, it is advisable
UN TUN
916 915 to supply the lamps from a separate battery
P1 ri because pulses caused by switching (low
R14 T10
5
filament resistance of an extinguished lamp)
R13
TUN might interfere with the circuit. The bias of
S2 C6
MIMI X
010 C6 (figure 5) must also be obtained from a
2.2p 419 separate battery because a maximum current
3
DUS of about 200 mA can occur.
TUN TUN -R12
command unit
TUP TUP
S4
indication
010 @
S2 S1

pulse outputs S3

14 90
O
5

N10 or N11, which has been at "0" level conductors become logically "1". In the extreme positions for the "shift
so far, changes to "1". Simultaneously, The contact potentials of the diodes D1 register for a zero", the "kennel"-
a positive pulse is fed to the two adjacent and D3 up to and including D5 ensure flipflops N12 -N13 and N14 -N15 are driven.
nands via the capacitor connected to this that the coupling rails reach the "1" These may be driven only when the sec-
output. The gate thus prepared by the potential before the inputs of the gates 1 ond register reports the correct position.
"1" signal via the conductor "left" or 2. This is necessary to ensure that the The outer direction determining gates N3
maintains the collecting line of its neigh- new main nand takes over the "0" signal and N8 , which drive the "kennel" flip-
bour at "0" until again via diode D1 the before the direction determining gate flops require three inputs for that pur-
"0" signal disappears and the remaining changes back to "1". pose; one being coupled to the corre-
fido Book 75 - 105

6 waiting time (coarse)

GND IN 0 GND IN (H) GND IN 0 GND IN

waiting time (fine)
command unit 2k 5
long
I
IV
waiting time
RI
pulse outputs
2 2 2 3
multiplexer II

waiting time
indication on

1/2x 7405
right
pulse
left GND 0 from
top bottom
pulse inputs
right
inputs "right"
11

coupling information
rails centre inputs
from vertical
horizontal left left"
1/2x 7405 register
register L_
from top GND
.top^ 11
informatio
inputs coupling
centre rails
11

from lamp field

"kennel" outputs bo t .blocking "kennel" outputs 11

bottom
II IV sta t start I III 11

11

inw"1-4-1. 11

D1214
"1.1215

lx 7400 41 . 1 x 7400
6x DUS

0
111

151 lx 7440
-lx 7440 ,

L L.
kennel II kennel IV kennel I
kennel III
2x :4 2x
o:o
6V 06# 6V
50 mA 50 mA
1x 7420

7405

ij field
lamp drivers
5 x 7440

lamps
9 x 6V/50mA

0. ki4

1490

sponding matrix line of the other register. the contact potentials of diode D10 and capacitor C6, so that the emitter of Ti
the base -emitter junction of T9. The drops from +4,5 V to +0,7 V. This pulse
Command -unit with indication latter is then conductive, so that T10 serves to drive the shift register.
Figure 5 shows a command -unit with causes the lamp to light up. The pilot Due to contact bounce, Fido is likely to
four push buttons. The other units are lamp indicates when a command can be make wild and unpredictable jumps, or
similar. given. The waiting time can be adjusted just stays where he is. To avoid such
Via P1 and R17 or R18, respectively, with P1. "disobedience", each push button must
capacitor C6 is negatively charged until When pushing a button, say S1 , T1 is be connected to a trigger. Even the
the voltage across C6 equals the sum of turned on by the negatively charged shortest pulse at the base of T1 is suffi-
106 - Book 75 fido elektor services to readers

Figure 7. Arrangement of
7 elektor
the "kennel" lamps for a O
field of 5 X 5 lamps.
services
Figure 8. Mini Fido. 0 O O00 to readers
0 O O000
0 O O00 EPS print service
Many elektor circuits are accompanied
00 O O 0 0 'D by printed circuit designs. Some of these
designs - but not all! - are also available
as ready -etched and predrilled boards,
0 O O00 which can be ordered from our Canter-
bury office. A complete list of the
available boards is published under the
'kennel' A
0© heading 'EPS print service' in every issue.
Delivery time is approximately three
weeks.
As a further service, boards which are
taken off the regular service list at some
0 push buttons future date will continue to be available
V in spite of this; delivery time will then
1490-7 be approximately six weeks. It should
be noted, however, that only boards
8
©0 0 0 0 0 0 0© 1490-8
which have at some time been published
in the EPS list are available; the fact that
a design for a board is published in a
particular article does not necessarily
imply that it can be supplied by elektor.
cient to cause the two transistors (T1 and rails must be connected to the reset
T2) to switch. As a result capacitor C6 is conductor via the diodes (D9 in figure 4). Technical queries
connected to the control line until the The words "left", "right", "top", "bot-
voltage drop across R13 caused by the tom", "vertical" and "horizontal" are Members of the technical staff will be
related to a group of push buttons which available to answer technical queries
charge current is no longer high enough, (relating to articles published in elektor)
and the trigger returns to its initial is fixed by an arbitrary position of a by telephone on Mondays from 14.00 to
position. Then capacitor C6 discharges player and is called command -unit 1. The
other command -units are numbered 16.30. Queries will not normally be
across R17 (R18) and P1. answered at other times.
clock -wise. The arrows in figure 5 are
related to the way in which Fido moves Letters should be addressed to the
The complete diagram as regards the player concerned. department concerned: TQ = Technical
Owing to the large extent of the circuit, Queries. Although we feel that this is an
some of the sections are represented as essential service to readers, we regret that
blocks in figure 6. The positions indicated Variations certain restrictions are necessary:
by the coupling rails are represented by The game can easily be changed. A first 1 Questions that are not related to
"0" -signals. For the remainder, only possibility is to expand the field so that articles published in elektor cannot
"1" -signals are used; hence the inverters the game will last longer (figure 7, accord- be answered.
7405 for inverting the signals. These ing to the principle in figure 3c). This will, 2. Questions concerning the connection
signals are fed to the lamp drivers 7440 of course, increase the cost of the unit of elektor designs to other units (e.g.
which cause the lamps to light up when by a considerable amount, especially if existing equipment) cannot normally
all inputs are "1". the 25 lamp version of figure 7 is used. be answered, owing to a lack of practi-
Since only two of the four inputs of the Furthermore, it should be noted that the cal experience with those other units.
lamp drivers are used, all the others can field is in fact only suitable for four or An answer can only be based on a
be connected to the positive of the eight players, whereas the smaller field comparison of our design specifi-
supply, which, however, is not necessary. can also be used by two without Fido cations with those of the other equip-
Once Fido has disappeared into a kennel, endlessly running up and down. ment.
that is to say: when a "0" signal has On the other hand, the field with 3. Hieroglyphs or illegible handwriting
reached the input of a goal flipflop, a 25 lamps can easily be connected to eight cannot be decoded; provided the
"1" is produced at the driver of the goal command -units, so that eight "dog sender's address is legible, the letter
lamp, and a "0" at the gate N20, lovers" can join the game. is returned unanswered.
which via the inverter N21 and six A "mini Fido" is also a possibility if we 4. Questions about suppliers for com-
diodes D11 up to and including D16 trans- restrict ourselves to one register (see fig- ponents are usually answered on the
fers this signal to the outputs of the ure 3c), and if the "kennels" are placed basis of advertisements, and readers
inverters II up to and including 16. As a at the two ends of the row of lamps (fig- can usually check these themselves.
result all the lamps in the field are ex- ure 8). In spite of the simple set-up the 5. As far as possible, answers will be on
tinguished. Furthermore, all the outer game can still be fun; playing with the standard reply forms.
direction -determining gates (figure 4) are push buttons alone is most amusing. In We trust that our readers will understand
blocked ("0" -signal at the inputs that are addition this version offers the possibility the reasons for these restrictions. On the
connected with the inverter outputs), of studying the register. one hand we feel that all technical
so that no further goal can be scored Of course, other possibilities can be queries should be answered as quickly
by the now invisible Fido, if more but- worked out, but then again it is up to the and completely as possible; on the other
tons were pushed. reader to find an arrangement in accord- hand this must not lead to overloading
The start- or reset button returns the goal ance with his taste and, lets face it, of our technical staff as this could lead
flipflops and the registers to their initial budget. to blown fuses and reduced quality in
positions again. The middle coupling N future issues ...
Manufacturer Colour Pin Function Performance Maximum Dimensions h Pin connections and per-
Type number
1 2 3 4 5 6 7 8 9 10 11 12 13 14 Data Ratings W H D formance data for common -
XP ly Vfs Vfd @° If Vrs Vrd lay Ptot anode 7 -segment LED dis-
plays.
Boss BIM -72R Red a f A np
np L e d nc c g np b A 697 0.25 1.9 19 10 5 5 25 400 10 19 4.6 7.7
Boss BIM -52G Green a f A np
np L e d nc c g b
np A 560 0.25 1.9 1.9 10 5 5 25 400 10 19 4.6 7.7
Boss BIM -82Y Yellow a f A np
np L e d nc c g b
np A 580 0.25 1.9 1.9 10 5 5 25 400 10 19 4.6 7.7
Dialco 745-0006 Red a f A np
np L e d A c g b
np A 650 - 3.2 1.6 20 6 3 30 380 10 19 3.0 6.9
EEP EP1 Red a f nc nc nc L e d nc c g b
nc A 690 1.0 2.1 2.1 15 5.5 5.5 40 750 10 19 3.2 8.5
EP21 Red a f L e d nc c A 697 0.25 1.9 1.9 10 5 5 25 400 10 19 4.6 7.7 Explanation of Symbols.
EEP A np np g np b
d nc c A 560 0.25 1.9 1.9 10 5 5 25 400 10 19 4.6 7.7 a -g Segment cathodes.
EEP EP21G Green a f A np np L e g np b
10 5 5 25 400 10 19 4.6 7.7 L Left-hand decimal
EEP EP21 Y Yellow a f A np np L e d nc c g np b A 580 0.25 1.9 1.9
2.2 2.2 20 3 3 40 750 10 19 3.2 8.5 point cathode.
EEP EP27 Red a f nc nc nc L e d nc c g nc b A 690 0.30 R Right-hand decimal
EEP EP28 Red a f nc nc nc L e d nc c g nc b A 690 0.60 2.2 2.2 20 3 3 40 750 10 19 3.2 8.5
point cathode.
Hewlett-Packard 5082-7730 Red a f A np np L e d nc c g np b A 655 0.25 1.6 1.6 20 6 6 25 400 10 19 4.6 7.6
Upper decimal point
Hewlett-Packard 5082-7731 Red a f A np np nc e d R c g np b A 655 0.251.6 1.6 20 6 6 25 400 10 19 4.6 7.6 (colon) cathode.
Hewlett-Packard 5082-7750 Red a f A np np L e d nc c g np b A 655 0.25 1.6 1.6 20 6 6 25 400 13 19 6.4 11.0 A Anode.
d b 1.6 1.6 20 6 6 25 400 13 19 6.4 11.0 nc No connection.
Hewlett-Packard 5082-7751 Red a f A np np nc e R c g np A 655 0.25
nc b 3.4 1.6 20 6 3 30 750 10 19 3.0 6.9 np No pin.
Litronix DL1A Red a f A nc nc L e d A c g A 630
19 3.0 6.9 Xp Peak emission wave-
Litronix DL10 Red a f A nc nc L e d A c g nc b A 630 3.4 1.6 20 6 3 30 750 10
length (nanometres).
Litronix DL10A Red a f A nc nc L e d A c g nc b A 630 3.4 1.6 20 6 3 25 650 10 19 3.0 6.9
Iv Luminous intensity
---
L e d c nc b A 630 1.4 1.7 1.7 20 3 3 30 500 11 20 7.4 7.6
Litronix DL707 Red a f A nc nc A g (millicandelas) at
Red a f A nc nc R e d A c nc b A 630 1.4 1.7 1.7 20 3 3 30 500 11 20 7.4 7.6 specified forward
Litronix DL707 R g
Monsanto MANI Red a f A nc nc L e d A c g nc b A 630 3.4 1.6 20 6 3 30 750 10 19 3.0 6.9 current.
Monsanto MANIA Red a f A nc nc L e d A c g nc b A 630 3.4 1.6 20 6 3 30 750 10 19 3.0 6.9 Vfs Segment forward
-- 40 960 11 20 5.8 6.9 voltage at specified
Monsanto MANS Green a f A np np L e d A c g np b A 565 0.23 2.5 2.5 20 3 3
30 960 11 20 5.8 6.9 current (volts).
Monsanto MAN7 Red a f A np np L e d A c g np b A 630 0.2 2.0 2.0 20 5 5
11 20 5.8 6.9
Vfd Decimal point for-
Monsanto MAN8 Yellow , a f A np np L e d A c g np b A 589 0.25 2.5 2.5 20 6 3 40 960
ward voltage drop at
Monsanto MAN51 Green a f. A np np R e d A c g np b A 565 0.32 2.5 2.5 20 3 3 30 700 10 20 5.0 7.6 specified current
Monsanto MAN52 Green a f A np np L e d A c g np b A 565 0.32 2.5 2.5 20 3 3 30 700 10 20 5.0 7.6 (volts).
Monsanto MAN71 Red a f A np np R e d A c g np b A 650 0.30 1.6 1.6 20 5 5 30 700 10 20 5.0 7.6 @If Specified forward
Monsanto MAN72 Red a f A np np L e d A c g np b A 650 0.30 1.6 1.6 20 5 5 30 700 10 20 5.0 7.6 current (milliamps).
R e d A c b A 590 0.34 2.5 2.5 20 3 3 30 700 10 20 5.0 7.6 Vrs Max. segment reverse
Monsanto MAN81 Yellow a f A np np g np
20 3 3 30 700 10 20 5.0 7.6 voltage (volts).
Monsanto MAN82 Yellow a f A np np L e d A c g np b A 590 0.34 2.5 2.5
10 20 5.0 7.6
Vrd Max. decimal point
Monsanto MAN3610 Orange a f A np np R e d A c g np b A 630 1.2 2.0 2.0 10 3 3 20 400
reverse voltage (volts).
Monsanto MAN3620 a f L e d A c g np b A 630 1.2 2.0 2.0 10 3 3 20 400 10 20 5.0 7.6 Max. continuous for-
Orange A np np lav
Red a f nc nc nc L e d nc c nc b A 690 1.0 2.1 2.1 15 5.5 5.5 40 750 10 19 3.1 8.4 ward current per
Norbain NOR1 g
NDP1 Red a f nc nc nc nc e d nc c g nc b A 690 1.0 2.1 15 5.5 - 40 750 10 19 3.1 8.4 segment (milliamps).
Norbain
NOR1R Red a nc f d c
nc nc nc R b 690 1.0 2.1
-
2.1 15 5.5 5.5 40 750 10 19 3.1 8.4 Ptot Max. total device
Norbain g nc e A
A 690 1.0 2.1 2.1 15 5.5 5.5 40 750 10 19 3.1 8.4 dissipation (milli -
Norbain NOR1C Red a f j nc nc L e d nc c g nc b
750 10 19 3.1 8.4 watts).
Norbain NOR7 Red a f nc nc nc L e d nc c g nc b A 690 0.3 2.2 2.2 20 3 3 40
W Width (millimetres).
NOR8 Red a f nc nc nc L e d nc c g nc b A 690 0.6 2.2 2.2 20 3 3 40 750 10 19 3.1 8.4
Norbain H Height (millimetres).
SLA1 Red a f nc nc nc L e d nc c g nc b A 690 1.0 2.1 2.1 15 5.5 5.5 40 750 10 19 3.2 8.4 D Depth (millimetres).
Opcoa
SLA7 Red a f nc nc nc L e d nc c g nc b A 690 0.3 2.1 2.1 20 3 3 40 750 10 19 3.2 8.4 h Character height
Opcoa
SLA11 Green a f nc nc nc L e d nc c g nc b A 560 0.7 2.6 2.6 40 5.5 5.5 50 1480 10 19 3.2 8.4 (millimetres).
Opcoa
SLA21 Yellow a f nc nc nc L e d nc c g nc b A 580 0.7 2.6 2.6 40 5.5 5.5 50 1480 10 19 3.2 8.4 All the parameters listed
Opcoa
TI L302 Red a f A np np L e d A c g np b A 650 0.28 3.4 1.6 20 6 3 30 800 10 19 3.0 6.5 are measured at 25°C.
Texas
Red a A f g np e c R np np A b 650 0.28 3.4 1.6 20 6 3 30 800 10 19 3.0 6.5 Values are typical, except
Texas TI L303 Ad
1.9 1.9 10 5 5 25 400 10 19 4.6 7.7 for maximum ratings
Xeiton XAN72 Red a f A np np L e d nc c g np b A 697 0.25
19 4.6 7.7
which must not be
Xeiton XAN52 Green a f A np np L e d nc c g np b A 560 0.25 1.9 1.9 10 5 5 25 400 10
exceeded.
XAN82 Yellow a f A np np L e d nc c g np b A 580 0.25 1.9 1.9 10 5 5 25 400 10 19 4.6 7.7
Xeiton
 IrIli
108 - Book 75 mos-ics

VDD GM L . EXTERNAL ,A11.;1-

41. V
8 ,,,
26
c: RESISTORS
F,5,-_, 0 0
,,

r
0 MailmilamamanEl-El VDD G H
A 8,,,o 10-111-10-11-11:-C1-0
.c, Z

Ti
,..., (JO R2 in 0 (5')
10-11-111 1:1-C1-CI-a VDD 14 ri, RI

a_a_a..:_a_a_c...0

a II
1131-11-11-13-11
rii 111 I
gi 0
R2

I
VC 0
RI

C(1) C12)
SF] ill
11,11111311""a"1
A
J C B K VS S
1 ani-o-onri vs,
VDDH GM A B D E VSS
11,11111:1111173,13
i \--,-/ Vss
L F E
Z 8
.
wL,,,,,, -,:L. VDD

aa al-a-a-a
.
41.

02 NC 03 NC
.11.F;,4
o0 j
8 I-37 aT=A74-46,L,,
=
i

1 N) VDD NC 01

JD

0
CI Maajima a -4
0 NCL F NC K E

CA
a_m_a_m_._...._.
l It 1
(0

oi
1-1-1-o-g-tro
ABJ K DVss
. COUN 1 ER
1 ani , 111 11
A vss
.4
0
N)
VDDK
amaamILCLCilma
FEFIG NC
o-o-ra
,2
0
, 07
a05-a c
Lis
06 04 VSS
[rrirgrrinra
IP 111 1111 .4
0
CO
VDD

1111A1 11211111.101:1 13
0 VCCG CVSS
.11111
d i
co
w
A H B I

0
,, ,
(21
v < " ,, 2 g 2 g 2 g
L'

RI
Lz t7,
S" D
MAIaailimaClai
N INPUT STI DI

1111111 OUTPUT 1 U ' 0 II S D

SU
L.LI

,, ,-----^=. 2 ..--"\--\ M
1-1-115-1-0-1
, ABCDNCVss
VDD 01

1 0 9 doh
01 U a
"Nila
KI 3I SET

I
1:1

INPUT LATCHES
2 111

ra_rennri
01 0-1 CLI RI KI J711 wimm.. VSS
.4
0 OUTPUT 60 -n LEVEL SHIF T
,vDD./-"-_,, _I
Q2 02 (..)
w
a
,..5

4
o
W
w DUAL J/K FLIP/FLOP
MIMI 8 VDD NC
C.) DISPL AY DRIVERS CO
14 13 2 11 1 9 8

IliMM M 02 .0.11. NJ 110-111-111-111-11:1-CLO

InniCIBEIND
I
C L 2 R2 K2 J2 S2
111111
inralrgranra
I I

Q2 02 CL2 R2
52 STROBE
- Q4 Q3 02_01
4 ).-
\_\,_ OUTPUTS
VEE V55

DUAL DATA FLIP/FLOP 02 *

\__.v.__/. Y
0 I- \___,./.._,
K2 J2 E Vss ,), LAI
-au_
_01 OUTPUT 2 2
0
L,
a
INPUT
... NC NC K JD
L
IIIIMM
(7)1 CLI RI DI SI F E

I I (T
0 1: MmilOamlEmill ELEI ro_o_cris...a."
PI
6 7

PI
3 4 5

,
I 2

Q, 5 ,, 4 H VSS 8 BCD INPUTS PI4 NC VSS

00
18 VDD 03 01 B C D A Q8
OUTPUT It,
1d IS 15 14 3 12 11
.4
0
CO
VDDRGML FE
A C..) MCCeneCimCman.0
0 a
I 11 11
cga co .4 g'

WI
Lj"I'

al VDD dm Prop 0- 0 ci ci d .,:r

030IBCDAQ8 ^ anrcramirra ridli
16 15 14 13

J 12 11 10

L_.
9
^04
Q2 00 Q7 09 05 06 VCC G A H B I
VSS

02_ co.
°J,,
.D..,,... DA,
02 -4 SEGMENT OUTPUTS
II: 03
0
(31 VDDf go dcba
04
4
04 02 00 Q7 09 Q5 06 VSS CI1313C11."0111,
16 15 14 13 12 11 10 9
A BJKCDVss
2 3
r 4 5 6 7 8
DECIMAL OUTPUTS I I

BCD 7 SEGMENT DECODER/DRIVER

I

- 0 EXTERNAL TRIGGER
Lt c40 g (.17 4, a VSS
.o.
0 1-,OUTPUT,Ti
I

LEVEL S
I

T
1 1 I

° COMPONENTS, INPUTS OUTPUTS

0. 0 0 NN'
I

PARALLEL INPUTS .0. /ev /ii: 1,:_e \ /__/\__\

0 0- w
L,t4 0
''(< CO IS
,.___,
-
10 10
_I
o c,
c.ri
?:-, ,-, -4- , 1 1 1
0
(.0
VDD el 6`,1( a + 1 02 02
VDD 0 0 0 H1-4 PI 3 PI .2 PI .1 inPUT LATCH
a a_ la 11-111-1-1:1 a
MI
15 14 13 11 10 9
C°
.......
16 11

0
41.

1- 'g 'g w 1 2
I
3 4
I

5 6 7 8
0-. CX2 IRX2
'-' VDD d -o',., o° -9- T 8' w
\2' 2
,.//
2'
lti2' ,z0-VEE \SS CX2

a
-A
16 5 14 13 12 11 10 9 02/0 13 13 PI -4 P1 .3 PI .2
2 BCD INPUTS
ul
1- en-LN
N.) DUAL
-.cud! 3 P1 -

Ew CO
CL P/S
77
M.M.V.
T/C IT J R

vDDJI-10 FEN/C
a pill,"_AI
R CI C.E. C.O. 9 4 8 .o.
DECADE COUNTER 0a)
1 2 3 4 5 6 7 8 00
14 3 12 11 0
,_
9 8
-1:1 "'CI
_, .3,5 H. 2i,"!5_-; VSS
vs s Li-,

gd a SERIAL IN -r4s--4RIGGEROUTRUTS
ca. {NAL
E.(\lrXT ccr3

COMPONENTS INPUTS

I I__
-4
OUTPUTS -4
0
/---/\---N.
OUTPUTS CLOCK
IN
1 -
cri
cc
L OUTPUTS
W
,-,6

U
:3

VDD on QI0 Qs 09 R 0 01
1 2 3 4 5 6 7
---- VDD B 044 038 028 01L3 : B
I--
w yO,
_ I/P _ 14
,,,w< I/P
:Am: ligmgliAmCmCi
N/C A B C D N/C VSS
.o.
M 00 mIll mal JLIM ma al
ry
prargmli
LT, CT'
C° VDD ct 0 Q5 '5" 04 ri_W -4-

.0 1
16 15 11 13 12 11 10 9 S. -A VDD

0 mmi
1
41

&s.
41 41
DUAL UP COUNTER
03 "5" 07 P.E.4"
R

5
CI
STAGE COUNTER
12 -STAGE COUNTER

gill 9 KII
D "1" "2" 02 01 Q3 "3- 35&.1. ElleAll"Milll
o -dmirio -a m-ol A 0-013-1-0-0-1-0
Al A m' QIA Q2A 03A 04A A VSS
1 2 3 4 5 6 7 8
012 06 05 07 04 03 02 VSS
/ 16 Al
11,1"1"1,13,1 (0)
_;
5
w
\---\/-----/ ,-I--I

;:t 'C2
QI 03"Iivp. VSS OUTPUTS 0 0 LAPUTS 2
o
-I I/"P -1%P.
V55

Note: A prefix to the type number denotes the manufacturer,

e.g. CD 4001 (RCA), MC 14001 (Motorola), N 4001 (Signetics), SCL 4001 (Solid State Scientific), SIL 4001 (Siltek).
 w6.,"
ttl-ics

V
4
0
-4
9.

. larr
-4

4
4
0
*
.-
-,C

14

- rati 1116
IA

14
1
48

13

13
r

qila mil
d ig II
4A

12

3
,

40

12
4

11

4
4
A

11

a
38

lir
10

10
JA

313

9
33

IA
8
=

.
V
4
4

V
4
ir

Ca
0
v

14

1A

vCC

14
1

N
A
13

ES 1 61 iilild
2
1V

13
61
12

2A

12
3

F.4
6*
11

11
1
511

10.

NC

10
5
A

III
4/1

NC

9
9

6
4

7
.....

8
8

.
ir'
V
4
CO
°)

'2,
"-
°
Input
V

14

14
1111A
1'
A
49
13

NC

13
IIIII

. u...Anvevamial
irrILAT"111111411
iir.._--
4A

12

12
4

4
11

11
38

Irja

GND
10

10

II_Oniv'villi.
11151

:
3A

9
31

7
44..
8

8
:

5:
V
4
V
Ilk
4

0.)

Z -J

''
s_
16

---v- .9___,
Outputs

*_
Outputs
'7----IA----5L-s, GND'' 6
15

r,
14

`-----v---
A
13

Ingot,

fe 9
--1
Deocoder /Drver

4
12

5
Book 75 - 109

.
,.__Ck._____s

11

6
is

OM

s-± -v-----
Inputs

n)

r.)

Ni
t

A
7

10

<
'
3

8
9

0,,,I

I
2 3 4 5 6 7 2 3 4 5 6 7 2 3 4 5 6 7 q' ,r, r-?: e cp -

L
1 1 1

V A : S." A : 5. 0
80
Input
OM ROW N V C R9(I ) 69(7) I-0 ,,,,
,-.;

Inputs Oulpuis V ---)

...,
4
.
V 5 `-' CO-. F'

0 v 44 48 4 0 38 3A 4, C i,11. ------In) '---Ei---7' 4 Input

A B &ND C 0

I\3+ 14 13 12 11 10 9 8 ^) 16 15 14 13 12 11 10 9 m 14 13 12 11 10 9 8
! + .

ma E. 11111111... 111m1.741

VV
-,,
8
ABCD to decimal decoder
C D
- 5 ,11115.1.

.
ao , 2
4
. 7 :
9

1
all 2 3 4
1
MU 5 6 7
I 1 2 3 4 5 6 7 8
WU. MMill
1 5' 6 2 3 4 7
.
5N74 144 N
Co

IV lA IB 21 2A 28 GND 0 1 2 3 4 5 6 GND Input ' ' ' 'CC t ) '0(2)

,
BC
Outputs

bel
fliff
OuIp V V
vc 6A 61 A 5V A 4 - VCC I C t' it input A D GND 8 C

-4+
...,
14 13

7
12 11

rP
10 9 8

i
--J 16 15

Igo bc d
AIRWW1111.W.UP.
14 13 12 11 10 9 c''' 14 13 12 11 10 9 8
-
T
+
,

- na wil -
Pill ''' to
-,.

I
0 o
cn
.*
BCD to 7 segment decoder/driver
:
BI/ -CC
IP
' rs.)

NSF
6I di n
n
4 1111MME M-1...1=1111
0
(3)
*
1 2 3
A
4
V
5
A
6
ir r
7 1 2 3 4 5 6 7 8
GND Input
1

ROO)
2 3
(2)
4
°CC
5 6 7 o
2
g
cn
11
" .
8 11
'8
_
7416 )
'e C'
Inputs T smt P O R:putInput
B'PM Aj
Inputs
F
--31 - 2le
zii
...1 V .-,- EIS
-4
'4'" ',cc 6A 60 5A 5 A 4
-4
V J 0 0 GND 1 0 0 -2: e NC NC :' Coal R.M CO 11---, ,TAN .
I.
NC --, .,...,

--1 14 13 12 10 9 8 w+ 14 13 12 10 9 8
11
. 11
. -,N) 14 13 12 11 10 9 8
Ai i., ....

P
,-,-

rPi g
CI WI
Wi Ill
. Al
0
li
0 a , z
= IV 6 ,a. 7.,.
F

Al 0 IZar
3
1.01
4 5 6 7
._ 11161,1 .,....,_
1 2 1 2 3 4 5 6 7 1 2 3 4 5 6 7 947413,.4
IA IV 2A 2V A Y II Clock Cl*e K vcc lock Itor 1
r AlNO ' A2 13 0 GND

V V Oulp,s
V Reol/ V
48 44 4V 38 3A 31 4, Clear Clock Preset 20 4 V C C ,t Rwy

-tv 6r.1 ---6C;4 7i' Clear Clock

v 2D
0
41.

4+
232

13 12 9 8
'4' vC

co 14 13 12 11 10 9 8
. 14 13 12 11 10 9 8
. NJ
14 11 10 . 0) 14 13 12 11 10 9 8
IIM

KIP EP
Willi
1.1171.9 0:11
1 Cock 0
',1-'

o1 e.

la
CH OG OF QE

8 bit shift
8000Q Clock
D 0 A
Cioc, 0 °Aar
Pr
1111A e: iiii.1=EMMi
2 3 4 5 6 7 2 3 4 5 6 7
2 3 4 5 6 7 2 3 4 5
l 6 7 1
1 1

A 28 cir in \.. _,LL31132C1 or 0ND

I 1V 2A 21 GND Clock Preset 10 GND s_m__,
A 8 _____________J
04 v13 vC vo v

Dab Inputs 5, .01 I npdIS outputs

V V 1R.w V Inputs Outputs Inputs
4:=5 VC 1C 3C 3B 3A 3
4 1
2
_
5
Clock
1 -2 GNO it 30 40
...I
-4 VCC Celt! Cc.
,

10 20 Ckor
2
28 2A 41. ' ow Dolo Delo'
V Data Cleor
1
s

o+ 14 13 12 11 10 9 8 curl 16 15 14 13 12 11 10 9 N., 16 15 14 13 12 111 10 9 uei

16 15 14 13 12 11 10
C D

9
co

o a 8 a o 5
omiturmr=
A Clear Borrow Corry lood C

Mill OA
Count Co,n1
Down uP OE O.
0

1INE..1=1. da. ....

:fli 11:121111111111"11 II 1171111.11 1
1 2 3 4 5 6 7 8
2 3 4 5 6 7 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 Doi. oB OA Counl Count Oc 0, u+D
to 28 le ID 10 Clock vCC 3D 4D 40 8 \ Do.° UP ,
1B 2A 2C 21 CAD
3-4 A 14 1 le Mut/ ...1 Input 5__.,
Cell Cepa Culputs Inputs Outputs

V V V V Del -la Inputs

.4 V 2D 2C NC 28 2A 21 .A. 11 10 15 GND 2 20 2b 2J 4 : 4A 4v 38 3A 31 VCC Clear '"--0--A-ITC' I.:
CI k
V
a)
C D

c 14 13 12 11 10 9 8
+
16 15 14 13 12 11 10 9 c,..) 14 13 12 11 10 9 8 (3 14 13 12 11 10 9 8
cn
v - =

4
1-1711'710111 0 a 0 r71110 ijr1,11: IIP 1111
0, Q111
il;

ll
N) Cleo, 0 B
Preset
+
wiliii)I J ClOck IL: Clock 1
OIL Si 0 rhilkirgall IV Coynl / Clock
CI k
V
42. Me 0 C A 0

NW
1

0 2 3 4 5 6 7 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 1 2 3 4 5 6 7
1A 14 N 1 15 ' Clock Preis, Orr 11 vCC CbdPre2t Clot IA 1B IV 2A 2B 21 GND Cour, / .0 A .A CIC 1
food
Doto Inputs
* open collector 1- Pin -compatible CMOS equivalents available from Teledyne Semiconductor and National Semiconductor
110 - Book 75 linear ics

OPAMPS, COMPARATORS SPECIAL TYPES

1. Output A
2. Inverting Input A
0 3.
4. V-
Noninverting Input A

DECOUPLINC OUTPUT 5. Noninverting Input B

6.
7.
Inverting Input B
Output 8 8 r-
,

e. v 00
pl

3 2

INPUT HIGH INPUT LOW 1. Output A

2. Inverting Input A
3. Noninverting Input A
GROUND
4. V-
NOTE: Pin 4 connected to case 5. Noninverting Input B
6. Inverting Input 8
7. Output
INPUT B. v.
8 COMP Pu;,E O B

-INPUT E 2 =V+
.INPUT E 3 6 =OUTPUT BOTTOM VIEW
OUTPUT
T CA
v- E COMP-J
AMPL If IE R NO
NC NC
.., 17.7/1 INPUTINIPLA Ground E vcc

NC= 1 14 =NC
-
Q)
VCC.
OUT
PUT
PUT
LAG
LAG
2
LAG
1
INV
INPUT MPUT
INV
Dltcnerge
CURRENT LIMIT COMP

.... 14 101{-9111111___ E CURRENT SENSE V

NC = 13 =NC 0-Pu, E
2 II 1 - INPUT Vo
R net
E
CCTAPPUTA E 3 12
INPUT
COMP
O B INPUT VOUT
-INPUT E 4 11 = V+ VREF Vz
INPUT = 10 = OUTPUT V NC
OUTPUT 1. Ground 5. Control Voltage
V- = 6 9
,--1COMP 2. Trigger 6. Threshold

NC = NC
T>
.j
''n OUT
PUT
1.
OUT INPUT INPUT NON
PUT LAG LAG
INV VCC
INV INPUT
3. Output
4. Bisset
7.
e. VoC
Discharge

CURRENT
CURRENT
LIMIT

COMP
NOTE: Pin 7 connected to bottom of LAG INPUT

0 00
7
1
SENSE
package. CO \
AMPLIFIER NU I

01 -INPUT V+
INPUT COMP B 0) Discharge E 3 vcc O
co
E O 0
Chita. 4 Threshold EDischarge +-INPUT
00
-Input 1 -Input 4
Control VOltsg E 17 Threshold VREF VOUT
.Input 4 V
144u11
E control V.
NOTE. On metal can, pin 5 is connected
3.-
ONO

ut to case.
'Input 2 Napa 3
V -Input 2 41444413 OutpTrigger 15 outp.
NEG INPUT V- a PUS INPUT VT
NOTE: Pin 4 connected to case. Output 2 041041 3
NC ^ NC

BAL NC NEG OUTPUT ,a1 POS. OUTPUT

IN V TAB NEG SENSE ' PUS SENSE

L.,,) - POWER SUPPLY VCO CONTROL

IN OUTPUT
8 0 COMPOSITE
INPUT LOOP FILTER NEG STAB PUS STAB

BAL 0 AUDIO AMP

OUTPUT
LEFT OUTPUT 8,
LOOP FILTER
PHASE NC BALANCE AOJ
INV ,,! 17CT 0 R
OUTPUT DEEMPHASIS INPUTS
INPUT RIGHT OUTPUT 8, PILOT MONITOR VOLT 007 1 GNU
NC NC DEEMPHASIS
THRESHOLD
NC NON-INV. AMPLIFIER
LAMP DRIVER IT
NC THRESHOLD
INPUT BIAS INPUT GND
FILTER NEG INPUT V -
BAL NC
NEG OUTPUT
V- compioNT
5
I
POS INPUT V
-IN V POWER SUPPLY 6

NOTE: Pin 4 is connected to case. UT

NEG SENSE , POS OUTPUT
OUTPUT AUOTTZ1r E E vc. CO NTROL TOP VIEW
TO 100
J SIN(( OUTPUT LOOP FILTER P44age 2

BAL DEEMPHASIST
MC 1311 NEG. STAB 1 POS SENSE
-EXTERNAL LEFT OUTPUT E MC 1310E E LOOP FILTER
9
NC NC
8 FREQUENCY
COMPENSATION
0 OR INHIBIT
TAB
RIGHT OUTPUT E
LM 1310N DETECTORPHASE
INPUTS
VOLT ADJ
,i0
POS STAB

NC .4 INPUT V+
DEEMPHASIS E
pA 758
PILOT MONITOR GNO
LAMP DRIVER E THRES 0 LO
DRIVE OUTPUT FILTER
IEMITTERI GNO E I-I:TEESI 0 LO
Cv.FLFTEARGE, NT IAL
SENSE
INPUTS tit., CURRENT
[PROGRAMMABLE
INPuT VOLTAGE REGULATORS CURRENT
LIMIT
(STROBE 0..0
GROUND , IN

DOLIPAEL-R-UASTH174'

YIN

NOTE: Pin 4 is connected to case. - CURRENT

03 LIMIT

- SENSE

V+
0 TAB Strobe
(A) Phase Compensation
Offset VT

8 null
SENSE BOOST
Inv. input Output
CURRENT
LIMIT

Compensation Non Inv. r1 Offset VIN

input 0 null
ONO SIN

- CURRENT
REFERENCE 5
LIMIT
NOTE: Pin 4 is connected to case. tl
+v _v NC 6 9 SENSE

- BOOST VOUT
Cso

co
r.) 05
Output 2 Output 3
>
Ca) 03 CA GNO
Output 1 Output 4
8CTl
NJ
ONO 4 -CURRENT LIMIT

Input 1- Input 44 +v,,,,,

1114341t 14 m InPut 4 -
+BOOST

Input 2- Input 3.
Vip, - CURRENT LIMIT

Input 2. 0 0 Input 3
T VIN
a. BOTTOM VIEW BOTTOM VIEW

NOTE: All IC's shown top view, unless otherwise stated.

transistors Book 75 - 111

Pmax (rnW)
VCEO (Volt) Ic(max) (mA) not cooled: hFE(min)
0 = < 20 0 = < 50 0 = < 300
PNP = P 00 = 2540 00 = 55-100 00 = 305-10000 = < 20 case nr. comments
Type
NPN = N 000 = 45-60 000 = 105-400 cooled:,,,_ 00 = 25-50
0000 = 65-80 '-'''' = =10-35
0000 = 405-2 A 00** 1-10 W 000 = 55-120
W 0000 = > 125
00000 = > 85 00000 = > 2 A
00*** = > 40 W

TUN N 0 00 0 000
TUP P 0 00 0 000
AC126 P 0 00 00 0000 2
AF239 P 0 0 0 0 1 grounded base: f fT = 700 MHz
BC107 N 000 00 0 000 2
BC108 N 0 00 0 000 2
BC109 N 0 00 0 0000 2 low noise
BC140 N 00 0000 00* 00 2
BC141 N 000 0000 00* 00 2
BC160 P 00 0000 00* 00 2
BC161 P 000 0000 00* 00 2
BC182 N 000 000 0 0000 2
BC212 P 000 000 0 000 2
BC546 N 0000 00 00 0000 2
e
BC556 P 0000 00 00 000 2
BD106 N 00 00000 00** 00 7
BD130 N 000 00000 00*** 0 7
BD132 P 000 00000 00** 00 9
BD137 N 000 0000 00* 00 9
BD138 P 000 0000 00* 00 9
BD139 N 0000 0000 00* 00 9
BD140 P 0000 0000 00* 00 9
BDY20 N 000 00000 00*** 0 7
BF180 N 0 0 0 0 1 grounded base: fT = 675 MHz

0
et
BF185 N 0 0 0 00 12 grounded base: fT = 220 MHz
BF194 N 0 0 0 000 10 grounded emitter: fT = 260 MHz C
BF195 N 0 0 0 000 10 grounded emitter: fT = 200 MHz
BF199
BF200
N
N
00
0
0
0
00
0
000
00
11
1
grounded emitter:
grounded base:
fT = 550 MHz
fT = 240 MHz
n-
BF254 N 00 0 0 000 11 grounded emitter: fT = 260 MHz
BF257 P 00000 00 00 00 2 grounded emitter: fT = 90 MHz
BF494 N 0 0 0 000 6 grounded emitter: fT = 260 MHz
BFX34 N 000 00000 00 00 2 fT = 70 MHz
BFX89 N 0 0 0 00 1 grounded emitter: fT = 1000 MHz
BFY90 N 0 0 0 00 1 grounded emitter: fT = 1000 MHz
BSX19 N 0 0000 0 000 2
BSX20 N 0 0000 0 000 2
000 0000 00 000 2 ceb
BSX61 N
HEP51 P 00 0000 00 000 1 fT = 150 MHz
HEP53 N 00 0000 00 000 1 fT = 200 MHz
HEP56 N 0 00 00 000 5 fT = 750 MHz
MJE171 P 000 00000 00** 00 9
MJE180 N 00 00000 00** 00 9
MJE181 N 000 00000 00** 00 9
MJE340 N 00000 0000 00** 00 9
MPS A05 N 000 0000 00 00 13 b
MPS A06 N 0000 0000 00 00 13
bc e
MPS A09 N 0000 0 00 000 13
MPS A10 N 00 00 00 00 13
MPS A13 N 00 000 00 0000 13
MPS A16 N 00 00 00 0000 13
MPS A17 N 00 00 00 0000 13
MPS A18 N 000 000 00 0000 13
MPS A55 P 000 0000 0 00 13
MPS A56 P 0000 0000 0 00 13
MPS U01 N 00 00000 00* 00 14
MPS U05 N 000 00000 00* 00 14
MPS U56 P 0000 00000 00* 00 14
MPS2926 N 0 00 00 00 13 fT = 300 MHz
MPS3394 N 00 00 00 000 13
MPS3702 P 00 000 00 000 13 fT = 100 MHz
MPS3706 N 0 0000 00 00 13
MPS6514 N 00 00 0 0000 13 fT = 480 MHz
TIP29 N 00 0000 00** 0 3
TIP30 P 00 0000 00** 0 3 b
TIP31 N 00 00000 00*** 0 3
TIP32 P 00 00000 00,,,,, 0 3
TIP140 N 000 00000 00**-, 0000 7 Darlington
TIP142 N 00000 00000 00*** 0000 7 Darlington
T1P2955 P 000 00000 00*** 0 3
TIP3055 N 000 00000 00*** 0 3
10 12
b
TIP5530 P 000 00000 00*** 0 3
2N696 N 000 0000 00 0 2
2N706 N 0 0 0 0 2
2N914 N 0 0000 00 00 2 case e
2N1613 N 000 0000 00 00 2
2N1711 N 000 0000 00 000 2
2N1983 N 00 0000 00 000 2
2N1984 N 00 0000 00 2
2N2219 N 00 0000 00 00 2
2N2222 N 00 0000 00 00 2
2N2925
2N2955
2N3054
N
P
N
00
00
000
00
00
00000
0
0
00***
0000
0
00
13
2
7
* MJE2955, TIP2955! 0 e

2N3055 N 000 00000 00*** 0 7

2N3553 N 00 0000 00* 0 2 fT = 500 MHz
2N3568 N 000 0000 0 000 13 b be
2N3638 P 00 0000 0 000 13
2N3702 P 00 000 00 000 13
2N3866 N 00 000 00* 0 2 fT = 700 MHz
2N3904
2N3905
2N3906
N
P
P
00
00
00
000
000
000
0
00
00
00
000
000
13
13
13
13
0
2N3907 N 000 0 0 000 13
2N4123 N 00 000 0 00 13
2N4124 N 00 000 0 000 13
2N4126 P 00 000 0 000 13
2N4401
2N4410
2N4427
N
N
N
00
0000
0
0000
000
000
0000
00
00
00*
00
0
000
0
000
13
13
2 fT = 700 MHz cbe
b
IID
2N5183 N 0 2
112 - Book 75 tup-tun-dug-dus

Wherever possible in Elektor circuits, transis-

tors and diodes are simply marked 'TUP'
(Transistor, Universal PNP), 'TUN' (Transistor,
Universal NPN), 'DUG' (Diode, Universal Ger-
manium) or 'DUS' (Diode, Universal Silicon).
This indicates that a large group of similar
devices can be used, provided they meet the
minimum specifications listed in tables la and

AUG 1 b.
For further information, see the article 'TUP-
TUN-DUG-DUS'.

Table 6. Various equivalents for the BC107,

Uceo lc hfe Ptot fT -108, ... families. The data are those given by
type
min. the Pro -Electron standard; individual manu-
max max min. max
facturers will sometimes give better specifi-
TUN NPN 20 V 100 mA 100 100 mW 100 MHz cations for their own products.
TUP PNP 20 V 100 mA 100 100 mW 100 MHz
NPN PNP Case Remarks
Table la. Minimum specifications for TUP and
TUN. BC 107 BC 177 C

Table lb. Minimum specifications for DUS and BC 108 BC 178 B

DUG. BC 109 BC 179 ,

type UR
max
IF
max
IR
max
Ptot
max
CD
max
BC 147
BC 148
BC 149
BC 157
BC 158
BC 159
B

F
250 Pmax =
mW

DUS Si 25 V 100 mA 1µA 250 mW 5 pF

20 V 35 mA 100 µA 250 mW 10 pF BC 207 BC 204 411-1k
DUG Ge
BC 208 BC 205 BRIJ
BC 209 BC 206
BC 237 BC 307
Table 2. Various transistor types that meet the Table 4. Various diodes that meet the DUS or
TUN specifications. DUG specifications. BC 238 BC 308 BC
BC 239 BC 309

TUN DUS DUG BC 317 BC 320

lcmax =
BC 107 BC 208 BC 384 BA 127 BA 318 OA 85 BC 318
BC 319
BC 321
BC 322
C, 150 mA
BC 108 BC 209 BC 407 BA 217 BAX 13 OA 91
BC 109 BC 237 BC 408 BA 218 BAY 61 OA 95 BC 347 BC 350
BC 147 BC 238 BC 409 BA 221 1N914 AA 116 BC 348 BC 351 C'

BC 148 BC 239 BC 413 BA 222 1 N4148 BC 349 BC 352

BC 149 BC 317 BC 414 BA 317
BC 407 BC 417 Pmax =
BC 171 BC 318 BC 547 BC 408 BC 418 H 250 mW
BC 172 BC 319 BC 548 BC 409 BC 419 '

BC 173 BC 347 BC 549 Table 5. Minimum for the

specifications
BC 582 BC 547 BC 557 Pmax =
BC 182
BC 183
BC 348
BC 349 BC 583
BC 584
BC107, -108, -109 and BC177, -178, -179
families (according to the
standard). Note that the BC179 does not
Pro -Electron BC 548
BC 549
BC 558
BC 559
a '
500 mW
BC 184 BC 382
BC 207 BC 383 necessarily meet the TUP specification BC 167 BC 257 169/259
(1c,max = 50 mA). BC 168 BC 258 a, I icmax =
50 mA
BC 169 BC 259
NPN PNP
BC 171 BC 251 251 . .. 253
Table 3. Various transistor types that meet the BC 107 BC 177 BC 172 BC 252 AN low noise
TUP specifications. BC 108 BC 178 BC 173 BC 253
BC 109 BC 179
BC 182 BC 212 icmax =
TUP Vceo 45 V 45 V BC 183 BC 213 Aii 200 mA
BC 253 BC 352 max
20 V 25 V BC 184 BC 214
BC 157
BC 415 20 V 20 V
BC 158 BC 261 BC 582 BC 512
BC 416 lcmax =
BC 177 BC 262 Vebo 6V 5V BC 583 BC 513 Bp, 200 mA
BC 178 BC 263 BC 417 5V 5V BC 584 BC 514
BC 418 max
BC 204 BC 307 5V 5V
BC 205
BC 206
BC 308
BC 309
BC 320
BC 419
BC 512
BC 513
Ic
max
100 mA
100 mA
100 mA
100 mA
BC 414
BC 414
BC 414
BC 416
BC 416
BC 416
is low noise

BC 212
BC 321 BC 514 100 mA 50 mA
BC 213 low noise
BC 214 BC 322 BC 557 Ptot. 300 mW 300 mW BC 413 BC 415 Big,
BC 251 BC 350 BC 558
max
300 mW300 mW BC 413 BC 415 VIIE
BC 252 BC 351 BC 559 300 mW 300 mW
BC 382
fT 150 MHz
150 MHz
130 MHz
130 MHz
BC 383
BC 384
at
min.
150 MHz 130 MHz
BC 437 c Pmax =
F 10 dB 10 dB BC 438 220 mW

TUP max
10 dB
4dB
10 dB
4dB
BC 439

TUB
BC 467 Pmax =
BC 468 II ' 1 220 mW
The letters after the type number BC 469

DUB denote the current gain:

A: a' (13, hfe) = 125-260
BC 261
BC 262 H
low noise

DUG
.
B: a' = 240-500 BC 263
C: a' = 450-900.