Study of SoIC and 3D Packaging

Yu-Ting Su, 108033113

Department of Power Mechanical Engineering
National Tsing Hua University
[email protected]

Abstract: report, we focus the 3D packaging technology of

The introduction of two different 3D IC in- the two largest rivals in industry, Intel and TSMC,
tegration packaging technology is reported, in- including the introduction, the structure, the pro-
cluding structure, process flow, application, relia- cess flow, the application etc. The 3D packaging
bility, and other relevant information. One tech- technology of Intel is called Foveros, while SoIC
nology is Foveros from Intel with an active inter- of TSMC.
poser with TSV, the other is SoIC from TSMC
with direct Cu-to-Cu bonding 2. Intel Foveros
In Dec. 12, 2018, at Intel “Architecture
Keywords: 3D IC integration, packaging, struc- Day,” they revealed next-generation technologies.
ture, process flow, reliability, Foveros, Intel, ac- One of the key points is “Foveros”. Foveros is a
tive interposer, TSV, SoIC, TSMC, Cu-to-Cu face-to-face (F2F) 3D packaging technology us-
bonding. ing active interposer with Through Silicon Via
(TSV). Compared to the passive interposer of
1. Introduction normal 2.5D packaging, Foveros has integrated
The well-known “Moore’s Law” in the circuit (IC) structure in its active interposer. With
semiconductor industry is the main driving force Foveros, we can achieve small form factor, higher
to keep forward. There are several applications in bandwidth, reduced latency and good power effi-
semiconductors that require continuous improve- ciency.
ment in performance, such as portable electronic
device (PED), high performance computing 2.1. Foveros structure
(HPC), 5th generation mobile network (5G) etc. Foveros can be classified into micro-bump
[1] [2] However, due to the physical limitations, chiplets 3D integration, because in its typical
the process scaling rate is slowing down. The con- structure, it will contain bumps to connect chips
cept of “More than Moore” becomes important. with different functions.
To increase the number of transistors per unit IC We can see that Foveros (Fig. 1) contains an
die area and introduce the concept of Heterogene- active interposer with TSV, and it is used to con-
ous Integration (HI), 3D packaging is now been nect compute chip and memory or chips with
researching. There are kinds of 3D packaging other functions on top by micro-bumps. [3]
such as micro-bump 3D integration, micro-bump
chiplets 3D integration, bumpless 3D integration,
bumpless chiplets 3D integration etc. [2] In this
 Ag plated (Fig. 3). Intel forms void free joints by
controlling the IMC and the bump height to insur-
ing the high yield and reliability. [5]

Figure 1. Intel Foveros technology.

2.2. Foveros process

With different applications, we may have
various process flows. However, the fundamental Figure 3. Cu pillars with Sn-Ag solder.

process is shown (Fig. 2) [4]: Chiplet to wafer

bonding → chiplet to wafer underfill → wafer TSV forming contains several steps: using
mold → mold and chiplet thinning → TSV reveal dielectric etching with Bosch etching first, coat-
→ interconnect plating → solder reflow → place ing the silicon with a conformal oxide to provide
Embedded Multi-die Interconnect Bridge (EMIB) isolation, Ta layer is introduced as a barrier, and a
→ place high bandwidth memory (HBM) and Cu film is for seed layer, and finally fill Cu with
transceivers → Foveros stack attach. an electroplating process. The values of resistance
of different TSV areas are shown in Figure 4. [5]

Figure 4. TSV Resistance-TSV area relation.

2.3. Foveros reliability

As mentioned in previous section 2.2,
Figure 2. Intel Foveros process flow forms void free joints by controlling the IMC
and the bump height to insuring the high yield
With micro-bumps, the face-to-face (F2F) and reliability. In packaging, bumps reliability is
bonding introduces shorter interconnect length. In important because bumps have the function of
the original Foveros, the bump pitch is about 50- deliver power. The measured normalized lifetime
36 microns and the diameter is about 25 microns. distribution in shown in Fig. 5. [7]
The micro-bumps are made by Cu pillar with Sn-
 The original Foveros has micro-bumps as
connection with 50-36 microns bump pitch. In
July 26, 2021, Intel held the online presentation
“Intel Accelerated” to talk about their process and
packaging innovations. Intel introduced two new
technologies and expected mass production in
Figure 5. Lifetime data from bump current stress 2023, one is Foveros Omni, the other is Foveros
measurements. Direct. The related information is organized in
Table 1. [2][9]
Both bump type has the robust reliability, as the

lifetime is 2-10 times the median time to failure. As Table 1. Foveros technology evolution.

for TSV defect reliability, several product units (1950) Foveros Foveros
Properties Foveros
were burn-in, and there is no defect observed. With all Omni Direct
the result, the reliability of Foveros technology is con- Pitch
50-36 25 ≤10
sidered robust. (micron)

Micro Cu Cu to Cu
Connection
2.3. Foveros application bump column Bonding
The first product using Foveros technology
is “Lakefield” (Fig. 6) [7], a hybrid processor sys- Foveros Omni (Fig. 7) can be classified into
tem with 10nm and 22nm FinFET (22FFL) in micro-bump chiplets 3D integration. Foveros
2
12x12 mm , 1mm thickness package on package Omni combines Foveros and the ODI concept by
(PoP) structure. The 10nm compute die (compute Intel. The power and the signal need to go through
core, graphics, memory controller) connects with TSV in original Foveros design. In Foveros Omni,
package substrate by the active interposer with Cu column is used to replace the function of TSV,
TSV, which is a 22nm base die (security control- directly send the signal to the top dies. Foveros
ler, USB ports, PCIe lanes). The Memory (SK Omni provide D2D connection and modular de-
Hynix LPDDR4 -8GB) and the Foveros connect sign, which enable mixing more than one top chip
to form a PoP system. With Foveros, we combine and base chips. Furthermore, the bump pitch is
chips in different process nodes into a single dropping to 25 microns only. [9]
packaging by 50 microns pitch Cu pillar micro-
bumps. [8]

Figure 6. Intel Lakefield with Foveros technology.

2.4. Foveros variant Figure 7. Foveros Omni concept.

 Foveros Direct (Fig. 8) can be classified
into bumpless 3D integration. It provides direct
Cu-to-Cu bonding, which causes reduced inter-
connect impedance. With the 10 microns bump
pitch, the interconnect density can be over 10,000
interconnection/mm2. To achieve Foveros Direct,
the low temperature direct bonding interconnect
(DBI) is important. [2][9][10]

Figure 9. low temperature DBI process.

An important technology used in DBI pro-

cess is CMP. Chemical mechanical polishing
(CMP) combines both physical and chemical way
to smooth the surface. If we skip the CMP step, a
Figure 8. Foveros Direct concept. large seam (unbonded oxide area) will show up
(Fig. 10a). With CMP process, the seam size can
2.5 Low temperature DBI be effectively reduced (Fig. 10b) or become invis-
Cu-to-Cu DBI (Fig. 9) has several im- ible (Fig. 10c). [11]
portant steps: 1. Use CMP process to provide a
<0.5 nm RMS interface roughness, while a Cu re-
cess will be produced simultaneously. (Fig 9a) 2.
Use plasma to activate the dielectric surface and
bond the surface together at room temperature,
which will introduce a Cu dishing gap. (Fig 9b) 3.
By the CTE mismatch, heat up to eliminate the
dishing gap. (Fig 9c) 4. Anneal to make Cu atoms
diffuse and make a good bonding condition (Fig
8d). We notice that with the first bonding of oxide,
it surrounds and protects Cu, so copper oxide is
not easily generated during subsequent heating,
which leads to a good bond quality. [2]
Figure 10. SEM images of DBI. (a)With large seam.

(b)With small seam. (c)With invisible seam.

3. TSMC SoIC There are two schemes provided, chip on wafer
TSMC SoIC (System on Integrated Chips) (CoW) and wafer on wafer (WoW). (Fig. 13) [12]
is the front-end (FE) technologies in TSMC
3DFabric (Fig. 11) [12], which means it utilizes
the fab or foundry technology rather than packag-
ing technology. SoIC uses bumpless bonding to
from interconnect, while packaging technology
uses bumps or micro-bumps. (Fig. 12) With SoIC Figure 13. WoW (left) and CoW (right) concepts.

[13], the size of a chip is significantly reduced and

provides good flexibility. The bump pitch is 9 mi- SoIC can also cooperate with the two other
crons now, which cause about 10,000 counts/mm2 technology in 3DFabric, CoWoS and InFO, to
bump density. In the future, the bump pitch is ex- provide design flexibility. (Fig. 14) [2]
pected to drop to 0.9 microns in 2033, corre-
sponding to 1,000,000 counts/mm2 density. [12]

Figure 11. TSMC 3Dfabric concept.

Figure 14. 3DFabric SoIC integration.

3.2. SoIC process

In traditional SoC (system on chip), we
need to form micro-bump and utilize flip-chip
and underfill. With SoIC technology, we reduce
the process step due to the bumpless characteris-
tic. (Fig. 15) [14]

Figure 12. Difference between SoIC and bump-tech

3.1. SoIC structure

SoIC can be classified into bumpless
chiplets 3D integration. SoIC uses direct hybrid
bonding instead of micro-bump interconnect. Figure 15. Comparison between SoC and SoIC steps.
 TSMC did not state the details of their SoIC
hybrid bonding technology, but we can guess that
it should have some similarities to the low tem-
perature Cu-to-Cu bonding, or DBI, we men-
tioned in section 2.5.
Figure 18. Information about TSMC-SoIC test chip.

3.3 SoIC application

AMD 3D V-Cache is a technology which is TSMC demonstrate the images of multi-
based on the SoIC technology. (Fig. 16) This con- layer DRAM samples adopting SoIC technology.
nect the Zen-3 processer base chip to L3 cache top (Fig. 19) With SoIC, the stacking height is re-
chip by direct Cu-to-Cu bonding. (Fig. 17) [15] duced to less than 600 microns for 12-Hi SoIC
bonding. [13]

Figure 16. AMD 3D chiplet technology.

Figure 19. SoIC DRAM samples images.

3.4 SoIC multi-layer DRAM

As mentioned in last section (Sec. 3.3),
TSMC shows the information of SoIC multi-layer
DRAM samples with 4-Hi/ 8-Hi/ 12-Hi and
shows the comparison of typical 3D DRAM and
Figure 17. AMD 3D V-Cache, L3D SoIC 3D DRAM. (Fig. 20) (Tab. 2) [13]

TSMC also announced internal test chip in-

formation of SoIC technology. (Fig. 18) The test
chip connects the top N5 logic CPU chip and base
N6 SRAM chip with F2B (face-to-back) SoIC
technology. [16]

Figure 20. Comparison of typical and SoIC DRAM.

 Table 2. Comparison of typical and SoIC DRAM. this section, we focus on the more general relia-
(12 DRAMs with controller) bility of SoIC application. Some parts of a SoIC-
Typical 3D LT-SoIC 3D embedded InFO_PoP were being test for EM

Bond type Micro-bump LT SoIC bond (electro-migration), SM (stress-migration), and

Z-form factor 1X 0.36X Vbd (breakdown voltage), including TSV, TDV

Die thickness 50 microns 25 microns (through dielectric via), and SoIC bond. The re-

Bandwidth sults are shown in Figure 21. While Figure 22.

1X 1.28X
density shows more test items including pressure cooker

Power test (PCT), high temperature storage (HTS), tem-

1X 0.81X
Consumption perature cycle test- condition C (TCC) (-
65~150℃), unbiased highly accelerated stress test

In 3D memory packaging, thermal com- (uHAST), for SoIC bond only. [14]

pression bond (TCB) and non-contact film bond

(NCF) are widely-used. With TCB or the epoxy
layer of NCF, it will cause interconnect reliability
problem by forming solder bridges and the en-
trapment of NCP fillers.
Using SoIC technology, we can effectively
avoid such a situation. Because it is a relatively
low-temperature bumpless process and no epoxy
material is used, the reliability of the characteris-
tics is quite good. Figure 21. shows the relevant
Figure 21. TSV, TDV, SoIC bond reliability on (a)
data of the 12-Hi DRAM reliability test, we can
EM, (b)SM, (c) Vbd.
notice from the result that the SoIC technology
enables the product to have high reliability. [13]

(a) (b)
Figure 21. Reliability test results of 12-Hi DRAM

samples, (a) breakdown voltage, (b) comparison of

TSV chain resistance under T0 and TCB-200.

3.5. SoIC reliability

Figure 22. SoIC bond reliability on (a)PCT, (b)HTS,
Sec. 3.4 talks about some reliability issues
(c)TCC, (d)uHAST.
in specific SoIC 3D stacking DRAM samples. In
 Table 3. demonstrate some test results of Table 4. electrical performance of 5 advanced packag-

InFO_PoP with SoIC. All the test results (Fig. ing structures in Fig. 23.

21,22, Tab. 3) show a robust reliability of SoIC- a b c d E

embedded InFO_PoP. [14] Bump density 0.8 1 1 16 16

Speed 0.01 0.1 1 3.7 11.9

Table 3. SoIC-embedded InFO_PoP reliability test. Bandwidth
0.01 0.1 1 59.7 191
Test Duration Density
Result
condition /Cycle Power
22.9 3.7 1 0.6 0.05
MR (260℃ multi-reflow) 10x Pass consumption

MR10x + TCC 200x Pass

MR3x + uHAST 96 hrs Pass From Table 4, we can see that SoIC has
MSL (moisture sensitivity much higher electrical performance than the typ-
Level 3 Pass
level) ical micro-bump 3DIC, and the SoIC in the form
TCB (-55~125℃) 700x Pass of F2F is the best because it does not need to use
TCB (-55~125℃) 1000x Pass additional TSVs. [17]
uHAST (130℃, 85%RH, In addition, in HPC applications, high-
96 hrs Pass
33.3-psi VP) speed and high-frequency data transmission is
uHAST (130℃, 85%RH, very important, and low insertion loss is one of
192 hrs Pass
33.3-psi VP) the important factors. Figure 24. shows the com-
parison of insertion loss between SoIC and gen-
3.6. SoIC performance eral flip chip structures at different frequencies, it
Foe advanced technology, in addition to en- can be found that through SoIC technology we
suring good reliability, electrical performance can achieve 0 insertion loss. [14]
needs to be measured and analyzed. Figure 23.
and Table 4. show the 5 advanced packaging
structures, including 2.5D CoWoS (chip on wafer
on substrate), F2B/F2F micro-bump 3DIC, and
F2B /F2F SoIC, and the performance comparison
among these structures, respectively. [17]

Figure 24. Comparison between insertion loss of

SoIC bond and flip-chip interconnect.

3.7. SoIC design flow

Figure 23. 5 advanced packaging structures: (a) 2.5D SoIC can be classified into bumpless
Interposer: uBump+1mm BEOL, (b) 3D-IC F2B: chiplets 3D integration. In multi-chip design,
uBump & TSV, (c) 3D-IC F2F: uBump, (d) SoIC there a fundamental design flow for 3D integra-
F2B: SoIC bond & TSV, (e) SoIC F2F: SoIC bond. tion: 1. Thermal analysis and optimization → 2.
Chip-to-chip interface design → 3. Multi-chip Standard for Test Access Architecture for Three-
testing → 4. APR and optimization → 5. Multi- Dimensional Stacked Integrated Circuits, can be
chip timing signoff → 6. Multi-chip physical ver- used for SoIC, which mainly specifies necessary
ification. (Fig. 25) [16] and optional DFT features included in each die.
APR (automatic placement and routing)
places and routes the cell in the previous process
to generate a layout. The placement is mainly to
optimize timing and congestion, and many DFM
(design for manufacturing) designs such as
dummy are also completed in this step.
Multi-chip timing signoff is a post simula-
tion (timing simulation). After the SoIC design is
placed and routed, use the EDA tool to extract
parasitic parameters to form an accurate post-lay-
out circuit netlist, and perform timing simulation
on this netlist to check whether the timing behav-
ior meets the requirements. It’s an important step
that This stage is very important because prob-
lems can be identified and corrected in advance
Figure 25. Multi-chip design flow. of production. Finally, we can do multi-chip phys-
ical verification.
Although SoIC has better heat dissipation
performance than typical 3D packaging, it still 4. Conclusion
has some thermal problems compared with 2D In this report, we introduce two advanced
packaging, so thermal analysis is also very im- 3D packaging technologies, Foveros and SoIC,
portant in SoIC. Moreover, thermal analysis can from Intel and TSMC, respectively. Foveros con-
be focused on low thermal resistance paths of in- tains an active interposer with TSV and will pro-
terconnects and back end of line power delivery pose an omni version in the future that uses cop-
network compared to surrounding dielectrics and per pillars instead of TSV for power and the sig-
further analyzed the SoIC modal by EDA (elec- nal transmission path and a direct version that no
tronic design automation) software. [16] longer uses micro-bump but direct copper-to-cop-
Chip-to-chip interface design is very im- per bonding. TSMC's SoIC is a bumpless chiplets
portant for chip-to-chip interconnect and commu- 3D integration technology, through the combina-
nication. It is including but not limited to routing tion of 3DFabric (CoWoS, InFO_PoP), it can get
design and signal oriented design. good flexibility, reliability and performance.
In multi-chip testing, although JEDEC also Finally, some comparisons for the non-
has development test standards, IEEE has a com- technical parts are given. TSMC is a foundry,
plete DFT standard. IEEE 1838-2019 [18], IEEE while Intel is an integrated device manufacturer
(IDM). TSMC's main business model is to help foveros-3d-packaging-technology/1/ (ac-
customers succeed together, so it continues to cessed Fri. 20, 2022)
promote open ecosystems, such as advanced 4. Intel, USA. Intel Foveros Technology E
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