QuickLogic® EOS™ S3 Sensor

Processing Platform Input/Output Multiplexor

(IOMUX) User Guide
••••••

Introduction
This document provides a functional overview of the QuickLogic EOS S3 sensor processing platform IOMUX. It also describes how
to program the IOMUX register block, which controls the 46 IOs.

Functional Overview
There are 46 IOs (or PADs) that can be multiplexed to/from various functions on the EOS S3 sensor processing platform. Each
pad can be programmed independently as an input pad, output pad, or bidirectional pad. Programming the IOMUX register block
(0x40004C00 – 0x40004DAC) controls the various functions that drive and sample the pad values. Refer to the Appendix –
Table 12 for IOMUX register descriptions.
NOTE: IOs and PADs are used interchangeably in this document. Both mean the same thing, which is an IO. For
example IO_6 is the same as PAD 6.
Figure 1 shows a block diagram of the implementation.
• The red muxes are controlled by IOMUX_PAD_0_CTRL[1:0]. This function determines which output can drive to a pad. There
is one red mux for each pad.
• The blue muxes select the output pad control, which can come from:
IOMUX_PAD_x_CTRL[12:5] – Register controlled (e.g., A0 register)
Other – Controlled for bidirectional signals (e.g., Serial Wire Debugger (SWD) and I 2C controllers)
Fabric (FB) – I/O controlled. These muxes are for output and/or bidirectional signaling from the device to the system.
• The yellow “AND” gate and mux allows the device to sample pad values to various functional blocks within the device. This logic
is for input and bidirectional signaling to the device from the system.
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Figure 1: IOMUX Block Diagram

When allocating pads in the system design for EOS S3, consider the following:
• The Cortex™ M4 processor, application processor (AP) (via SPI slave), and SWD can read/write the IOMUX registers. The
IOMUX registers are located in the Always-On power domain. If the power is cycled or a device reset is asserted, the IOMUX
register settings will default back to the reset state. The programmable logic (Fabric), which is a slave IP, cannot configure the
IOMUX registers. The M4, AP, or SWD is required to set up the IOMUX settings for the Fabric to use.
• Eight pads can be used as general purpose IOs (GPIOs), which the M4 can drive and sample, using the IOMUX_IO_REG_SEL
(0x40004D60), MISC_IO_INPUT (0x40005100), and MISC_IO_OUTPUT (0x40005104) register controls.
• The Fabric can control all 46 pads, assuming the M4 sets up the appropriate IOMUX programming.
• Eight of the pads can be used as external interrupts to the system (e.g., sensor interrupt or GPIO interrupt), as interrupts to M4 or
sensor interrupts to FFE.
• The other pads can be used for serial interfaces such as SPI slave, multiple SPI masters, SWD, UART, IRDA, I 2C masters, audio
microphone inputs (PDM or I2S), and I2S output to the AP.
• Eight of the pads can be used as debug monitoring pins (debug_mon). Some of PMU, CRU, Audio, and FFE internal signaling
can be brought out to eight pads. For example, CRU can bring out clocks to a pad to monitor frequency.
Refer to the Appendix – Table 13 for possible function/pad assignments. This is for system design, as it shows all the possible IO
assignments.
IMPORTANT: Determine functions for all 46 pads first as per the system design, then program the IOMUX register
accordingly.

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Programming the IOMUX Registers

How to Select the Output Function
Each IO output can be driven from one of four different functional outputs, as shown by the red muxes in Figure 1. Only one
function can drive to the pad as output.
There are 46 IOMUX_PAD_x_CTRL registers, where ‘x’ is a register number from 0 to 45, one register per pad. Program the
corresponding register IOMUX_PAD_x_CTRL bits [1:0] to select the function that drives the corresponding pad.
Each IOMUX_PAD_x_CTRL register looks similar to the example shown in Table 1.

Table 1: IOMUX_PAD_0_CTRL Register Definition

Offset Name/Field Bit(s) Type Default Description

0x40004C00 IOMUX_PAD_0_CTRL 31:0

Functional selection for IO output.

PAD_0_FUNC_SEL 1:0 RW 0x0 For details, see the Appendix –
Table 11
Control selection for IO output:
0x0: A0 registers (as defined
PAD_0_CTRL_SEL 4:3 RW 0x0 below) 0x1:
Others
0x2: Fabric

Active low output enable:

PAD_0_OEN 5 RW 0x1 0x1: driver disabled
0x0: normal operation

Driver state control:

0x0: Z
PAD_0_P 7:6 RW 0x1 0x1: pull up
0x2: pull down
0x3: keeper

Drive Strength:
0x0: 2 mA
PAD_0_E 9:8 RW 0x1 0x1: 4 mA
0x2: 8 mA
0x3: 12 mA

Slew Rate:
PAD_0_SR 10 RW 0x0 0x1: Fast
0x0: Slow (half frequency)

Receive enable:
PAD_0_REN 11 RW 0x0 0x1: enable
0x0: disable

Schmitt Trigger:
PAD_0_SMT 12 RW 0x0 0x1: enable
0x0: disable

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For pad 0, program IOMUX_PAD_0_CTRL[1:0] to select the function that outputs to pad 0. When looking at the register definition
of IOMUX_PAD_0_CTRL, bit encoding is NOT listed in the highlighted bit field. Refer instead to the Appendix – Table 11
functional IOMUX descriptions.
Table 2 is a partial list of pads 0 through 2 (from the Appendix – Table 11) that shows IOMUX output pad programming options.

Table 2: EOS S3 IOMUX Select

Mux Select
Pad No. for OUT Ball/Function Type Default Ctrl
(default = 0)

0 0 SCL0 BIDIR A0_Reg

0 1 FBIO_0 BIDIR

1 0 SDA0 BIDIR A0_Reg

1 1 FBIO_1 BIDIR

2 0 FBIO_2 BIDIR A0_Reg

2 1 spi_sensor_ssn2 OUT

2 2 debug_mon[0] OUT

2 3 batt_mon OUT

2 sensor_interrupt IN

The following are programming examples based on the information in Table 2:

• Example 1: To program IOMUX_PAD_0_CTRL[1:0]:
Set to 0 for I2C0 CLK (SCL0) to drive pad 0
Set to 1 for Fabric IO 0 (FBIO_0) to drive pad 0
2 and 3 are not assigned and are reserved
• Example 2: To program IOMUX_PAD_1_CTRL[1:0]:
Set to 0 for I2C0 DAT (SDA0) to drive pad 1
Set to 1 for Fabric IO 1 (FBIO_1) to drive pad 1
2 and 3 are not assigned and are reserved.
• Example 3: To program IOMUX_PAD_2_CTRL[1:0]:
Set to 0 for Fabric IO 2 (FBIO_2) to drive PAD2
Set to 1 for SPI sensor device select 2 (spi_sensor_ssn2) to drive PAD2

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Set to 2 to bring out debug monitor point (debug_mon[0]) to drive PAD2

Set to 3 to bring out battery monitor IO (batt_mon) to drive PAD2
NOTE: If the pad is used as an input pad, then bits IOMUX_PAD_x_CTRL[1:0] can be ignored or left as is. PAD2 can
also be an input pad assigned to a sensor interrupt.
IOMUX_PAD_43_CTRL (0x40004CAC) is protected from accidental writes. To program this register, program MISC_LOCK_EN
(0x40005310) to 0x1ACCES551 prior to writing IOMUX_PAD_43_CTRL. See
Table 3 for details.

Table 3: MISC_LOCK_KEY_CTRL Register Definition

Offset Name/Field Bit(s) Type Default Description

MISC_LOCK_KEY_CTRL 31:0

Enable write access to all below

registers by writing 0x1ACCE551.
Disable write access by writing any
other value.

M4 WDT Intr/reset clear

0x4000_4830[4:3]
M4 WDT Intr/reset enable AP
0x4000_4834[4:3]
LOCK_KEY 31:1 WO 0x0
0x40005310 Pad #43 (AP_INTR)
0x40004CAC[12:0]

M4 Low Power Configuration

0x40004484[1:0]

M4 WDT Clock Gate

0x40004054[0]

0: lock disabled, write to register is

enabled
LOCK_KEY_EN 0 RW 0x1 1: lock enable, write to register is
disabled

The pad controls for the pad are controlled by IOMUX_PAD_x_CTRL[4:3]. See Table 4 for details. This is the blue-colored mux
seen in Figure 1.

Table 4: IOMUX_PAD_0_CTRL Register Definition - Bits 4:3

Offset Name/Field Bit(s) Type Default Description

IOMUX_PAD_0_CTRL 31:0

Control selection for IO output

0x40004C00 0x0: A0 registers (as defined
PAD_0_CTRL_SEL 4:3 RW 0x0 below)
0x1: Others
0x2: Fabric

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• Select 0 if the output enable from the pad is controlled by IOMUX_PAD_x_CTRL[5]. Since IOMUX is located in the A0 (Always-
On) power domain, this is considered an A0 register.
Program IOMUX_PAD_x_CTRL[5]
– Set to 0 to be an output pad.
– Set to 1 to be an input pad. Output driver within pad is disabled.
• Select 1 if an alternate function controls the output enable dynamically. For example, I2C master(s) need bidirectional control of
the output enable for the I2C DAT pin (SDAx). Another example, SWD needs bidirectional control of the output enable for SWD
DATA pin (SW_DP_IO).
IOMUX_PAD_x_CTRL[5] is ignored.
• Select 2 if Fabric controls the output enable dynamically.
IOMUX_PAD_x_CTRL[5] is ignored.

Table 5: IOMUX_PAD_CTRL Register Definition - Bit 5

Offset Name/Field Bit(s) Type Default Description

IOMUX_PAD_0_CTRL 31:0

0x40004C00 Active low output enable

PAD_0_OEN 5 RW 0x1 0x1: driver disabled
0x0: normal operation

How to Select an Input Function

Each functional input can be selected from the eight IOs. See the yellow-colored “AND” gate and mux in Figure 1. To set up input
pads:
• Program IOMUX_PAD_x_CTRL[11] – Receive enable (yellow colored “AND” gate):
Set to 1 to be an input pad.
Set to 0 to IOMUX_PAD_x_CTRL[5] to disable as an output pad.
• Program the input mux to route the pad signal to the functional block inside the device (yellow colored mux):
Each functional input has IOMUX_<function>_SEL (0x40004d00 - 0x40004dac).

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Table 6: IOMUX_SDA0_SEL / IOMUX_SDA1_SEL Register Definitions

Offset Name/Field Bit(s) Type Default Description

IOMUX_SDA0_SEL 31:0

0x40004D00 Sel
SDA0_SEL 0 RW 0x0 0: 1
1: pad #1

IOMUX_SDA1_SEL 31:0

Sel
0x40004D04 0: 1
SDA1_SEL 1:0 RW 0x0 1: pad #15
2: pad #32
3: pad #44

See the following examples:

Example 1: I2C0 DAT pin (SDA0) can get its input from PAD1.
• Program IOMUX_SDA0_SEL (0x40004D00) = 1.
This enables the yellow mux between PAD1 to I2C0 master.
• Program IOMUX_PAD_1_CTRL (0x40004C04) = 0x808.
Bit[1:0] = 0, selects the SDA0 function.
Bit[4:3] = 1, selects the Other function. This means the I2C0 master block controls the output enable.
Bit[5] is ignored. Can write 0 for now.
Bit[11]:1, sets the receive enable. This is required for the I2C0 master to detect the I2C0 DAT pin change, since this is a
bidirectional pin.
Example 2: I2C1 DAT pin (SDA1) can get its input from three possible pads: PAD15, PAD32, PAD44.
Option 1 if PAD15 is selected:
• Program IOMUX_SDA1_SEL (0x40004D04) = 1 for pad 15.
• Program IOMUX_PAD_15_CTRL (0x40004C3C) = 0x80A
Bit[1:0] = 2, selects SDA_1 for PAD15. See Table 7.
Bit[4:3] = 1, selects the Other function. This means I2C1 master controls the output enable.
Bit[5] is ignored. Can write 0 for now.
Bit[11] = 1, sets the receive enable. This is required for the I2C1 master to detect I2C1 DAT pin change, since this is a
bidirectional pin.
Option 2 if PAD32 is selected:
• Program IOMUX_SDA1_SEL (0x40004D04) = 2 for pad 32.
• Program IOMUX_PAD_32_CTRL (0x40004C80) = 0x80B.
Bit[1:0] = 3, selects SDA_1 for PAD32. See Table 7.
Bit[4:3] = 1, selects the Other function. This means I2C1 master controls the output enable.

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Bit[5] is ignored. Can write 0 for now.

Bit[11] = 1, sets the receive enable. This is required for the I2C1 master to detect the I2C1 DAT pin change, since this is a
bidirectional pin.
Option 3 if PAD44 is selected:
• Program IOMUX_SDA1_SEL (0x40004D04) = 3 for pad 44.
• Program IOMUX_PAD_44_CTRL (0x40004CB0) = 0x80A.
Bit[1:0] = 2, selects SDA_1 for PAD44. See Table 7.
Bit[4:3] = 1, selects the Other function. This means I2C1 master block will control the output enable.
Bit[5] is ignored. Can write 0 for now.
Bit[11] = 1, sets the receive enable. This is required for the I2C1 master to detect the I2C1 DAT pin change, since this is a
bidirectional pin.

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Table 7 shows a portion of the Appendix – Table 11.

Table 7: IOMUX Assignment for Pads 15, 32, 44

Mux Select
for OUT Ball Name/
Pad No. Type
(default = 0) Function

15 0 SW_DP_IO BIDIR

15 1 FBIO_15 BIDIR

15 2 SDA_1 BIDIR

15 3 UART_txd OUT

15 sensor_interrupt IN

15 IrDA_Sirin IN

32 0 FBIO_32 BIDIR

32 1 spi_sensor_ssn5 OUT

32 2 debug_mon[6] OUT

32 3 SDA_1 OUT

44 0 SW_DP_IO BIDIR

44 1 FBIO_44 BIDIR

44 2 SDA_1 BIDIR

44 3 UART_txd BIDIR

44 sensor_interrupt IN

44 IrDA_Sirin IN

NOTE: Only one input pad can be selected for a functional block.

How to use GPIOs

In EOS S3, eight pins can be used as GPIOs by the M4. Sixteen pads can be assigned to the eight IO functions. Once the eight pads
are selected by IOMUX_IO_REG_SEL (0x40004D74) (see Table 8), the M4 can drive to the pad using MISC_IO_OUTPUT or
sample the pads reading MISC_IO_INPUT (0x40005100) (see Table 9).

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IOMUX_IO_REG_SEL (0x40004D74) is the register definition (see Table 8) that shows the possible pad assignments for GPIOs.
• Pad 6 or 24 can be GPIO 0.
• Pad 9 or 26 can be GPIO 1.
• Pad 11 or 28 can be GPIO 2.
• Pad 14 or 30 can be GPIO 3.
• Pad 18 or 31 can be GPIO 4.
• Pad 21 or 36 can be GPIO 5.
• Pad 22 or 38 can be GPIO 6.
• Pad 23 or 45 can be GPIO 7.

Table 8: IOMUX_IO_REG_SEL Register Definition

Offset Name/Field Bit(s) Type Default Description

IOMUX_IO_REG_SEL 31:0

Selects which IO input will be

registered.
Bit Sel Pad#
0 0 6
0 1 24
1 0 9
1 1 26
2 0 11
0x40004D74 2 1 28
IO_REG_SEL 7:0 RW 0x0 3 0 14
3 1 30
4 0 18
4 1 31
5 0 21
5 1 36
6 0 22
6 1 38
7 0 23
7 1 45

Table 9: MISC_IO_INPUT / MISC_IO_OUTPUT Register Definition

Offset Name/Field Bit(s) Type Default Description

MISC_IO_INPUT 31:0
0x40005100
IO_IN 7:0 RO 0x0 Reads the value of the IO pins

MISC_IO_OUTPUT 31:0

0x40005104
Allows FW to drive the IO with the
IO_OUT 7:0 RW 0x0
values specified in this register

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For example, set up all eight GPIOs to the following pads:

1. Program IOMUX_IO_REG_SEL (0x40004D60) to 8’b11110000.
• PAD6 as GPIO 0. Write bit[0] = 0.
• PAD9 as GPIO 1. Write bit[1] = 0.
• PAD11 as GPIO 2. Write bit[2] = 0.
• PAD14 as GPIO 3. Write bit[3] = 0.
• PAD31 as GPIO 4. Write bit[4] = 1.
• PAD36 as GPIO 5. Write bit[5] = 1.
• PAD38 as GPIO 6. Write bit[6] = 1.
• PAD45 as GPIO 7. Write bit[7] = 1.
2. Program the IOMUX pad controls, pad 6, 9, 11, and 14 as output pads.
• Write 0x3 to IOMUX_PAD_6, 9, 11, and 14_CTRL registers.
Bit[4:3] = 0, selects A0 register control (this must be programmed before bit[12:5] is programmed).
Bit[1:0] = 3, selects the GPIO function for output (see the Appendix – Table 11).
Bit[5] = 0, selects output driver enabled. Configures as an output pad.
Bit[11] = 0, disables receive enable (input enable).
Bit[7:6], Bit[9:8], Bit[12] are pad driver characteristics. Keep all 0 for now. Refer to Table 1 for details.
3. Program the IOMUX pad controls, pad 31, 36, 38, and 45 as inputs pads.
• Write 0x823 to IOMUX_PAD_31, 36, 38, and 45_CTRL registers.
Bit[4:3] = 0, selects A0 register control (this must be programmed before bit[12:5] is programmed).
Bit[1:0] = 3, selects the GPIO function for output (see the Appendix – Table 11).
Bit[5] = 1, disables output driver enabled.
Bit[11] = 1, enables receive enable (input enable). Configures as an input pad.
Bit[7:6], Bit[9:8], Bit[12] are pad driver characteristics. Keep all 0 for now. Refer to Table 1for details.
4. Drive all GPIO 0 through 3 to all ONES.
• Write 4’b1111 to MISC_IO_OUTPUT.
• Pads 6, 9, 11, and 14 go HIGH.
5. Drive all GPIO 0 through 3 to all ZEROS.
• Write 4’b0000 to MISC_IO_OUTPUT.
• Pads 6, 9, 11, and 14 go LOW.
6. Drive all GPIO 0 through 3 to all 4’b1000.
• Write 4’b1000 to MISC_IO_OUTPUT.
• Pad 14 goes HIGH and pads 6, 9, and 11 stay LOW.
7. Sample GPIO 4 through 7.

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• Read MISC_IO_INPUT. The values present on PAD31, PAD36, PAD38, and PAD45 map to values MISC_IO_INPUT[4],
[5], [6], and [7].

Bootstrap Impacts in IOMUX

Several of the pads (8, 9, 19, and 20) are used as bootstrap pins. Bootstrap pins are used to indicate device modes when the device is
coming out of reset. Setting a bootstrap requires the IO to be asserted to a certain value (0 or 1) during the device reset assertion and
de-assertion. The rising edge of the device reset latches the bootstrap value. These bootstraps can have an impact on the IOMUX
function.

The following example is for PAD14:

• If bootstrap PAD8 is set to 0 when the device reset is released, PAD14 is a SWD Debug Clock pin.
• If bootstrap PAD8 is set to 1 when the device reset is released, PAD14 is a Fabric IO pin. (This requires no programming and
occurs in hardware.)
The M4 processor can still program the IOMUX_PAD_14_CTRL to change the output mux select to 1, 2, and 3. But the 0 definition
changes by bootstrap.
The IOMUX_PAD_15_CTRL output mux select 0 is tied to the SWD Data pin, but only when bootstrap #8 = 0. When bootstrap
#8 =1, the IOMUX_PAD15_CTRL defaults to 0, but the SWD is not active in this strap mode. This means that
IOMUX_PAD15_CTRL[1:0] must be reprogrammed to be non-zero. Refer to Table 10 for PAD 14 and PAD 15 output control.

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Table 10: Pad 14 Output Mux Definition

Mux Select
for OUT Ball Name/ Default
Pad No. Type Comment
(default = 0) Function Ctrl

14 0 SW_DP_CLK IN Others Bootstrap #8 = 0

14 0 FBIO_14 BIDIR Choose this when #8 = 1

14 1 IrDA_Sirout OUT

14 2 SCL_1 BIDIR

14 3 gpio[3] BIDIR

14 UART_rxd IN

14 sensor_interrupt IN

15 0 SW_DP_IO BIDIR bootstrap #8 = 0

15 1 FBIO_15 BIDIR choose this when #8 = 1

15 2 SDA_1 BIDIR

15 3 UART_txd OUT

15 sensor_interrupt IN

15 IrDA_Sirin IN

Bootstrap PAD 9 Impacts PAD 6

If bootstrap PAD 9 is set to 1 when the device reset is released, PAD 6 becomes the FCLK input (fast clock input) which overrides
the internal OSC output. This IOMUX selection can only be cleared by system reset, since this is a bootstrap function. Writing to
IOMUX_PAD_6_CTRL register [1:0] has no impact when bootstrap PAD 9 is in effect.
Similarly, pads 15, 16, 17, 18, 19, 34, 36, 38, 39, 44, and 45 are also impacted by different bootstrap modes. See the Appendix –
Table 11 and look at the Comment column.

How to Program Fabric IO

The on-device programmable logic (Fabric) can use all 46 IOs. The IOMUX must be programmed by the M4 processor first. Then
the Fabric design can be loaded by the M4 processor, and the Fabric output isolation released. The following 46 IOs are configured
by the M4 processor. A subset of the following C routine can be used to configure the Fabric IOs for your system design. Each Fabric
IO is assigned to each IO respectively.

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void setup_iomux()
{ unsigned int wdata0,
wdata1;

Misc_LOCK_KEY_CTRL = 0x1ACCE551;

// drive strength - 4ma,driver_state = Z,slew rate =

slow wdata0 = 0x110; // sets [1:0] = 0 wdata1 =
0x111;// sets [1:0] = 1

IOMUX_PAD_0_CTRL = wdata1; // FBIO0

IOMUX_PAD_1_CTRL = wdata1; // FBIO1
IOMUX_PAD_2_CTRL = wdata0; //FBIO2
IOMUX_PAD_3_CTRL = wdata0;
IOMUX_PAD_4_CTRL = wdata0;
IOMUX_PAD_5_CTRL = wdata0;
IOMUX_PAD_6_CTRL = wdata0;
IOMUX_PAD_7_CTRL = wdata0;
IOMUX_PAD_8_CTRL = wdata0;
IOMUX_PAD_9_CTRL = wdata0;
IOMUX_PAD_10_CTRL = wdata0;
IOMUX_PAD_11_CTRL = wdata0;
IOMUX_PAD_12_CTRL = wdata0;
IOMUX_PAD_13_CTRL = wdata0;
IOMUX_PAD_14_CTRL = wdata0;
IOMUX_PAD_15_CTRL = wdata1;
IOMUX_PAD_16_CTRL = wdata0;
IOMUX_PAD_17_CTRL = wdata1;

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IOMUX_PAD_18_CTRL = wdata0;
IOMUX_PAD_19_CTRL = wdata0;
IOMUX_PAD_20_CTRL = wdata0;
IOMUX_PAD_21_CTRL = wdata0;
IOMUX_PAD_22_CTRL = wdata0;
IOMUX_PAD_23_CTRL = wdata0;
IOMUX_PAD_24_CTRL = wdata0;
IOMUX_PAD_25_CTRL = wdata0;
IOMUX_PAD_26_CTRL = wdata0;
IOMUX_PAD_27_CTRL = wdata0;
IOMUX_PAD_28_CTRL = wdata0;
IOMUX_PAD_29_CTRL = wdata0;
IOMUX_PAD_30_CTRL = wdata0;
IOMUX_PAD_31_CTRL = wdata0;
IOMUX_PAD_32_CTRL = wdata0;
IOMUX_PAD_33_CTRL = wdata0;
IOMUX_PAD_34_CTRL = wdata1;
IOMUX_PAD_35_CTRL = wdata0;
IOMUX_PAD_36_CTRL = wdata0;
IOMUX_PAD_37_CTRL = wdata0;
IOMUX_PAD_38_CTRL = wdata1;
IOMUX_PAD_39_CTRL = wdata1;
IOMUX_PAD_40_CTRL = wdata0;
IOMUX_PAD_41_CTRL = wdata0;
IOMUX_PAD_42_CTRL = wdata0;
IOMUX_PAD_43_CTRL = wdata1;
IOMUX_PAD_42_CTRL = wdata0;
IOMUX_PAD_43_CTRL = wdata1;// FBIO43
IOMUX_PAD_44_CTRL = wdata1; //FBIO44
IOMUX_PAD_45_CTRL = wdata0; // FBIO45

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// enable the FBIO pads to reach the PADS

IOMUX_FBIO_SEL_1 = 0xFFFFFFFF;// select fbio 0 - 31
IOMUX_FBIO_SEL_2 = 0x3FFF; // select fbio 32 - 45

return;
}

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QuickLogic® EOSTM S3 Sensor Processing Platform Input/Output Multiplexor (IOMUX) User Guide Rev 1.1

Appendix
Table 11 shows the EOS S3 IOMUX output assignments.

Table 11: Functional IOMUX

Pad Mux Sel for Ball Name/ Type Def Ctrl Def Def Def Must Comment
No. OUT Function P Out RX Bond
(Default=0) En En
0 0 SCL0 BIDIR A0_Reg PU N N Y OE can be
controlled by FFE
0 1 FBIO_0 BIDIR

1 0 SDA0 BIDIR A0_Reg PU N N Y OE can be

controlled by FFE
1 1 FBIO_1 BIDIR

2 0 FBIO_2 BIDIR A0_Reg Z N N

2 1 spi_sensor_ssn2 OUT

2 2 debug_mon[0] OUT

2 3 batt_mon OUT

2 sensor_interrupt IN

3 0 S_INTR_0 IN A0_Reg Z N N Y

3 0 FBIO_3 BIDIR

4 0 FBIO_4 BIDIR A0_Reg Z N N

4 1 spi_sensor_ssn3 OUT

4 2 debug_mon[1] OUT

4 3 sda_1_dpu OUT

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QuickLogic® EOSTM S3 Sensor Processing Platform Input/Output Multiplexor (IOMUX) User Guide Rev 1.1

Pad Mux Sel for Ball Name/ Type Def Ctrl Def Def Def Must Comment
No. OUT Function P Out RX Bond
(Default=0) En En
4 sensor_interrupt IN

5 0 FBIO_5 BIDIR A0_Reg Z N N

5 1 spi_sensor_ssn4 OUT

5 2 debug_mon[2] OUT

5 3 sda_0_dpu OUT

5 sensor_interrupt IN

6 0 FBIO_6 BIDIR A0_Reg Z N N Y

6 1 spi_sensor_mosi OUT

6 2 debug_mon[3] BIDIR

6 3 gpio[0] BIDIR

6 IN

6 IN

6 FCLK IN Bootstrap #9 = 1

6 IrDA_Sirin IN

6 sensor_interrupt IN

7 0 FBIO_7 BIDIR A0_Reg Z N N

7 1 spi_sensor_ssn5 OUT

7 2 debug_mon[4] OUT

7 3 SWV OUT

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QuickLogic® EOSTM S3 Sensor Processing Platform Input/Output Multiplexor (IOMUX) User Guide Rev 1.1

Pad Mux Sel for Ball Name/ Type Def Ctrl Def Def Def Must Comment
No. OUT Function P Out RX Bond
(Default=0) En En
7 sensor_interrupt IN

8 0 FBIO_8 BIDIR A0_Reg Z N N Y

8 1 pdm_cko OUT

8 2 i2s_cko OUT

8 3 IrDA_Sirout OUT

8 sensor_interrupt IN

8 spi_sensor_miso IN

9 0 FBIO_9 BIDIR A0_Reg PD N Y Y

9 1 spi_sensor_ssn1 OUT Select controls from

A0 (PAD_5_CTRL_
SEL=0x0)
9 2 i2s_wd_cko OUT

9 3 gpio[1] BIDIR

9 pdm_stat_i IN

9 sensor_interrupt IN

10 0 FBIO_10 BIDIR A0_Reg PD N N

10 1 spi_sensor_clk OUT Y

10 2 Reserved

10 3 SWV OUT

10 sensor_interrupt IN

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QuickLogic® EOSTM S3 Sensor Processing Platform Input/Output Multiplexor (IOMUX) User Guide Rev 1.1

Pad Mux Sel for Ball Name/ Type Def Ctrl Def Def Def Must Comment
No. OUT Function P Out RX Bond
(Default=0) En En
10 i2s_din IN

10 pdm_din IN

11 0 FBIO_11 BIDIR A0_Reg Z N N

11 1 spi_sensor_ssn6 OUT

11 2 debug_mon[5] OUT

11 3 gpio[2] BIDIR

11 sensor_interrupt IN

12 0 FBIO_12 BIDIR A0_Reg Z N N

12 1 spi_sensor_ssn7 OUT

12 2 debug_mon[6] OUT

12 3 IrDA_Sirout OUT

12 sensor_interrupt IN

13 0 FBIO_13 BIDIR A0_Reg Z N N

13 1 spi_sensor_ssn8 OUT

13 2 debug_mon[7] OUT

13 3 SWV OUT

13 sensor_interrupt IN

14 0 SW_DP_CLK IN Others PU N Y Y Bootstrap #8 = 0

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QuickLogic® EOSTM S3 Sensor Processing Platform Input/Output Multiplexor (IOMUX) User Guide Rev 1.1

Pad Mux Sel for Ball Name/ Type Def Ctrl Def Def Def Must Comment
No. OUT Function P Out RX Bond
(Default=0) En En
14 0 FBIO_14 BIDIR Z N N Choose this when
#8 = 1
14 1 IrDA_Sirout OUT

14 2 SCL_1 BIDIR

14 3 gpio[3] BIDIR

14 UART_rxd IN

14 sensor_interrupt IN

15 0 SW_DP_IO BIDIR Others PU M4 Y Y Bootstrap #8 = 0

15 1 FBIO_15 BIDIR Z N N Choose this when

#8 = 1
15 2 SDA_1 BIDIR

15 3 UART_txd OUT

15 sensor_interrupt IN

15 IrDA_Sirin IN

16 0 SPIs_CLK IN A0_Reg Z N Y Y Bootstrap #20 = 1

16 0 FBIO_16 BIDIR A0_Reg Z N N

16 UART_rxd IN

17 0 SPIs_MISO OUT Others Z SPIs_ N Y Bootstrap #20 = 1

SSn
17 1 FBIO_17 BIDIR Z N N

17 nUARTCTS IN

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QuickLogic® EOSTM S3 Sensor Processing Platform Input/Output Multiplexor (IOMUX) User Guide Rev 1.1

Pad Mux Sel for Ball Name/ Type Def Ctrl Def Def Def Must Comment
No. OUT Function P Out RX Bond
(Default=0) En En
18 0 FBIO_18 BIDIR A0_Reg Z N N

18 1 SWV OUT

18 2 debug_mon[0] OUT

18 3 gpio[4] BIDIR

18 sensor_interrupt IN

19 0 SPIs_MOSI IN A0_Reg PD N Y Y Bootstrap #20 = 1

This is used as a
bootstrap for
debugger mode as
a M4 reset release
mechanism
19 0 FBIO_19 BIDIR A0_Reg Z N N

19 1 nUARTRTS OUT

20 0 SPIs_SSn IN A0_Reg PD N Y Y

20 0 FBIO_20 BIDIR A0_Reg Z N N

20 1 UART_txd OUT This is for UART

BLE, and as output
to prevent
strapping

21 0 FBIO_21 BIDIR A0_Reg Z N N

21 1 nUARTRTS OUT

21 2 debug_mon[1] OUT

21 3 gpio[5] BIDIR

21 IrDA_Sirin IN

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QuickLogic® EOSTM S3 Sensor Processing Platform Input/Output Multiplexor (IOMUX) User Guide Rev 1.1

Pad Mux Sel for Ball Name/ Type Def Ctrl Def Def Def Must Comment
No. OUT Function P Out RX Bond
(Default=0) En En
21 sensor_interrupt IN

22 0 FBIO_22 BIDIR A0_Reg Z N N

22 1 IrDA_Sirout OUT

22 2 debug_mon[2] OUT

22 3 gpio[6] BIDIR

22 sensor_interrupt IN

22 nUARTCTS IN

23 0 FBIO_23 BIDIR A0_Reg Z N N Y

23 1 SPIm_SSn2 OUT

23 2 SWV OUT

23 3 gpio[7] BIDIR

23 ap_i2s_wd_clk_i IN
n
23 sensor_interrupt IN

24 0 FBIO_24 BIDIR A0_Reg Z N N Y

24 1 ap_i2s_dout OUT

24 2 UART_txd OUT

24 3 gpio[0] BIDIR

24 IrDA_Sirin IN

24 sensor_interrupt IN

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QuickLogic® EOSTM S3 Sensor Processing Platform Input/Output Multiplexor (IOMUX) User Guide Rev 1.1

Pad Mux Sel for Ball Name/ Type Def Ctrl Def Def Def Must Comment
No. OUT Function P Out RX Bond
(Default=0) En En

25 0 FBIO_25 BIDIR A0_Reg Z N N Y

25 1 SPIm_SSn3 OUT

25 2 SWV OUT

25 3 IrDA_Sirout OUT

25 IN

25 UART_rxd IN

25 sensor_interrupt IN

26 0 FBIO_26 BIDIR A0_Reg Z N N

26 1 spi_sensor_ssn4 OUT

26 2 debug_mon[3] OUT

26 3 gpio[1] BIDIR

26 sensor_interrupt IN

27 0 FBIO_27 BIDIR A0_Reg Z N N

27 1 spi_sensor_ssn5 OUT

27 2 debug_mon[4] OUT

27 3 SPIm_SSn2 OUT

27 sensor_interrupt IN

28 0 FBIO_28 BIDIR A0_Reg Z N N Y

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QuickLogic® EOSTM S3 Sensor Processing Platform Input/Output Multiplexor (IOMUX) User Guide Rev 1.1

Pad Mux Sel for Ball Name/ Type Def Ctrl Def Def Def Must Comment
No. OUT Function P Out RX Bond
(Default=0) En En
28 1 spi_sensor_mosi OUT

28 2 debug_mon[5] BIDIR

28 3 gpio[2] BIDIR

28 i2s_din IN

28 pdm_din IN

28 sensor_interrupt IN

28 IrDA_Sirin IN

29 0 FBIO_29 BIDIR A0_Reg Z N N Y

29 1 pdm_cko OUT

29 2 i2s_cko OUT

29 3 IrDA_Sirout OUT

29 sensor_interrupt IN

29 spi_sensor_miso IN

30 0 FBIO_30 BIDIR A0_Reg PD N Y Y

30 1 spi_sensor_ssn1 OUT Select controls from

A0 (PAD_5_CTRL_
SEL=0x0)
30 2 i2s_wd_cko OUT

30 3 gpio[3] BIDIR

30 pdm_stat_i IN

30 sensor_interrupt IN

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QuickLogic® EOSTM S3 Sensor Processing Platform Input/Output Multiplexor (IOMUX) User Guide Rev 1.1

Pad Mux Sel for Ball Name/ Type Def Ctrl Def Def Def Must Comment
No. OUT Function P Out RX Bond
(Default=0) En En

31 0 FBIO_31 BIDIR A0_Reg PD N N

31 1 spi_sensor_clk OUT Y

31 2 Reserved

31 3 gpio[4] BIDIR

31 sensor_interrupt IN

31 ap_i2s_clk_in IN

32 0 FBIO_32 BIDIR A0_Reg Z N N

32 1 spi_sensor_ssn5 OUT

32 2 debug_mon[6] OUT

32 3 SDA_1 OUT

32 sensor_interrupt IN

33 0 FBIO_33 BIDIR A0_Reg Z N N

33 1 spi_sensor_ssn6 OUT

33 2 debug_mon[7] OUT

33 3 SCL_1 OUT

33 sensor_interrupt IN

34 0 SPIm_CLK OUT Others Z Y N Y Bootstrap #20 = 0

34 1 FBIO_34 BIDIR Others Z N N Choose this when

#20 = 1

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QuickLogic® EOSTM S3 Sensor Processing Platform Input/Output Multiplexor (IOMUX) User Guide Rev 1.1

Pad Mux Sel for Ball Name/ Type Def Ctrl Def Def Def Must Comment
No. OUT Function P Out RX Bond
(Default=0) En En
34 2 ap_pdm_stat_o BIDIR

34 3 debug_mon[0] OUT

34 sensor_interrupt IN

35 0 FBIO_35 BIDIR A0_Reg Z N N

35 1 SPIm_SSn3 OUT

35 2 spi_sensor_ssn7 OUT

35 3 debug_mon[1] OUT

35 sensor_interrupt IN

36 0 SPIm_MISO IN Others Z N Y Y Bootstrap #20 = 0

36 0 FBIO_36 BIDIR Others Z N N Choose this when

#20 = 1
36 1 SWV OUT

36 2 spi_sensor_ssn2 BIDIR

36 3 gpio[5] BIDIR

36 sensor_interrupt IN

37 0 FBIO_37 BIDIR A0_Reg Z N N

37 1 SDA_2_DPU OUT

37 2 spi_sensor_ssn8 OUT

37 3 debug_mon[2] OUT

37 sensor_interrupt IN

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QuickLogic® EOSTM S3 Sensor Processing Platform Input/Output Multiplexor (IOMUX) User Guide Rev 1.1

Pad Mux Sel for Ball Name/ Type Def Ctrl Def Def Def Must Comment
No. OUT Function P Out RX Bond
(Default=0) En En

38 0 SPIm_MOSI OUT Others Z Y N Y Bootstrap #20 = 0

38 1 FBIO_38 BIDIR Others Z N N Choose this when

#20 = 1
38 2 debug_mon[3] BIDIR

38 3 gpio[6] BIDIR

38 sensor_interrupt IN

38 ap_pdm_cko_in IN

39 0 SPIm_SSn1 OUT Others Z Y N Y Bootstrap #20 = 0

39 1 FBIO_39 BIDIR Others Z N N Choose this when

#20 = 1
39 2 ap_pdm_io OUT

39 3 debug_mon[4] OUT

39 sensor_interrupt IN

40 0 FBIO_40 BIDIR A0_Reg Z N N

40 1 SCL_2 OUT

40 2 debug_mon[5] OUT

40 3 Reserved BIDIR

40 sensor_interrupt IN

40 IrDA_Sirin IN

41 0 FBIO_41 BIDIR A0_Reg Z N N

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QuickLogic® EOSTM S3 Sensor Processing Platform Input/Output Multiplexor (IOMUX) User Guide Rev 1.1

Pad Mux Sel for Ball Name/ Type Def Ctrl Def Def Def Must Comment
No. OUT Function P Out RX Bond
(Default=0) En En
41 1 SDA_2 OUT

41 2 debug_mon[6] OUT

41 3 IrDA_Sirout

41 sensor_interrupt IN

42 0 FBIO_42 BIDIR A0_Reg Z N N

42 1 SWV OUT

42 2 debug_mon[7] OUT

42 3 SDA_1_DPU

42 sensor_interrupt IN

43 0 AP_INTR OUT A0_Reg Z N N Y

43 1 FBIO_43 BIDIR

44 0 SW_DP_IO BIDIR Other PU M4 Y Y Bootstrap #8 = 1

44 1 FBIO_44 BIDIR A0_Reg Z N N Choose this when

#8 = 0
44 2 SDA_1 BIDIR

44 3 UART_txd BIDIR

44 sensor_interrupt IN

44 IrDA_Sirin IN

45 0 SW_DP_CLK IN Other PU N Y Y Bootstrap #8 = 1

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QuickLogic® EOSTM S3 Sensor Processing Platform Input/Output Multiplexor (IOMUX) User Guide Rev 1.1

Pad Mux Sel for Ball Name/ Type Def Ctrl Def Def Def Must Comment
No. OUT Function P Out RX Bond
(Default=0) En En
45 0 FBIO_45 BIDIR A0_Reg Z N N Choose this when
#8 = 0
45 1 IrDA_Sirout OUT

45 2 SCL_1 OUT

45 3 gpio[7] BIDIR

45 sensor_interrupt IN

45 UART_rxd IN

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QuickLogic® EOSTM S3 Sensor Processing Platform Input/Output Multiplexor (IOMUX) User Guide Rev 1.1

Table 12 shows the IOMUX registers descriptions as reference. The IOMUX address base is at 0x40004C00. Add the register offset
to the address base for the exact register address. The complete EOS S3 register map can be found in the QuickLogic EOS S3 Sensor
Processing Platform Register Map Guide.

Table 12: IOMUX Registers

Offset Name/Field Bits Type Default Description

PAD_0_CTRL 31:0

Functional selection for IO output. For

PAD_0_FUNC_SEL 1:0 RW 0x0 details, see the Appendix – Table
11.
Control selection for IO output
0x0: A0 registers (as defined below)
PAD_0_CTRL_SEL 4:3 RW 0x0 0x1: Others
0x2: Fabric

Active low output enable

PAD_0_OEN 5 RW 0x1 0x1: driver disabled
0x0: normal operation

Driver state control

0x0: Z
PAD_0_P 7:6 RW 0x1 0x1: pull up
0x000 0x2: pull down
0x3: keeper

Drive Strength
0x0: 2mA
PAD_0_E 9:8 RW 0x1 0x1: 4mA
0x2: 8mA
0x3: 12mA

Slew Rate
PAD_0_SR 10 RW 0x0 0x1: Fast
0x0: Slow (half frequency)

Receive enable
PAD_0_REN 11 RW 0x0 0x1: enable
0x0: disable

Schmitt Trigger
PAD_0_SMT 12 RW 0x0 0x1: enable
0x0: disable

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QuickLogic® EOSTM S3 Sensor Processing Platform Input/Output Multiplexor (IOMUX) User Guide Rev 1.1

Offset Name/Field Bits Type Default Description

PAD_1_CTRL 31:0

Functional selection for IO output. For

PAD_1_FUNC_SEL 1:0 RW 0x0 details, see the Appendix – Table
11.
Control selection for IO output
0x0: A0 registers (as defined below)
PAD_1_CTRL_SEL 4:3 RW 0x0 0x1: Others
0x2: Fabric

Active low output enable

PAD_1_OEN 5 RW 0x1 0x1: driver disabled
0x0: normal operation

Driver state control

0x0: Z
PAD_1_P 7:6 RW 0x1 0x1: pull up
0x004 0x2: pull down
0x3: keeper

Drive Strength
0x0: 2mA
PAD_1_E 9:8 RW 0x1 0x1: 4mA
0x2: 8mA
0x3: 12mA

Slew Rate
PAD_1_SR 10 RW 0x0 0x1: Fast
0x0: Slow (half frequency)

Receive enable
PAD_1_REN 11 RW 0x0 0x1: enable
0x0: disable

Schmitt Trigger
PAD_1_SMT 12 RW 0x0 0x1: enable
0x0: disable

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QuickLogic® EOSTM S3 Sensor Processing Platform Input/Output Multiplexor (IOMUX) User Guide Rev 1.1

Offset Name/Field Bits Type Default Description

PAD_2_CTRL 31:0

Functional selection for IO output. For

PAD_2_FUNC_SEL 1:0 RW 0x0 details, see the Appendix – Table
11.
Control selection for IO output
0x0: A0 registers (as defined below)
PAD_2_CTRL_SEL 4:3 RW 0x0 0x1: Others
0x2: Fabric

Active low output enable

PAD_2_OEN 5 RW 0x1 0x1: driver disabled
0x0: normal operation

Driver state control

0x0: Z
PAD_2_P 7:6 RW 0x0 0x1: pull up
0x008 0x2: pull down
0x3: keeper

Drive Strength
0x0: 2mA
PAD_2_E 9:8 RW 0x1 0x1: 4mA
0x2: 8mA
0x3: 12mA

Slew Rate
PAD_2_SR 10 RW 0x0 0x1: Fast
0x0: Slow (half frequency)

Receive enable
PAD_2_REN 11 RW 0x0 0x1: enable
0x0: disable

Schmitt Trigger
PAD_2_SMT 12 RW 0x0 0x1: enable
0x0: disable

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QuickLogic® EOSTM S3 Sensor Processing Platform Input/Output Multiplexor (IOMUX) User Guide Rev 1.1

Offset Name/Field Bits Type Default Description

PAD_3_CTRL 31:0

Functional selection for IO output. For

PAD_3_FUNC_SEL 1:0 RW 0x0 details, see the Appendix – Table
11.
Control selection for IO output
0x0: A0 registers (as defined below)
PAD_3_CTRL_SEL 4:3 RW 0x0 0x1: Others
0x2: Fabric

Active low output enable

PAD_3_OEN 5 RW 0x1 0x1: driver disabled
0x0: normal operation

Driver state control

0x0: Z
PAD_3_P 7:6 RW 0x0 0x1: pull up
0x00C 0x2: pull down
0x3: keeper

Drive Strength
0x0: 2mA
PAD_3_E 9:8 RW 0x1 0x1: 4mA
0x2: 8mA
0x3: 12mA

Slew Rate
PAD_3_SR 10 RW 0x0 0x1: Fast
0x0: Slow (half frequency)

Receive enable
PAD_3_REN 11 RW 0x0 0x1: enable
0x0: disable

Schmitt Trigger
PAD_3_SMT 12 RW 0x0 0x1: enable
0x0: disable

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QuickLogic® EOSTM S3 Sensor Processing Platform Input/Output Multiplexor (IOMUX) User Guide Rev 1.1

Offset Name/Field Bits Type Default Description

PAD_4_CTRL 31:0

Functional selection for IO output. For

PAD_4_FUNC_SEL 1:0 RW 0x0 details, see the Appendix – Table
11.
Control selection for IO output
0x0: A0 registers (as defined below)
PAD_4_CTRL_SEL 4:3 RW 0x0 0x1: Others
0x2: Fabric

Active low output enable

PAD_4_OEN 5 RW 0x1 0x1: driver disabled
0x0: normal operation

Driver state control

0x0: Z
PAD_4_P 7:6 RW 0x0 0x1: pull up
0x010 0x2: pull down
0x3: keeper

Drive Strength
0x0: 2mA
PAD_4_E 9:8 RW 0x1 0x1: 4mA
0x2: 8mA
0x3: 12mA

Slew Rate
PAD_4_SR 10 RW 0x0 0x1: Fast
0x0: Slow (half frequency)

Receive enable
PAD_4_REN 11 RW 0x0 0x1: enable
0x0: disable

Schmitt Trigger
PAD_4_SMT 12 RW 0x0 0x1: enable
0x0: disable

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QuickLogic® EOSTM S3 Sensor Processing Platform Input/Output Multiplexor (IOMUX) User Guide Rev 1.1

Offset Name/Field Bits Type Default Description

PAD_5_CTRL 31:0

Functional selection for IO output. For

PAD_5_FUNC_SEL 1:0 RW 0x0 details, see the Appendix – Table
11.
Control selection for IO output
0x0: A0 registers (as defined below) *
0x1: Others
PAD_5_CTRL_SEL 4:3 RW 0x0 0x2: Fabric
* Exception: when FUNC_SEL=2, the
control is from FFE.

Active low output enable

PAD_5_OEN 5 RW 0x1 0x1: driver disabled
0x0: normal operation

Driver state control

0x0: Z
0x014 PAD_5_P 7:6 RW 0x0 0x1: pull up
0x2: pull down
0x3: keeper

Drive Strength
0x0: 2mA
PAD_5_E 9:8 RW 0x1 0x1: 4mA
0x2: 8mA
0x3: 12mA

Slew Rate
PAD_5_SR 10 RW 0x0 0x1: Fast
0x0: Slow (half frequency)

Receive enable
PAD_5_REN 11 RW 0x0 0x1: enable
0x0: disable

Schmitt Trigger
PAD_5_SMT 12 RW 0x0 0x1: enable
0x0: disable

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QuickLogic® EOSTM S3 Sensor Processing Platform Input/Output Multiplexor (IOMUX) User Guide Rev 1.1

Offset Name/Field Bits Type Default Description

PAD_6_CTRL 31:0

Functional selection for IO output. For

PAD_6_FUNC_SEL 1:0 RW 0x0 details, see the Appendix – Table
11.
Control selection for IO output
0x0: A0 registers (as defined below) *
0x1: Others
PAD_6_CTRL_SEL 4:3 RW 0x1 0x2: Fabric
* Exception: when FUNC_SEL=2, the
control is from FFE.

Active low output enable

PAD_6_OEN 5 RW 0x1 0x1: driver disabled
0x0: normal operation

Driver state control

0x0: Z
0x018 PAD_6_P 7:6 RW 0x0 0x1: pull up
0x2: pull down
0x3: keeper

Drive Strength
0x0: 2mA
PAD_6_E 9:8 RW 0x1 0x1: 4mA
0x2: 8mA
0x3: 12mA

Slew Rate
PAD_6_SR 10 RW 0x0 0x1: Fast
0x0: Slow (half frequency)

Receive enable
PAD_6_REN 11 RW 0x0 0x1: enable
0x0: disable

Schmitt Trigger
PAD_6_SMT 12 RW 0x0 0x1: enable
0x0: disable

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QuickLogic® EOSTM S3 Sensor Processing Platform Input/Output Multiplexor (IOMUX) User Guide Rev 1.1

Offset Name/Field Bits Type Default Description

PAD_7_CTRL 31:0

Functional selection for IO output. For

PAD_7_FUNC_SEL 1:0 RW 0x0 details, see the Appendix – Table
11.
Control selection for IO output
0x0: A0 registers (as defined below)
PAD_7_CTRL_SEL 4:3 RW 0x0 0x1: Others
0x2: Fabric

Active low output enable

PAD_7_OEN 5 RW 0x1 0x1: driver disabled
0x0: normal operation

Driver state control

0x0: Z
PAD_7_P 7:6 RW 0x0 0x1: pull up
0x01C 0x2: pull down
0x3: keeper

Drive Strength
0x0: 2mA
PAD_7_E 9:8 RW 0x1 0x1: 4mA
0x2: 8mA
0x3: 12mA

Slew Rate
PAD_7_SR 10 RW 0x0 0x1: Fast
0x0: Slow (half frequency)

Receive enable
PAD_7_REN 11 RW 0x0 0x1: enable
0x0: disable

Schmitt Trigger
PAD_7_SMT 12 RW 0x0 0x1: enable
0x0: disable

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QuickLogic® EOSTM S3 Sensor Processing Platform Input/Output Multiplexor (IOMUX) User Guide Rev 1.1

Offset Name/Field Bits Type Default Description

PAD_8_CTRL 31:0

Functional selection for IO output. For

PAD_8_FUNC_SEL 1:0 RW 0x0 details, see the Appendix – Table
11.
Control selection for IO output
0x0: A0 registers (as defined below)
PAD_8_CTRL_SEL 4:3 RW 0x0 0x1: Others
0x2: Fabric

Active low output enable

PAD_8_OEN 5 RW 0x1 0x1: driver disabled
0x0: normal operation

Driver state control

0x0: Z
PAD_8_P 7:6 RW 0x2 0x1: pull up
0x020 0x2: pull down
0x3: keeper

Drive Strength
0x0: 2mA
PAD_8_E 9:8 RW 0x1 0x1: 4mA
0x2: 8mA
0x3: 12mA

Slew Rate
PAD_8_SR 10 RW 0x0 0x1: Fast
0x0: Slow (half frequency)

Receive enable
PAD_8_REN 11 RW 0x1 0x1: enable
0x0: disable

Schmitt Trigger
PAD_8_SMT 12 RW 0x0 0x1: enable
0x0: disable

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QuickLogic® EOSTM S3 Sensor Processing Platform Input/Output Multiplexor (IOMUX) User Guide Rev 1.1

Offset Name/Field Bits Type Default Description

PAD_9_CTRL 31:0

Functional selection for IO output. For

PAD_9_FUNC_SEL 1:0 RW 0x0 details, see the Appendix – Table
11.
Control selection for IO output
0x0: A0 registers (as defined below)
PAD_9_CTRL_SEL 4:3 RW 0x0 0x1: Others
0x2: Fabric

Active low output enable

PAD_9_OEN 5 RW 0x1 0x1: driver disabled
0x0: normal operation

Driver state control

0x0: Z
PAD_9_P 7:6 RW 0x2 0x1: pull up
0x024 0x2: pull down
0x3: keeper

Drive Strength
0x0: 2mA
PAD_9_E 9:8 RW 0x1 0x1: 4mA
0x2: 8mA
0x3: 12mA

Slew Rate
PAD_9_SR 10 RW 0x0 0x1: Fast
0x0: Slow (half frequency)

Receive enable
PAD_9_REN 11 RW 0x1 0x1: enable
0x0: disable

Schmitt Trigger
PAD_9_SMT 12 RW 0x0 0x1: enable
0x0: disable

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QuickLogic® EOSTM S3 Sensor Processing Platform Input/Output Multiplexor (IOMUX) User Guide Rev 1.1

Offset Name/Field Bits Type Default Description

PAD_10_CTRL 31:0

Functional selection for IO output. For

PAD_10_FUNC_SEL 1:0 RW 0x0 details, see the Appendix – Table
11.
Control selection for IO output
0x0: A0 registers (as defined below)
PAD_10_CTRL_SEL 4:3 RW 0x0 0x1: Others
0x2: Fabric

Active low output enable

PAD_10_OEN 5 RW 0x1 0x1: driver disabled
0x0: normal operation

Driver state control

0x0: Z
PAD_10_P 7:6 RW 0x0 0x1: pull up
0x028 0x2: pull down
0x3: keeper

Drive Strength
0x0: 2mA
PAD_10_E 9:8 RW 0x1 0x1: 4mA
0x2: 8mA
0x3: 12mA

Slew Rate
PAD_10_SR 10 RW 0x0 0x1: Fast
0x0: Slow (half frequency)

Receive enable
PAD_10_REN 11 RW 0x0 0x1: enable
0x0: disable

Schmitt Trigger
PAD_10_SMT 12 RW 0x0 0x1: enable
0x0: disable

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QuickLogic® EOSTM S3 Sensor Processing Platform Input/Output Multiplexor (IOMUX) User Guide Rev 1.1

Offset Name/Field Bits Type Default Description

PAD_11_CTRL 31:0

Functional selection for IO output. For

PAD_11_FUNC_SEL 1:0 RW 0x0 details, see the Appendix – Table
11.
Control selection for IO output
0x0: A0 registers (as defined below)
PAD_11_CTRL_SEL 4:3 RW 0x0 0x1: Others
0x2: Fabric

Active low output enable

PAD_11_OEN 5 RW 0x1 0x1: driver disabled
0x0: normal operation

Driver state control

0x0: Z
PAD_11_P 7:6 RW 0x0 0x1: pull up
0x02C 0x2: pull down
0x3: keeper

Drive Strength
0x0: 2mA
PAD_11_E 9:8 RW 0x1 0x1: 4mA
0x2: 8mA
0x3: 12mA

Slew Rate
PAD_11_SR 10 RW 0x0 0x1: Fast
0x0: Slow (half frequency)

Receive enable
PAD_11_REN 11 RW 0x0 0x1: enable
0x0: disable

Schmitt Trigger
PAD_11_SMT 12 RW 0x0 0x1: enable
0x0: disable

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QuickLogic® EOSTM S3 Sensor Processing Platform Input/Output Multiplexor (IOMUX) User Guide Rev 1.1

Offset Name/Field Bits Type Default Description

PAD_12_CTRL 31:0

Functional selection for IO output. For

PAD_12_FUNC_SEL 1:0 RW 0x0 details, see the Appendix – Table
11.
Control selection for IO output
0x0: A0 registers (as defined below)
PAD_12_CTRL_SEL 4:3 RW 0x0 0x1: Others
0x2: Fabric

Active low output enable

PAD_12_OEN 5 RW 0x1 0x1: driver disabled
0x0: normal operation

Driver state control

0x0: Z
PAD_12_P 7:6 RW 0x0 0x1: pull up
0x030 0x2: pull down
0x3: keeper

Drive Strength
0x0: 2mA
PAD_12_E 9:8 RW 0x1 0x1: 4mA
0x2: 8mA
0x3: 12mA

Slew Rate
PAD_12_SR 10 RW 0x0 0x1: Fast
0x0: Slow (half frequency)

Receive enable
PAD_12_REN 11 RW 0x0 0x1: enable
0x0: disable

Schmitt Trigger
PAD_12_SMT 12 RW 0x0 0x1: enable
0x0: disable

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QuickLogic® EOSTM S3 Sensor Processing Platform Input/Output Multiplexor (IOMUX) User Guide Rev 1.1

Offset Name/Field Bits Type Default Description

PAD_13_CTRL 31:0

Functional selection for IO output. For

PAD_13_FUNC_SEL 1:0 RW 0x0 details, see the Appendix – Table
11.
Control selection for IO output
0x0: A0 registers (as defined below)
PAD_13_CTRL_SEL 4:3 RW 0x0 0x1: Others
0x2: Fabric

Active low output enable

PAD_13_OEN 5 RW 0x1 0x1: driver disabled
0x0: normal operation

Driver state control

0x0: Z
PAD_13_P 7:6 RW 0x0 0x1: pull up
0x034 0x2: pull down
0x3: keeper

Drive Strength
0x0: 2mA
PAD_13_E 9:8 RW 0x1 0x1: 4mA
0x2: 8mA
0x3: 12mA

Slew Rate
PAD_13_SR 10 RW 0x0 0x1: Fast
0x0: Slow (half frequency)

Receive enable
PAD_13_REN 11 RW 0x0 0x1: enable
0x0: disable

Schmitt Trigger
PAD_13_SMT 12 RW 0x0 0x1: enable
0x0: disable

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QuickLogic® EOSTM S3 Sensor Processing Platform Input/Output Multiplexor (IOMUX) User Guide Rev 1.1

Offset Name/Field Bits Type Default Description

PAD_14_CTRL 31:0

Functional selection for IO output. For

PAD_14_FUNC_SEL 1:0 RW 0x0 details, see the Appendix – Table
11.
Control selection for IO output
0x0: A0 registers (as defined below)
PAD_14_CTRL_SEL 4:3 RW 0x1 0x1: Others
0x2: Fabric

Active low output enable

PAD_14_OEN 5 RW 0x1 0x1: driver disabled
0x0: normal operation

Driver state control

0x0: Z
PAD_14_P 7:6 RW 0x0 0x1: pull up
0x038 0x2: pull down
0x3: keeper

Drive Strength
0x0: 2mA
PAD_14_E 9:8 RW 0x1 0x1: 4mA
0x2: 8mA
0x3: 12mA

Slew Rate
PAD_14_SR 10 RW 0x0 0x1: Fast
0x0: Slow (half frequency)

Receive enable
PAD_14_REN 11 RW 0x0 0x1: enable
0x0: disable

Schmitt Trigger
PAD_14_SMT 12 RW 0x0 0x1: enable
0x0: disable

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QuickLogic® EOSTM S3 Sensor Processing Platform Input/Output Multiplexor (IOMUX) User Guide Rev 1.1

Offset Name/Field Bits Type Default Description

PAD_15_CTRL 31:0

Functional selection for IO output. For

PAD_15_FUNC_SEL 1:0 RW 0x0 details, see the Appendix – Table
11.
Control selection for IO output
0x0: A0 registers (as defined below)
PAD_15_CTRL_SEL 4:3 RW 0x1 0x1: Others
0x2: Fabric

Active low output enable

PAD_15_OEN 5 RW 0x1 0x1: driver disabled
0x0: normal operation

Driver state control

0x0: Z
PAD_15_P 7:6 RW 0x0 0x1: pull up
0x03C 0x2: pull down
0x3: keeper

Drive Strength
0x0: 2mA
PAD_15_E 9:8 RW 0x1 0x1: 4mA
0x2: 8mA
0x3: 12mA

Slew Rate
PAD_15_SR 10 RW 0x0 0x1: Fast
0x0: Slow (half frequency)

Receive enable
PAD_15_REN 11 RW 0x0 0x1: enable
0x0: disable

Schmitt Trigger
PAD_15_SMT 12 RW 0x0 0x1: enable
0x0: disable

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QuickLogic® EOSTM S3 Sensor Processing Platform Input/Output Multiplexor (IOMUX) User Guide Rev 1.1

Offset Name/Field Bits Type Default Description

PAD_16_CTRL 31:0

Functional selection for IO output. For

PAD_16_FUNC_SEL 1:0 RW 0x0 details, see the Appendix – Table
11.
Control selection for IO output
0x0: A0 registers (as defined below)
PAD_16_CTRL_SEL 4:3 RW 0x0 0x1: Others
0x2: Fabric

Active low output enable

PAD_16_OEN 5 RW 0x1 0x1: driver disabled
0x0: normal operation

Driver state control

0x0: Z
PAD_16_P 7:6 RW 0x0 0x1: pull up
0x040 0x2: pull down
0x3: keeper

Drive Strength
0x0: 2mA
PAD_16_E 9:8 RW 0x1 0x1: 4mA
0x2: 8mA
0x3: 12mA

Slew Rate
PAD_16_SR 10 RW 0x0 0x1: Fast
0x0: Slow (half frequency)

Receive enable
PAD_16_REN 11 RW 0x1 0x1: enable
0x0: disable

Schmitt Trigger
PAD_16_SMT 12 RW 0x0 0x1: enable
0x0: disable

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QuickLogic® EOSTM S3 Sensor Processing Platform Input/Output Multiplexor (IOMUX) User Guide Rev 1.1

Offset Name/Field Bits Type Default Description

PAD_17_CTRL 31:0

Functional selection for IO output. For

PAD_17_FUNC_SEL 1:0 RW 0x0 details, see the Appendix – Table
11.
Control selection for IO output
0x0: A0 registers (as defined below)
PAD_17_CTRL_SEL 4:3 RW 0x1 0x1: Others
0x2: Fabric

Active low output enable

PAD_17_OEN 5 RW 0x1 0x1: driver disabled
0x0: normal operation

Driver state control

0x0: Z
PAD_17_P 7:6 RW 0x0 0x1: pull up
0x044 0x2: pull down
0x3: keeper

Drive Strength
0x0: 2mA
PAD_17_E 9:8 RW 0x1 0x1: 4mA
0x2: 8mA
0x3: 12mA

Slew Rate
PAD_17_SR 10 RW 0x0 0x1: Fast
0x0: Slow (half frequency)

Receive enable
PAD_17_REN 11 RW 0x0 0x1: enable
0x0: disable

Schmitt Trigger
PAD_17_SMT 12 RW 0x0 0x1: enable
0x0: disable

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QuickLogic® EOSTM S3 Sensor Processing Platform Input/Output Multiplexor (IOMUX) User Guide Rev 1.1

Offset Name/Field Bits Type Default Description

PAD_18_CTRL 31:0

Functional selection for IO output. For

PAD_18_FUNC_SEL 1:0 RW 0x0 details, see the Appendix – Table
11.
Control selection for IO output
0x0: A0 registers (as defined below)
PAD_18_CTRL_SEL 4:3 RW 0x0 0x1: Others
0x2: Fabric

Active low output enable

PAD_18_OEN 5 RW 0x1 0x1: driver disabled
0x0: normal operation

Driver state control

0x0: Z
PAD_18_P 7:6 RW 0x0 0x1: pull up
0x048 0x2: pull down
0x3: keeper

Drive Strength
0x0: 2mA
PAD_18_E 9:8 RW 0x1 0x1: 4mA
0x2: 8mA
0x3: 12mA

Slew Rate
PAD_18_SR 10 RW 0x0 0x1: Fast
0x0: Slow (half frequency)

Receive enable
PAD_18_REN 11 RW 0x0 0x1: enable
0x0: disable

Schmitt Trigger
PAD_18_SMT 12 RW 0x0 0x1: enable
0x0: disable

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QuickLogic® EOSTM S3 Sensor Processing Platform Input/Output Multiplexor (IOMUX) User Guide Rev 1.1

Offset Name/Field Bits Type Default Description

PAD_19_CTRL 31:0

Functional selection for IO output. For

PAD_19_FUNC_SEL 1:0 RW 0x0 details, see the Appendix – Table
11.
Control selection for IO output
0x0: A0 registers (as defined below)
PAD_19_CTRL_SEL 4:3 RW 0x0 0x1: Others
0x2: Fabric

Active low output enable

PAD_19_OEN 5 RW 0x1 0x1: driver disabled
0x0: normal operation

Driver state control

0x0: Z
PAD_19_P 7:6 RW 0x2 0x1: pull up
0x04C 0x2: pull down
0x3: keeper

Drive Strength
0x0: 2mA
PAD_19_E 9:8 RW 0x1 0x1: 4mA
0x2: 8mA
0x3: 12mA

Slew Rate
PAD_19_SR 10 RW 0x0 0x1: Fast
0x0: Slow (half frequency)

Receive enable
PAD_19_REN 11 RW 0x1 0x1: enable
0x0: disable

Schmitt Trigger
PAD_19_SMT 12 RW 0x0 0x1: enable
0x0: disable

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QuickLogic® EOSTM S3 Sensor Processing Platform Input/Output Multiplexor (IOMUX) User Guide Rev 1.1

Offset Name/Field Bits Type Default Description

PAD_20_CTRL 31:0

Functional selection for IO output. For

PAD_20_FUNC_SEL 1:0 RW 0x0 details, see the Appendix – Table
11.
Control selection for IO output
0x0: A0 registers (as defined below)
PAD_20_CTRL_SEL 4:3 RW 0x0 0x1: Others
0x2: Fabric

Active low output enable

PAD_20_OEN 5 RW 0x1 0x1: driver disabled
0x0: normal operation

Driver state control

0x0: Z
PAD_20_P 7:6 RW 0x2 0x1: pull up
0x050 0x2: pull down
0x3: keeper

Drive Strength
0x0: 2mA
PAD_20_E 9:8 RW 0x1 0x1: 4mA
0x2: 8mA
0x3: 12mA

Slew Rate
PAD_20_SR 10 RW 0x0 0x1: Fast
0x0: Slow (half frequency)

Receive enable
PAD_20_REN 11 RW 0x1 0x1: enable
0x0: disable

Schmitt Trigger
PAD_20_SMT 12 RW 0x0 0x1: enable
0x0: disable

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QuickLogic® EOSTM S3 Sensor Processing Platform Input/Output Multiplexor (IOMUX) User Guide Rev 1.1

Offset Name/Field Bits Type Default Description

PAD_21_CTRL 31:0

Functional selection for IO output. For

PAD_21_FUNC_SEL 1:0 RW 0x0 details, see the Appendix – Table
11.
Control selection for IO output
0x0: A0 registers (as defined below)
PAD_21_CTRL_SEL 4:3 RW 0x0 0x1: Others
0x2: Fabric

Active low output enable

PAD_21_OEN 5 RW 0x1 0x1: driver disabled
0x0: normal operation

Driver state control

0x0: Z
PAD_21_P 7:6 RW 0x0 0x1: pull up
0x054 0x2: pull down
0x3: keeper

Drive Strength
0x0: 2mA
PAD_21_E 9:8 RW 0x1 0x1: 4mA
0x2: 8mA
0x3: 12mA

Slew Rate
PAD_21_SR 10 RW 0x0 0x1: Fast
0x0: Slow (half frequency)

Receive enable
PAD_21_REN 11 RW 0x0 0x1: enable
0x0: disable

Schmitt Trigger
PAD_21_SMT 12 RW 0x0 0x1: enable
0x0: disable

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QuickLogic® EOSTM S3 Sensor Processing Platform Input/Output Multiplexor (IOMUX) User Guide Rev 1.1

Offset Name/Field Bits Type Default Description

PAD_22_CTRL 31:0

Functional selection for IO output. For

PAD_22_FUNC_SEL 1:0 RW 0x0 details, see the Appendix – Table
11.
Control selection for IO output
0x0: A0 registers (as defined below)
PAD_22_CTRL_SEL 4:3 RW 0x0 0x1: Others
0x2: Fabric

Active low output enable

PAD_22_OEN 5 RW 0x1 0x1: driver disabled
0x0: normal operation

Driver state control

0x0: Z
PAD_22_P 7:6 RW 0x0 0x1: pull up
0x058 0x2: pull down
0x3: keeper

Drive Strength
0x0: 2mA
PAD_22_E 9:8 RW 0x1 0x1: 4mA
0x2: 8mA
0x3: 12mA

Slew Rate
PAD_22_SR 10 RW 0x0 0x1: Fast
0x0: Slow (half frequency)

Receive enable
PAD_22_REN 11 RW 0x0 0x1: enable
0x0: disable

Schmitt Trigger
PAD_22_SMT 12 RW 0x0 0x1: enable
0x0: disable

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QuickLogic® EOSTM S3 Sensor Processing Platform Input/Output Multiplexor (IOMUX) User Guide Rev 1.1

Offset Name/Field Bits Type Default Description

PAD_23_CTRL 31:0

Functional selection for IO output. For

PAD_23_FUNC_SEL 1:0 RW 0x0 details, see the Appendix – Table
11.
Control selection for IO output
0x0: A0 registers (as defined below)
PAD_23_CTRL_SEL 4:3 RW 0x0 0x1: Others
0x2: Fabric

Active low output enable

PAD_23_OEN 5 RW 0x1 0x1: driver disabled
0x0: normal operation

Driver state control

0x0: Z
PAD_23_P 7:6 RW 0x0 0x1: pull up
0x05C 0x2: pull down
0x3: keeper

Drive Strength
0x0: 2mA
PAD_23_E 9:8 RW 0x1 0x1: 4mA
0x2: 8mA
0x3: 12mA

Slew Rate
PAD_23_SR 10 RW 0x0 0x1: Fast
0x0: Slow (half frequency)

Receive enable
PAD_23_REN 11 RW 0x0 0x1: enable
0x0: disable

Schmitt Trigger
PAD_23_SMT 12 RW 0x0 0x1: enable
0x0: disable

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QuickLogic® EOSTM S3 Sensor Processing Platform Input/Output Multiplexor (IOMUX) User Guide Rev 1.1

Offset Name/Field Bits Type Default Description

PAD_24_CTRL 31:0

Functional selection for IO output. For

PAD_24_FUNC_SEL 1:0 RW 0x0 details, see the Appendix – Table
11.
Control selection for IO output
0x0: A0 registers (as defined below)
PAD_24_CTRL_SEL 4:3 RW 0x0 0x1: Others
0x2: Fabric

Active low output enable

PAD_24_OEN 5 RW 0x1 0x1: driver disabled
0x0: normal operation

Driver state control

0x0: Z
PAD_24_P 7:6 RW 0x0 0x1: pull up
0x060 0x2: pull down
0x3: keeper

Drive Strength
0x0: 2mA
PAD_24_E 9:8 RW 0x1 0x1: 4mA
0x2: 8mA
0x3: 12mA

Slew Rate
PAD_24_SR 10 RW 0x0 0x1: Fast
0x0: Slow (half frequency)

Receive enable
PAD_24_REN 11 RW 0x0 0x1: enable
0x0: disable

Schmitt Trigger
PAD_24_SMT 12 RW 0x0 0x1: enable
0x0: disable

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QuickLogic® EOSTM S3 Sensor Processing Platform Input/Output Multiplexor (IOMUX) User Guide Rev 1.1

Offset Name/Field Bits Type Default Description

PAD_25_CTRL 31:0

Functional selection for IO output. For

PAD_25_FUNC_SEL 1:0 RW 0x0 details, see the Appendix – Table
11.
Control selection for IO output
0x0: A0 registers (as defined below)
PAD_25_CTRL_SEL 4:3 RW 0x0 0x1: Others
0x2: Fabric

Active low output enable

PAD_25_OEN 5 RW 0x1 0x1: driver disabled
0x0: normal operation

Driver state control

0x0: Z
PAD_25_P 7:6 RW 0x0 0x1: pull up
0x064 0x2: pull down
0x3: keeper

Drive Strength
0x0: 2mA
PAD_25_E 9:8 RW 0x1 0x1: 4mA
0x2: 8mA
0x3: 12mA

Slew Rate
PAD_25_SR 10 RW 0x0 0x1: Fast
0x0: Slow (half frequency)

Receive enable
PAD_25_REN 11 RW 0x0 0x1: enable
0x0: disable

Schmitt Trigger
PAD_25_SMT 12 RW 0x0 0x1: enable
0x0: disable

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QuickLogic® EOSTM S3 Sensor Processing Platform Input/Output Multiplexor (IOMUX) User Guide Rev 1.1

Offset Name/Field Bits Type Default Description

PAD_26_CTRL 31:0

Functional selection for IO output. For

PAD_26_FUNC_SEL 1:0 RW 0x0 details, see the Appendix – Table
11.
Control selection for IO output
0x0: A0 registers (as defined below)
PAD_26_CTRL_SEL 4:3 RW 0x0 0x1: Others
0x2: Fabric

Active low output enable

PAD_26_OEN 5 RW 0x1 0x1: driver disabled
0x0: normal operation

Driver state control

0x0: Z
PAD_26_P 7:6 RW 0x0 0x1: pull up
0x068 0x2: pull down
0x3: keeper

Drive Strength
0x0: 2mA
PAD_26_E 9:8 RW 0x1 0x1: 4mA
0x2: 8mA
0x3: 12mA

Slew Rate
PAD_26_SR 10 RW 0x0 0x1: Fast
0x0: Slow (half frequency)

Receive enable
PAD_26_REN 11 RW 0x0 0x1: enable
0x0: disable

Schmitt Trigger
PAD_26_SMT 12 RW 0x0 0x1: enable
0x0: disable

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QuickLogic® EOSTM S3 Sensor Processing Platform Input/Output Multiplexor (IOMUX) User Guide Rev 1.1

Offset Name/Field Bits Type Default Description

PAD_27_CTRL 31:0

Functional selection for IO output. For

PAD_27_FUNC_SEL 1:0 RW 0x0 details, see the Appendix – Table
11.
Control selection for IO output
0x0: A0 registers (as defined below)
PAD_27_CTRL_SEL 4:3 RW 0x0 0x1: Others
0x2: Fabric

Active low output enable

PAD_27_OEN 5 RW 0x1 0x1: driver disabled
0x0: normal operation

Driver state control

0x0: Z
PAD_27_P 7:6 RW 0x0 0x1: pull up
0x06C 0x2: pull down
0x3: keeper

Drive Strength
0x0: 2mA
PAD_27_E 9:8 RW 0x1 0x1: 4mA
0x2: 8mA
0x3: 12mA

Slew Rate
PAD_27_SR 10 RW 0x0 0x1: Fast
0x0: Slow (half frequency)

Receive enable
PAD_27_REN 11 RW 0x0 0x1: enable
0x0: disable

Schmitt Trigger
PAD_27_SMT 12 RW 0x0 0x1: enable
0x0: disable

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QuickLogic® EOSTM S3 Sensor Processing Platform Input/Output Multiplexor (IOMUX) User Guide Rev 1.1

Offset Name/Field Bits Type Default Description

PAD_28_CTRL 31:0

Functional selection for IO output. For

PAD_28_FUNC_SEL 1:0 RW 0x0 details, see the Appendix – Table
11.
Control selection for IO output
0x0: A0 registers (as defined below)
PAD_28_CTRL_SEL 4:3 RW 0x0 0x1: Others
0x2: Fabric

Active low output enable

PAD_28_OEN 5 RW 0x1 0x1: driver disabled
0x0: normal operation

Driver state control

0x0: Z
PAD_28_P 7:6 RW 0x0 0x1: pull up
0x070 0x2: pull down
0x3: keeper

Drive Strength
0x0: 2mA
PAD_28_E 9:8 RW 0x1 0x1: 4mA
0x2: 8mA
0x3: 12mA

Slew Rate
PAD_28_SR 10 RW 0x0 0x1: Fast
0x0: Slow (half frequency)

Receive enable
PAD_28_REN 11 RW 0x0 0x1: enable
0x0: disable

Schmitt Trigger
PAD_28_SMT 12 RW 0x0 0x1: enable
0x0: disable

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QuickLogic® EOSTM S3 Sensor Processing Platform Input/Output Multiplexor (IOMUX) User Guide Rev 1.1

Offset Name/Field Bits Type Default Description

PAD_29_CTRL 31:0

Functional selection for IO output. For

PAD_29_FUNC_SEL 1:0 RW 0x0 details, see the Appendix – Table
11.
Control selection for IO output
0x0: A0 registers (as defined below)
PAD_29_CTRL_SEL 4:3 RW 0x0 0x1: Others
0x2: Fabric

Active low output enable

PAD_29_OEN 5 RW 0x1 0x1: driver disabled
0x0: normal operation

Driver state control

0x0: Z
PAD_29_P 7:6 RW 0x0 0x1: pull up
0x074 0x2: pull down
0x3: keeper

Drive Strength
0x0: 2mA
PAD_29_E 9:8 RW 0x1 0x1: 4mA
0x2: 8mA
0x3: 12mA

Slew Rate
PAD_29_SR 10 RW 0x0 0x1: Fast
0x0: Slow (half frequency)

Receive enable
PAD_29_REN 11 RW 0x0 0x1: enable
0x0: disable

Schmitt Trigger
PAD_29_SMT 12 RW 0x0 0x1: enable
0x0: disable

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QuickLogic® EOSTM S3 Sensor Processing Platform Input/Output Multiplexor (IOMUX) User Guide Rev 1.1

Offset Name/Field Bits Type Default Description

PAD_30_CTRL 31:0

Functional selection for IO output. For

PAD_30_FUNC_SEL 1:0 RW 0x0 details, see the Appendix – Table
11.
Control selection for IO output
0x0: A0 registers (as defined below)
PAD_30_CTRL_SEL 4:3 RW 0x0 0x1: Others
0x2: Fabric

Active low output enable

PAD_30_OEN 5 RW 0x1 0x1: driver disabled
0x0: normal operation

Driver state control

0x0: Z
PAD_30_P 7:6 RW 0x0 0x1: pull up
0x078 0x2: pull down
0x3: keeper

Drive Strength
0x0: 2mA
PAD_30_E 9:8 RW 0x1 0x1: 4mA
0x2: 8mA
0x3: 12mA

Slew Rate
PAD_30_SR 10 RW 0x0 0x1: Fast
0x0: Slow (half frequency)

Receive enable
PAD_30_REN 11 RW 0x0 0x1: enable
0x0: disable

Schmitt Trigger
PAD_30_SMT 12 RW 0x0 0x1: enable
0x0: disable

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Offset Name/Field Bits Type Default Description

PAD_31_CTRL 31:0

Functional selection for IO output. For

PAD_31_FUNC_SEL 1:0 RW 0x0 details, see the Appendix – Table
11.
Control selection for IO output
0x0: A0 registers (as defined below)
PAD_31_CTRL_SEL 4:3 RW 0x0 0x1: Others
0x2: Fabric

Active low output enable

PAD_31_OEN 5 RW 0x1 0x1: driver disabled
0x0: normal operation

Driver state control

0x0: Z
PAD_31_P 7:6 RW 0x0 0x1: pull up
0x07C 0x2: pull down
0x3: keeper

Drive Strength
0x0: 2mA
PAD_31_E 9:8 RW 0x1 0x1: 4mA
0x2: 8mA
0x3: 12mA

Slew Rate
PAD_31_SR 10 RW 0x0 0x1: Fast
0x0: Slow (half frequency)

Receive enable
PAD_31_REN 11 RW 0x0 0x1: enable
0x0: disable

Schmitt Trigger
PAD_31_SMT 12 RW 0x0 0x1: enable
0x0: disable

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Offset Name/Field Bits Type Default Description

PAD_32_CTRL 31:0

Functional selection for IO output. For

PAD_32_FUNC_SEL 1:0 RW 0x0 details, see the Appendix – Table
11.
Control selection for IO output
0x0: A0 registers (as defined below)
PAD_32_CTRL_SEL 4:3 RW 0x0 0x1: Others
0x2: Fabric

Active low output enable

PAD_32_OEN 5 RW 0x1 0x1: driver disabled
0x0: normal operation

Driver state control

0x0: Z
PAD_32_P 7:6 RW 0x0 0x1: pull up
0x080 0x2: pull down
0x3: keeper

Drive Strength
0x0: 2mA
PAD_32_E 9:8 RW 0x1 0x1: 4mA
0x2: 8mA
0x3: 12mA

Slew Rate
PAD_32_SR 10 RW 0x0 0x1: Fast
0x0: Slow (half frequency)

Receive enable
PAD_32_REN 11 RW 0x0 0x1: enable
0x0: disable

Schmitt Trigger
PAD_32_SMT 12 RW 0x0 0x1: enable
0x0: disable

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Offset Name/Field Bits Type Default Description

PAD_33_CTRL 31:0

Functional selection for IO output. For

PAD_33_FUNC_SEL 1:0 RW 0x0 details, see the Appendix – Table
11.
Control selection for IO output
0x0: A0 registers (as defined below)
PAD_33_CTRL_SEL 4:3 RW 0x0 0x1: Others
0x2: Fabric

Active low output enable

PAD_33_OEN 5 RW 0x1 0x1: driver disabled
0x0: normal operation

Driver state control

0x0: Z
PAD_33_P 7:6 RW 0x0 0x1: pull up
0x084 0x2: pull down
0x3: keeper

Drive Strength
0x0: 2mA
PAD_33_E 9:8 RW 0x1 0x1: 4mA
0x2: 8mA
0x3: 12mA

Slew Rate
PAD_33_SR 10 RW 0x0 0x1: Fast
0x0: Slow (half frequency)

Receive enable
PAD_33_REN 11 RW 0x0 0x1: enable
0x0: disable

Schmitt Trigger
PAD_33_SMT 12 RW 0x0 0x1: enable
0x0: disable

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Offset Name/Field Bits Type Default Description

PAD_34_CTRL 31:0

Functional selection for IO output. For

PAD_34_FUNC_SEL 1:0 RW 0x0 details, see the Appendix – Table
11.
Control selection for IO output
0x0: A0 registers (as defined below)
PAD_34_CTRL_SEL 4:3 RW 0x1 0x1: Others
0x2: Fabric

Active low output enable

PAD_34_OEN 5 RW 0x1 0x1: driver disabled
0x0: normal operation

Driver state control

0x0: Z
PAD_34_P 7:6 RW 0x0 0x1: pull up
0x088 0x2: pull down
0x3: keeper

Drive Strength
0x0: 2mA
PAD_34_E 9:8 RW 0x1 0x1: 4mA
0x2: 8mA
0x3: 12mA

Slew Rate
PAD_34_SR 10 RW 0x0 0x1: Fast
0x0: Slow (half frequency)

Receive enable
PAD_34_REN 11 RW 0x0 0x1: enable
0x0: disable

Schmitt Trigger
PAD_34_SMT 12 RW 0x0 0x1: enable
0x0: disable

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Offset Name/Field Bits Type Default Description

PAD_35_CTRL 31:0

Functional selection for IO output. For

PAD_35_FUNC_SEL 1:0 RW 0x0 details, see the Appendix – Table
11.
Control selection for IO output
0x0: A0 registers (as defined below) *
0x1: Others
PAD_35_CTRL_SEL 4:3 RW 0x0 0x2: Fabric
* Exception: when FUNC_SEL=2, the
control is from FFE.

Active low output enable

PAD_35_OEN 5 RW 0x1 0x1: driver disabled
0x0: normal operation

Driver state control

0x0: Z
0x08C PAD_35_P 7:6 RW 0x0 0x1: pull up
0x2: pull down
0x3: keeper

Drive Strength
0x0: 2mA
PAD_35_E 9:8 RW 0x1 0x1: 4mA
0x2: 8mA
0x3: 12mA

Slew Rate
PAD_35_SR 10 RW 0x0 0x1: Fast
0x0: Slow (half frequency)

Receive enable
PAD_35_REN 11 RW 0x0 0x1: enable
0x0: disable

Schmitt Trigger
PAD_35_SMT 12 RW 0x0 0x1: enable
0x0: disable

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Offset Name/Field Bits Type Default Description

PAD_36_CTRL 31:0

Functional selection for IO output. For

PAD_36_FUNC_SEL 1:0 RW 0x0 details, see the Appendix – Table
11.
Control selection for IO output
0x0: A0 registers (as defined below) *
0x1: Others
PAD_36_CTRL_SEL 4:3 RW 0x1 0x2: Fabric
* Exception: when FUNC_SEL=2, the
control is from FFE.

Active low output enable

PAD_36_OEN 5 RW 0x1 0x1: driver disabled
0x0: normal operation

Driver state control

0x0: Z
0x090 PAD_36_P 7:6 RW 0x0 0x1: pull up
0x2: pull down
0x3: keeper

Drive Strength
0x0: 2mA
PAD_36_E 9:8 RW 0x1 0x1: 4mA
0x2: 8mA
0x3: 12mA

Slew Rate
PAD_36_SR 10 RW 0x0 0x1: Fast
0x0: Slow (half frequency)

Receive enable
PAD_36_REN 11 RW 0x0 0x1: enable
0x0: disable

Schmitt Trigger
PAD_36_SMT 12 RW 0x0 0x1: enable
0x0: disable

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Offset Name/Field Bits Type Default Description

PAD_37_CTRL 31:0

Functional selection for IO output. For

PAD_37_FUNC_SEL 1:0 RW 0x0 details, see the Appendix – Table
11.
Control selection for IO output
0x0: A0 registers (as defined below) *
0x1: Others
PAD_37_CTRL_SEL 4:3 RW 0x0 0x2: Fabric
* Exception: when FUNC_SEL=2, the
control is from FFE.

Active low output enable

PAD_37_OEN 5 RW 0x1 0x1: driver disabled
0x0: normal operation

Driver state control

0x0: Z
0x094 PAD_37_P 7:6 RW 0x0 0x1: pull up
0x2: pull down
0x3: keeper

Drive Strength
0x0: 2mA
PAD_37_E 9:8 RW 0x1 0x1: 4mA
0x2: 8mA
0x3: 12mA

Slew Rate
PAD_37_SR 10 RW 0x0 0x1: Fast
0x0: Slow (half frequency)

Receive enable
PAD_37_REN 11 RW 0x0 0x1: enable
0x0: disable

Schmitt Trigger
PAD_37_SMT 12 RW 0x0 0x1: enable
0x0: disable

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Offset Name/Field Bits Type Default Description

PAD_38_CTRL 31:0

Functional selection for IO output. For

PAD_38_FUNC_SEL 1:0 RW 0x0 details, see the Appendix – Table
11.
Control selection for IO output
0x0: A0 registers (as defined below) *
0x1: Others
PAD_38_CTRL_SEL 4:3 RW 0x1 0x2: Fabric
* Exception: when FUNC_SEL=2, the
control is from FFE.

Active low output enable

PAD_38_OEN 5 RW 0x1 0x1: driver disabled
0x0: normal operation

Driver state control

0x0: Z
0x098 PAD_38_P 7:6 RW 0x0 0x1: pull up
0x2: pull down
0x3: keeper

Drive Strength
0x0: 2mA
PAD_38_E 9:8 RW 0x1 0x1: 4mA
0x2: 8mA
0x3: 12mA

Slew Rate
PAD_38_SR 10 RW 0x0 0x1: Fast
0x0: Slow (half frequency)

Receive enable
PAD_38_REN 11 RW 0x0 0x1: enable
0x0: disable

Schmitt Trigger
PAD_38_SMT 12 RW 0x0 0x1: enable
0x0: disable

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Offset Name/Field Bits Type Default Description

PAD_39_CTRL 31:0

Functional selection for IO output. For

PAD_39_FUNC_SEL 1:0 RW 0x0 details, see the Appendix – Table
11.
Control selection for IO output
0x0: A0 registers (as defined below) *
0x1: Others
PAD_39_CTRL_SEL 4:3 RW 0x1 0x2: Fabric
* Exception: when FUNC_SEL=2, the
control is from FFE.

Active low output enable

PAD_39_OEN 5 RW 0x1 0x1: driver disabled
0x0: normal operation

Driver state control

0x0: Z
0x09C PAD_39_P 7:6 RW 0x0 0x1: pull up
0x2: pull down
0x3: keeper

Drive Strength
0x0: 2mA
PAD_39_E 9:8 RW 0x1 0x1: 4mA
0x2: 8mA
0x3: 12mA

Slew Rate
PAD_39_SR 10 RW 0x0 0x1: Fast
0x0: Slow (half frequency)

Receive enable
PAD_39_REN 11 RW 0x0 0x1: enable
0x0: disable

Schmitt Trigger
PAD_39_SMT 12 RW 0x0 0x1: enable
0x0: disable

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Offset Name/Field Bits Type Default Description

PAD_40_CTRL 31:0

Functional selection for IO output. For

PAD_40_FUNC_SEL 1:0 RW 0x0 details, see the Appendix – Table
11.
Control selection for IO output
0x0: A0 registers (as defined below) *
0x1: Others
PAD_40_CTRL_SEL 4:3 RW 0x0 0x2: Fabric
* Exception: when FUNC_SEL=2, the
control is from FFE.

Active low output enable

PAD_40_OEN 5 RW 0x1 0x1: driver disabled
0x0: normal operation

Driver state control

0x0: Z
0x0A0 PAD_40_P 7:6 RW 0x0 0x1: pull up
0x2: pull down
0x3: keeper

Drive Strength
0x0: 2mA
PAD_40_E 9:8 RW 0x1 0x1: 4mA
0x2: 8mA
0x3: 12mA

Slew Rate
PAD_40_SR 10 RW 0x0 0x1: Fast
0x0: Slow (half frequency)

Receive enable
PAD_40_REN 11 RW 0x0 0x1: enable
0x0: disable

Schmitt Trigger
PAD_40_SMT 12 RW 0x0 0x1: enable
0x0: disable

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Offset Name/Field Bits Type Default Description

PAD_41_CTRL 31:0

Functional selection for IO output. For

PAD_41_FUNC_SEL 1:0 RW 0x0 details, see the Appendix – Table
11.
Control selection for IO output
0x0: A0 registers (as defined below) *
0x1: Others
PAD_41_CTRL_SEL 4:3 RW 0x0 0x2: Fabric
* Exception: when FUNC_SEL=2, the
control is from FFE.

Active low output enable

PAD_41_OEN 5 RW 0x1 0x1: driver disabled
0x0: normal operation

Driver state control

0x0: Z
0x0A4 PAD_41_P 7:6 RW 0x0 0x1: pull up
0x2: pull down
0x3: keeper

Drive Strength
0x0: 2mA
PAD_41_E 9:8 RW 0x1 0x1: 4mA
0x2: 8mA
0x3: 12mA

Slew Rate
PAD_41_SR 10 RW 0x0 0x1: Fast
0x0: Slow (half frequency)

Receive enable
PAD_41_REN 11 RW 0x0 0x1: enable
0x0: disable

Schmitt Trigger
PAD_41_SMT 12 RW 0x0 0x1: enable
0x0: disable

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Offset Name/Field Bits Type Default Description

PAD_42_CTRL 31:0

Functional selection for IO output. For

PAD_42_FUNC_SEL 1:0 RW 0x0 details, see the Appendix – Table
11.
Control selection for IO output
0x0: A0 registers (as defined below) *
0x1: Others
PAD_42_CTRL_SEL 4:3 RW 0x0 0x2: Fabric
* Exception: when FUNC_SEL=2, the
control is from FFE.

Active low output enable

PAD_42_OEN 5 RW 0x1 0x1: driver disabled
0x0: normal operation

Driver state control

0x0: Z
0x0A8 PAD_42_P 7:6 RW 0x0 0x1: pull up
0x2: pull down
0x3: keeper

Drive Strength
0x0: 2mA
PAD_42_E 9:8 RW 0x1 0x1: 4mA
0x2: 8mA
0x3: 12mA

Slew Rate
PAD_42_SR 10 RW 0x0 0x1: Fast
0x0: Slow (half frequency)

Receive enable
PAD_42_REN 11 RW 0x0 0x1: enable
0x0: disable

Schmitt Trigger
PAD_42_SMT 12 RW 0x0 0x1: enable
0x0: disable

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Offset Name/Field Bits Type Default Description

PAD_43_CTRL 31:0

Functional selection for IO output. For

PAD_43_FUNC_SEL 1:0 RW 0x0 details, see the Appendix – Table
11.
Control selection for IO output
0x0: A0 registers (as defined below) *
0x1: Others
PAD_43_CTRL_SEL 4:3 RW 0x0 0x2: Fabric
* Exception: when FUNC_SEL=2, the
control is from FFE.

Active low output enable

PAD_43_OEN 5 RW 0x1 0x1: driver disabled
0x0: normal operation

Driver state control

0x0: Z
0x0AC PAD_43_P 7:6 RW 0x0 0x1: pull up
0x2: pull down
0x3: keeper

Drive Strength
0x0: 2mA
PAD_43_E 9:8 RW 0x1 0x1: 4mA
0x2: 8mA
0x3: 12mA

Slew Rate
PAD_43_SR 10 RW 0x0 0x1: Fast
0x0: Slow (half frequency)

Receive enable
PAD_43_REN 11 RW 0x0 0x1: enable
0x0: disable

Schmitt Trigger
PAD_43_SMT 12 RW 0x0 0x1: enable
0x0: disable

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Offset Name/Field Bits Type Default Description

PAD_44_CTRL 31:0

Functional selection for IO output. For

PAD_44_FUNC_SEL 1:0 RW 0x0 details, see the Appendix – Table
11.
Control selection for IO output
0x0: A0 registers (as defined below) *
0x1: Others
PAD_44_CTRL_SEL 4:3 RW 0x1 0x2: Fabric
* Exception: when FUNC_SEL=2, the
control is from FFE.

Active low output enable

PAD_44_OEN 5 RW 0x1 0x1: driver disabled
0x0: normal operation

Driver state control

0x0: Z
0x0B0 PAD_44_P 7:6 RW 0x0 0x1: pull up
0x2: pull down
0x3: keeper

Drive Strength
0x0: 2mA
PAD_44_E 9:8 RW 0x1 0x1: 4mA
0x2: 8mA
0x3: 12mA

Slew Rate
PAD_44_SR 10 RW 0x0 0x1: Fast
0x0: Slow (half frequency)

Receive enable
PAD_44_REN 11 RW 0x0 0x1: enable
0x0: disable

Schmitt Trigger
PAD_44_SMT 12 RW 0x0 0x1: enable
0x0: disable

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Offset Name/Field Bits Type Default Description

PAD_45_CTRL 31:0

Functional selection for IO output. For

PAD_45_FUNC_SEL 1:0 RW 0x0 details, see the Appendix – Table
11.
Control selection for IO output
0x0: A0 registers (as defined below) *
0x1: Others
PAD_45_CTRL_SEL 4:3 RW 0x1 0x2: Fabric
* Exception: when FUNC_SEL=2, the
control is from FFE.

Active low output enable

PAD_45_OEN 5 RW 0x1 0x1: driver disabled
0x0: normal operation

Driver state control

0x0: Z
0x0B4 PAD_45_P 7:6 RW 0x0 0x1: pull up
0x2: pull down
0x3: keeper

Drive Strength
0x0: 2mA
PAD_45_E 9:8 RW 0x1 0x1: 4mA
0x2: 8mA
0x3: 12mA

Slew Rate
PAD_45_SR 10 RW 0x0 0x1: Fast
0x0: Slow (half frequency)

Receive enable
PAD_45_REN 11 RW 0x0 0x1: enable
0x0: disable

Schmitt Trigger
PAD_45_SMT 12 RW 0x0 0x1: enable
0x0: disable

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Offset Name/Field Bits Type Default Description

0x100 SDA0_SEL 31:0

SDA0_SEL 0 RW 0x0 Sel

0: 1
1: pad #1

0x104 SDA1_SEL 31:0

SDA1_SEL 1:0 RW 0x0 Sel

0: 1
1: pad #15
2: pad #32
3: pad #44

0x108 SDA2_SEL 31:0

SDA2_SEL 0 RW 0x0 Sel

0: 1
1: pad #41

0x10C SCL0_SEL 31:0

SCL0_SEL 0 RW 0x0 Sel

0: 1
1: pad #0

0x110 SCL1_SEL 31:0

SCL1_SEL 1:0 RW 0x0 Sel

0: 1
1: pad #14
2: pad #33
3: pad #45

0x114 SCL2_SEL 31:0

SCL2_SEL 0 RW 0x0 Sel

0: 1
1: pad #40

0x118 SPIs_CLK_SEL 31:0

SPIs_CLK_SEL 0 RW 0x0 Sel

0: pad #16
1: 0

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Offset Name/Field Bits Type Default Description

0x11C SPIs_SSn_SEL 31:0

SPIs_SSn_SEL 0 RW 0x0 Sel

0: pad #20
1: 0

0x120 SPIs_MOSI_SEL 31:0

SPIs_MOSI_SEL 0 RW 0x0 Sel

0: pad #19
1: 0

0x124 SPIm_MISO_SEL 31:0

SPIm_MISO_SEL 0 RW 0x0 Sel

0: pad #36
1: 0

0x128 PDM_DATA_SEL 31:0

PDM_DATA_SEL 1:0 RW 0x0 Sel

0: 0
1: pad #10
2: pad #28

0x12C I2S_DATA_SEL 31:0

I2S_DATA_SEL 1:0 RW 0x0 Sel

0: 0
1: pad #10
2: pad #28

0x130 FCLK_SEL 31:0

FCLK_SEL 2:0 RW 0x0 Sel Value

7 1
6 0
IO selection
Sel Pad#
4 27
3 26
2 10
1 7
0 2

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Offset Name/Field Bits Type Default Description

0x134 UART_RXD_SEL 31:0

UART_RXD_SEL 2:0 RW 0x0 Sel

0: 0
1: pad #14
2: pad #16
3: pad #25
4: pad #45
0x138 IrDA_Sirin_SEL 31:0

IrDA_Sirin_SEL 2:0 RW 0x0 Sel

0: 0
1: pad #6
2: pad #15
3: pad #21
4: pad #24
5: pad #28
6: pad #40
7: pad #44

0x13C S_INTR_0_SEL 31:0

S_INTR_0_SEL 0 RW 0x0 Sel

0: 0
1: pad #3

0x140 S_INTR_1_SEL 31:0

S_INTR_1_SEL 2:0 RW 0x0 Sel

0: 0
1: pad #2
2: pad #6
3: pad #18
4: pad #24
5: pad #35
6: pad #36

0x144 S_INTR_2_SEL 31:0

S_INTR_2_SEL 2:0 RW 0x0 Sel

0: 0
1: pad #4
2: pad #8
3: pad #21
4: pad #25
5: pad #37
6: pad #38

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Offset Name/Field Bits Type Default Description

0x148 S_INTR_3_SEL 31:0

S_INTR_3_SEL 2:0 RW 0x0 Sel

0: 0
1: pad #5
2: pad #9
3: pad #22
4: pad #28
5: pad #39
6: pad #40

0x14C S_INTR_4_SEL 31:0

S_INTR_4_SEL 2:0 RW 0x0 Sel

0: 0
1: pad #7
2: pad #10
3: pad #26
4: pad #29
5: pad #44

0x150 S_INTR_5_SEL 31:0

S_INTR_5_SEL 2:0 RW 0x0 Sel

0: 0
1: pad #11
2: pad #14
3: pad #27
4: pad #30
5: pad #45

0x154 S_INTR_6_SEL 31:0

S_INTR_6_SEL 2:0 RW 0x0 Sel

0: 0
1: pad #12
2: pad #15
3: pad #31
4: pad #32
5: pad #41

0x158 S_INTR_7_SEL 31:0

S_INTR_7_SEL 2:0 RW 0x0 Sel

0: 0
1: pad #13
2: pad #23
3: pad #33

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Offset Name/Field Bits Type Default Description

4: pad #34
5: pad #42

0x15C NUARTCTS_SEL 31:0

NUARTCTS_SEL 1:0 RW 0x0 Sel

0: 1
1: pad #17
2: pad #22

0x160 IO_REG_SEL 31:0

IO_REG_SEL 7:0 RW 0x0 Selects which IO input will be

registered
Bit Sel Pad#
0 0 6
0 1 24
1 0 9
1 1 26
2 0 11
2 1 28
3 0 14
3 1 30
4 0 18
4 1 31
5 0 21
5 1 36
6 0 22
6 1 38
7 0 23
7 1 45

0x170 SW_CLK_SEL 31:0

SW_CLK_SEL 0 RW 0x0 Sel

0: pad #14 / #45 (pad selection will
depend on strap #8)
1: 0

0x174 SW_IO_SEL 31:0

SW_IO_SEL 0 RW 0x0 Sel

0: pad #15 / #44 (pad selection will
depend on strap #8)
1: 0

0x180 FBIO_SEL_1 31:0

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Offset Name/Field Bits Type Default Description

FBIO_SEL_1 31:0 RW 0x0 Sel
0: 0
1: pad

0x184 FBIO_SEL_2 31:0

FBIO_SEL_2 13:0 RW 0x0 Sel

0: 0
1: pad

0x190 SPI_SENSOR_MISO_SEL 31:0

SPI_SENSOR_MISO_SEL 1:0 RW 0x0 Sel

0: 0
1: pad #8
2: pad #29

0x194 SPI_SENSOR_MOSI_SEL 31:0

SPI_SENSOR_MOSI_SEL 1:0 RW 0x0 Sel

0: 0
1: pad #6
2: pad #28

0x1A0 I2S_WD_CLKIN_SEL 31:0

I2S_WD_CLKIN_SEL 0 RW 0x0 Sel

0: 0
1: pad #23

0x1A4 I2S_CLKIN_SEL 31:0

I2S_CLKIN_SEL 0 RW 0x0 Sel

0: 0
1: pad #31

0x1A8 PDM_STAT_IN_SEL 31:0

PDM_STAT_IN_SEL 1:0 RW 0x0 Sel

0: 0
1: pad #9
2: pad #30

0x1AC PDM_CLKIN_SEL 31:0

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QuickLogic® EOSTM S3 Sensor Processing Platform Input/Output Multiplexor (IOMUX) User Guide Rev 1.1

Offset Name/Field Bits Type Default Description

PDM_CLKIN_SEL 0 RW 0x0 Sel
0: 0
1: pad #38

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QuickLogic® EOSTM S3 Sensor Processing Platform Input/Output Multiplexor (IOMUX) User Guide Rev 1.1

Table 13 shows the mode configuration for each pin.

Table 13: Mode Configurationa,b,c

Pin No./ Smart- Wearable Debugger1 Debugger2

Mode phone
Bootstrap IO20=1 IO20=0 IO8=0 IO8=1 Audio I2C SPI_Sensor Infrared UART Dbg_Mon GPIO Sensor
Interrupt
IO19=1 IO19=1

0 SCL_0 SCL_0 SCL_0

1 SDA_0 SDA_0 SDA_0

2 spi_sensor_ debug_ Sensor_

ssn2 mon0 Interrupt1
3 Sensor_ Sensor_ Sensor_
Interrupt0 Interrupt0 Interrupt0
4 SDA_1_DP spi_sensor_ debug_ Sensor_
U ssn3 mon1 Interrupt2
5 SDA_0_DP spi_sensor_ debug_ Sensor_
U ssn4 mon2 Interrupt3
6 spi_sensor_ IrDA_Sirin debug_ gpio0 Sensor_
mosi mon3 Interrupt1
7 SWV spi_sensor_ debug_ Sensor_
ssn5 mon4 Interrupt4
8 i2s_cko / spi_sensor_ IrDA_Sirout Sensor_
pdm_cko miso Interrupt2
9 i2s_wd_cko spi_sensor_ gpio1 Sensor_
/ pdm_stat_i ssn1 Interrupt3
10 SWV i2s_din / spi_sensor_ Sensor_
pdm_din clk Interrupt4
11 spi_sensor_ debug_ gpio2 Sensor_
ssn6 mon5 Interrupt5
12 spi_sensor_ IrDA_Sirout debug_ Sensor_
ssn7 mon6 Interrupt6
13 SWV spi_sensor_ IrDA_Sirin debug_ Sensor_
ssn8 mon7 Interrupt7
14 SW_CLK SCL_1 IrDA_Sirout UART_rxd gpio3 Sensor_
Interrupt5
15 SW_IO SDA_1 IrDA_Sirin UART_txd Sensor_
Interrupt6

16 SPIs_CLK UART_rxd

17 SPIs_MISO nUARTCTS

18 SWV debug_ gpio4 Sensor_

mon0 Interrupt1
19 SPIs_MOSI nUARTRTS

20 SPIs_SSn UART_txd

21 IrDA_Sirin nUARTRTS debug_ gpio5 Sensor_I

mon1 nterrupt2
22 IrDA_Sirout nUARTCTS debug_ gpio6 Sensor_
mon2 Interrupt3
23 SPIm_SSn2 SWV ap_i2s_wd_ gpio7 Sensor_
clk_in Interrupt7
24 ap_i2s_dout IrDA_Sirin UART_txd gpio0 Sensor_
Interrupt1
25 SPIm_SSn3 SWV IrDA_Sirout UART_rxd Sensor_
Interrupt2
26 spi_sensor_ debug_ gpio1 Sensor_
ssn4 mon3 Interrupt4
27 SPIm_SSn2 spi_sensor_ debug_ Sensor_
ssn5 mon4 Interrupt5
28 i2s_din / spi_sensor_ IrDA_Sirin debug_ gpio2 Sensor_
pdm_din mosi mon5 Interrupt3
29 i2s_cko / spi_sensor_ IrDA_Sirout Sensor_
pdm_cko miso Interrupt4
30 i2s_wd_cko spi_sensor_ gpio3 Sensor_
/ pdm_stat_i ssn1 Interrupt5

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QuickLogic® EOSTM S3 Sensor Processing Platform Input/Output Multiplexor (IOMUX) User Guide Rev 1.1

Pin No./ Smart- Wearable Debugger1 Debugger2

Mode phone
Bootstrap IO20=1 IO20=0 IO8=0 IO8=1 Audio I2C SPI_Sensor Infrared UART Dbg_Mon GPIO Sensor
Interrupt
IO19=1 IO19=1

31 ap_i2s_ spi_sensor_ gpio4 Sensor_

clk_in clk Interrupt6
32 SDA_1 spi_sensor_ debug_ Sensor_
ssn5 mon6 Interrupt6
33 SCL_1 spi_sensor_ debug_ Sensor_
ssn6 mon7 Interrupt7
34 SPIm_CLK ap_pdm_ debug_ Sensor_
stat_o mon0 Interrupt7
35 SPIm_SSn3 spi_sensor_ debug_ Sensor_
ssn7 mon1 Interrupt1
36 SPIm_ SWV spi_sensor_ gpio5 Sensor_
MISO ssn2 Interrupt1
37 SDA_2_ spi_sensor_ debug_ Sensor_
DPU ssn8 mon2 Interrupt2
38 SPIm_ ap_pdm_ debug_ gpio6 Sensor_
MOSI cko_in mon3 Interrupt2
39 SPIm_SSn1 ap_pdm_io debug_ Sensor_
mon4 Interrupt3
40 SCL_2 IrDA_Sirin debug_ Sensor_
mon5 Interrupt3
41 SDA_2 IrDA_Sirout debug_ Sensor_
mon6 Interrupt6
42 SWV SDA_1_ debug_ Sensor_
DPU mon7 Interrupt7
43 AP AP Interrupt
Interrupt
44 SW_IO SDA_1 IrDA_Sirin UART_txd Sensor_
Interrupt4
45 SW_CLK SCL_1 IrDA_Sirout UART_rxd gpio7 Sensor_
Interrupt5

a. Battery monitoring pin is Pad 2.

b. FCLK pin is Pad 6 when bootstrap 8 =1 and bootstrap 9 = 1.
c. Fabric IO is assigned to each pad based on the bootstrap number (e.g., Fabric IO_0 is Pad 0, Fabric IO_1 is Pad 1, Fabric IO_2 is Pad 2, etc.)

Contact Information
Phone: (408) 990-4000 (US)
+(44) 1932-21-3160 (Europe)
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E-mail: [email protected]
Sales: [email protected]
[email protected]
[email protected]
[email protected]
[email protected]
Support: www.quicklogic.com/support
Internet: www.quicklogic.com

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QuickLogic® EOSTM S3 Sensor Processing Platform Input/Output Multiplexor (IOMUX) User Guide Rev 1.1

Revision History
Revision Date Comments
1.0 August 2016 st
1 release
1.1 April 2020 Add register 0x134

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