Table of Contents

HLS Hero Workshop About this Workbook

Pre-Lab: Workshop Pre-requisites
Page 3
Page 4
Lab 1: Vitis HLS Flow Page 7
Lab 2: Vitis HLS Interfacing Page 48
Lab 3: Vitis HLS Optimization Page 63

Course Workbook Lab 4: Vitis HLS Arbitrary Precision Math

Lab 5: Vitis HLS Vitis Libraries
Page 79
Page 89

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About this Workbook

The contents of this workbook are created by Adiuvo Engineering & Training, Ltd.
Pre-Lab
If you have any questions about the contents, or need assistance, please contact Adam
Taylor at [email protected].
HLS Hero

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 Pre-Lab Pre-Lab
Required Hardware Downloads and Installations
Step 1 – Download and install the following at least 1 day prior to the workshop. This may take a
significant amount of time and drive space.

None Required Watch the video available here to show how to configure the installation

Vitis 2021.2 Download

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What is HLS
High Level Synthesis (HLS) enables generation of
Lab 1 RTL modules from higher level language such as C,
C++, OpenCL
Vitis HLS Flow
Of course, SW engineers still consider these low-
level languages.

HLS offers several benefits for the development of

Signal / Data / Image processing algorithms

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HLS Benefits Seconds / Minutes Iteration
Creating HLS Solutions
Software written for CPUs and software written for FPGAs is fundamentally
different
Developing in Higher Level language C Design
enables a faster iteration time.
• Development Time decreased as 1. Not all C constructs can be synthesised
untimed language – No RTL / Hours / Days Iteration 2. Learn about synthesizable C/C++ coding styles.
Behavioral level 3. Need to focus on correct micro architecture
1. Understand the producers and consumers
• Increased level of abstraction – 2. Decompose the algorithm into small section which interconnect
accelerates development RTL RTL
3. Understand throughput required for each element to achieve overall performance
goals
• Verification time is reduced as
untimed Simulation Verified RTL Verified RTL 4. Learn how to interpret the design reports

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HLS Flow Untimed to Timed

Create Solution, Create the C Module and Test Bench – Leverage Libraries where possible
Simulate & Debug Verify algorithm performance in SW
Scheduling
• Determines which operations occur
Synthesize Convert C Module to RTL during each clock cycle
Binding
• Determines which hardware resource
Analyse & Optimize Interfaces and Performance of synthesized implementation implements each scheduled operation
Optimize
Control logic extraction
• Extracts the control logic to create a
Co Simulation Simulation of the RTL module against the C Test Bench finite state machine (FSM) that
sequences the operations in the RTL
design

Package the IP Package for use in Vitis (XO) or Vivado (Xact IP)

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 Lab 1
Lab 1: Vitis HLS Flow
Clock Definition Step 1 – Open Vitis HLS 2021.2 and create a new project

Clock frequency & selected device

used to determine timing of operations
– Scheduling Phase

Uncertainty leaves time for final

component placement and net routing

If left blank 27% is used

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Lab 1 Lab 1
Lab 1: Vitis HLS Flow Lab 1: Vitis HLS Flow
Step 1 – Enter a project name and select a location and click next Step 1 – I used the name VHlab1

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 Lab 1 Lab 1
Lab 1: Vitis HLS Flow Lab 1: Vitis HLS Flow
Step 1 – Click Next Step 1 – Click Next

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Lab 1 Lab 1
Lab 1: Vitis HLS Flow Lab 1: Vitis HLS Flow
Step 1 – Leave all unchanged except for part selection, click to select Step 1 – Select board and select the SP701 Spartan 7 Board, Click OK

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 Lab 1 Lab 1
Lab 1: Vitis HLS Flow Lab 1: Vitis HLS Flow
Step 1 – Click Finish to create the project Step 1 – This will open the project ready for us to create the application

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Lab 1 Lab 1
Lab 1: Vitis HLS Flow Lab 1: Vitis HLS Flow
Step 1 – Right Click on Source and Select new Source File Step 1 – Enter the name of the file as lab1.cpp, click save

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 Lab 1 Lab 1
Lab 1: Vitis HLS Flow Lab 1: Vitis HLS Flow
Step 1 – Enter the code as below – or Copy from the files on the GitHub. Save the file. Step 1 – Right Click on Source and Select new Source File

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Lab 1 Lab 1
Lab 1: Vitis HLS Flow Lab 1: Vitis HLS Flow
Step 1 – Enter the name of the file as lab1.h click save Step 1 – Enter the code as below – or Copy from the files on the GitHub. Save the file.

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 Lab 1 Lab 1
Lab 1: Vitis HLS Flow Lab 1: Vitis HLS Flow
Step 1 – Right Click on Test Bench and Select new Test Bench File. Step 1 – Enter the name of the file as tb_lab1.cpp click save

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Lab 1 Lab 1
Lab 1: Vitis HLS Flow Lab 1: Vitis HLS Flow
Step 1 – Enter the code as below – or Copy from the files on the GitHub. Save the file. Step 1 – From the Run menus select C Simulation

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 Lab 1 Lab 1
Lab 1: Vitis HLS Flow Lab 1: Vitis HLS Flow
Step 1 – On the dialog box select the launch debugger option, click OK Step 1 – This will open the debugger view, with the program paused for execution – we can run,
pause, single step using the menu, along with insert breakpoints

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Lab 1 Lab 1
Lab 1: Vitis HLS Flow Lab 1: Vitis HLS Flow
Step 1 – Single Step a few of the instructions, hold the pointer over a variable and notice the contents Step 1 – Double click in the margin of line 29 to insert a breakpoint – this will be shown by a blue
pop up for inspection circle.

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 Lab 1 Lab 1
Lab 1: Vitis HLS Flow Lab 1: Vitis HLS Flow
Step 1 – Click Run and you will see the breakpoint be hit, double click again in the margin to remove Step 1 – The application should run through, outputting pass or fail in the console and then terminate
the breakpoint and hit run. its run.

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Lab 1 Lab 1
Lab 1: Vitis HLS Flow Lab 1: Vitis HLS Flow
Step 1 – Exit the debug display by clicking exit debug Step 1 – From the setting menu select Project Settings

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 Lab 1 Lab 1
Lab 1: Vitis HLS Flow Lab 1: Vitis HLS Flow
Step 1 – Select Browse to select the top function Step 1 – Select lab1 (or the name of your function if you named it differently)

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Lab 1 Lab 1
Lab 1: Vitis HLS Flow Lab 1: Vitis HLS Flow
Step 1 – Click OK Step 1 – Click on run and select C Synthesis

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 Lab 1 Lab 1
Lab 1: Vitis HLS Flow Lab 1: Vitis HLS Flow
Step 1 – Leave all options unchanged and select OK Step 1 – Once synthesis is complete you will see the report open notice the resources and interfaces

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Lab 1 Lab 1
Lab 1: Vitis HLS Flow Lab 1: Vitis HLS Flow
Step 1 – Scroll down the report you will see the Top level Controls and Interface Info Step 1 – From the Schedule menu select Schedule View

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 Lab 1 Lab 1
Lab 1: Vitis HLS Flow Lab 1: Vitis HLS Flow
Step 1 – Examine the schedule view Step 1 – From the run menu select Co-Simulation

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Lab 1 Lab 1
Lab 1: Vitis HLS Flow Lab 1: Vitis HLS Flow
Step 1 – Leave the options unchanged and click OK Step 1 – Observe the report which shows the completion of the Co Simulation and pass / fail.

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 Lab 1 Summary
Lab 1 Summary
The concludes lab 1, throughout this lab we have demonstrated

1. How to create a project in Vitis HLS

2. How to create source and test benches

Lab 2
3. How to run C simulation
Vitis HLS Interfacing
4. How to set up the project for synthesis

5. How to synthesize the design

6. How to run Co-Simulaiton

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Interfacing Vivado Interfacing

Interfacing depends on flow
Instantiate appropriate interface to
Vitis - XO integrate with design
• AXI – Data Accessed via Memory Map
• AXIS – Data Accessed via Stream Do we want to start and stop block,
• AXI Lite – Register Access synchronize or be data driven.

Vivado – IP XACT Are we controlling the block from SW

• Block Level – Controls Flow / Status
• Protocol Level – Controls
What about data interfaces.

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 Lab 2 Lab 2
Lab 2: Vitis HLS Interfacing Lab 2: Vitis HLS Interfacing
Step 1 – Create a new project called VHLab2, click OK. Step 1 – Create a new source file called lab2.cpp and enter the code below or copy from the GitHub.

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Lab 2 Lab 2
Lab 2: Vitis HLS Interfacing Lab 2: Vitis HLS Interfacing
Step 1 – Create a new source file called lab2.h and enter the code below or copy from the GitHub. Step 1 – Create a new source file called tb_lab2.cpp and enter the code below or copy from the
GitHub.

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 Lab 2 Lab 2
Lab 2: Vitis HLS Interfacing Lab 2: Vitis HLS Interfacing
Step 1 – Run a C Simulation in the debugger, notice how this time the application is batch based Step 1 – Close the C Simulation and open the Lab2.cpp file, select the directives' view. Right click on
the lb2_label0 and select Insert Directive.

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Lab 2 Lab 2
Lab 2: Vitis HLS Interfacing Lab 2: Vitis HLS Interfacing
Step 1 – Insert the directive LOOP_TRIPCOUNT this informs the tool how many times the loop will Step 1 – Run the Synthesis you will notice the Trip Count is now recorded under the lab2 label0
execute in the maximum case.

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 Lab 2 Lab 2
Lab 2: Vitis HLS Interfacing Lab 2: Vitis HLS Interfacing
Step 1 – Examine the HW Interfaces and notice the RAM Interfaces are AP_MEMORY and Register Step 1 – In the synthesis view add in a new directive for the source code for the port loop. Select
Interfaces. INTERFACE directive and for the mode select S_AXILITE

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Lab 2 Lab 2
Lab 2: Vitis HLS Interfacing Lab 2: Vitis HLS Interfacing
Step 1 – In the synthesis view add in a new directive for the source code for the function. Select Step 1 – The Directives should appear as shown in the directives tab – Rerun synthesis
INTERFACE directive and for the mode select S_AXILITE

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 Lab 2 Lab 2 Summary
Lab 2: Vitis HLS Interfacing Lab 2 Summary
Step 1 – Examine the HW Interfaces in the report and notice control of the block and loop register are The concludes lab 2, throughout this lab we have demonstrated
now AXI registers

1. How to inform the synthesis tool about number of loop iterations

2. How to control register interfaces to use AXI Interfaces

3. How to control the IP Block control signals be Implemented as AXI

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Lab 3
Lab 3: Vitis HLS Optimization
Step 1 – Create a new project called VHlab3.cpp

Lab 3
Vitis HLS Optimization

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 Lab 3 Lab 3
Lab 3: Vitis HLS Optimization Lab 3: Vitis HLS Optimization
Step 1 – Create a new source file called lab3.cpp and enter the code below or copy from the GitHub. Step 1 – Create a new source file called lab3.h and enter the code below or copy from the GitHub.

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Lab 3 Lab 3
Lab 3: Vitis HLS Optimization Lab 3: Vitis HLS Optimization
Step 1 – Create a new source file called tb_lab3.cpp and enter the code below or copy from the Step 1 – Right Click on Test Bench File and select add Test Bench File
GitHub.

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 Lab 3 Lab 3
Lab 3: Vitis HLS Optimization Lab 3: Vitis HLS Optimization
Step 1 – Add in the input.dat file provided on the GitHub Step 1 – Run the C Simulation and ensure the result is as shown below.

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Lab 3 Lab 3
Lab 3: Vitis HLS Optimization Lab 3: Vitis HLS Optimization
Step 1 – Select the top function of Sensor_Filter to allow synthesis – perform synthesis. Step 1 – Observe the synthesis interval and resources reported in the synthesis report.

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 Lab 3 Lab 3
Lab 3: Vitis HLS Optimization Lab 3: Vitis HLS Optimization
Step 1 – Open the Function Call Graph for the Synthesis. Step 1 – Observe the information presented, change the heat map.

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Lab 3 Lab 3
Lab 3: Vitis HLS Optimization Lab 3: Vitis HLS Optimization
Step 1 – In the directives view for the source code add in a pragma to unroll the loop labelled accum. Step 1 – In the directives view for the source code add in a pragma to partition the array Input .

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 Lab 3 Lab 3 Summary
Lab 3: Vitis HLS Optimization Lab 3 Summary
Step 1 – Rerun synthesis and observe the interval and resources again. The concludes lab 3, throughout this lab we have demonstrated

1. How to add optimization pragmas

2. How optimization pragma will change the resource and latency performance

3. How to visualize the optimization impacts

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Lab 4
Lab 4: Vitis HLS Arbitrary Precision Math
Step 1 – Create a new project called vhlab4.

Lab 4
Vitis HLS Arbitrary Precision Math

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 Lab 4 Lab 4
Lab 4: Vitis HLS Arbitrary Precision Math Lab 4: Vitis HLS Arbitrary Precision Math
Step 1 – Create a new source file called lab4.cpp and enter the code below or copy from the GitHub. Step 1 – Create a new source file called lab4.h and enter the code below or copy from the GitHub.

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Lab 4 Lab 4
Lab 4: Vitis HLS Arbitrary Precision Math Lab 4: Vitis HLS Arbitrary Precision Math
Step 1 – Create a new source file called tb_lab4.cpp and enter the code below or copy from the Step 1 – Run the Synthesis observe the interval and the resources required.
GitHub.

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 Lab 4 Lab 4
Lab 4: Vitis HLS Arbitrary Precision Math Lab 4: Vitis HLS Arbitrary Precision Math
Step 1 – Examine the analysis view to see the operations involved. Step 1 – In the file lab4.h comment out the line define float_type.

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Lab 4 Lab 4 Summary

Lab 4: Vitis HLS Arbitrary Precision Math Lab 4 Summary
Step 1 – Rerun synthesis and observe the interval and resources. The concludes lab 4, throughout this lab we have demonstrated

1. How to switch between floating point and arbitrary precision in your application

2. The benefit of using arbitrary precision numbers

3. The difference in performance between the use of floating-point vs arbitrary precision

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 Lab 5
Lab 5: Vitis HLS Vitis Libraries
Step 1 – Open the Vitis libraries repository in GitHub.

Lab 5
Vitis HLS Vitis Libraries

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Lab 5 Lab 5
Lab 5: Vitis HLS Vitis Libraries Lab 5: Vitis HLS Vitis Libraries
Step 1 – Download or clone the repository. Step 1 – If you downloaded the Zip Extract the files .

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 Lab 5 Lab 5
Lab 5: Vitis HLS Vitis Libraries Lab 5: Vitis HLS Vitis Libraries
Step 1 – Create a project called vhlab5. Step 1 – Right click on source and select Add Source File .

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Lab 5 Lab 5
Lab 5: Vitis HLS Vitis Libraries Lab 5: Vitis HLS Vitis Libraries
Step 1 – Select the files, data_path.hpp, top_module.cpp and top_module.hpp from the location Step 1 – Right click on Test Bench and select Add Source File .
<install>\Vitis_Libraries\dsp\L1\examples\1Dfix_impluse\src

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 Lab 5 Lab 5
Lab 5: Vitis HLS Vitis Libraries Lab 5: Vitis HLS Vitis Libraries
Step 1 – Select the file main.cpp from the location Step 1 – Select the fft_top as the top function for the project
<install>\Vitis_Libraries\dsp\L1\examples\1Dfix_impluse\src

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Lab 5 Lab 5
Lab 5: Vitis HLS Vitis Libraries Lab 5: Vitis HLS Vitis Libraries
Step 1 – Set the Cflags and Csimflags to Step 1 – Run synthesis this might take some time
-I../../../../../GIT/Vitis_Libraries/dsp/L1/include/hw/vitis_fft/fixed

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 Lab 5 Lab 5
Lab 5: Vitis HLS Vitis Libraries Lab 5: Vitis HLS Vitis Libraries
Step 1 – Examine the function call graph Step 1 – Examine the Dataflow graph

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Lab 5 Lab 5
Lab 5: Vitis HLS Vitis Libraries Lab 5: Vitis HLS Vitis Libraries
Step 1 – Notice there is a timing error, Step 1 – Right click on the error and select go to timing violation

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 Lab 5 Lab 5
Lab 5: Vitis HLS Vitis Libraries Lab 5: Vitis HLS Vitis Libraries
Step 1 – Observe the timing violation in the schedule viewer Step 1 – Back in the timing violation, go to the source- notice the line of code causing the delay is
highlighted.

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Lab 5 Summary
Lab 5 Summary
The concludes lab 5, throughout this lab we have demonstrated

1. How to access Vitis Libraries

2. How to include Level One elements from the library within Vitis HLS

3. How to include the Vitis libraries to build to application

4. How to observe the results in the function call and dataflow graph

5. How to identify a timing violation

6. How to view the violation in the schedule viewer

7. How to identify the violation in the source code.

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