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Day Wise DP

This document contains a day wise schedule for the subject Digital Principles, which is part of the BCA Semester I course at St. Joseph's Degree College in Hyderabad, India. It lists the topics that will be covered each class, organized into 5 units - Binary Systems, Minimization, Combinational Logic, Synchronous Sequential Logic, Registers and Counters, and Asynchronous Sequential Circuits. The schedule provides the structure for the semester-long course taught by instructor Mrs. Asha Tabassum.

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38 views3 pages

Day Wise DP

This document contains a day wise schedule for the subject Digital Principles, which is part of the BCA Semester I course at St. Joseph's Degree College in Hyderabad, India. It lists the topics that will be covered each class, organized into 5 units - Binary Systems, Minimization, Combinational Logic, Synchronous Sequential Logic, Registers and Counters, and Asynchronous Sequential Circuits. The schedule provides the structure for the semester-long course taught by instructor Mrs. Asha Tabassum.

Uploaded by

innocentparinde
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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St.

JOSEPH’S DEGREE COLLEGE


Dept.Of Computer Science (BCA)

(Affiliated to Osmania University)


Co-Ed campus, Tolichowki, Hyderabad. Ph.No. 9063484237

Day wise schedule Semester I

Course :BCA Semester I


Subject Code : BCA102PC
Subject Name : Digital Priciples
Name of the faculty : Mrs Asha Tabassum

S.N
Name of the Topic Class
o
UNIT – I
1.
BINARY SYSTEMS
2. Digital Systems
3. Binary Numbers
4. Number Base Conversions
5. Octal And Hexadecimal Numbers
6. Complements
7. Signed Binary Numbers
Binary Codes
8.
9. Binary Storage and Registers
10. Binary Logic
11. BOOLEAN ALGEBRA AND LOGIC GATES
12. Basic Theorems and properties of Boolean Algebra
13. Boolean Functions
14. Canonical and Standard Forms
15. Digital Logic Gates
UNIT – II
16.
MINIMIZATION

17. K-Map Method – Table Methos

18. POS - SOP


19. Don’t Care
20. NAND
21. NOR Implementation
22. COMBINATIONAL LOGIC
23. Combinational Circuits
24. Analysis and Design Procedure
25. Binary Adder
26. Subtractor
27. Decimal Adder
28. Binary Multiplier
29. Magnitude Comparator
Decoders
30.
31. Encoders
Multiplexers
32.
UNIT III
33. SYNCHRONOUS SEQUENTIAL LOGIC

34. Sequential Circuits - Latches


35. Flip-Flops
An analysis of Clocked Sequential Circuits
36.
State Reduction and Assignment Design Procedure
37.

UNIT IV
38. REGISTERS AND COUNTERS

39. Registers
40. Shift Registers
41. Ripple Counters
42. Synchronous Counters
43. Ring Counters-Johnson Counter
44. UNIT V
ASYNCHRONOUS SEQUENTIAL CIRCUIT
45. Introduction
46. Analysis Procedure
47. Circuits with Latches
48. Design Procedure
49. Revision

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