14/11/2023, 11:56 [Selected] Digital IC back-end process - (4) Clock Tree Synthesis_Why clock tree synthesis is necessary - C…

Digital IC back-end process - (4) Clock Tree Synthesis Clock Tree Synthesis
Luka Meow Published on 2022-03-11 17:27:59 Reading volume: 7.4k Collection 156 Likes 12
Classification column: Digital IC backend notes Article tags: fpga development c language Development language

Digital IC backend n… The column contains this content 220 subscriptions 27 articles S

Refer to the original blog address: https://blog.csdn.net/weixin_46752319/article/details/107387584

ICC clock tree synthesis

Clock tree synthesis refers to the clock buffer /inverter tree that grows from the root point of a certain clock to each sink point. The tool attempts t
sinks belonging to a certain clock the same length, that is, to make the time it takes for a clock signal to reach each terminal node to be the same as

Before clock tree synthesis is performed, the clock tree has not yet been generated. The clock logic structure is as shown in the figure on the left. A
source terminal (root) eventually fans out to the clock terminals of many registers. But we know that the drive and load of the path that the clock sou
reach different registers are different, so the time when the clock signal reaches the clock end of each register is also different. The time deviation w
reaches different registers is called skew. The traditional CTS is for Reduce skew.

After clock tree synthesis, a clock tree is formed by adding three-level buffers with three colored triangles as shown in the figure on the right. The clo
will first reach the buffers at all levels so that the time it finally reaches the clock end of each register is almost the same.

Therefore, the purpose of clock tree synthesis is twofold:

1. Keep the clock skew as small as possible, especially for clock quality requirements or high-frequency clocks;

2. Keep clock latency as short as possible.

First of all, for a design, the most important step to perform clock tree synthesis is to define the clock terminal. Both root and sink need to know, and
software calculates the delay according to the definition.

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First define the root point of the clock and use create_clock to define the root point of the clock.

If it is a generated clock (generated clock), it needs to be defined using create_generated_clock, and its master clock needs to be clearly defined. A
time, it is required that the generate clock and master clock can be traced.

As shown in the figure above, the Master clock, CLKP and Generated clock are named CLKPDIV2 and defined using the command:

Icc_shell>create_clock -name CLKP [get_pins UPLL0/CLKOUT]

Icc_shell>create_generated_clock -name CLKPDIV2 -source UPLL0/CLKOUT -add -master_clock CLKP -divide_by 2 [get_pins UFF0/Q]

The master clock is the master clock defined through create_clock, which is CLKP in the figure; the divided clock is defined as the generated clock t
command.

When generating a generated clock, you must clearly understand the phase relationship between the generated clock and the master clock (rise->r
>fall or fall->rise or fall->fall). These relationships are grafted by the bridge source clock, so there is generated The relationship between clock and s
clock, and source clock and master clock.

(Personal understanding: source)

In the above figure, the source clock is the master clock. However, if the relationship between the generated clock and the master clock found
to the statement is inconsistent with the actual relationship, otherwise it will cause some analysis errors.

As shown in the figure, the master clock is CLK and the generated clock is uDIV.

If defined: create_clock -period 10 clk

create_generated_clock -name CLKdiv2 -divide_by 2 -source clk [get_pins Udiv/Q]

Then according to the definition, the phase relationship between master clock and gerenated clock is as shown in the figure:

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According to the above definition, generated_clock is defined on the divided-by-two output terminal Q, and its source is CLK. But we see that the clo
terminals CK and CLK of the Udiv register are inverted (that is, the phase difference is 180 degrees).

In fact, the phase relationship between master clock and gerenated clock should be:

The first method of correction is to change the source of the generated clock, that is, make the path between the generated clock and the source clo
and single (single means that the declared phase edge relationship is consistent with the actual phase edge relationship). The general approach is
source clock to the clock end of the flip-flop.

The corresponding command should be create_generated_clock -name CLKdiv2 -divide_by 2 -source [get_pins Udiv/Clk] [get_pins Udiv/Q]

The second is to directly declare the phase edge relationship between the generated clock and the master clock. as follows:

create_generated_clock -name CLKdiv2 -edges {2 4 6} -source CLK [get_pins Udiv/Q]

Considering the convenience of later review constraint, it is strongly recommended to use the second method to implement it (this method is used in
projects).

(Personal thoughts. In the ICC man page, the -source master_pin option for create_generated_clock
Specifies the master clock pin, which is either a master clock source pin or a pin in the fanout of the master clock and driving the generated clock de
The clock waveform at the master pin is used for deriving the generated clock waveform.

In other words, the -source option can be followed by the clock pin that drives the flip-flop that generates the clock? I don't quite understand the con
source clock.

For a multi-level frequency division clock like this, the definition of FFdiv3 is

Create_generated_clock -name CLK_mux_div3 -divide_by 3 -source FFdiv3/CK -master CLK_mux -add

Create_generated_clock -name CLKdiv2_mux_div3 -divide_by 3 -source FFdiv3/CK -master CLKdiv2_mux -add

Create_generated_clock -name CLKdiv4_mux_div3 -divide_by 3 -source FFdiv3/CK -master CLKdiv4_mux -add)

After defining the clock source end, you need to determine the endpoints of the timing path.

Pin type Alias explain Tool handling

Sink pin/sync
CTS will optimize the timing DRC and the skew and insertion delay of the c
Stop pin pin Nodes that need to be balanced

CTS will ignore the optimization of insertion delay and skew T

but still fixes timing DRC on the clock tree pre

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Go through this node to find the final sink calculation and optimize insertion
Non_stop The signal passes through this
skew
pin node

The processing is the same as the stop pin, but there is some delay on the
Float pin The final node is "hidden" behind

Set the priority of clock tree exceptions (set_clock_tree_exceptions)

1. Non-stop pins (-non_stop_pins) 2. Exclude pins (-exclude_pins) 3. Stop pins (-stop_pins) 4. Floating pins (-float_pins)

Others: 5. Don’t touch subtrees (-dont_touch_subtrees)

1. Nonstop pins

Unbroken pins: ICC traces through unbroken pins to find the true clock tree endpoint. The clock pin that drives the sequential unit that generates the
implicit uninterruptible pin.

Icc_shell>set_clock_tree_exceptions -non_stop_pins { list of pins }

·ICC believes that the clock input pin of the integrated clock gating ICG (integrated clock-gating) unit is an implicit uninterrupted pin, and there is no
manually set it, as shown in ① in the figure. (The clock gating cell is an indispensable unit for reducing dynamic power. ICG can also eliminate glitch

·If the fan-out of the timing unit drives the generated clock, that is, the timing unit is used for frequency division to generate the generated clock, as s
in the figure. ICC treats the clock pins of this timing unit as implicit nonstop pins and traces the real clock tree endpoints through the timing unit.

2. Exclude pins (Ignore pins)

Excluded pins: clock tree endpoints excluded from clock tree timing calculation and optimization, that is, clock tree balance is not performed. ICC on
Exclude pins in calculations and optimization design rule constraints (logical DRC, i.e. max_cap/max_tran/max_fanout/max_length).

Icc_shell>set_clock_tree_exceptions -exclude_pins { list of pins }

·Implicit exclude pins

ICC will trace backward from the clock source and automatically determine implicit stop pins and implicit exclude pins (it is automatically determined
called implicit).

ICC defines the following clock endpoints as implicitly excluded pins:

·Another clock fans out the source pins of the clock tree (Source pins)

•Non-clock input pins of sequential units

•Multiplexer select pin

•Tri-state enable pin

•Output port
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•Incorrectly defined clock pin (e.g. clock pin has no triggering edge information or no timing arc to the output pin) pre
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• Keep the input pin of the buffer or inverter constant (by using set_case_analysis)

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•Input pins of combinational logic cells or integrated clock gating cells that do not have any fan-out or do not have any enabled timing arcs

All non-clock pins (such as the D pin of FF or the input of combinational logic) are called excluded (ignored) pins. These pins do not need to be cons
during clock tree propagation and no balancing is required.

In addition to ICC-inferred exclude pins (implicit exclude pins), ICC also supports user-defined (or explicit) exclude pins. For example, you can defin
exclude pin to exclude all branches of a clock tree leading from some combinational logic (as shown in the figure below), or to exclude an implicit st

3. Stop pins (Sink pins)

Stop pin: The endpoint of the clock tree used for balancing delays. During clock tree synthesis, ICC will use Stop pins to calculate and optimize des
constraints and clock tree timing (Skew and Insertion Delay). Stop pins are also called Sink pins, which is what we call the sink end of the clock tree
balance.

Icc_shell>set_clock_tree_exceptions -stop_pins { list of pins }

All clock pins of ##FF are called stop (sync) pins. The clock signal should not propagate after reaching the SYC/STOP pin.

The default clock sink is the implicit stop pin. Additionally, ICC supports user-defined (or explicit) stop pins. For example, you can define a stop pin t
branch on a combinational unit input, or use an implicit exclude pin as a clock sink.

ICC assigns zero phase delay to all stop pins (implicit and explicit) and uses this delay during delay balancing.

Therefore, the tool only balances the delays (minimize skew) of stop pins. If other pins need to be optimized, the pins need to be set and told to ICC

4. Float pins

Floating Pin: A clock pin with special insertion delay requirements. Similar to stop pins, but the pin's internal clock delay is taken into account when
clock tree. When the tool calculates the insertion delay (Insertion delay) of the Float Pins, it will add the Float Pin delay (positive or negative) to the
Insertion delay.

As shown in the figure above, it is the clock input pin of the hard macro and needs to be considered when building the clock tree. But before it can b
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a sync pin, the macro's internal tree needs to be balanced. The final node is hidden behind. pre

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• -float_pin_max_delay_fall max_delay_fall_value

• -float_pin_max_delay_rise max_delay_rise_value

• -float_pin_min_delay_fall min_delay_fall_value

• -float_pin_min_delay_rise min_delay_rise_value

• -float_pin_logic_level logic_level_value

(PS: When using -float_pins, at least one floating pin delay option must be specified)

# Specifying a negative float pin

Icc_shell>set_clock_tree_exceptions -float_pins U1/CLK -float_pin_max_delay_rise -0.5 -float_pin_max_delay_fall -0.5

#Specifying a positive float pin

Icc_shell>set_clock_tree_exceptions -float_pins U4/CLK -float_pin_max_delay_rise 0.5 -float_pin_max_delay_fall 0.5

Add pin insertion delay and specify negative float pins

Reduce pin insertion delay and specify positive pin delay (positive float pins)

The internal delay information of the Hard macro is represented in the unit's timing model (.lib). ICC uses this model to determine the external clock
Hard macro as a clock sink. During CTS, the ICC balances skew on the macro external clock pin and minimizes insertion delay.

When you need to change the Hard macro timing characteristics, you need to use floating pins to specify the timing characteristics of the Hard mac
clock tree.

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Explain these pins with examples in the student guide. As shown in the figure, the pin of the macro is defined as an implicit exclude pin, so ICC will
calculate the skew and insertion delay of the macro after the pin. Luka Meow focus on 12

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Through the set_clock_tree_exceptions -stop_pins command, the macro pin is defined as a stop pin. ICC can optimize its skew and insertion delay.
in the figure, we find that ICC balances the clock to IP_CLK end and the clock to FF clk end, and The delay within the macro is not considered.

When IP_CLK is set to a float pin, the timing characteristics of the macro's internal clock tree can be considered, so that the insertion delay from the
the FF inside the macro is balanced with the insertion delay from the clock to the external FF. Clock.

5. Dont_touch_subtrees

Don't touch subtree: In some cases, you want to preserve part of the existing clock tree and need to set it like this. For example, when two clock net
share part of some clock logic behind a multiplexer. The portion of the clock tree that is retained is called the untouched subtree.

Icc_shell>set_clock_tree_exceptions -dont_touch_subtrees

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When there is a designed clock tree in the design (Pre-exisiting clock tree in the picture), you can use set_clock_tree_exceptions -dont_touch_subtr
to set it as the dont_touch attribute. CTS will compare other designed clock trees with the pre-existing clock tree. balance

Or remove it through the remove_clock_tree command, and CTS will recalculate the delay from CLOCK to the sink.

The above is an introduction to clock endpoints. And what we are talking about is balancing between various paths under the same clock.

If there are multiple clock root terminals defined by create_clock in the design, the two clocks are not synchronized, but some of their registers will t
default, when CTS builds CLOCK1 and CLOCK2, it will build clock trees separately and will not perform inter-clock balance.

To balance multiple clock trees, you need to add commands to the tool.

The picture above shows two clocks without inter-clock balance.

icc_shell>set_inter_clock_delay_options -balance_group "Clk1 Clk2" -balance_group_name group2

balance_inter_clock_delay -clock_trees { clock_1 clock_2 }

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The picture above shows the two clocks after inter-clock balance. PS:
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TNS: total negative slack, the total negative timing time, that is, the Luka
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WNS: worst negative slack

THS: the negative timing sum of total hold slack total hold time

WHS: worst hold slack worst hold time negative timing

If slack is a positive value, it means that the design timing requirements are met; if it is a negative value, it means that the design timing requiremen
met.

Therefore, the setup time still needs to be repaired.

-delay_offset指定延迟偏移值。

正值表示-offset_to选项中指定的时钟落后于-offset_from选项中指定的时钟。

负值表示-offset_to选项中指定的时钟早于-offset_from选项中指定的时钟。

lab中教了一种检查时钟树的方法，有助于进行时钟端点的设置等。

·查看设计中的时钟偏移和属性ℹicc_shell>report_clock -skew -attributes

通过报告可以查看设计中定义的时钟、生成时钟及其属性。

·查看时钟树总体情况 icc_shell>report_clock_tree -summary

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可以查看时钟树的最大路径，即最大插入延迟，所驱动的sink端和插入的buffer的面积等，在还未进行CTS前暂未插入buffer，面积为0。同时可以发现
SD_DDR_CLK所驱动的sink端为0。

通过之前report_clock，我们知道该时钟是生成时钟。

·查看它的source port icc_shell>report_port sd_CK

direction为out, output的port 没有endpoint。

·查看设计中是否存在violation icc_shell>report_constraint -all

该设计中只有hold的违例和面积违例，面积违例可以忽略，而在CTS之后才修复hold violation，此时设计符合CTS的条件。

·通过gui方式查看时钟树详细信息，可以帮助工程师快速理清clock的结构和debug clock tree 质量

GUI>Clock>New Interactive CTS Window

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可以看到各个clk驱动的sink端的数目及cell例化的名字，以及时钟驱动这个cell使用上升沿驱动还是下降沿驱动等。

其中有些clock驱动的pin设置为exception:implicit_exclude_pin 这些pin都是MUX的select pins，需要被忽略，不做skew和latency的优化，通过查看s

可以更好的分析。

而该设计中，将MUX的引脚设定为stop pins。

icc_shell>set_clock_tree_exceptions -stop_pins {I_SDRAM_TOP/I_SDRAM_IF/sd_mux_*/S} 使用通配符*查找所有要求的端口 Gui>Clock>

Exceptions

此时，所有查找到的pins已被更改为stop pins，

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在对时钟的root点和端点进行准确的定义后，开始进行对时钟树综合的设置。
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·设置目标skew

Gui>Clock>Set Clock Options

ICC默认target skew为0，但是设置可接受的skew可以减少run time icc_shell>set_clock_tree_options -target_skew 0.1

同时可以设置target early delay（即insertion delay）一般可不设置

设置max_fanout , max_transition , max_capacitance

·设置时钟树的references

时钟树综合前给软件指定创建时钟树的单元，一般用时钟buffer或时钟反相器。

Buffer:上升下降时间基本相同，逻辑简单，便于post-CTS对时钟树的修改；面积大，功耗大，insertion delay大。

反相器：面积小，功耗小，insertion delay小，对时钟duty cycle有利；不易做时钟树的修改。

一般库里的时钟buffer或inverter都是以CLK或CK开头，可用通配符查找

icc_shell>set_clock_tree_references -references { CLKBUFHSV12 ...$list}

-references { list } -sizing_only

-references { list } -delay_insertion_only

Gui>Clock>Set Clock Tree References

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·时钟树布线规则的定义

首先删除之前定义的NDR（non-default rule） icc_shell>remove_routing_rules -all

为时钟线定义NDR（一般设置双倍线宽，双倍间距）
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时钟的翻转频率较高，clock path 上受到的串扰以及 EM 影响也较大。因此，通常会采取双倍宽度的绕线宽度。默认的绕线规则都是单位宽度，就是指
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Icc_shell>define_routing_rule clk_rule(your rule name) -default_reference_rule -multiplier_spacing 2 -multiplier_width 2

或者

Icc_shell>define_routing_rule CLOCK_DOUBLE_SPACING \

-spacings {METAL1 xx METAL2 xx METAL3 xx METAL4 xx METAL5 xx} \

-widths {METAL1 xx METAL2 xx METAL3 xx METAL4 xx METAL5 xx} xx是设置的参数

Gui>Route>Routing Setup>Define Routing Rule>New

为时钟布线选择自己定义的NDR以及金属层次。由于标准单元出pin大部分是M1/M2，如果设置ndr rule，会导致很多DRC。因此，在sink端使用默认
线宽、间距）进行布线。

Icc_shell>set_clock_tree_options -routing_rule CLOCK_DOUBLE_SPACING -layer_list {METAL3 METAL5} \

-use_default_routing_for_sinks 1

为了使得clock tree质量更好，我们往往将高层用来作为时钟信号的走线。 T
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·时钟树综合前准备

查看时钟树综合设定，确认上述设定正确 icc_shell>report_clock_tree -settings

进行物理检查 icc_shell>check_physical_design -stage pre_clock_opt -display

设置时钟树延迟计算模式

arnoldi > awe > elmore 精确程度

icc_shell>set_delay_calculation_options -preroute awe -postroute arnoldi

-routed_clock arnoldi -arnoldi_effort medium -awe_effort medium

检查时钟树 icc_shell>check_clock_tree

·时钟树综合

①icc_shell>clock_opt -only_cts -no_clock_route

根据时钟域以及路径关系， skew 可以分为global skew，local skew，interclock skew。

·Global skew 是指，同一时钟域，任意两个路径的最大 skew 。任意两条路径，不管是不是timing path，都会算作gloabl skew计算的对象。CTS时，

的是global skew, 会尽可能地将global skew做小。

icc_shell>report_clock_tree -summary 报告global skew

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报告每个时钟树在CTS阶段插入的buffer数量和面积，时钟树的最长路径延时，最重要的是时钟skew的大小，即同一时钟域下，最大路径减最小路径的

·Local skew 是指，同一时钟域，任意两个有逻辑关联关系的路径最大 skew 。这边需要注明，必须是存在逻辑关系的path才会计算local skew，也就是

是timing path。如下图所示，在分析timing的时候，更多地是关注local skew。

icc_shell>report_clock_timing -type skew -significant_digits 3 报告local skew

·interClock skew 是指，不同时钟域之间路径的最大 skew

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·icc_shell>report_timing Luka Meow focus on

生成时序报告，主要检查slack为正，时序符合要求 12

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·icc_shell>report_constraint -all 查看违规报告

如图中只存在的是hold和面积的违规，并且前面的报告分析CTS的质量满足，Pre-CTS完成。

·Post-CTS

clock的Timing分为两种模式，ideal clock和propagated clock。

CTS之前并没有clock, 因此我们需要建立一个ideal的clock，这时从clock端口到寄存器CK端口的network delay来自sdc中的set_clock_latency设置；

做完CTS，并且update好IO latency之后，我们的clock就会自动的转换成propagated的clock，这时network delay就是实际时钟互连线网络的RC extra

的delay。

CTS之后由于时钟树已经建立，所以需要将时钟网络以及高扇出网络的理想属性移除，并开始修复hold违反。下面逐一进行讲解如何操作。

·在CTS后，工具会自动移除所有时钟的理想属性。最好也手工设置

icc_shell>remove_ideal_network [ all_fanout -flat -clock_tree ]

icc_shell>remove_clock_latency $clk

将其设置为icc_shell>set_propagate_clock [ get_attr $clock source ]

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·重新定义关于clock uncertainty的定义，去掉其中估计的clock skew的部分 12

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clock uncertainty分为setup和hold，preCTS和postCTS几种不同的情况
一般的处理原则是：
pre CTS，setup： uncertainty = PLL jitter + 预估的clock skew pre CTS，hold： uncertainty = 预估的clock skew

post CTS，set_propagate_clock [all_clocks]

post CTS，setup： uncertainty = PLL jitter post CTS，hold： uncertainty = 0

有时fundry要求hold uncertainty保留一定的量，这时就把那个保留量加到上面的公式中

icc_shell>set_clock_uncertainty -setup 1 $clk icc_shell>set_clock_uncertainty -hold 0.1 $clk

在移除理想属性以及sdc中的latency信息之后用update_clock_latency来更新latency信息。

icc_shell>update_clock_latency

·CTS之后（post CTS）开始关心hold time

icc_shell>set_fix_hold [ all_clocks ]

查看设计的报告 icc_shell>report_qor (quality of result)

Psyn经常配合-area_recovery选项，对面积进行优化

设置icc_shell>set_max_area 0

icc_shell>set physopt_area_critical_range 0.2 该命令表示在timing slack 大于某个值的paths 上 optimize area（power）

指定若path存在指定的slack的值，则会对面积进行优化，因为对面积的优化会导致时序变差，只有有slack余量能对进行面积优化

一般给的建议是 place是 10% period CTS 8% route 5%

Icc_shell>extract_rc 提取寄生参数

②icc_shell>clock_opt -only_psyn -area_recovery -optimize_dft -no_clock_route

Gui>Clock>Core CTS and Optimization

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14/11/2023, 11:56 [Selected] Digital IC back-end process - (4) Clock Tree Synthesis_Why clock tree synthesis is necessary - C…

icc_shell>report_qor

可以看到前后对比的qor 经过hold的修复 已经没有hold的WNS和TNS

icc_shell>report_constraint -all 查看违规

经过hold修复，已经没有hold的违规

最后，进行时钟的绕线

③route_zrt_group -all_clock_nets -reuse_existing_global_route true

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14/11/2023, 11:56 [Selected] Digital IC back-end process - (4) Clock Tree Synthesis_Why clock tree synthesis is necessary - C…

icc_shell>report_constraint -all confirms that no violations occur

icc_shell>report_design -physical

Save the design save_mw_cel -as clock_opt_route

Clock tree stage completed

Add to:

After the clock tree stage is completed, since many inverters or buffers are inserted into the design, these units are also standard units and need to

derive_pg_net connects them to P/G net and pin, otherwise a short-circuit error will occur in verify_lvs.

The knowledge points of the article match the official knowledge archives, allowing you to further learn related knowledge.

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ICC图文流程——(四)时钟树综合Clock Tree Synthesis 热门推荐 weixin_46752319的

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