MT7628 ProgrammingGuide 20140428 (E2)
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Barak DavidovichMT7628 ProgrammingGuide 20140428 (E2)
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MT7628
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PROGRAMMING GUIDE
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Version: 1.0
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Release date: 2014-06-03
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© 2014 MediaTek Inc.
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This document contains information that is proprietary to MediaTek Inc.
Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited.
Specifications are subject to change without notice.
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MT7628 Overview
The MT7628 SoC includes a high performance 580/575 MHz MIPS24KEc CPU core and high speed USB2.0/PCIe
EO
interfaces, which is designed to enable a multitude of high performance, cost-effective IEEE 802.11n
applications with a MediaTek WiFi client card.
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Functional Block Diagram
16-Bit
EJTAG
DDR1/DDR2
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PLLs & SSC PADRING DDR PHY
MT7628 Block Diagram
To CPU
CLKGEN IOMUX
interrupts
RSTGEN Strap Pin
DDR1/DDR2
MIPS 24KEc Memory Controller
64KB I-Cache Rbus
32KB D-Cache OCP_IF 2ch Arbiter INTC
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(580/575MHz) OCP Bridge
PWM x4 PWM
8ch QoS Arbiter
SPI(M) x2 SPI
ne FID
SPI(S) SPI
RBUS (SYS_CLK)
UARTL x3 UART
APB BUS
GPIO GPIO
APB BUS
I2C I2C
SDXC AES SUTIF
syn ON
WPDMA PDMA GDMA
eMMC Engine USB 2.0 PCIe 1.1 3wSPI I2S I2S
Host Host
Controller Controller MAC
PCM PCM
WLAN Switch
UTMI PIPE BBP Timer
USB 2.0 PHY PCIe 1.1 PHY RF 11n 2x2 5-Port EPHY
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SDXC
USB Host PCIe Host RJ45 x5
Host
2.4GHz
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Figure 1-1 MT7628 Block Diagram
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There are several masters (MIPS 24KEc, USB, PCI Express, SDXC, FE) in the MT7628 SoC on a high performance,
low latency Rbus. In addition, the MT7628 SoC supports lower speed peripherals such as UART Lite, GPIO, I2C
and SPI via a low speed peripheral bus (Pbus). The DDR/DDR2 controller is the only bus slave on the Rbus. It
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includes an Advanced Memory Scheduler to arbitrate the requests from bus masters, enhancing the
performance of memory access intensive tasks.
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Document Revision History
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Revision Date Author Description
1.0 2014-04-28 PeterCT Wu Initial Draft
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Table of Contents
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MT7628 OVERVIEW 2
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FUNCTIONAL BLOCK DIAGRAM 2
DOCUMENT REVISION HISTORY 3
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TABLE OF CONTENTS 4
TABLE OF FIGURES 6
LIST OF TABLES 7
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1. MIPS 24KEC PROCESSOR 8
1.1 FEATURES 8
1.2 BLOCK DIAGRAM 9
1.3 MEMORY MAP SUMMARY 10
1.3 INTERUPT TABLE SUMMARY 11
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1.4 CLOCK PLAN 12
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2. REGISTERS 13
2.1 NOMENCLATURE 13
2.2 SYSTEM CONTROL 14
2.2.1 FEATURES 14
2.2.2 BLOCK DIAGRAM 14
2.2.3 REGISTERS 15
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2.3 TIMER 32
2.3.1 FEATURES 32
2.3.2 BLOCK DIAGRAM 32
2.3.3 REGISTERS 33
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2.4 INTERRUPT CONTROLLER 38
2.4.1 REGISTERS 38
2.5 EMC CONTROLLER 46
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2.5.1 REGSITER 46
2.6 R-BUS CONTROLLER 63
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2.6.1 FEATURES 63
2.6.2 BLOCK DIAGRAM 63
2.7 MIPS CNT 74
2.7.1 REGISTERS 74
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2.8 GENERAL PURPOSE IO 76
2.8.1 FEATURES 76
2.8.2 BLOCK DIAGRAM 76
2.8.3 GPIO PIN MAPPING 77
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2.8.4 REGISTER 77
2.9 SPI SLAVE 91
2.9.1 SPI SLAVE CONTROL 91
2.9.2 REGSITERS 93
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2
2.10 I C CONTROLLER 96
2.10.1 FEATURES 96
2.10.2 LIST OF REGISTERS 96
2.11 I2S CONTROLLER 103
2.11.1 FEATURES 103
2.11.2 BLOCK DIAGRAM 103
2.11.3 REGISTERS 104
OR
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2.12 SPI CONTROLLER 110
2.12.1 FEATURES 110
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2.12.2 BLOCK DIAGRAM 110
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2.12.3 REGISTERS 110
2.13 UART LITE 121
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2.13.1 FEATURES 121
2.13.2 REGISTERS 121
2.14 PCM CONTROLLER 135
2.14.1 FEATURES 135
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2.14.2 BLOCK DIAGRAM 135
2.14.3 LIST OF REGISTERS 136
2.14.4 PCM CONFIGURATION 136
2.14.5 REGISTER 138
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2.15 GENERIC DMA CONTROLLER 155
2.15.1 FEATURES 155
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2.15.2 BLOCK DIAGRAM 155
2.15.3 PERIPHERAL CHANNEL CONNECTION 155
2.15.4 REGISTERS 156
2.16 AES CONTROLLER 204
2.16.1 REGISTERS 204
2.17 PWM (PULSE WIDTH MODULATION) 214
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2.17.1 REGISTERS 214
2.18 FRAME ENGINE 232
2.18.1 REGISTERS 232
2.19 SWITCH CONTROLLER 251
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2.19.1 REGISTERS 251
2.20 MSDC 301
2.20.1 REGISTERS 301
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2.21 PCI EXPRESS 328
2.21.1 REGISTERS 328
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2.22 USB HOST CONTROLLER 336
2.22.1 REGISTERS 336
3. LIST 345
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Table of Figures
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FIGURE 1-1 MT7628 BLOCK DIAGRAM .......................................................................................................................... 2
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FIGURE 1-1 MIPS 24KEC CPU BLOCK DIAGRAM ..................................................................................................... 9
FIGURE 1-2 MT7628 CLOCK DIAGRAM ........................................................................................................................ 12
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FIGURE 2-1 SYSTEM CONTROL BLOCK DIAGRAM ............................................................................................................. 14
FIGURE 2-2 TIMER BLOCK DIAGRAM ............................................................................................................................. 32
FIGURE 2-9 QOS ARBITRATION BLOCK DIAGRAM ............................................................................................................ 63
FIGURE 2-3 PROGRAMMABLE I/O BLOCK DIAGRAM ........................................................................................................ 76
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2
FIGURE 2-7 I S TRANSMITTER BLOCK DIAGRAM ............................................................................................................ 103
FIGURE 2-8 I2S TRANSMIT/RECEIVE ........................................................................................................................... 103
FIGURE 2-6 SPI CONTROLLER BLOCK DIAGRAM ............................................................................................................ 110
FIGURE 2-4 PCM CONTROLLER BLOCK DIAGRAM .......................................................................................................... 135
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FIGURE 2-5 GENERIC DMA CONTROLLER BLOCK DIAGRAM............................................................................................. 155
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List of Tables
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TABLE 1 THE IIR[5:0] CODES ASSOCIATED WITH THE POSSIBLE INTERRUPTS......................................................................... 123
TABLE 2 DIVISOR NEEDED TO GENERATE A GIVEN BAUD RATE............................................................................................ 128
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TABLE 3 DIVISOR NEEDED TO GENERATE A GIVEN BAUD RATE FROM 13MHZ BASED ON DIFFERENT HIGHSPEED VALUE ............. 130
TABLE 4 DIVISOR NEEDED TO GENERATE A GIVEN BAUD RATE FROM 26 MHZ BASED ON DIFFERENT HIGHSPEED VALUE ............ 131
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TABLE 5 DIVISOR NEEDED TO GENERATE A GIVEN BAUD RATE FROM 52 MHZ BASED ON DIFFERENT HIGHSPEED VALUE ............ 131
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1. MIPS 24KEc Processor
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1.1 Features
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8-stage pipeline
32-bit address paths
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64-bit data paths to caches and external interfaces
MIPS32-Compatible Instruction Set
Multiply-Accumulate and Multiply-Subtract Instructions (MADD, MADDU, MSUB, MSUBU)
Targeted Multiply Instruction (MUL)
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Zero/One Detect Instructions (CLZ, CLO)
Wait instructions (WAIT)
Conditional Move instructions (MOVZ, MOVN)
Prefetch instructions (PREF)
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MIPS32 Enhanced Architecture (Release 2) Features
Vectored interrupts and support for an external interrupt controller
ne FID
Programmable exception vector base
Atomic interrupt enable/disable
GPR shadow registers (one, three or seven additional shadows can be optionally added to minimize
latency for interrupt handlers)
Bit field manipulation instructions
MIPS32 Privileged Resource Architecture
syn ON
MIPS DSP ASE
Fractional data types (Q15, Q31)
Saturating arithmetic
SIMD instructions operate on 2x16 b or 4x8 b simultaneously
3 additional pairs of accumulator registers
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Programmable Memory Management Unit
32 dual-entry JTLB with variable page sizes
4-entry ITLB
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8-entry DTLB
Optional simple Fixed Mapping Translation (FMT) mechanism
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MIPS16e™ Code Compression
16-bit encodings of 32-bit instructions to improve code density
Special PC-relative instructions for efficient loading of addresses and constants
SAVE & RESTORE macro instructions for setting up and tearing down stack frames within subroutines
Improved support for handling 8 and 16-bit datatypes
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Programmable L1 Cache Sizes
Instruction cache size: 32 KB
Data cache size: 16 KB
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4-Way Set Associative
Up to 8 outstanding load misses
Write-back and write-through support
32-byte cache line size
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1.2 Block Diagram
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ISPRAM DMA
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OCP I/F Instruction EJTAG Off/on chip
i-cache 0/8/16/32/64 KB trace I/F
scratchpad
4-way set associative
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RAM Trace
TAP
User-defined Off-chip
CorExtend Debug I/F
block
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CorExtend
Fetch Unit
8-entry instruction buffer
512-entry BHT
4-entry RPS OCP
MDU
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Interface on-
BIU chip Bus(es)
Execution Unit 4-entry merging
ne FID
User-defined (RF/ALU/ MMU write buffer,
COP2 block Shift) 16/32/64 JTLB or FMT 10 outstanding
CP2 reads
Non-blocking load/store
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unit
8 outstanding misses
DSPRAM
System Co-
DMA OCP
processor
Interface
D-cache Data scratchpad
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0/8/16/32/64 KB RAM
Power 4-way set associative
Managment
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Fixed / Required
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Optional
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Figure 1-1 MIPS 24KEc CPU Block Diagram
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1.3 Memory Map Summary
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Start End Size Description
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0000.0000 - 0FFF.FFFF 256 MBytes DDR 256 MB
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1000.0000 - 1000.00FF 256 Bytes SYSCTL
1000.0100 - 1000.01FF 256 Bytes TIMER
1000.0200 - 1000.02FF 256 Bytes INTCTL
1000.0300 - 1000.03FF 256 Bytes EXT_MC_ARB (DDR/DDR II)
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1000.0400 - 1000.04FF 256 Bytes Rbus Matrix CTRL
1000.0500 - 1000.05FF 256 Bytes MIPS CNT
1000.0600 - 1000.06FF 256 Bytes GPIO
1000.0700 - 1000.07FF 256 Bytes SPI Slave
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1000.0800 - 1000.08FF 256 Bytes <<Reserved>>
1000.0900 - 1000.09FF 256 Bytes I2C
1000.0A00 - 1000.0AFF 256 Bytes I2S
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1000.0B00 - 1000.0BFF 256 Bytes SPI Master
1000.0C00 - 1000.0CFF 256 Bytes UARTLITE 1
1000.0D00 - 1000.0DFF 256 Bytes UARTLITE 2
1000.0E00 - 1000.0EFF 256 Bytes UARTLITE 3
1000.0F00 - 1000.0FFF 256 Bytes <<Reserved>>
syn ON
1000.1000 - 1000.17FF 2 KBytes RGCTL
1000.1800 - 1000.1FFF 2 KBytes <<Reserved>>
1000.2000 - 1000.27FF 2 KBytes PCM (up to 16 channels)
1000.2800 - 1000.2FFF 2 KBytes Generic DMA (up to 16 channels)
1000.3000 - 1000.3FFF 4 KBytes <<Reserved>>
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1000.4000 - 1000.4FFF 4 KBytes AES Engine
1000.5000 - 1000.5FFF 4 Kbytes PWM
1000.6000 - 100F.FFFF <<Reserved>>
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1010.0000 - 1010.FFFF 64 Kbytes Frame Engine
1011.0000 - 1011.7FFF 32 KBytes Ethernet Switch
1011.8000 - 1011.FFFF 32 KBytes <<Reserved>>
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1012.0000 1012.7FFF 32 KBytes USB PHY
1012.8000 - 1012.FFFF 32 KBytes <<Reserved>>
1013.0000 - 1013.7FFF 32 KBytes SDXC / eMMC
1013.8000 - 1013.FFFF 32 KBytes <<Reserved>>
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1014.0000 - 1017.FFFF 256 KBytes PCI Experss
1018.0000 - 101B.FFFF 256 KBytes <<Reserved>>
101C.0000 - 101F.FFFF 256 KBytes USB Host Controller
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1020.0000 - 102F.FFFF 1 MBytes <<Reserved>>
1030.0000 - 103F.FFFF 1 MBytes WLAN MAC/BBP
1040.0000 - 1BFF.FFFF <<Reserved>>
1C00.0000 - 1C3F.FFFF 4 MBytes SPI Flash Direct Access
1C40.0000 - 1FFF.FFFF <<Reserved>>
M
2000.0000 - 2FFF.FFFF 256 MBytes PCIE Direct Access
3000.9999 - 3FFF.FFFF <<Reserved>>
OR
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1.3 Interupt Table Summary
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SI_Int -
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Module Source Pin Level/Edge
SI_Int0 soc_cirq cpu_irq0 Level
.tw IA
SI_Int1 soc_cirq cpu_irq1 Level
SI_Int2 PCIE pcie_int_req Level
SI_Int3 FE fe_int_req Level
SI_Int4 WLAN wlan_int_req Level
om NT
SI_Int5 MIPS24Kec/aux_tick SI_TIMERInt/stk_int Level
INTC -
Module Source Pin Level/Edge
x.c E
soc_cirq_int0 SYSCTL sysctl_int Level
soc_cirq_int1 SPIS SW interrupt Level
soc_cirq_int2
ne FID
soc_cirq_int3 DRAMC mc_int Level
soc_cirq_int4 PCM pcm_int Level
soc_cirq_int5
soc_cirq_int6 GPIO gpio_int Level
soc_cirq_int7 GDMA gdma_int Level
syn ON
soc_cirq_int8
soc_cirq_int9 MIPS24Kec pc_int Level
soc_cirq_int10 I2S i2s_int Level
soc_cirq_int11 SPI spi_int Level
soc_cirq_int12
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soc_cirq_int13 AES aes_int Level
soc_cirq_int14 SDXC sdxc_int Level
soc_cirq_int15 PCTRL r2p_int Level
ien K
soc_cirq_int16 PCIE pcie_link_down_rst_int Level
soc_cirq_int17 ESW esw_int Level
soc_cirq_int18 USB20 uhstl_int Level
ch TE
soc_cirq_int19
soc_cirq_int20 UART-LITE uart0_int Level
soc_cirq_int21 UART-LITE uart1_int Level
soc_cirq_int22 UART-LITE uart2_int Level
am IA
soc_cirq_int23 TIMER wdtimer_int Level
soc_cirq_int24 TIMER timer0_int Level
soc_cirq_int25 TIMER timer1_int Level
soc_cirq_int26 PWM pwm_irq Level
ad ED
soc_cirq_int27 WLAN wlan_wakeup_int Level
soc_cirq_int28
soc_cirq_int29
soc_cirq_int30
M
soc_cirq_int31
OR
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1.4 Clock Plan
EO
US L
Pull-up/dwon
QI_IORDY_V33
QI_IORDY_V33
.tw IA
PAD_PORST_N
xtal_sel[1:0]
EXT_BGCLK 1 QI_PMU_RST
dkydelitch xtest_mode
pincap scan_mod
olt_mode
…..
NI_BGCLK 0
ANA_PMU_A102 35KHz ~ 40MHz
03A
wifisys_top
om NT
NI_EXCLK (7603)
sync_en_wf0_txdig (dig_en_wf0_txdig)
QI_SYSRDY_33
C wifisys_top_txdig_f480m_clk_int
G
AD_XO_BBTOP_CLK
25/40MHz 20/25MHz
AD_XO_F20M_CLK_USB
x.c E
PAD_XTALIN DA_XO_PREBUF_EN /3 sys_clk
PAD_CLKOUTP I
S C 25/40MHz /1 for 25/40M
AD_XO_BBTOP_CLK
PAD_CLKOUTN O G
1 /10 for 580M
cpu_clk
ne FID
DA_XO_DIGPREBUF_EN
A10203_RF [40]: 580MHz frac_gen
1 ocp_clk
osc_rdy
I [25]: 575MHz 0
S AD_XO_EPHY_CK
CPU PLL
O 0
(SSC) /3 dram_clk
25/40MHz
BBP I
PLL S AD_TOP_TXDIG_F480M_CLK_INT PCM/I2S
O
/2 PCM_240
USB2.0 Host
syn ON
Freq@XTAL=20M Freq@XTAL=25M Freq@XTAL=40M IP
PCIe, CPUPLL, SoC,
AD_XO_BBTOP_CK 20 25 40 20MHz
WiFi 240 MHz
AD_XO_F20M_CLK_USB 20 25 20 WiFi USB PHY
/24 120 MHz
AD_XO_EPHY_CK 20 25 40 EPHY (pll)
AD_TOP_TXDIG_F480M_
CLK_INTP_CK
480 480 480 SoC, WiFi
1 25/40MHz
clk_peri
@ C
(timer/uart/I2C)
0
/12
25/40MHz
(DA_PE1_NS_XTAL_CK) 100MHz
PCIe PCIe PCIe_CLK
DRV (EXT)
ien K
PHY-A
(pll) 125MHz
0
PCIe pcie_clk
25MHz (from EPHY) (host)
PHY-D
1
125MHz (from EPHY)
ch TE
PCIe Host
0
pcie_aux_clk
(host)
/100 1
250MHz
25/40MHz ck_250m
am IA
EPHY PLL
20/25/40MHz ck_50m
50MHz
SWPHY_top
ad ED
Figure 1-2 MT7628 Clock Diagram
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2. Registers
EO
2.1 Nomenclature
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The following nomenclature is used for register types:
.tw IA
RO Read Only
WO Write Only
RW Read or Write
RC Read Clear
om NT
W1C Write One Clear
- Reserved bit
X Undefined binary value
x.c E
ne FID
syn ON
@ C
ien K
ch TE
am IA
ad ED
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2.2 System Control
EO
2.2.1 Features
US L
Provides read-only chip revision registers
Provides a window to access boot-strapping signals
.tw IA
Supports memory remapping configurations
Supports software reset to each platform building block
Provides registers to determine GPIO and other peripheral pin muxing schemes
Provides some power-on-reset only test registers for software programmers
om NT
Combines miscellaneous registers (such as clock skew control, status register, memo registers, etc)
2.2.2 Block Diagram
x.c E
System Control Block
ne FID
Memory Remapping
CPU Rbus Wrapper
Boot Strapping Signals
GPIO Pin Muxing Scheme
Pin Muxing Block
System Control
Registers Per Block S/W Reset
Platform Blocks
syn ON
Cache Hit/Miss Strobes
Miscellaneous Registers
PCIe, PCM, ...
To/From MIPS
APBus Interface
@ C
ien K
Figure 2-1 System Control Block Diagram
ch TE
am IA
ad ED
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2.2.3 Registers
SYSCTL Changes LOG
EO
Revision Date Author Change Log
US L
0.1 2013/10/3 PeterCT Wu Initial for MT7628
0.2 2014/4/28 PeterCT Wu MT7628 E2
.tw IA
Module name: SYSCTL Base address: (+10000000h)
om NT
Address Name Widt Register Function
h
10000000 CHIPID0_3 32 CHIP ID ASCII Character 0-3
10000004 CHIPID4_7 32 CHIP ID ASCII Character 4-7
x.c E
10000008 EE_CFG 32 E-Fuse Configuration
1000000C CHIP_REV_ID 32 Chip Revision Identification
ne FID
10000010 SYSCFG0 32 System Configuration Register 0
10000014 SYSCFG1 32 System Configuration Register 1
10000018 TESTSTAT 32 Firmware Test Status
1000001C TESTSTAT2 32 Firmware Test Status 2
10000028 ROM_STATUS 32 Andes ROM Status
1000002C CLKCFG0 32 Clock Configuration Register 0
syn ON
10000030 CLKCFG1 32 Clock Configuration Register 1
10000034 RSTCTL 32 Reset Control Register
10000038 RSTSTAT 32 Reset Status Register
1000003C AGPIO_CFG 32 Analog GPIO Configuration
@ C
10000040 N9_GPIO_INT 32 Andes GPIO Interrupt
N9_GPIO_MAS
10000044 K 32 Andes GPIO Mask
ien K
10000060 GPIO1_MODE 32 GPIO1 purpose selection
10000064 GPIO2_MODE 32 GPIO2 purpose selection
10000068 MEMO1 32 Memory1
ch TE
1000006C MEMO2 32 Memory2
10000070 EXT_MEMO1 32 Extend Application #1
10000074 EXT_MEMO2 32 Extend Application #2
10000078 EXT_MEMO3 32 Extend Application #3
am IA
1000007C EXT_MEMO4 32 Extend Application #4
ad ED
3637544
10000000 CHIPID0_3 CHIP ID ASCII Character 0-3
D
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name CHIP_ID3 CHIP_ID2
M
Type RO RO
Reset 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name CHIP_ID1 CHIP_ID0
Type RO RO
Reset 0 1 0 1 0 1 0 0 0 1 0 0 1 1 0 1
Bit(s) Name Description
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Bit(s) Name Description
31:24 CHIP_ID3 ASCII CHIP Name Identification Character 3
EO
23:16 CHIP_ID2 ASCII CHIP Name Identification Character 2
US L
15:8 CHIP_ID1 ASCII CHIP Name Identification Character 1
7:0 CHIP_ID0 ASCII CHIP Name Identification Character 0
.tw IA
2020383
10000004 CHIPID4_7 CHIP ID ASCII Character 4-7
om NT
2
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name CHIP_ID7 CHIP_ID6
Type RO RO
Reset 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0
x.c E
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name CHIP_ID5 CHIP_ID4
Type RO RO
ne FID
Reset 0 0 1 1 1 0 0 0 0 0 1 1 0 0 1 0
Bit(s) Name Description
31:24 CHIP_ID7 ASCII CHIP Name Identification Character 3
23:16 CHIP_ID6 ASCII CHIP Name Identification Character 2
syn ON
15:8 CHIP_ID5 ASCII CHIP Name Identification Character 1
7:0 CHIP_ID4 ASCII CHIP Name Identification Character 0
@ C
0000000
10000008 EE_CFG E-Fuse Configuration
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
ien K
EE_CFG1
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ch TE
Name EE_CFG0
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
am IA
31:16 EE_CFG1 E-Fuse Configuration 1
15:0 EE_CFG0 E-Fuse Configuration 0
ad ED
0001010
1000000C CHIP_REV_ID Chip Revision Identification
2
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M
PK
Name G_I
D
Type RO
Reset 1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name VER_ID ECO_ID
Type RO RO
Reset 0 0 0 1 0 0 1 0
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Bit(s) Name Description
EO
16 PKG_ID Package ID
US L
0: DRQFN10x10-110
1: DRQFN12x12-156
11:8 VER_ID Chip Version ID
.tw IA
3:0 ECO_ID Chip ECO ID
om NT
0000010
10000010 SYSCFG0 System Configuration Register 0
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name TEST_CODE BS_SHADOW[8:4]
x.c E
Type RW RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ne FID
DB XT
TES TES
G_J AL_ DR
T_ EXT T_
TA FR AM
Name BS_SHADOW[3:0]
G_
MO
EQ
_B MO CHIP_MODE
_TY
DE_ G DE_
MO _SE PE
1 0
DE L
Type RO RO RO RO RO RO RO RO
syn ON
Reset 0 0 0 0 1 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:24 TEST_CODE Default value is from bootstrap and can be modified by software.
20:12 BS_SHADOW BS shadow register for last boot-up value (by manual boot-strap
@ C
SYSCFG1.PULL_EN)
Displays a backup copy of the last bootup value
8 DBG_JTAG_MODE JTAG for MIPS and Andes
ien K
1: Normal Boot-up
0: JTAG mode(MIPS & Andes)
7 TEST_MODE_1 Test Mode[1:0]
ch TE
6 XTAL_FREQ_SEL XTAL Frequency Selection
0: 25MHz DIP
1: 40MHz SMD (3225)
5 EXT_BG External BG Clock
am IA
0: BG clock from PMU
1: BG clock from the external pin
4 TEST_MODE_0 Test Mode[1:0]
0: SUTIF
ad ED
1: 3-wire SPI
3:1 CHIP_MODE Chip Mode
A vector to set chip function/test/debug modes in non-test/debug operation.
For more information see the Bootstrapping Pins Description in the datasheet
for this chip.
M
000: Boot from PLL (boot from SPI 3-Byte ADR)
001: Boot from PLL (boot from SPI 4-Byte ADR)
010: Boot from XTAL (boot from SPI 3-Byte ADR)
011: Boot from XTAL (boot from SPI 4-Byte ADR)
100: SCAN mode
101: IDDQ mode
110: Power-On mode
111: UTIF test mode
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Bit(s) Name Description
0 DRAM_TYPE DDR type
EO
[note] This DDR attribute is not valid for KN package.. ( 7628KN has DDR1
KGD)
US L
0: DDR2
1: DDR1
.tw IA
0000000
10000014 SYSCFG1 System Configuration Register 1
om NT
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PU
Name LL_
EN
x.c E
Type RW
Reset 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ne FID
Name
Type
Reset
Bit(s) Name Description
16 PULL_EN Internal Manual Boot-Strap
syn ON
1: enable
0: disable
0000000
@ C
10000018 TESTSTAT Firmware Test Status
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name TESTSTAT[31:16]
ien K
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ch TE
Name TESTSTAT[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
am IA
31:0 TESTSTAT Firmware Test Status register
NOTE: This register is reset only by a power-on reset.
ad ED
0000000
1000001C TESTSTAT2 Firmware Test Status 2
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M
Name TESTSTAT2[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name TESTSTAT2[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Bit(s) Name Description
31:0 TESTSTAT2 Firmware Test Status Register 2
EO
NOTE: This register is reset only by a power-on reset.
US L
.tw IA
ROM_STATU 0000000
10000028 Andes ROM Status
S 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
om NT
Type
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name STATUS
Type RO
x.c E
Reset 0 0 0 0 0 0 0 0
ne FID
Bit(s) Name Description
7:0 STATUS Andes ROM Status
0: Power-on default
1: ROM initialization done
2: Wifi driver loaded
syn ON
0020100
1000002C CLKCFG0 Clock Configuration Register 0
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INT
@ C
_CL
K_F
Name OSC_1US_DIV INT_CLK_FDIV
FR
AC[
ien K
4:4]
Type RW RW RW
Reset 0 0 0 0 0 0 0 1 0 0 0 0
ch TE
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PCI PE DIS CP CP
EN_
E_E RI_ _B U_F U_F
DIS BB
Name INT_CLK_FFRAC[3:0] REFCLK0_RATE XT_ CL BP_ RM RM
_N9 P_C
125 K_S SLE _B _XT
LK
M EL EP BP AL
am IA
Type RW RW RW RW RW RW RW RW RW
Reset 0 0 0 1 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
ad ED
29:24 OSC_1US_DIV Oscillator 1 usec Divider
Sets the maximum for the reference clock counter for either a 20 MHz or 40
MHz external XTAL input. The count increments each 1usec (indicating 1
MHz), up to the maximum, before resetting to zero. This counts the frequency
of an external XTAL. This count is used to output a 32 KHz frequency to the
M
REFCLK0 pin.
0: Automatically generates a 1 usec system tick regardless of whether XTAL
frequency is 20 MHz or 40 MHz.
39: Default value for an external 40 MHz XTAL.
19: Default value for an external 20 MHz XTAL.
Others: Manual mode for tick generation.
22:18 INT_CLK_FDIV Internal Clock Frequency Divider for I2S/PCM
The frequency divider used to generate the Fraction-N clock frequency.
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Bit(s) Name Description
Valid values range from 1 to 31.
EO
Fraction-N clock frequency = (INT_CLK_FFRAC/INT_CLK_FDIV)*PLL_FREQ
16:12 INT_CLK_FFRAC Internal Clock Fraction-N Frequency for I2S/PCM
US L
A parameter used in conjunction with INT_CLK_FDIV to generate the
Fraction-N clock frequency.
.tw IA
Valid values range from 0 to 31.
Fraction-N clock Frequency =
(INT_CLK_FFRAC/INT_CLK_FDIV)*PLL_FREQ
11:9 REFCLK0_RATE Output clock rate of reference Clock 0
om NT
7: CPUPLL Clock/8
6: Off
5: Internal Fraction-N_CLK/2 (I2S/PCM)
4: 48 MHz
3: 40 MHz
x.c E
2: 25 MHz
1: 12 MHz
0: Xtal clock(25/40 MHz by boot strap)
ne FID
7 DIS_N9 Pause Andes Execution
[Note] This bit is initialized by HW STRAP and can be changed by SW
afterwards.
1: Enable
0: default
5 PCIE_EXT_125M PCIe 125MHZ Clock Source
syn ON
1: Ext. 125MHz Source (EPHY)
0: PCIe PHY 125M
4 PERI_CLK_SEL Peripheral Clock Source Select
1: XTAL input
0: 40 MHz from BBP 480 MHz divided by 12
@ C
3 DIS_BBP_SLEEP BBPPLL Sleep Mode Control
1: Disable BBPPLL entering SLEEP mode
0: BBPPLL SLEEP mode
ien K
2 EN_BBP_CLK BBPPLL 480MHz Clock
1: BBPPLL Clock Enable
0: BBPPLL Clock Disable
ch TE
1 CPU_FRM_BBP CPU clock from BBPPLL
1: 480MHz BBPPLL
0: 580MHz CPUPLL
0 CPU_FRM_XTAL CPU clock from XTAL
am IA
[Note] This bit is initialized by HW STRAP and can be changed by SW
afterwards.
1: XTAL input
0: CPUPLL
ad ED
F69F7F0
10000030 CLKCFG1 Clock Configuration Register 1
0
M
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CR
PW SD MIP UP ET UA UA
YPT PCI SPI I2S I2C
M_ XC_ SC_ HY_ H_ RT2 RT1
O_ E_C _CL _CL _CL
Name CL CL
CL
CL
LK_
CL CL _CL _CL
K_E K_E K_E
K_E K_E K_E K_E K_E K_E K_E
K_E EN N N N
N N N N N N N
N
Type RW RW RW RW RW RW RW RW RW RW RW RW
Reset 1 1 1 1 1 1 1 1 1 1 1 1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
GD UA PC TIM
PIO MC INT
MA RT0 M_ ER_
_CL _CL _CL
EO
Name _CL
K_E
_CL CL
K_E K_E
CL
K_E K_E K_E K_E
N N N
N N N N
US L
Type RW RW RW RW RW RW RW
Reset 1 1 1 1 1 1 1
.tw IA
Bit(s) Name Description
31 PWM_CLK_EN PWM clock control
1: Clock Enable
om NT
0: Clock Disable
30 SDXC_CLK_EN SDXC clock control
1: Clock Enable
0: Clock Disable
x.c E
29 CRYPTO_CLK_EN AUX system tick counter clock control
1: Clock Enable
0: Clock Disable
ne FID
28 MIPSC_CLK_EN MIPS Counter clock control
1: Clock Enable
0: Clock Disable
26 PCIE_CLK_EN PCIE2 clock control
1: Clock Enable
0: Clock Disable
syn ON
25 UPHY_CLK_EN UPHY clock control
1: Clock Enable
0: Clock Disable
23 ETH_CLK_EN ETH clock control
@ C
1: Clock Enable
0: Clock Disable
20 UART2_CLK_EN UART2 clock control
1: Clock Enable
ien K
0: Clock Disable
19 UART1_CLK_EN UART1 clock control
ch TE
1: Clock Enable
0: Clock Disable
18 SPI_CLK_EN SPI clock control
1: Clock Enable
0: Clock Disable
am IA
17 I2S_CLK_EN I2S clock control
1: Clock Enable
0: Clock Disable
16 I2C_CLK_EN I2C clock control
ad ED
1: Clock Enable
0: Clock Disable
14 GDMA_CLK_EN GDMA clock control
1: Clock Enable
M
0: Clock Disable
13 PIO_CLK_EN PIO clock control
1: Clock Enable
0: Clock Disable
12 UART0_CLK_EN UART0 clock control
1: Clock Enable
0: Clock Disable
11 PCM_CLK_EN PCM clock control
OR
MediaTek Confidential © 2014 MediaTek Inc. Page 21 of 347
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Bit(s) Name Description
1: Clock Enable
EO
0: Clock Disable
10 MC_CLK_EN MC clock control
US L
1: Clock Enable
0: Clock Disable
.tw IA
9 INT_CLK_EN INT clock control
1: Clock Enable
0: Clock Disable
om NT
8 TIMER_CLK_EN TIMER clock control
1: Clock Enable
0: Clock Disable
x.c E
0400040
10000034 RSTCTL Reset Control Register
0
ne FID
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AU
CR
PW SD X_S EP ET UH UA UA
YPT PCI SPI I2S I2C
M_ XC_ TC HY_ H_ ST_ RT2 RT1
Name O_ E_R _RS _RS _RS
RS RS K_ RS RS RS _RS _RS
RS ST T T T
T T RS T T T T T
T
T
syn ON
Type RW RW RW RW RW RW RW RW RW RW RW RW RW
Reset 0 0 0 0 1 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GD UA PC TIM
PIO MC INT HIF WIF SPI SY
MA RT0 M_ ER_
Name _RS
_RS
_RS RS
_RS _RS
RS
_RS I_R S_R S_R
T T T T ST ST ST
@ C
T T T T
W1
Type RW RW RW RW RW RW RW RW RW RW
C
Reset 0 0 0 0 1 0 0 0 0 0 0
ien K
Bit(s) Name Description
ch TE
31 PWM_RST PWM reset control
1: Reset Assert
0: Reset Deassert
30 SDXC_RST SDXC reset control
1: Reset Assert
am IA
0: Reset Deassert
29 CRYPTO_RST Crypto engine reset control
1: Reset Assert
0: Reset Deassert
ad ED
28 AUX_STCK_RST AUX system tick counter clock control
1: Reset Assert
0: Reset Deassert
26 PCIE_RST PCIE reset control
M
1: Reset Assert
0: Reset Deassert
24 EPHY_RST EPHY reset control
1: Reset Assert
0: Reset Deassert
23 ETH_RST ETH reset control
1: Reset Assert
0: Reset Deassert
OR
MediaTek Confidential © 2014 MediaTek Inc. Page 22 of 347
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Bit(s) Name Description
22 UHST_RST USB PHY reset control
EO
1: Reset Assert
0: Reset Deassert
US L
20 UART2_RST UART2 reset control
1: Reset Assert
.tw IA
0: Reset Deassert
19 UART1_RST UART1 reset control
1: Reset Assert
om NT
0: Reset Deassert
18 SPI_RST SPI reset control
1: Reset Assert
0: Reset Deassert
17 I2S_RST I2S reset control
x.c E
1: Reset Assert
0: Reset Deassert
ne FID
16 I2C_RST I2C reset control
1: Reset Assert
0: Reset Deassert
14 GDMA_RST GDMA reset control
1: Reset Assert
0: Reset Deassert
syn ON
13 PIO_RST PIO reset control
1: Reset Assert
0: Reset Deassert
12 UART0_RST UART0 reset control
1: Reset Assert
@ C
0: Reset Deassert
11 PCM_RST PCM reset control
1: Reset Assert
ien K
0: Reset Deassert
10 MC_RST MC reset control
1: Reset Assert
ch TE
0: Reset Deassert
9 INT_RST INT reset control
1: Reset Assert
0: Reset Deassert
am IA
8 TIMER_RST TIMER reset control
1: Reset Assert
0: Reset Deassert
5 HIF_RST WIFI HIF reset control
ad ED
[Note] WPDMA reset control
1: Reset Assert
0: Reset Deassert
4 WIFI_RST WIFI reset control
[Note] This bit will reset Andes and initialize XTAL and BBPPLL again, MIPS
M
must carefully use it.
1: Reset Assert
0: Reset Deassert
3 SPIS_RST SPI Slave control
1: Reset Assert
0: Reset Deassert
0 SYS_RST Whole System Reset Control
[Note] Except for power-on CR, this bit reset the whole system include itself.
OR
MediaTek Confidential © 2014 MediaTek Inc. Page 23 of 347
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Bit(s) Name Description
1: Whole System Reset
EO
0: NA
US L
.tw IA
C003000
10000038 RSTSTAT Reset Status Register
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WD
om NT
WD
T2S
T2R
YS
Name ST WDTRSTPD
RS
O_
T_E
EN
N
Type RW RW RW
x.c E
Reset 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WD
ne FID
N9_
RS N9S
WD SW WD
T_T YS
Name ON
RS
RS
SYS RS
T_E RST T
9_E T
N
N
W1 W1 W1
Type RW RW
C C C
syn ON
Reset 0 0 0 0 0
Bit(s) Name Description
31 WDT2SYSRST_EN WDT reset apply to System Reset
Enables watchdog timeout to trigger a system reset.
@ C
1: Enable
0: Disable
30 WDT2RSTO_EN WDT reset apply to watch dog reset pin out.
1: Enable
ien K
0: Disable
29:16 WDTRSTPD Watchdog Reset Output Low Period
ch TE
Controls the WDT reset output low period. For example:
If the pin share mode was set correctly and WDT2RSTO_EN=1,
When WDTRSTPD= 0, you can see duration of 1 usec low on the WDT reset
output pin.
When WDTRSTPD= 3, you can see duration of 4 usec low on the WDT reset
am IA
output pin.
(unit: 1 usec)
9 WDRST_TON9_EN MIPS software reset or watch-dog reset apply to N9 subsys.
When this bit is set, MIPS can reset N9 or N9 is reset when MISP watch-dog
ad ED
reset happen.
0: disable
1: Enable
8 N9_WDRST_EN N9 watch-dog reset applies to MIPS subsys.
When N9 WDRST happens, N9 will also reset MIPS system.
M
0: disable
1: Enable
3 N9SYSRST N9 watch-dog reset occurred
This bit will be set if N9 wifisys is reset by its watch-dog mechanism. Writing a
'1' will clear this bit. Writing a '0' has not effect.
NOTE: This register is reset only by a power on reset.
0: Has no effect.
1: Clears this bit.
OR
MediaTek Confidential © 2014 MediaTek Inc. Page 24 of 347
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Bit(s) Name Description
2 SWSYSRST Software system reset occurred
EO
This bit will be set if software reset the chip by writing to the RSTSYS bit in
RSTCTL. Writing a '1' will clear this bit. Writing a '0' has not effect.
US L
NOTE: This register is reset only by a power on reset.
0: Has no effect.
.tw IA
1: Clears this bit.
1 WDRST Watchdog reset occurred
This bit will be set if the watchdog timer reset the chip. Writing a '1' will clear
this bit. Writing a '0' has not effect.
om NT
NOTE: This register is reset only by power-on reset.
0: Has no effect.
1: Clears this bit.
x.c E
001F001
1000003C AGPIO_CFG Analog GPIO Configuration
F
ne FID
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EP
HY_
Name EPHY_GPIO_AIO_EN
P0_
DIS
Type RW RW
Reset
syn ON
1 1 1 1 1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RE
RF_ I2S I2S I2S I2S
WL F_C
OL EIN _CL _W _SD _SD
ED_ LK
Name T_ T_S K_ S_A O_ I_AI
OD O_
MO EL AIO IO_ AIO O_
_EN AIO
@ C
DE _EN EN _EN EN
_EN
Type RW RW RW RW RW RW RW RW
Reset 0 0 0 1 1 1 1 1
ien K
Bit(s) Name Description
20:17 EPHY_GPIO_AIO_E EPHY P1 ~ P4 digital PAD selection (P1 ~ P4 Disable)
ch TE
N (note: When any bit of bit[20:17] is set to 1, P1 ~ P4 will be swtiched to digital
PADs together.)
0: Analog PAD
1: Digital PAD
16 EPHY_P0_DIS EPHY P0 Disable
am IA
0: Enable
1: Disable
12 RF_OLT_MODE Enable RF OLT mode
0: DIsable
ad ED
1: Enable
9 EINT_SEL Andes EINT Source
0: from W_UTIF
1: from GPIO [23:20]
M
8 WLED_OD_EN WLED Open-Drain
0: DIsable
1: Open-Drain
4 REF_CLKO_AIO_E REF Clock Output PAD Selection
N 0: Analog PAD
1: Digital PAD
3 I2S_CLK_AIO_EN I2S Clock PAD Selection
0: Analog PAD
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Bit(s) Name Description
1: Digital PAD
EO
2 I2S_WS_AIO_EN I2S WS PAD Selection
US L
0: Analog PAD
1: Digital PAD
1 I2S_SDO_AIO_EN I2S CSDO PAD Selection
.tw IA
0: Analog PAD
1: Digital PAD
0 I2S_SDI_AIO_EN I2S SDI PAD Selection
om NT
0: Analog PAD
1: Digital PAD
x.c E
0000000
10000040 N9_GPIO_INT Andes GPIO Interrupt
0
ne FID
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GPI
O_I
Name NT[
16:
16]
W1
Type
C
syn ON
Reset 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name GPIO_INT[15:0]
Type W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
@ C
Bit(s) Name Description
16:0 GPIO_INT Andes GPIO INT
ien K
N9_GPIO_MA 0001FFF
ch TE
10000044 Andes GPIO Mask
SK F
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GPI
O_
am IA
MA
Name SK[
16:
16]
Type RW
ad ED
Reset 1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name GPIO_MASK[15:0]
Type RW
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
M
Bit(s) Name Description
16:0 GPIO_MASK Andes GPIO MASK
5405040
10000060 GPIO1_MODE GPIO1 purpose selection
4
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RE PE
EO
FCL RS
PWM1_MO PWM0_MO UART2_M UART1_M
Name I2C_MODE K_ T_
DE DE ODE ODE
MO MO
US L
DE DE
Type RW RW RW RW RW RW RW
.tw IA
Reset 0 1 0 1 0 1 0 0 0 0 1 1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WD SPI
T_ _M UART0_M SPI_CS1_ SPIS_MOD GPIO_MO
Name MO OD
SD_MODE
ODE
I2S_MODE
MODE E DE
om NT
DE E
Type RW RW RW RW RW RW RW RW
Reset 0 0 0 1 0 0 0 0 0 0 0 1 0 0
Bit(s) Name Description
x.c E
31:30 PWM1_MODE PWM1 GPIO mode
3: SDXC D6
ne FID
2: UTIF[5]
1: GPIO
0: PWM ch1
29:28 PWM0_MODE PWM0 GPIO mode
3: SDXC D7
2: UTIF[4]
1: GPIO
syn ON
0: PWM ch0
27:26 UART2_MODE UART2 GPIO mode
3: SDXC D5/D4
2: PWM ch2/ch3
1: GPIO
@ C
0: UART-Lite #2
25:24 UART1_MODE UART1 GPIO mode
3: SW_R, SW_T
ien K
2: PWM ch0/ch1
1: GPIO
0: UART-Lite #1
ch TE
21:20 I2C_MODE I2C GPIO mode
2: S-UART (debug)
1: GPIO
0: I2C
18 REFCLK_MODE REFCLK GPIO mode
am IA
1: GPIO
0: REFCLK (12M)
16 PERST_MODE PCIe RESET GPIO mode
1: GPIO
ad ED
0: PCIe reset
14 WDT_MODE Watch dog timeout GPIO mode
1: GPIO
0: Watch dog
M
12 SPI_MODE SPI GPIO mode
1: GPIO
0: SPI
11:10 SD_MODE SDXC GPIO mode
3: Andes JTAG
2: UTIF[17:10]
1: GPIO
0: SDXC
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Bit(s) Name Description
9:8 UART0_MODE UART0 GPIO mode
EO
1: GPIO
0: UART-Lite #0
US L
7:6 I2S_MODE I2S GPIO mode
3: ANTSEL[5:2]
.tw IA
2: PCM
1: GPIO
0: I2S
5:4 SPI_CS1_MODE SPI CS1 GPIO mode
om NT
2: REFCLK
1: GPIO
0: SPI CS1
3:2 SPIS_MODE SPI Slave GPIO mode
x.c E
3: PWM CH0/1 and UART2
2: UTIF[3:0]
1: GPIO
ne FID
0: SPI Slave
1:0 GPIO_MODE GPIO mode
3: PCIe Reset
2: REFCLK (12M)
1: GPIO
0: GPIO
syn ON
0555055
10000064 GPIO2_MODE GPIO2 purpose selection
5
@ C
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P4_LED_K P3_LED_K P2_LED_K P1_LED_K P0_LED_K WLED_KN
Name
N_MODE N_MODE N_MODE N_MODE N_MODE _MODE
Type RW RW RW RW RW RW
Reset
ien K
0 1 0 1 0 1 0 1 0 1 0 1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P4_LED_A P3_LED_A P2_LED_A P1_LED_A P0_LED_A WLED_AN
Name N_MODE N_MODE N_MODE N_MODE N_MODE _MODE
ch TE
Type RW RW RW RW RW RW
Reset 0 1 0 1 0 1 0 1 0 1 0 1
Bit(s) Name Description
am IA
27:26 P4_LED_KN_MODE EPHY P4 LED GPIO mode
[Note] Only valid for MT7628KN.
3: JTAG (JTRST_N)
2: UTIF[6]
ad ED
1: GPIO
0: EPHY P4 LED
25:24 P3_LED_KN_MODE EPHY P3 LED GPIO mode
[Note] Only valid for MT7628KN.
3: JTAG (JTCLK)
M
2: UTIF[7]
1: GPIO
0: EPHY P3 LED
23:22 P2_LED_KN_MODE EPHY P2 LED GPIO mode
[Note] Only valid for MT7628KN.
3: JTAG (JTMS)
2: UTIF[8]
1: GPIO
0: EPHY P2 LED
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Bit(s) Name Description
21:20 P1_LED_KN_MODE EPHY P1 LED GPIO mode
EO
[Note] Only valid for MT7628KN.
3: JTAG (JTDI)
US L
2: UTIF[9]
1: GPIO
.tw IA
0: EPHY P1 LED
19:18 P0_LED_KN_MODE EPHY P0 LED GPIO mode
[Note] Only valid for MT7628KN.
3: JTAG(JTDO)
om NT
2: Reserved
1: GPIO
0: EPHY P0 LED
17:16 WLED_KN_MODE WLED GPIO mode
[Note] Only valid for MT7628KN.
x.c E
3: Reserved
2: Reserved
1: GPIO
ne FID
0: WLED
11:10 P4_LED_AN_MODE EPHY P4 LED GPIO mode
[Note] Only valid for MT7628AN.
3: JTAG (JTRST_N)
2: UTIF[6]
1: GPIO
syn ON
0: EPHY P4 LED
9:8 P3_LED_AN_MODE EPHY P3 LED GPIO mode
[Note] Only valid for MT7628AN.
3: JTAG (JTCLK)
2: UTIF[7]
@ C
1: GPIO
0: EPHY P3 LED
7:6 P2_LED_AN_MODE EPHY P2 LED GPIO mode
[Note] Only valid for MT7628AN.
ien K
3: JTAG (JTMS)
2: UTIF[8]
1: GPIO
ch TE
0: EPHY P2 LED
5:4 P1_LED_AN_MODE EPHY P1 LED GPIO mode
[Note] Only valid for MT7628AN.
3: JTAG (JTDI)
2: UTIF[9]
am IA
1: GPIO
0: EPHY P1 LED
3:2 P0_LED_AN_MODE EPHY P0 LED GPIO mode
[Note] Only valid for MT7628AN.
ad ED
3: JTAG(JTDO)
2: Reserved
1: GPIO
0: EPHY P0 LED
1:0 WLED_AN_MODE WLED GPIO mode
M
[Note] Only valid for MT7628AN.
3: Reserved
2: Reserved
1: GPIO
0: WLED
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
0000000
10000068 MEMO1 Memory1
EO
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
US L
Name MEMO1[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
.tw IA
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name MEMO1[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
om NT
Bit(s) Name Description
31:0 MEMO1 Memory1
x.c E
0000000
1000006C MEMO2 Memory2
ne FID
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name MEMO2[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
syn ON
Name MEMO2[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:0 MEMO2 Memory2
@ C
ien K
0000000
10000070 EXT_MEMO1 Extend Application #1
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ch TE
Name MEMO1[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name MEMO1[15:0]
am IA
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
ad ED
31:0 MEMO1 Extend Application #1
0000000
M
10000074 EXT_MEMO2 Extend Application #2
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name MEMO2[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name MEMO2[15:0]
Type RW
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
EO
Bit(s) Name Description
31:0 MEMO2 Extend Application #2
US L
.tw IA
0000000
10000078 EXT_MEMO3 Extend Application #3
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
om NT
Name MEMO3[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name MEMO3[15:0]
x.c E
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ne FID
Bit(s) Name Description
31:0 MEMO3 Extend Application #3
0000000
syn ON
1000007C EXT_MEMO4 Extend Application #4
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name MEMO4[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
@ C
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name MEMO4[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ien K
Bit(s) Name Description
ch TE
31:0 MEMO4 Extend Application #4
am IA
ad ED
OR M
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
2.3 Timer
EO
2.3.1 Features
US L
Independent 1usec tick pre-scale for each timer.
Independent interrupts for each timer.
.tw IA
Two general-purpose timers and a watchdog timer. Watchdog timer resets system on time-out.
Timer Modes
Periodic
In periodic mode, the timer counts down to zero from the limited value. An interrupt is generated when
om NT
the count is zero. After reaching zero, the limited value is reloaded into the timer and the timer counts
down again. A limited value of zero disables the timer.
Timeout
x.c E
In timeout mode, the timer counts down to zero from the limited value. An interrupt is generated when
the count is zero. In this mode, the ENABLE bit is reset when the timer reaches zero, stopping the
ne FID
counter.
Watchdog
In watchdog mode, the timer counts down to zero from the limited value. If the load value is not reloaded
or the timer is not disabled before the count is zero, the chip will be reset. When this occurs, every
register in the chip is reset except the watchdog reset status bit WDRST in the RSTSTAT register in the
syn ON
system control block; it remains set to alert firmware of the timeout event when it re-executes its
bootstrap.
2.3.2 Block Diagram
@ C
Timer 0
Limited Value Prescale
ien K
Counter Mode Control
Timer 0 Interrupt
ch TE
Timer 1 Interrupt
Watchdog Timer (Timer 1)
Interrupt
Control
Limited Value Prescale
am IA
Counter Mode Control
ad ED
Timer 2
Watchdog Timeout
Limited Value Prescale
APBus Signals
M
Counter Mode Control
Figure 2-2 Timer Block Diagram
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
2.3.3 Registers
EO
TIMER Changes LOG
US L
Revision Date Author Change Log
0.1 2012/8/24 Leon Chung Initialization
.tw IA
0.2 2013/12/10 Rick Ho 1. Modify T0CTL_REG Bit[4] to WO and add Bit[3] RO
2. Modify WDTCTL_REG Bit[4] to WO and add Bit[3]
RO 3. Modify T1CTL_REG Bit[4] to WO and add Bit[3]
RO
om NT
Module name: TIMER Base address: (+10000100h)
Address Name Widt Register Function
h
x.c E
10000100 TGLB_REG 32 RISC Global Control Register
ne FID
10000110 T0CTL_REG 32 RISC Timer 0 Control Register
10000114 T0LMT_REG 32 RISC Timer 0 Limit Register
10000118 T0_REG 32 RISC Timer 0 Register
10000120 WDTCTL_REG 32 Watch Dog Timer Control Register
10000124 WDTLMT_REG 32 Watch Dog Timer Limit Register
10000128 WDT_REG 32 Watch Dog Timer Register
syn ON
10000130 T1CTL_REG 32 RISC Timer 1 Control Register
10000134 T1LMT_REG 32 RISC Timer 1 Limit Register
10000138 T1_REG 32 RISC Timer 1 Register
@ C
0000000
10000100 TGLB_REG RISC Global Control Register
0
ien K
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RESV1[20:5]
Type RO
ch TE
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WD WD
T1R T0R T1I T0I
Name RESV1[4:0]
ST
TR
ST
RESV0
NT
TIN
NT
ST T
am IA
W1 W1 W1 W1 W1 W1
Type RO RO
C C C C C C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ad ED
Bit(s) Name Description
31:11 RESV1 Reserved
10 T1RST Timer 1 reset
1: to reset timer 1 to T1LMT value
M
9 WDTRST Watch dog timer reset
1: to reset watch dog timer to WDTLMT value
8 T0RST Timer 0 reset
1: to reset timer 0 to T0LMT value
7:3 RESV0 Reserved
2 T1INT Timer 1 interrupt status
1 WDTINT Watch dog timer interrupt status
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Bit(s) Name Description
0 T0INT Timer 0 interrupt status
EO
US L
0000000
.tw IA
10000110 T0CTL_REG RISC Timer 0 Control Register
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name T0PRES
Type RW
om NT
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
T0A
T0E T0A L_S
Name RESV2 RESV1 RESV0
N L TAT
US
x.c E
Type RO RW RO WO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s)
31:16
15:8
7
ne FID
Name
T0PRES
RESV2
T0EN
Description
Timer 0 count down tick pre-scale. Unit is 1u second.
Reserved
Timer 0 count down enable
syn ON
6:5 RESV1 Reserved
4 T0AL Timer 0 auto load enable
1: Enable
0: Disable
3 T0AL_STATUS Timer 0 auto load enable status
@ C
1: Enable
0: Disable
2:0 RESV0 Reserved
ien K
ch TE
0000000
10000114 T0LMT_REG RISC Timer 0 Limit Register
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RESV0
Type RO
am IA
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name T0LMT
Type RW
Reset
ad ED
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:16 RESV0 Reserved
15:0 T0LMT Timer 0 Limit.
M
When T0AL is set to 1, T0LMT will be loaded into timer 0 when timer 0 is
enabled or when count down to 0.
0000FFF
10000118 T0_REG RISC Timer 0 Register
F
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RESV0
EO
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
US L
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name T0
Type RW
.tw IA
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit(s) Name Description
31:16 RESV0 Reserved
om NT
15:0 T0 RISC down-count timer 0
x.c E
WDTCTL_RE 0000000
10000120 Watch Dog Timer Control Register
G 0
ne FID
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name WDTPRES
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WD
WD TAL
WD
syn ON
Name RESV2 TE RESV1
TAL
_ST RESV0
N AT
US
Type RO RW RO WO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
@ C
Bit(s) Name Description
31:16 WDTPRES Watch dog timer count down tick pre-scale. Unit is 1u second.
15:8 RESV2 Reserved
ien K
7 WDTEN Watch dog timer count down enable
6:5 RESV1 Reserved
ch TE
4 WDTAL Watch dog timer auto load enable
1: Enable
0: Disable
3 WDTAL_STATUS Watch dog timer auto load enable status
1: Enable
am IA
0: Disable
2:0 RESV0 Reserved
ad ED
WDTLMT_RE 0000000
10000124 Watch Dog Timer Limit Register
G 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M
Name RESV0
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name WDTLMT
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Bit(s) Name Description
31:16 RESV0 Reserved
EO
15:0 WDTLMT Watch dog timer Limit.
US L
When WDTAL is set to 1, WDTLMT will be loaded into watch dog timer when
watch dog timer is enabled or when count down to 0.
.tw IA
0000FFF
10000128 WDT_REG Watch Dog Timer Register
F
om NT
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RESV0
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
x.c E
Name WDT
Type RW
Reset
ne FID
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit(s) Name Description
31:16 RESV0 Reserved
15:0 WDT watch dog timer.
syn ON
0000000
10000130 T1CTL_REG RISC Timer 1 Control Register
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
@ C
Name T1PRES
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ien K
T1A
T1E T1A L_S
Name RESV2
N
RESV1
L TAT
RESV0
ch TE
US
Type RO RW RO WO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
am IA
31:16 T1PRES Timer 1 count down tick pre-scale. Unit is 1u second.
15:8 RESV2 Reserved
7 T1EN Timer 1 count down enable
ad ED
6:5 RESV1 Reserved
4 T1AL Timer 1 auto load enable
1: Enable
0: Disable
3 T1AL_STATUS Timer 1 auto load enable status
M
1: Enable
0: Disable
2:0 RESV0 Reserved
10000134 T1LMT_REG RISC Timer 1 Limit Register 0000000
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EO
Name RESV0
Type RO
US L
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
.tw IA
Name T1LMT
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
om NT
31:16 RESV0 Reserved
15:0 T1LMT Timer 1 Limit.
When T1AL is set to 1, T1LMT will be loaded into timer 1 when timer 1 is
enabled or when count down to 0.
x.c E
ne FID
0000FFF
10000138 T1_REG RISC Timer 1 Register
F
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RESV0
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
syn ON
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name T1
Type RW
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
@ C
Bit(s) Name Description
31:16 RESV0 Reserved
15:0 T1 RISC down-count timer 1
ien K
ch TE
am IA
ad ED
OR M
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
2.4 Interrupt Controller
EO
2.4.1 Registers
US L
CIRQ Changes LOG
.tw IA
Revision Date Author Change Log
0.1 2012/6/15 YuShu Xiao Initialization
om NT
Module name: CIRQ Base address: (+10000200h)
Address Name Widt Register Function
h
x.c E
IRQ Selection 0 Register
The registers allow the interrupt sources to be mapped onto
10000200 IRQ_SEL0 32
ne FID
interrupt requests IRQ.
When write data to this register, the FIQ_SEL register will be
update to the inverse data at the same time.
Reserved
10000204 IRQ_SEL1 32
Reserved
Reserved
10000208 IRQ_SEL2 32
Reserved
syn ON
Reserved
1000020C IRQ_SEL3 32
Reserved
FIQ Selection Register
The registers allow the interrupt sources to be mapped onto
1000026C FIQ_SEL 32 interrupt requests FIQ.
@ C
When write data to this register, the IRQ_SEL0 register will be
update to the inverse data at the same time.
IRQ Mask Register
10000270 IRQ_MASK 32 This register contains a mask bit for each interrupt line in IRQ
ien K
Controller.
FIQ Mask Register
ch TE
10000274 FIQ_MASK 32 This register contains a mask bit for each interrupt line in FIQ
Controller
IRQ_MASK_CL IRQ Mask Clear Register
10000278 R 32
This register is used to clear bits in IRQ Mask Register.
FIQ_MASK_CL FIQ Mask Clear Register
am IA
1000027C 32
R This register is used to clear bits in FIQ Mask Register.
IRQ_MASK_SE IRQ Mask Set Register
10000280 T 32
This register is used to set bits in the IRQ Mask Register.
FIQ Mask Set Register
ad ED
FIQ_MASK_SE
10000284 T 32
This register is used to set bits in the FIQ Mask Register.
IRQ End of Interrupt Register
This register provides a mean for software to relinquish and to
10000288 IRQ_EOI 32 refresh the interrupt controller.
Writing a 1 to a specific bit results in an IRQ End of Interrupt
M
command issued internally to the corresponding interrupt line.
FIQ End of Interrupt Register
This register provides a mean for software to relinquish and to
1000028C FIQ_EOI 32 refresh the interrupt controller.
Writing a 1 to a specific bit results in an FIQ End of Interrupt
command issued internally to the corresponding interrupt line.
IRQ Sensitive Register
10000290 IRQ_SENS 32
This register is used to set the IRQ interrupts as either edge or
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
level sensitive.
FIQ Sensitive Register
EO
10000294 FIQ_SENS 32 This register is used to set the FIQ interrupts as either edge or
level sensitive.
US L
Software Interrupt Register
Setting 1 to the specific bit position generates a software
10000298 INT_SOFT 32
.tw IA
interrupt for corresponding interrupt line before interrupt input
multiplex.
This register is used for debug purpose.
IRQ Status Register
1000029C IRQ_STAT 32 Reading this register will get the IRQ interrupt sources with
om NT
masking.
FIQ Status Register
100002A0 FIQ_STAT 32 Reading this register will get the FIQ interrupt sources with
masking.
Interrupt Pure Register
x.c E
100002A4 INT_PURE 32 Reading this register will get the pure interrupt sources without
masking.
ne FID
Interrupt Mode Selection Register
100002A8 INT_MSEL 32 This register is used to select the interrupt modes of
MIPS1004Kc.
0000000
syn ON
10000200 IRQ_SEL0 IRQ Selection 0 Register
1
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name IRQ0[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
@ C
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name IRQ0[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
ien K
Bit(s) Name Description
ch TE
31:0 IRQ0 IRQ Selection 0
0: Clear IRQ_SEL0 and Set FIQ_SEL
1: Set IRQ_SEL0 and Clear FIQ_SEL
am IA
0000000
10000204 IRQ_SEL1 Reserved
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ad ED
Name RESV[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RESV[15:0]
M
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:0 RESV Reserved
OR
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Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
0000000
10000208 IRQ_SEL2 Reserved
EO
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
US L
Name RESV[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
.tw IA
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RESV[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
om NT
Bit(s) Name Description
31:0 RESV Reserved
x.c E
0000000
1000020C IRQ_SEL3 Reserved
ne FID
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RESV[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
syn ON
Name RESV[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:0 RESV Reserved
@ C
ien K
0000000
1000026C FIQ_SEL FIQ Selection Register
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ch TE
Name FIQ[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name FIQ[15:0]
am IA
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
ad ED
31:0 FIQ FIQ Selection
0: Clear FIQ_SEL and Set IRQ_SEL0
1: Set FIQ_SEL and Clear IRQ_SEL0
M
0000000
10000270 IRQ_MASK IRQ Mask Register
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name IRQ0[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Name IRQ0[15:0]
Type RW
EO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
US L
Bit(s) Name Description
31:0 IRQ0 IRQ Mask
.tw IA
0: Interrupt is disabled
1: Interrupt is enabled
om NT
0000000
10000274 FIQ_MASK FIQ Mask Register
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name FIQ[31:16]
x.c E
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ne FID
Name FIQ[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:0 FIQ FIQ Mask
syn ON
0: Interrupt is disabled
1: Interrupt is enabled
@ C
IRQ_MASK_C 0000000
10000278 IRQ Mask Clear Register
LR 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ien K
Name IRQ0[31:16]
Type WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ch TE
Name IRQ0[15:0]
Type WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
am IA
Bit(s) Name Description
31:0 IRQ0 IRQ Mask Clear
0: No effect
1: Clear the corresponding MASK bit
ad ED
FIQ_MASK_C 0000000
1000027C FIQ Mask Clear Register
LR 0
M
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name FIQ[31:16]
Type WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name FIQ[15:0]
Type WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
OR
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Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Bit(s) Name Description
31:0 FIQ FIQ Mask Clear
EO
0: No effect
1: Clear the corresponding MASK bit
US L
.tw IA
IRQ_MASK_S 0000000
10000280 IRQ Mask Set Register
ET 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
om NT
Name IRQ0[31:16]
Type WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name IRQ0[15:0]
x.c E
Type WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ne FID
Bit(s) Name Description
31:0 IRQ0 IRQ Mask Set
0: No effect
1: Set the corresponding MASK bit
syn ON
FIQ_MASK_S 0000000
10000284 FIQ Mask Set Register
ET 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name FIQ[31:16]
@ C
Type WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
ien K
FIQ[15:0]
Type WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ch TE
Bit(s) Name Description
31:0 FIQ FIQ Mask Set
0: No effect
1: Set the corresponding MASK bit
am IA
0000000
ad ED
10000288 IRQ_EOI IRQ End of Interrupt Register
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name IRQ0[31:16]
Type W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
M
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name IRQ0[15:0]
Type W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:0 IRQ0 IRQ End of Interrupt
0: No service is currently in progress or pending
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Bit(s) Name Description
1: Interrupt request is in-service
EO
US L
0000000
1000028C FIQ_EOI FIQ End of Interrupt Register
.tw IA
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name FIQ[31:16]
Type W1C
om NT
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name FIQ[15:0]
Type W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
x.c E
Bit(s) Name Description
ne FID
31:0 FIQ FIQ End of Interrupt
0: No service is currently in progress or pending
1: Interrupt request is in-service
0000000
syn ON
10000290 IRQ_SENS IRQ Sensitive Register
1
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name IRQ0[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
@ C
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name IRQ0[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
ien K
Bit(s) Name Description
ch TE
31:0 IRQ0 IRQ Sensitive
0: Edge sensitivity with Pos-edge Edge
1: Level sensitivity with active High
am IA
0000000
10000294 FIQ_SENS FIQ Sensitive Register
1
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ad ED
Name FIQ[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name FIQ[15:0]
M
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Bit(s) Name Description
31:0 FIQ FIQ Sensitive
0: Edge sensitivity with Pos-edge Edge
1: Level sensitivity with active High
OR
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Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
EO
0000000
10000298 INT_SOFT Software Interrupt Register
0
US L
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name INT[31:16]
Type
.tw IA
RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name INT[15:0]
Type RW
om NT
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:0 INT Software Interrupt
x.c E
ne FID
0000000
1000029C IRQ_STAT IRQ Status Register
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name IRQ0[31:16]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
syn ON
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name IRQ0[15:0]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
@ C
31:0 IRQ0 IRQ Status
0: No interrupt request is generated
1: Interrupt request is pending
ien K
ch TE
0000000
100002A0 FIQ_STAT FIQ Status Register
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name FIQ[31:16]
am IA
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name FIQ[15:0]
Type RO
ad ED
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:0 FIQ FIQ Status
M
0: No interrupt request is generated
1: Interrupt request is pending
0000000
100002A4 INT_PURE Interrupt Pure Register
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Name INT[31:16]
Type RO
EO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
US L
Name INT[15:0]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
.tw IA
Bit(s) Name Description
31:0 INT Pure Interrupt
om NT
0: No interrupt source is asserted
1: Interrupt source is asserted
0000000
x.c E
100002A8 INT_MSEL Interrupt Mode Selection Register
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ne FID
Name RESV[30:15]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RESV[14:0] SEL
Type RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
syn ON
Bit(s) Name Description
31:1 RESV Reserved
0 SEL Interrupt Mode Selection
@ C
0: Compatibility & Vectored Interrupt Mode
1: External Interrupt Controller Mode
ien K
ch TE
am IA
ad ED
OR M
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
2.5 EMC Controller
EO
2.5.1 Regsiter
US L
EXT_MC_ARB Changes LOG
.tw IA
Revision Date Author Change Log
0.1 2012/10/5 Lancelot Initialization
0.2 2013/8/19 YS Xiao Modify to MT7628
om NT
Module name: EXT_MC_ARB Base address: (+10000300h)
Address Name Widt Register Function
h
x.c E
10000300 SDRAM_CFG0 32 SDRAM Configuration 0
10000304 SDRAM_CFG1 32 SDRAM Configuration 1
ne FID
ILL_ACC_ADD
10000308 R 32 Illegal Access Address Capture
1000030C ILL_ACC_TYPE 32 Illegal Access Type Capture
DDR_SELF_RE
10000310 FRESH 32 ODT and Self-Refresh Configuration
SDR_DDR_PW
syn ON
10000314 R_SAVE_CNT 32 Self-Refresh Time Count
10000320 DLL_DBG 32 DRAM DLL Debug Probe
10000340 DDR_CFG0 32 DDR1/DDR2 controller configuration 0 register
10000344 DDR_CFG1 32 DDR1/DDR2 controller configuration 1 register
@ C
10000348 DDR_CFG2 32 DDR1/DDR2 controller configuration 2 register
1000034C DDR_CFG3 32 DDR1/DDR2 controller configuration 3 register
10000350 DDR_CFG4 32 DDR1/DDR2 controller configuration 4 register
ien K
10000360 DDR_DQ_DLY 32 DDR1/DDR2 DQ delay control register
10000364 DDR_DQS_DLY 32 DDR1/DDR2 DQS delay control register
10000368 DDR_DLL_SLV 32 DDR1/DDR2 DLL slave control register
ch TE
1000036C DDR_DLL_MST 32 DDR1/DDR2 DLL master control register
10000380 MC_ARB_CFG 32 MC 2 to 1 arbiter setting
10000384 MC_AG_BW 32 MC Channel BW/QoS_Type/DueDate Setting
10000390 RB_DBG 32 RB Debug
am IA
10000394 RB_STATE 32 RB Debug State
10000398 RB_BW 32 RB Bandwidth
1000039C RB_LAT 32 RB Latency
ad ED
5192528
10000300 SDRAM_CFG0 SDRAM Configuration 0
2
M
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DIS
_CL CLK_SLE TW
Name TMRD TRFC RSV0 TCAS
K_ W R
GT
Type RW RW RW RW RW RO RW
Reset 0 1 0 1 0 0 0 1 1 0 0 1 0 0 1 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name TRAS RSV1 TRCD TRC RSV2 TRP
OR
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Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Type RW RO RW RW RO RW
Reset 0 1 0 1 0 0 1 0 1 0 0 0 0 0 1 0
EO
Bit(s) Name Description
US L
31 DIS_CLK_GT Disable Clock Gating
Disables clock gating of the SDR DRAM controller.
.tw IA
0: Enable
1: Disable
30:29 CLK_SLEW Reserved
28 TWR Write Recovery Time
om NT
(unit: system clock cycles - 1)
27:24 TMRD Load Mode Register command to any other command delay.
(unit: system clock cycles - 1)
23:20 TRFC Auto Refresh period
x.c E
(unit: system clock cycles - 1)
19:18 RSV0 Reserved
ne FID
17:16 TCAS CAS Latency Time
(unit: system clock cycles - 1)
15:12 TRAS The Active To Precharge command delay.
(unit: system clock cycles - 1)
11:10 RSV1 Reserved
syn ON
9:8 TRCD Active To Read or Write delay (RAS to CAS delay)
(unit: system clock cycles - 1)
7:4 TRC Active To Active command period
(unit: system clock cycles - 1)
3:2 RSV2 Reserved
@ C
1:0 TRP Precharge command period
(unit: system clock cycles - 1)
ien K
SDRAM_CFG 0112060
ch TE
10000304 SDRAM Configuration 1
1 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SD SD PW
RA RA RB PW R_ SD
M_I M_I C_ R_ DO RA
am IA
NUMROW
Name NIT NIT MA DO WN RSV0 M_ RSV1 NUMCOLS RSV2
S
_ST _D PPI WN _M WID
AR ON NG _EN OD TH
T E E
Type RW RO RW RW RW RO RW RO RW RO RW
ad ED
Reset 0 0 0 0 0 0 0 1 0 0 0 1 0 0 1 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name TREFR
Type RW
Reset 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0
M
Bit(s) Name Description
31 SDRAM_INIT_STAR SDRAM Initialization Start performs the SDRAM initialization sequence.
T Can not set this bit to 0 after initialization.
1: Start intialization
30 SDRAM_INIT_DON SDRAM Initialization Done
E Indicates the SDRAM has been initialized.
0: Not initialized.
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Bit(s) Name Description
1: Initialized.
EO
29 RBC_MAPPING RBC Mapping
US L
Selects the address mapping scheme.
0: {BANK ADDR, ROW ADDR, COL ADDR} address mapping scheme
1: {ROW ADDR, BANK ADDR, COL ADDR} address mapping scheme
.tw IA
28 PWR_DOWN_EN Power Down Enable
Enables the SDRAM precharge power-down mode to save standby power.
0: Disable
1: Enable
om NT
27 PWR_DOWN_MOD Power Down Mode
E 0: Precharge power down mode
1: Active power down
26:25 RSV0 Reserved
x.c E
24 SDRAM_WIDTH SDRAM Width
Selects the number of SDRAM data bus bits.
0: 16 bits
ne FID
1: 32 bits
23:22 RSV1 Reserved
21:20 NUMCOLS Number of Columns
Selects the number of column address bits.
0: 8 Column address bits
syn ON
1: 9 Column address bits (default)
2: 10 Column address bits
3 11 Column address bits
19:18 RSV2 Reserved
17:16 NUMROWS Number of Rows
@ C
Selects the number of row address bits.
0: 11 Row address bits
1: 12 Row address bits (default)
2: 13 Row address bits
ien K
3: 14 Row address bits
15:0 TREFR AUTO REFRESH period
(unit: SDRAM clock cycles - 1).
ch TE
ILL_ACC_AD 0000000
10000308 Illegal Access Address Capture
DR 0
am IA
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name ILL_ACC_ADDR[31:16]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ad ED
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name ILL_ACC_ADDR[15:0]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
M
Bit(s) Name Description
31:0 ILL_ACC_ADDR Illegal Access Address if any bus masters (including CPU) issue illegal
accesses (e.g. accesses to reserved memory space, or non-double-
word accesses to configuration registers), the address of the illegal
transaction is captured in this register.
An illegal interrupt is generated to indicate this exception.
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
ILL_ACC_TYP 0000000
1000030C Illegal Access Type Capture
EO
E 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
US L
ILL ILL
_IN _A
Name T_S CC RSV0 ILL_ACC_BSEL
.tw IA
TAT _W
US R
W1
Type C
RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
om NT
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RSV1 ILL_IID ILL_ACC_LEN
Type RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
x.c E
Bit(s) Name Description
31 ILL_INT_STATUS Illegal Access Interrupt Status
ne FID
Indicates whether the ilegal access interrupt is cleared or pending.
Read
0: Cleared
1: Pending
Write
1: Clear both the ILL_ACC_ADDR and ILL_ACC_TYPE registers and thus
clear ILL_INT_STATUS.
syn ON
30 ILL_ACC_WR Illegal Access Write
Indicates the illegal access is a read or a write.
0: A read access
1: A write access
29:20 RSV0 Reserved
@ C
19:16 ILL_ACC_BSEL Illegal Access Byte Select
Indicates which bytes were illegally accessed.
15:11 RSV1 Reserved
ien K
10:8 ILL_IID Illegal Access Initiator ID
Indicates the initiator ID of the illegal access.
ch TE
0: CPU
1: DMA
2: PPE
3: Ethernet PDMA Rx
4: Ethernet PDMA Tx
5: PCI/PCIE
am IA
6: Embedded WLAN MAC/BBP
7: USB
7:0 ILL_ACC_LEN Illegal Access Length
ad ED
Indicates the access size of the illegal access.
(unit: bytes)
DDR_SELF_R 0E12000
M
10000310 ODT and Self-Refresh Configuration
EFRESH 1
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RSV0 ODT_SRC_SEL ODT_OFF_DLY ODT_ON_DLY
Type RO RW RW RW
Reset 0 0 0 0 1 1 1 0 0 0 0 1 0 0 1 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SR_ SR SR
Name RSV1 RSV2
AU AC RE
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
TO_ K_ Q_
EN B B
EO
Type RO RW RO RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
US L
Bit(s) Name Description
.tw IA
31:28 RSV0 Reserved
27:24 ODT_SRC_SEL ODT Source Select
Sets the DDR pad ODT control source.
0: Dasavtive[0]
om NT
1: Dasavtive[1]
...
11: Dasavtive[11]
12: DQS_WINDOW
13: ODT_LOCAL
14: Always on
x.c E
15: Always off
23:20 ODT_OFF_DLY ODT Off Delay
ne FID
Sets the delay time of the ODT_OFF signal based on the ODT_ON signal.
0: 0 T
1: 0.5 T
2: 1.5 T
3: 2.5 T
...
15: 14.5 T
syn ON
19:16 ODT_ON_DLY ODT On Delay
Sets the delay time of the ODT_ON signal based on the ODT source signal.
0: 0 T
1: 1 T
2: 2 T
@ C
...
15: 15 T
15:5 RSV1 Reserved
ien K
4 SR_AUTO_EN Auto Self-Refresh Enable
Enables auto self-refresh for power saving.
0: Disable
ch TE
1: Enable
3:2 RSV2 Reserved
1 SRACK_B Self-Refresh Acknowledge Status
Indicates whether DDR2 is in self-refresh mode or has exited from self-
refresh mode.
am IA
When DDR2 changes from self-refresh mode to normal mode, it takes about
200 clock cycles.
0: The DDR2 is in self-refresh mode.
1: The DDR2 has exited from self-refresh mode.
ad ED
0 SRREQ_B Self-Refresh Request Control
Requests DDR2 to enter or exit self-refresh mode.
It is low active.
0: Enter self-refresh mode.
1: Exit self-refresh mode.
M
SDR_DDR_P
0003FFF
10000314 WR_SAVE_C Self-Refresh Time Count
F
NT
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name PD_CNT SR_TAR_CNT[23:16]
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Type RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1
EO
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name SR_TAR_CNT[15:0]
US L
Type RW
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
.tw IA
Bit(s) Name Description
31:24 PD_CNT Power Down Count
Counts the times self-refresh mode is entered
om NT
23:0 SR_TAR_CNT Self-Refresh Time Count
This counter is only referenced when the SDR (PWR_DOWN_EN ) or DDR
(SR_AUTO_EN) is set.
This counter measures the period SDR or DDR is in IDLE status.
When the IDLE period has reached the specified time period, the SDR or
x.c E
DDR automatically enter power-saving or selfrefresh mode.
Use the following equations to configure the counter.
DRAM_CLK_FREQ is PLL_CLK (600 MHz) divided by 3
ne FID
DDR: (SR_TAR_CNT * 256 + 255) / DRAM_CLK_FREQ
SDR: (SR_TAR_CNT * 256) / DRAM_CLK_FREQ
DDR reference table
200 MHz: (32'h03FFFF * 256 + 255) * 5 ns ~= 335 ms
SDRAM reference table
120 MHz: 32'h03FFFF * 256 * 8.3 ns ~= 560 ms
syn ON
0000000
10000320 DLL_DBG DRAM DLL Debug Probe
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
@ C
TDC_STA
Name RSV0 RSV1
BLE[5:4]
Type RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ien K
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AD
LL_
ch TE
LO
RS CURR_ST
Name TDC_STABLE[3:0] MST_DLY_SEL
V2 ATE
CK
_D
ON
E
Type RO RO RO RO RO
am IA
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:20 RSV0 Reserved
ad ED
19:18 RSV1 Reserved
17:12 TDC_STABLE ADLL master coarse-grain delay code
11:4 MST_DLY_SEL ADLL master final delay code
3 RSV2 Reserved
M
2:1 CURR_STATE ADLL controller FSM current state
0 ADLL_LOCK_DONE ADLL lock done signal
249B425
10000340 DDR_CFG0 DDR1/DDR2 controller configuration 0 register
B
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name T_RRD T_RAS T_RP T_RFC[5:3]
EO
Type RW RW RW RW
Reset 0 0 1 0 0 1 0 0 1 0 0 1 1 0 1 1
US L
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name T_RFC[2:0] T_REFI
Type RW RW
.tw IA
Reset 0 1 0 0 0 0 1 0 0 1 0 1 1 0 1 1
Bit(s) Name Description
31:28 T_RRD The minimum number of clock cycles from an active command to the
om NT
next active command for different banks (TRRD). For DDR2 devices, this
is required to be a minimum of 2 regardless of the cycle time.
27:23 T_RAS The number of clock cycles from an active command until a pre-charge
command is allowed. To obtain this value, one should divide the
minimum RAS# to pre-charge delay of the SDRAM by the clock cycle
x.c E
time (TRAS). The sum of Active-to-Pre-charge and Pre-charge-to-Active
should be equal or larger than active-to-active delay of the same ban
ne FID
(TRC)
22:19 T_RP The number of clock cycles needed for the SDRAM to recover from a
pre-charge command and ready to accept the next active command. To
obtain this value, one should divide the RAS# pre-charge time of the
SDRAM (TRP) by the clock cycle time. The sum of Active-to-Pre-charge
and Pre-charge-to-Active should be equal or larger than active-to-active
delay of the same bank (TRC)
syn ON
18:13 T_RFC Half the number of clock cycles needed for the SDRAM to recover from
a refresh signal to be ready to take the next command. To obtain this
value, one should divide the SDRAM row cycle time (TRFC) by the clock
cycle time.
12:0 T_REFI The number of clock cycles from one refresh command to the next
@ C
refresh command. To obtain this value, one should divide the periodic
refresh interval (TREFI) by the clock cycle time. The actual timing of
issuing a pre-charge command may be delayed by if the SDRAM is
processing a normal access. However, the delay is not accumulative so
ien K
there is no need to shorten the refresh interval to account for memory
access time. The non-accumulative refresh delay typically increases
memory bandwidth by a few percentage points.
ch TE
222E242
10000344 DDR_CFG1 DDR1/DDR2 controller configuration 1 register
4
am IA
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
US
ER_
DA IND_SDRAM_SIZ IND_SDRA
Name T_WTR T_RTP RSV0
ad ED
TA_ E M_WIDTH
WID
TH
Type RW RW RO RW RW RW
Reset 0 0 1 0 0 0 1 0 0 0 1 0 1 1 1 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M
TOTAL_SD
EXT_BAN
Name RAM_WID T_WR T_MRD T_RCD
K
TH
Type RW RW RW RW RW
Reset 0 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0
Bit(s) Name Description
31:28 T_WTR The write-to-read delay (TWTR) (last write data to the next read
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Bit(s) Name Description
command) as specified by the DDR2 data sheet
EO
27:24 T_RTP The read-to-pre-charge delay (TRTP) as specified by the DDR2 data
sheet. Note that this is a DDR2 requirement, and requires a minimum of
US L
2 cycles. These bits are ignored in DDR mode.
23:22 RSV0 Reserved
.tw IA
21 USER_DATA_WIDT Specify user data width
H 0: 32-bit
1: 64-bit
When user data width is 32-bit, total SDRAM width (bit[13:12]) must be 10.
om NT
NOTE: This system is always 64-bit. Please do not modify this setting.
20:18 IND_SDRAM_SIZE Specify individual SRAM size
000: Reserved
001: Individual SDRAM is 64 Mbit, (DDR only)
010: Individual SDRAM is 128 Mbit, (DDR only)
x.c E
011: Individual SDRAM is 256 Mbit.
100: Individual SDRAM is 512 Mbit.
ne FID
101: Individual SDRAM is 1 Gbit.
110: Individual SDRAM is 2 Gbit, (DDR2 only).
111: Reserved
17:16 IND_SDRAM_WIDT Specify individual SRAM data width
H 00: Reserved
01: 8-bit.
10: 16-bit.
syn ON
11: Reserved
15:14 EXT_BANK Specify bank/module configuration
00: 1 external bank, 1 module. (CS#[0])
01: 2 external bank, 1 module. (CS#[1:0]),
10: Reserved
@ C
11: 2 external banks, 2 modules. (CS#[1:0])
NOTE: only one CS pin.
13:12 TOTAL_SDRAM_WI This field specifies the total data width to the SDRAM. For example, if
DTH four 8-bit wide DDR2 chips are used in parallel to form a 32-bit DDR2
ien K
data width, this field should be defined as 11 to indicate a 32-bit width.
In this case, bit[17:16] should be defined as 01.
00: Reserved
ch TE
01: Reserved
10: 16-bit
11: 32-bit. Allowed only when user data width is 64-bit (bit21 is 1).
11:8 T_WR The clock cycles needed for the DDR to recover from a write command
and be able to accept a pre-charge command. To obtain this value,
am IA
divide the SDRAM write recovery time by the clock cycle time (TWR)
7:4 T_MRD The number of clock cycles after the setting of the mode registers in the
DDR and before the issue of the next command. To obtain this value,
divide the Mode Register Set Cycle time (TMRD) by the clock cycle time.
ad ED
3:0 T_RCD The number of clock cycles from an active command to a read/write
assertion. To obtain this value, divide the RAS# to CAS# delay time
(TRCD) by the clock cycle time.
M
43FFE44
10000348 DDR_CFG2 DDR1/DDR2 controller configuration 2 register
3
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DD
DQS0_GA DQS1_GA
RE R2_
Name TING_WIN TING_WIN RSV0[12:3]
GE MO
DOW DOW
DE
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Type RW RW RW RW RO
Reset 0 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1
EO
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BU
TES
US L
DLL RS
TM
Name RSV0[2:0] PD WR RE CAS_LATENCY T_T BURST_LENGTH
OD
SET YP
E
.tw IA
E
Type RO RW RW RW RW RW RO RW
Reset 1 1 1 0 0 1 0 0 0 1 0 0 0 0 1 1
Bit(s) Name Description
om NT
31 REGE This bit should be high when external registers are inserted in the
controller and address signals are sent between the controller and the
DDR SDRAM. One example of such instance is when register mode
SDRAM DIMM is used. This bit should be low when the control and
address signals from the controller is connected to the SDRAM without
x.c E
register delay.
30 DDR2_MODE This bit determines whether the memory controller is in DDR1 or DDR2
ne FID
mode.
0: DDR1 mode
1: DDR2 mode
29:28 DQS0_GATING_WI Controls the mask for the data strobe 0 (DQS0) window leading and
NDOW trailing edge.
00: Half extended cycle for the leading and trailing edge of DQS window
syn ON
(maximum window)
01: Only half extended cycle for leading edge of DQS window
10: Only half extended cycle for trailing edge of DQS window
11: No extended cycle for leading and trailing edge of DQS window (minimum
window)
27:26 DQS1_GATING_WI Controls the mask for the data strobe 1 DQS1 window leading and
@ C
NDOW trailing edge.
00: Half extended cycle for the leading and trailing edge of DQS window
(maximum window)
ien K
01: Only half extended cycle for leading edge of DQS window
10: Only half extended cycle for trailing edge of DQS window
11: No extended cycle for leading and trailing edge of DQS window (minimum
window)
ch TE
25:13 RSV0 Reserved
12 PD Active Memory Power Down Exit Time
0: Fast exit time (TXARD)
1: Slow exit time(TXARDS)
am IA
This bit is used for DDR2 only. This bit must be 0 for DDR1.
11:9 WR Auto Pre-charge Write Recovery (TDAL)
These bits must be 0 for DDR1.
ad ED
8 DLLRESET SDRAM Delay Locked Loop (DLL) Reset
0: Normal operation
1: Normal operation with DLL reset
7 TESTMODE Set SDRAM to run test mode.
0: Normal operation.
M
1: Test mode.
The user must keep this bit at 0 if SDRAM does not support TESTMODE bit.
6:4 CAS_LATENCY Specifies the number of the clock cycles from the assertion of a
read/write signal to the SDRAM until the first valid data on the output
from the SDRAM. The valid numbers are:
101: 1.5 for DDR1 or 5 for DDR2.
010: 2
110: 2.5 (DDR1 only)
011: 3
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Bit(s) Name Description
100: 4 (DDR2 only)
EO
3 BURST_TYPE This register is hardwired to 0 to indicate a sequential burst type.
US L
2:0 BURST_LENGTH Indicates the burst length of the read/write transaction.
010: 4 bursts
011: 8 bursts
.tw IA
NOTE:
1. A burst of 4 is not allowed when user data is 64-bit while SDRAM data is
16-bit.
2. A burst of 8 is allowed in all user/SDRAM data width combination.
om NT
3. Other values for burst length are not allowed.
FFFFE41
1000034C DDR_CFG3 DDR1/DDR2 controller configuration 3 register
x.c E
2
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ne FID
Name RSV0[18:3]
Type RO
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIS
Q_ _DI
RD RTT ADDITIVE_LATEN RTT
Name RSV0[2:0] OF FF_ OCD DS DLL
OS 1 CY 0
syn ON
F DQ
S
Type RO RW RW RW RW RW RW RW RW RW
Reset 1 1 1 0 0 1 0 0 0 0 0 1 0 0 1 0
Bit(s) Name Description
@ C
31:13 RSV0 Reserved
12 Q_OFF Output Buffer Disable
0: Enabled
ien K
1: Disabled
This bit is used for DDR2 only. This bit must be 0 for DDR1.
11 RDOS Redundant Data Strobe (DQS)
ch TE
This bit enables the redundant DQS function if supported by the SDRAM.
0: Disable
1: Enable
This bit is used for DDR2 only and must be 0 for DDR1.
10 DIS_DIFF_DQS Disable differential DQS
am IA
0: Enable
1: Disable
This bit is used for DDR2 only and must be 0 for DDR1.
ad ED
9:7 OCD Off-Chip Driver Impedance Calibration (OCD)
These bits support the OCD function if supported by the SDRAM. The value
programmed in these register bits will be programmed into the SDRAM at
EMR1 programming. Settings are vendor-dependant.
6 RTT1 Internal Termination Resistor (RTT) bit 1
M
Used together with bit 2 (RTT0) to control On-Die Termination (ODT).
Combine values for (RTT1, RTT0) to select ODT settings.
00: ODT disabled.
01: 75 ohm
10: 150 ohm
11: Reserved
This bit is used for DDR2 only and must be 0 for DDR1.
5:3 ADDITIVE_LATENC Additive Latency
Y 000: 0 cycle
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Bit(s) Name Description
001: 1 cycle
EO
010: 2 cycles
011: 3 cycles
US L
100: 4 cycles
101: 5 cycles
Others: Reserved
.tw IA
This bit is used for DDR2 only and must be 0 for DDR1.
2 RTT0 Internal Termination Resistor (RTT) bit 0
Used together with bit 6 (RTT1) to control ODT.
om NT
This bit is used for DDR2 only and must be 0 for DDR1.
1 DS SDRAM drive Strength
0: 100% drive strength.
1: 60% drive strength.
0 DLL SDRAM Delay Locked Loop (DLL) Enable
x.c E
0: Disable
1: Enable
10000350
Bit 31
ne FID
DDR_CFG4
30 29 28
DDR1/DDR2 controller configuration 4 register
27 26 25 24 23 22 21 20 19 18
FFFFFF
17
F4
16
syn ON
Name RSV0[26:11]
Type RO
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RSV0[10:0] FAW
Type RO RW
@ C
Reset 1 1 1 1 1 1 1 1 1 1 1 1 0 1 0 0
Bit(s) Name Description
ien K
31:5 RSV0 Reserved
4:0 FAW Four Activated Windows (FAW) Period
DDR2 devices impose a restriction in that no more than 4 ACTIVE commands
ch TE
may be issued in a given FAW period. To obtain this
value, one should divide the Four Bank Activate period (TFAW) of the DDR
by the clock cycle time. These bits are ignored in 4 bank devices.
am IA
0000888
10000360 DDR_DQ_DLY DDR1/DDR2 DQ delay control register
8
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ad ED
Name DQ_GROUP1_DELAY_SEL DQ_GROUP0_DELAY_SEL
Type RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DQ_GROUP1_DELAY_C DQ_GROUP1_DELAY_FI DQ_GROUP0_DELAY_C DQ_GROUP0_DELAY_FI
Name
M
OARSE_TUNING NE_TUNING OARSE_TUNING NE_TUNING
Type RW RW RW RW
Reset 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0
Bit(s) Name Description
31:24 DQ_GROUP1_DEL Force Data Group 1 (MD8 to MD15) Output Delay. Valid when
AY_SEL DQ_DLY_SEL_EN is 1.
bit7~4: for coarse-grain delay setting
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Bit(s) Name Description
bit3~0: for fine-grain delay setting
EO
23:16 DQ_GROUP0_DEL Force Data Group 0 (MD0 to MD7) Output Delay. Valid when
AY_SEL DQ_DLY_SEL_EN is 1.
US L
bit7~4: for coarse-grain delay setting
bit3~0: for fine-grain delay setting
.tw IA
15:12 DQ_GROUP1_DEL Data Group 1 (MD8 to MD15) Output Delay Coarse-Grain Tuning
AY_COARSE_TUNI 0x0 to 0x7: Decrease delay by 250 ps per step.
NG 0x8: Keep DLL delay.
0x9 to 0xF: Increase delay by 250 ps per step.
om NT
11:8 DQ_GROUP1_DEL Data Group 1 (MD8 to MD15) Output Delay Fine-Grain Tuning
AY_FINE_TUNING 0x0 to 0x7: Decrease delay by 30 ps per step.
0x8: Keep DLL delay.
0x9 to 0xF: Increase delay by 30 ps per step.
x.c E
7:4 DQ_GROUP0_DEL Data Group 0 (MD0 to MD7) Output Delay Coarse-Grain Tuning
AY_COARSE_TUNI 0x0 to 0x7: Decrease delay by 250 ps per step.
NG 0x8: Keep DLL delay.
ne FID
0x9 to 0xF: Increase delay by 250 ps per step.
3:0 DQ_GROUP0_DEL Data Group 0 (MD0 to MD7) Output Delay Fine-Grain Tuning
AY_FINE_TUNING 0x0 to 0x7: Decrease delay by 30 ps per step.
0x8: Keep DLL delay.
0x9 to 0xF: Increase delay by 30 ps per step.
syn ON
DDR_DQS_DL 0000888
10000364 DDR1/DDR2 DQS delay control register
Y 8
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
@ C
Name DQS1_DELAY_SEL DQS0_DELAY_SEL
Type RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ien K
DQS1_DELAY_COARSE DQS1_DELAY_FINE_TU DQS0_DELAY_COARSE DQS0_DELAY_FINE_TU
Name
_TUNING NING _TUNING NING
Type RW RW RW RW
ch TE
Reset 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0
Bit(s) Name Description
31:24 DQS1_DELAY_SEL Force Data Strobe 1 (MDQS1) Input Delay. Valid when
DQS_DLY_SEL_EN is 1
am IA
bit7~4: for coarse-grain delay setting
bit3~0: for fine-grain delay setting
23:16 DQS0_DELAY_SEL Force Data Strobe 0 (MDQS0) Input Delay. Valid when
DQS_DLY_SEL_EN is 1
ad ED
bit7~4: for coarse-grain delay setting
bit3~0: for fine-grain delay setting
15:12 DQS1_DELAY_COA Data Strobe 1 Input Delay Coarse-Grain Tuning
RSE_TUNING 0x0 to 0x7: Decrease delay by 250 ps per step.
M
0x8: Keep DLL delay.
0x9 to 0xF: Increase delay by 250 ps per step.
11:8 DQS1_DELAY_FIN Data Strobe 1 Input Delay Fine-Grain Tuning
E_TUNING 0x0 to 0x7: Decrease delay by 30 ps per step.
0x8: Keep DLL delay.
0x9 to 0xF: Increase delay by 30 ps per step.
7:4 DQS0_DELAY_COA Data Strobe 0 Input Delay Coarse-Grain Tuning
RSE_TUNING 0x0 to 0x7: Decrease delay by 250 ps per step.
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Bit(s) Name Description
0x8: Keep DLL delay.
EO
0x9 to 0xF: Increase delay by 250 ps per step.
3:0 DQS0_DELAY_FIN Data Strobe 0 Input Delay Fine-Grain Tuning
US L
E_TUNING 0x0 to 0x7: Decrease delay by 30 ps per step.
0x8: Keep DLL delay.
.tw IA
0x9 to 0xF: Increase delay by 30 ps per step.
om NT
DDR_DLL_SL 0000000
10000368 DDR1/DDR2 DLL slave control register
V 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RSV0[22:7]
Type RO
x.c E
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DLL
ne FID
_SL
DQ DQ
V_U
S_D _DL
PD
Name RSV0[6:0] RSV1 LY_ RSV2 Y_S
AT
SEL EL_
E_
_EN EN
MO
DE
syn ON
Type RO RW RO RW RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:9 RSV0 Reserved
@ C
8 DLL_SLV_UPDATE Set DLL slave update mode.
_MODE 0: Update delay code only when bank is activated.
1: Continous update
ien K
7:5 RSV1 Reserved
4 DQS_DLY_SEL_EN 0: DQS Input Delay decided by DLL.
1: Force DQS Input Delay by DQS0_DELAY_SEL / DQS1_DELAY_SEL.
ch TE
3:1 RSV2 Reserved
0 DQ_DLY_SEL_EN 0: DQ Output Delay decided by DLL.
1: Force DQ Output Delay by DQ_GROUP0_DELAY_SEL /
DQ_GROUP1_DELAY_SEL.
am IA
DDR_DLL_MS 0000000
1000036C DDR1/DDR2 DLL master control register
ad ED
T 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DLL DLL DLL
_M _M _M
AS_ AS_ AS_
M
Name RE RSV0 BY BY RSV1[11:4]
LO PA PA
CK SS_ SS_
_EN FD CD
Type RW RO RW RW RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RSV1[3:0] DLL_MAS_FIXED_FD RSV2 DLL_MAS_FIXED_CD
Type RO RW RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Bit(s) Name Description
EO
31 DLL_MAS_RELOCK Delayed Locked Loop (DLL) Master Relock Enable
US L
_EN 0: Disable relocking scheme.
1: Enable relocking scheme. DLL supports restarting locking from initial value
if DLL is not locked after waiting 512 cycles.
.tw IA
30:26 RSV0 Reserved
25 DLL_MAS_BYPASS DLL Bypass Fine Grain Delay
_FD 0: Fine-grain delay code is determined by DLL.
om NT
1: Fine-grain delay code is fixed by DLL_MAS_FIXED_FD.
24 DLL_MAS_BYPASS DLL Bypass Coarse Grain Delay
_CD 0: Coarse-grain delay code is determined by DLL
1: Coarse-grain delay code is fixed by DLL_MAS_FIXED_CD.
23:12 RSV1 Reserved
x.c E
11:8 DLL_MAS_FIXED_F DLL Fixed Fine Grain Delay
D Specifies the fine-grain delay. The effective range is 0 to 15. Each step is
ne FID
about 30 ps.
7:6 RSV2 Reserved
5:0 DLL_MAS_FIXED_ DLL Fixed Coarse Grain Delay
CD Specifies the coarse-grain delay. The delay = ((x-2)/4-1)*250 ps, the effective
range of x is 10 to 52.
syn ON
MC_ARB_CF 07FAC6
10000380 MC 2 to 1 arbiter setting
G 88
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
@ C
pre
clas
em trtc
Name RSV0 s_e cls_priority[23:16]
pt_ _en
n
en
ien K
Type RO RW RW RW RW
Reset 0 0 0 0 0 1 1 1 1 1 1 1 1 0 1 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ch TE
Name cls_priority[15:0]
Type RW
Reset 1 1 0 0 0 1 1 0 1 0 0 0 1 0 0 0
Bit(s) Name Description
am IA
31:27 RSV0 Reserved
26 preempt_en Preemption Enable
Request preemption, higher priority requestor may change current request
transaction
ad ED
0: Disable Preemption
1: Enable Preemption
25 trtc_en Two Rate Three Color Bandwidth (TRTC) Meter Enable
0: Disable TRTC
1: Enable TRTC
M
24 class_en QoS Classifier Enable
0: Disable CLASS
1: Enable CLASS
TRTC (0) CLASS (0) Round Robin
TRTC (0) CLASS (1) Fixed Priority
TRTC (1) CLASS (0) BW RR
TRTC (1) CLASS (1) QoS Arb
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Bit(s) Name Description
23:0 cls_priority Class Priority
EO
This field is used for class priority for second arbitration.
{BEy(3'd7), LCg(3'd6), BSy(3'd5), LSy(3'd4), BEg (3'd3), BSg (3'd2),
US L
LSg(3'd1), LCgd(3'd0)}
.tw IA
0110FF4
10000384 MC_AG_BW MC Channel BW/QoS_Type/DueDate Setting
0
om NT
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ag_ ag_ ag_qos_ty
Name RSV0 RSV1 ag_duedate
wr sel pe
Type WO RO RW RO RW RW
Reset 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0
x.c E
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name ag_pir ag_cir
Type RW RW
ne FID
Reset 1 1 1 1 1 1 1 1 0 1 0 0 0 0 0 0
Bit(s) Name Description
31 ag_wr Agent Write
0: Read
1: Write
syn ON
30:29 RSV0 Reserved
28 ag_sel DMA Agent Select
Selects a DMA agent to configure.
0: CPU (Rbus0)
1: DMA (Rbus1)
@ C
27:26 RSV1 Reserved
25:24 ag_qos_type Agent QoS Type
0: Latency critical
ien K
1: Latency sensitive (CPU)
2: Bandwidth sensitive (DMA)
3: Best Effort
ch TE
23:16 ag_duedate Due date for latency critical agent
(unit: system bus clock cycle
- system bus is 300 MHz or 225 MHz depending on bootstrap value.)
15:8 ag_pir Peak Information Rate for the Agent
am IA
The PIR is greater than or equal to the CIR. Bandwidth which exceeds PIR is
marked red.
0x00: 0 MB/s
0x01: 8 MB/s
...
ad ED
0x40: 512 MB/s
...
0xFF: 2040 MB/s (Max)
7:0 ag_cir Committed Information Rate for the Agent
M
Bandwidth which falls below the CIR is marked green. BW which exceeds the
CIR but is below the EIR is marked yellow.
0x00: 0 MB/s
0x01: 8 MB/s
...
0x40: 512 MB/s (default)
...
0xFF: 2040 MB/s (Max)
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
EO
0000000
10000390 RB_DBG RB Debug
0
US L
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RSV0[30:15]
Type
.tw IA
RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
rb_
Name RSV0[14:0]
sel
om NT
Type RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:1 RSV0 Reserved
x.c E
0 rb_sel RB channel select for debug message dump
10000394
Bit 31
ne FID
RB_STATE
30 29 28
RB Debug State
27 26 25 24 23 22 21 20 19 18
0000000
17
0
16
Name RSV0[20:5]
syn ON
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
rb_r
Name RSV0[4:0] rb_state rb_length
w
Type RO RO RO RO
@ C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
ien K
31:11 RSV0 Reserved
10 rb_rw RB channel RW
ch TE
9:8 rb_state RB channel State
2'b00: IDLE
2'b01: REQ
2'b10: ACK
2'b11: DATA
am IA
7:0 rb_length RB channel burst length (Byte)
ad ED
0000000
10000398 RB_BW RB Bandwidth
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
bw_ RS
Name rst V0
avg_bw peak_bw[9:6]
M
Type WO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name peak_bw[5:0] rb_bw
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Bit(s) Name Description
31 bw_rst Write 1 will reset BW values.
EO
30 RSV0 Reserved
US L
29:20 avg_bw Average BW (MB/S)
19:10 peak_bw Peak BW (MB/S)
.tw IA
9:0 rb_bw RB channel BW (MB/S)
om NT
0000000
1000039C RB_LAT RB Latency
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
lat_ RS
Name avg_lat peak_lat[9:6]
rst V0
x.c E
Type WO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ne FID
Name peak_lat[5:0] rd_lat
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31 lat_rst Write 1 will reset latency values
syn ON
30 RSV0 Reserved
29:20 avg_lat Average read latency (T)
19:10 peak_lat Peak read latency (T)
9:0 rd_lat RB channel read latency (T)
@ C
ien K
ch TE
am IA
ad ED
OR M
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
2.6 R-Bus Controller
EO
2.6.1 Features
US L
8 channel QoS Arbiter
Configurable Bandwidth and Duedate for each agent
.tw IA
QoS classifier can be programmed for RR, BW RR, Fixed Priority and QoS Arb
2.6.2 Block Diagram
om NT
N requestors (N=8) Req#0 Req#1 Req#2 Req#7
x.c E
ne FID
N Run time classifiers
(based on QoS type,
due date and color)
TRTC TRTC TRTC TRTC N Meters
N Classifiers
syn ON
Classifier Classifier Classifier Classifier
M(=8) run time
QoS types
M first
LCgd LSg ... LCg BEy stage arbiters
arbiter arbiter arbiter arbiter
@ C
(N ports/arbiter)
1 second
ien K
8 to 1 Strict priority arbiter
stage arbiter
(based on service priority)
(M ports)
ch TE
N-port QoS Arbiter
am IA
Figure 2-3 QoS Arbitration Block Diagram
ad ED
2.6.3 Regsiter
Rbus_Matrix_CTRL Changes LOG
Revision Date Author Change Log
M
0.1 2012/10/2 Lancelot Initialization
0.2 2013/1/3 Lancelot Add sleep count
0.2 2013/8/19 YS Xiao Modify to as MT7621's dma_ch_csr
Module name: Rbus_Matrix_CTRL Base address: (+10000400h)
Address Name Widt Register Function
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
h
DMA_ARB_CF
10000400 32 DMA 8 to 1 arbiter setting
EO
G
DMA_AG_BW_
US L
10000404 32 DMA Channel BW/QoS_Type/DueDate Setting
CFG
1000040C DMA_ROUTE 32 DMA Routing
.tw IA
10000410 DMA_MON_AG 32 DMA Monitor Agent Select
_SEL
10000414 DMA_STATE 32 DMA State
10000418 DMA_BW 32 DMA Bandwidth
om NT
1000041C DMA_LAT 32 DMA Latency
10000420 OCP_CFG0 32 OCP to Rbus configuration
10000424 OCP_CFG1 32 Read bypass write mask
10000430 R2P_MONITOR 32 Rbus to APbus monitor
x.c E
R2P_ERR_ADD
10000434 R 32 Rbus to APbus error address
ne FID
10000440 DYN_CFG0 32 Dynamic cpu/ocp frequency control
10000444 DYN_CFG1 32 CPU sleep step frequency control
10000448 DYN_CFG2 32 Dyn CFG Probe
1000044C DYN_CFG3 32 SI_Sleep Serial Counter Setting
10000450 DYN_CFG4 32 SI_Sleep Issue Count Counter
syn ON
10000454 DYN_CFG5 32 Sleep Time Counter for SI_Sleep
10000458 DYN_CFG6 32 Operation Time Counter for non SI_Sleep
@ C
DMA_ARB_C 04FAC6
10000400 DMA 8 to 1 arbiter setting
FG 88
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
pre
ien K
clas
em trtc
Name RSV0 s_e cls_priority[23:16]
pt_ _en
n
en
ch TE
Type RO RW RW RW RW
Reset 0 0 0 0 0 1 0 0 1 1 1 1 1 0 1 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name cls_priority[15:0]
Type RW
Reset
am IA
1 1 0 0 0 1 1 0 1 0 0 0 1 0 0 0
Bit(s) Name Description
31:27 RSV0 Reserved
ad ED
26 preempt_en Preemption Enable
Request preemption, higher priority requestor may change current request
transaction
0: Disable Preemption
1: Enable Preemption
M
25 trtc_en Two Rate Three Color Bandwidth (TRTC) Meter Enable
0: Disable TRTC
1: Enable TRTC
24 class_en QoS Classifier Enable
0: Disable CLASS
1: Enable CLASS
TRTC (0) CLASS (0) Round Robin
TRTC (0) CLASS (1) Fixed Priority
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Bit(s) Name Description
TRTC (1) CLASS (0) BW RR
EO
TRTC (1) CLASS (1) QoS Arb
23:0 cls_priority Class Priority
US L
This field is used for class priority for second arbitration.
{BEy(3'd7), LCg(3'd6), BSy(3'd5), LSy(3'd4), BEg (3'd3), BSg (3'd2),
.tw IA
LSg(3'd1), LCgd(3'd0)}
om NT
DMA_AG_BW 0220802
10000404 DMA Channel BW/QoS_Type/DueDate Setting
_CFG 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ag_ ag_qos_ty
Name wr
ag_sel RSV0
pe
ag_duedate
x.c E
W1
Type C
RW RO RW RW
Reset 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0
ne FID
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name ag_pir ag_cir
Type RW RW
Reset 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0
Bit(s) Name Description
syn ON
31 ag_wr Agent Write
0: Read
1: Write
30:28 ag_sel DMA Agent Select
Selects a DMA agent to configure.
@ C
0: SDXC
1: GDMA
2: SPI Slave/3-Wire SPI Slave/PUTIF
3: Switch
ien K
4: WLAN
5: PCIe
6: AES
ch TE
7: USB20
27:26 RSV0 Reserved
25:24 ag_qos_type Agent QoS Type
0: Latency critical
1: Latency sensitive
am IA
2: Bandwidth sensitive (default)
3: Best Effort
23:16 ag_duedate Due date for latency critical agent
ad ED
(unit: system bus clock cycle
- system bus is 300 MHz or 225 MHz depending on bootstrap value.)
15:8 ag_pir Peak Information Rate for the Agent
The PIR is greater than or equal to the CIR. Bandwidth which exceeds PIR is
marked red.
M
0x00: 0 MB/s
0x01: 4 MB/s
...
0x80: 512 MB/s (default)
...
0xFF: 1020 MB/s (Max)
7:0 ag_cir Committed Information Rate for the Agent
Bandwidth which falls below the CIR is marked green. BW which exceeds the
CIR but is below the EIR is marked yellow.
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Bit(s) Name Description
0x00: 0 MB/s
EO
0x01: 4 MB/s
...
US L
0x20: 128 MB/s (default)
...
0xFF: 1020 MB/s (Max)
.tw IA
0000000
om NT
1000040C DMA_ROUTE DMA Routing
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RSV0[30:15]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
x.c E
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
dm
ne FID
a_r
Name RSV0[14:0]
out
e
Type RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
syn ON
31:1 RSV0 Reserved
0 dma_route DMA routing
0: DMA will access to DRAM
1: DMA will access to CSR
@ C
DMA_MON_A 0000000
10000410 DMA Monitor Agent Select
ien K
G_SEL 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RSV0[28:13]
ch TE
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RSV0[12:0] dma_sel
Type RO RW
am IA
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:3 RSV0 Reserved
ad ED
2:0 dma_sel DMA Monitor Agent Select
Selects a DMA agent to dump DMA_STATE, DMA_BW and DMA_LAT's
content.
0: SDXC
1: GDMA
M
2: SPI Slave/3-Wire SPI Slave/PUTIF
3: Switch
4: WLAN
5: PCIe
6: AES
7: USB20
OR
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MT7628
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Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
0000000
10000414 DMA_STATE DMA State
EO
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
US L
Name RSV0[20:5]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
.tw IA
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
dm
Name RSV0[4:0] a_r dma_state dma_length
w
om NT
Type RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:11 RSV0 Reserved
x.c E
10 dma_rw DMA channel RW state
9:8 dma_state DMA channel State
ne FID
2'b00: IDLE
2'b01: REQ
2'b10: ACK
2'b11: DATA
7:0 dma_length DMA channel burst length (Byte) state
syn ON
0000000
10000418 DMA_BW DMA Bandwidth
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
@ C
bw_ RS
Name avg_bw peak_bw[9:6]
rst V0
Type WO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ien K
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name peak_bw[5:0] dma_bw
Type RO RO
ch TE
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31 bw_rst Write 1 will reset BW values.
am IA
30 RSV0 Reserved
29:20 avg_bw Average BW (MB/S)
19:10 peak_bw Peak BW (MB/S)
9:0 dma_bw DMA channel BW (MB/S)
ad ED
0000000
1000041C DMA_LAT DMA Latency
0
M
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
lat_ RS
Name rst V0
avg_lat peak_lat[9:6]
Type WO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name peak_lat[5:0] rd_lat
Type RO RO
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
EO
Bit(s) Name Description
31 lat_rst Write 1 will reset latency values
US L
30 RSV0 Reserved
.tw IA
29:20 avg_lat Average read latency (T)
19:10 peak_lat Peak read latency (T)
9:0 rd_lat DMA channel read latency (T)
om NT
0000000
10000420 OCP_CFG0 OCP to Rbus configuration
1
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
x.c E
Name RSV0[27:12]
Type RO
ne FID
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ocp
syn rbu rd_
_sy
c_ s_a byp
Name RSV0[11:0] nc_
met syn ass
cm
hod c _wr
d
Type RO RW RW RW RW
syn ON
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Bit(s) Name Description
31:4 RSV0 Reserved
@ C
3 sync_method OCP Synchronization Command Method
0: All empty (Wait until all FIFOs are empty )
1: CMD empty (Wait until the CMD FIFO is empty)
2 ocp_sync_cmd OCP Synchronization Command Method Enable
ien K
Remaps this RD CMD to address 0x0000_0000. Initiate DRAM control before
enabling this option.
0: Disable
ch TE
1: Enable
1 rbus_async Async Mode for RBUS
0: Set HW to switch between sync or async mode dynamically.
1: Force RBUS to A.sync mode.
am IA
0 rd_bypass_wr Read Bypass Write Enable
Allows read commands to bypass write commands for OCP_IF when the
address does not conflict.
0: Disable
ad ED
1: Enable
FFFFFF
10000424 OCP_CFG1 Read bypass write mask
M
FF
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name rd_bypass_wr_mask[31:16]
Type RW
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name rd_bypass_wr_mask[15:0]
Type RW
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Bit(s) Name Description
EO
31:0 rd_bypass_wr_mask Mask bit for read bypass write address
US L
.tw IA
R2P_MONITO 0000000
10000430 Rbus to APbus monitor
R 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
om NT
r2p
_in
Name RSV0
c_cl
r
W1
Type RO
C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
x.c E
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name r2p_err_cnt r2p_inc_cnt
ne FID
Type RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:17 RSV0 Reserved
16 r2p_inc_clr R2APB Interrupt Clear
syn ON
Write 1 to clear this interrupt.
15:10 r2p_err_cnt R2APB error counter
9:0 r2p_inc_cnt R2APB Interrupt Countdown Timer
Sets a delay timer which begins counting down when an R2P error is
detected.
@ C
When the timer reaches zero the R2P interrupt is then triggered.
10'b0000000000: Disable R2P monitoring
10'b0000000001: 20 us
10'b0000000010: 40 us
ien K
...
10'b1000000000: 40 ms
ch TE
R2P_ERR_AD 0000000
10000434 Rbus to APbus error address
DR 0
am IA
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name r2p_err_addr[31:16]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ad ED
Name r2p_err_addr[15:0]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
M
31:0 r2p_err_addr R2APB address record for previous error found
00030A0
10000440 DYN_CFG0 Dynamic cpu/ocp frequency control
1
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Name RSV0 cpu_ocp_ratio
Type RO RW
EO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
US L
Name RSV1 cpu_fdiv RSV2 cpu_ffrac
Type RO RW RO RW
Reset 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 1
.tw IA
Bit(s) Name Description
31:19 RSV0 Reserved
om NT
18:16 cpu_ocp_ratio CPU OCP Ratio
The ratio between the system bus frequency and the CPU frequency.
3'b011: SYS/CPU = 1/3
3'b100: SYS/CPU = 1/4 (Not used in MT7628)
15:12 RSV1 Reserved
x.c E
11:8 cpu_fdiv CPU Frequency Divider
The frequency divider is used to generate the CPU frequency. Valid values
ne FID
range from 1 to 15.
NOTE1: CPU_FDIV must be equaled to N*CPU_FFRAC(N is a integer
number) when rbus_async equal to 1'b0.
NOTE2: CPU_FDIV must be larger than or equal to CPU_FFRAC when
rbus_async equal to 1'b1.
7:4 RSV2 Reserved
syn ON
3:0 cpu_ffrac CPU Frequency Fractional
A parameter used in conjunction with the CPU frequency divider to determine
the CPU frequency. Input a value in the following equation to determine the
CPU frequency.
CPU frequency = PLL_FREQ*(CPU_FFRAC/CPU_FDIV)
NOTE: If the chip runs in USB OHCI mode, the OCP frequency cannot be
@ C
lower than 30 MHz. It means that
PLL_FREQ*(CPU_FFRAC/CPU_FDIV)/CPU_OCP_RATIO >= 30 MHz.
ien K
00230A0
10000444 DYN_CFG1 CPU sleep step frequency control
6
ch TE
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ste
slp RS
Name p_e RSV0 step_cnt step_ocp_ratio
_en V1
n
Type RW RW RO RW RO RO
am IA
Reset 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RSV2 step_fdiv RSV3 step_ffrac
Type RO RO RO RW
ad ED
Reset 0 0 0 0 1 0 1 0 0 0 0 0 0 1 1 0
Bit(s) Name Description
31 slp_en Sleep Mode Enable
Enables sleep mode when MIPS SI_Sleep is asserted.
M
0: Disable
1: Enable
Sleep Mode CPU Frequency = PLL_FREQ*(1/CPU_FDIV)
30 step_en Step Jump Enable
Enables step jump after MIPS exits sleep mode. The CPU will jump to the
normal frequency in increments defined by STEP_FFRAC.bit[4:0] of this
register.
0: Disable
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Bit(s) Name Description
1: Enable
EO
29:28 RSV0 Reserved
US L
27:20 step_cnt Step Counter
Sets the period of each step jump. When the counter counts down to zero,
the CPU clock automatically changes to the next step frequency.
.tw IA
The count period unit is 1 us.
19 RSV1 Reserved
18:16 step_ocp_ratio Step OCP Ratio (Fix to cpu_ocp_ratio)
om NT
The ratio between the system bus frequency and the CPU frequency.
3'b011: SYS/CPU = 1/3
3'b100: SYS/CPU = 1/4 (Not used in MT7628)
15:12 RSV2 Reserved
11:8 step_fdiv Step Frequency Divider (Fix to CPU_FDIV)
x.c E
The frequency divider is used to generate the CPU frequency after the CPU
exits from sleep mode and returns to normal operation. Valid values range
ne FID
from 1 to 15.
7:4 RSV3 Reserved
3:0 step_ffrac Step Frequency Fraction
The fractional size of the increment in CPU frequency after the CPU exits
from sleep mode and returns to normal operation. This step is only valid when
SLP_STEP_EN is enabled.
syn ON
FRAC_VALUE = PREVIOUS_FRAC_VALUE + STEP_FFRAC
CPU Frequency = (FRAC_VALUE/CPU_FDIV)*PLL_FREQ
00030A0
@ C
10000448 DYN_CFG2 Dyn CFG Probe
1
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
sa
ien K
me RS
Name RSV0 dfc_fsm RSV1
_fre V2
cpu_ocp_ratio
q
Type RO RO RO RO RO RO
ch TE
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RSV3 cpu_fdiv RSV4 cpu_ffrac
Type RO RO RO RO
Reset 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 1
am IA
Bit(s) Name Description
31:27 RSV0 Dynamic frequency controller's main FSM current state
ad ED
26:24 dfc_fsm Dynamic frequency controller's main FSM current state
23:21 RSV1 Reserved
20 same_freq Indicates that the SYS and DRAM clocks are on the same frequency.
19 RSV2 Reserved
M
18:16 cpu_ocp_ratio OCP ratio after changed frequency
15:12 RSV3 Reserved
11:8 cpu_fdiv CPU fdiv after changed frequency
7:4 RSV4 Reserved
3:0 cpu_ffrac CPU ffrac after changed frequency
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
0000000
1000044C DYN_CFG3 SI_Sleep Serial Counter Setting
EO
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
US L
si_s
lp_
Name cnt
RSV0 si_slp_time_unit[27:16]
.tw IA
_en
Type RW RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
om NT
Name si_slp_time_unit[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
x.c E
31 si_slp_cnt_en SI_Sleep Serial Counter Enable
30:28 RSV0 Reserved
ne FID
27:0 si_slp_time_unit SI_Sleep Time Counter unit
28'h0000000: count per 1us
28'h0000001: count per 2us
28'h0000002: count per 3us
...
28'hfffffff: count per 268435456us
syn ON
0000000
10000450 DYN_CFG4 SI_Sleep Issue Count Counter
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
@ C
Name si_slp_cnt[31:16]
Type W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ien K
Name si_slp_cnt[15:0]
Type W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ch TE
Bit(s) Name Description
31:0 si_slp_cnt SI_Sleep Issue Count Counter
Write to this register will clear the counter value.
am IA
0000000
10000454 DYN_CFG5 Sleep Time Counter for SI_Sleep
ad ED
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name si_slp_time_unit_cnt[31:16]
Type W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
M
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name si_slp_time_unit_cnt[15:0]
Type W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:0 si_slp_time_unit_cnt Sleep Time Counter for SI_Sleep
Finally, CPU in SI_Sleep time is "si_slp_time_unit_cnt*si_slp_time_unit(us)".
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Bit(s) Name Description
Write to this register will clear the counter value.
EO
US L
0000000
10000458 DYN_CFG6 Operation Time Counter for non SI_Sleep
.tw IA
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name si_opt_time_unit_cnt[31:16]
Type W1C
om NT
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name si_opt_time_unit_cnt[15:0]
Type W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
x.c E
Bit(s) Name Description
ne FID
31:0 si_opt_time_unit_cnt Operation Time Counter for non SI_Sleep
Finally, CPU in non SI_Sleep time is
"si_opt_time_unit_cnt*si_slp_time_unit(us)".
Write to this register will clear the counter value.
syn ON
@ C
ien K
ch TE
am IA
ad ED
OR M
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
2.7 MIPS CNT
EO
2.7.1 Registers
US L
MIPS_CNT Changes LOG
.tw IA
Revision Date Author Change Log
0.1 2013/1/14 YuShu Xiao Initialization
om NT
Module name: MIPS_CNT Base address: (+10000500h)
Address Name Widt Register Function
h
x.c E
STCK_CNT_CF
10000500 G 32 MIPS Configuration
ne FID
MIPS Compare
Sets the cutoff point for the free run counter (MIPS counter). If
10000504 CMP_CNT 32 the free run counter equals the compare counter, then the timer
circuit generates an interrupt. The interrupt remains active until
the compare counter is written again.
MIPS Counter
10000508 CNT 32 The MIPS counter (free run counter) increases by 1 every 20 us
syn ON
(50 KHz). The counter continues to count until it reaches the
value loaded into CMP_CNT.
STCK_CNT_C 0000000
@ C
10000500 MIPS Configuration
FG 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RESV[29:14]
ien K
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ch TE
EXT
CN
_ST
Name RESV[13:0] T_E
K_E
N
N
Type RO RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
am IA
Bit(s) Name Description
31:2 RESV
ad ED
1 EXT_STK_EN External System Tick Enable - Selects the system tick source.
0: Use the MIPS internal timer interrupts.
1: Use the external timer interrupt from an external MIPS counter.
0 CNT_EN Counter Enable - Enable the free run counter (MIPS counter).
0: Disable
M
1: Enable
0000000
10000504 CMP_CNT MIPS Compare
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RESV
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
EO
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name CMP_CNT
US L
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
.tw IA
Bit(s) Name Description
31:16 RESV
15:0 CMP_CNT Compare Count
om NT
0000000
10000508 CNT MIPS Counter
0
x.c E
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RESV
Type
ne FID
RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name CNT
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
syn ON
Bit(s) Name Description
31:16 RESV
15:0 CNT MIPS Counter
@ C
ien K
ch TE
am IA
ad ED
OR M
MediaTek Confidential © 2014 MediaTek Inc. Page 75 of 347
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
2.8 General Purpose IO
EO
2.8.1 Features
US L
Parameterized numbers of independent inputs, outputs, and inouts
Independent polarity controls for each pin
.tw IA
Independently masked edge detect interrupt on any input transition
2.8.2 Block Diagram
om NT
gpio_top cfg_ctrl[95:0] gpio_oe[95:0]
x96
gpio_reg cfg_data[95:0] gpio_control gpio_out[95:0]
x.c E
PBus signals
ne FID
Configuration
gpio_in[95:0]
Registers
gpio_interrupt
gpio_int I/O PAD
syn ON
Figure 2-4 Programmable I/O Block Diagram
@ C
ien K
ch TE
am IA
ad ED
OR M
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
EO
2.8.3 GPIO pin mapping
PAD Name Function 0 Function 1 Function 2 Function 3 strap pmux_group GPIO
US L
PAD_I2S_SDI i2ssdi (I) gpio (I/O) pcmdrx (I) antsel[5] (O) i2s_gpio_psel[2:0] 0
PAD_I2S_SDO i2ssdo (O) gpio (I/O) pcmdtx (O) antsel[4] (O) 0 i2s_gpio_psel[2:0] 1
.tw IA
PAD_I2S_WS i2sws(I/O) gpio (I/O) pcmclk (I/O) antsel[3] (O) i2s_gpio_psel[2:0] 2
PAD_I2S_CLK i2sclk (I/O) gpio (I/O) pcmfs (I/O) antsel[2] (O) i2s_gpio_psel[2:0] 3
PAD_I2C_SCLK i2c_sclk (I/O) gpio (I/O) sutif_txd (O) ext_bgclk (I) i2c_gpio_psel[2:0] 4
PAD_I2C_SD i2c_sd (I/O) gpio (I/O) sutif_rxd (I) i2c_gpio_psel[2:0] 5
om NT
PAD_SPI_CS1 spi_cs1 (O) gpio (I/O) co_clko (O) 1 spi_cs1_psel[2:0] 6
PAD_SPI_CLK spi_clk (O) gpio (I/O) 2 spi_gpio_psel[1:0] 7
PAD_SPI_MOSI spi_mosi (I/O) gpio (I/O) 3 spi_gpio_psel[1:0] 8
PAD_SPI_MISO spi_miso (I/O) gpio (I/O) spi_gpio_psel[1:0] 9
PAD_SPI_CS0 spi_cs0 (O) gpio (I/O) spi_gpio_psel[1:0] 10
x.c E
PAD_GPIO0 gpio (I/O) gpio (I/O) co_clko (O) perst_n (O) 4 gpio_psel[2:0] 11
PAD_TXD0 txd0 (O) gpio (I/O) 5 uart0_gpio_psel[2:0] 12
ne FID
PAD_RXD0 rxd0 (I) gpio (I/O) uart0_gpio_psel[2:0] 13
PAD_MDI_TP_P1 spis_cs (I) gpio (I/O) w_utif[0] (I/O) pwm_ch0 (O) spis_gpio_psel[2:0] 14
PAD_MDI_TN_P1 spis_clk (I) gpio (I/O) w_utif[1] (I/O) pwm_ch1 (O) spis_gpio_psel[2:0] 15
PAD_MDI_RP_P1 spis_miso (O) gpio (I/O) w_utif[2] (I/O) txd2 (O) spis_gpio_psel[2:0] 16
PAD_MDI_RN_P1 spis_mosi (I) gpio (I/O) w_utif[3] (I/O) rxd2 (I) spis_gpio_psel[2:0] 17
PAD_MDI_RP_P2 pwm_ch0 (O) gpio (I/O) w_utif[4] (I/O) sd_d7 (I/O) pwm0_gpio_psel[2:0] 18
syn ON
PAD_MDI_RN_P2 pwm_ch1 (O) gpio (I/O) w_utif[5] (I/O) sd_d6 (I/O) pwm1_gpio_psel[2:0] 19
PAD_MDI_TP_P2 txd2 (O) gpio (I/O) pwm_ch2 (O) sd_d5 (I/O) uart2_gpio_psel[2:0] 20
PAD_MDI_TN_P2 rxd2 (I) gpio (I/O) pwm_ch3 (O) sd_d4 (I/O) uart2_gpio_psel[2:0] 21
PAD_MDI_TP_P3 sd_wp (I) gpio (I/O) w_utif[10] (I/O) w_dbgin (I) sd_gpio_psel[2:0] 22
PAD_MDI_TN_P3 sd_cd (I) gpio (I/O) w_utif[11] (I/O) w_dbgack (O) sd_gpio_psel[2:0] 23
@ C
PAD_MDI_RP_P3 sd_d1 (I/O) gpio (I/O) w_utif[12] (I/O) w_jtclk (I) sd_gpio_psel[2:0] 24
PAD_MDI_RN_P3 sd_d0 (I/O) gpio (I/O) w_utif[13] (I/O) w_jtdi (I) sd_gpio_psel[2:0] 25
PAD_MDI_RP_P4 sd_clk (I/O) gpio (I/O) w_utif[14] (I/O) w_jtdo (O) sd_gpio_psel[2:0] 26
ien K
PAD_MDI_RN_P4 sd_cmd (I/O) gpio (I/O) w_utif[15] (I/O) dbg_uart_txd (O) sd_gpio_psel[2:0] 27
PAD_MDI_TP_P4 sd_d3 (I/O) gpio (I/O) w_utif[16] (I/O) w_jtms (I) sd_gpio_psel[2:0] 28
PAD_MDI_TN_P4 sd_d2 (I/O) gpio (I/O) w_utif[17] (I/O) w_jtrst_n (I) sd_gpio_psel[2:0] 29
ch TE
PAD_EPHY_LED4_K ephy_led4_k (O) gpio (I/O) w_utif_k[6] (I/O) jtrstn_k (I) p4_led_kn_psel[2:0] 30
PAD_EPHY_LED3_K ephy_led3_k (O) gpio (I/O) w_utif_k[7] (I/O) jtclk_k (I) p3_led_kn_psel[2:0] 31
PAD_EPHY_LED2_K ephy_led2_k (O) gpio (I/O) w_utif_k[8] (I/O) jtms_k (I) p2_led_kn_psel[2:0] 32
PAD_EPHY_LED1_K ephy_led1_k (O) gpio (I/O) w_utif_k[9] (I/O) jtdi_k (I) p1_led_kn_psel[2:0] 33
am IA
PAD_EPHY_LED0_K ephy_led0_k (O) gpio (I/O) jtdo_k (I/O) p0_led_kn_psel[2:0] 34
PAD_WLED_K wled_k (I/O) gpio (I/O) wled_kn_psel[2:0] 35
PAD_PERST_N perst_n (O) gpio (I/O) 6 prest_gpio_psel[1:0] 36
PAD_CO_CLKO co_clko (O) gpio (I/O) 7 rclk_gpio_psel[1:0] 37
ad ED
PAD_WDT_RST_N wdt (I/O) gpio (I/O) wdt_gpio_psel[1:0] 38
PAD_EPHY_LED4_N ephy_led4_n (O) gpio (I/O) w_utif_n[6] (I/O) jtrstn_n (I) p4_led_gpio_psel[2:0] 39
PAD_EPHY_LED3_N ephy_led3_n (O) gpio (I/O) w_utif_n[7] (I/O) jtclk_n (I) p3_led_gpio_psel[2:0] 40
PAD_EPHY_LED2_N ephy_led2_n (O) gpio (I/O) w_utif_n[8] (I/O) jtms_n (I) p2_led_gpio_psel[2:0] 41
PAD_EPHY_LED1_N ephy_led1_n (O) gpio (I/O) w_utif_n[9] (I/O) jtdi_n (I) p1_led_gpio_psel[2:0] 42
M
PAD_EPHY_LED0_N ephy_led0_n (O) gpio (I/O) jtdo_n (I/O) p0_led_gpio_psel[2:0] 43
PAD_WLED_N wled_n (I/O) gpio (I/O) wled_gpio_psel[2:0] 44
PAD_TXD1 txd1 (O) gpio (I/O) pwm_ch0 (O) antsel[1] (O) 8 uart1_gpio_psel[2:0] 45
PAD_RXD1 rxd1 (I) gpio (I/O) pwm_ch1 (O) antsel[0] (O) uart1_gpio_psel[2:0] 46
2.8.4 Register
OR
MediaTek Confidential © 2014 MediaTek Inc. Page 77 of 347
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
GPIO Changes LOG
EO
Revision Date Author Change Log
0.1 2012/6/21 YuShu Xiao Initialization
US L
.tw IA
Module name: GPIO Base address: (+10000600h)
Address Name Widt Register Function
h
om NT
GPIO0 to GPIO31 direction control register
These direction control registers are used to select the data
10000600 GPIO_CTRL_0 32 direction of the GPIO pin.
The value driven onto the GPIO pins, are controlled by the
GPIO_POL_x, and GPIO_DATA_x registers.
x.c E
GPIO32 to GPIO63 direction control register
These direction control registers are used to select the data
10000604 GPIO_CTRL_1 32 direction of the GPIO pin.
ne FID
The value driven onto the GPIO pins, are controlled by the
GPIO_POL_x, and GPIO_DATA_x registers.
GPIO64 to GPIO95 direction control register
These direction control registers are used to select the data
10000608 GPIO_CTRL_2 32 direction of the GPIO pin.
The value driven onto the GPIO pins, are controlled by the
GPIO_POL_x, and GPIO_DATA_x registers.
syn ON
GPIO0 to GPIO31 polarity control register
10000610 GPIO_POL_0 32 These polarity control registers are used to control the polarity of
the data is driven on or read from the GPIO pin.
GPIO32 to GPIO63 polarity control register
10000614 GPIO_POL_1 32 These polarity control registers are used to control the polarity of
@ C
the data is driven on or read from the GPIO pin.
GPIO64 to GPIO95 polarity control register
10000618 GPIO_POL_2 32 These polarity control registers are used to control the polarity of
the data is driven on or read from the GPIO pin.
ien K
GPIO0 to GPIO31 data register
10000620 GPIO_DATA_0 32 These data registers store current GPIO data value for GPIO
input mode, or output driven value for GPIO output mode.
ch TE
Bit position stand for correspondent GPIO pin.
GPIO32 to GPIO63 data register
10000624 GPIO_DATA_1 32 These data registers store current GPIO data value for GPIO
input mode, or output driven value for GPIO output mode.
Bit position stand for correspondent GPIO pin.
am IA
GPIO64 to GPIO95 data register
10000628 GPIO_DATA_2 32 These data registers store current GPIO data value for GPIO
input mode, or output driven value for GPIO output mode.
Bit position stand for correspondent GPIO pin.
ad ED
GPIO0 to GPIO31 data set register
10000630 GPIO_DSET_0 32 These data set registers are used to set bits in the
GPIO_DATA_x registers.
GPIO32 to GPIO63 data set register
10000634 GPIO_DSET_1 32 These data set registers are used to set bits in the
M
GPIO_DATA_x registers.
GPIO64 to GPIO95 data set register
10000638 GPIO_DSET_2 32 These data set registers are used to set bits in the
GPIO_DATA_x registers.
GPIO0 to GPIO31 data clear register
10000640 GPIO_DCLR_0 32 These data set registers are used to clear bits in the
GPIO_DATA_x registers.
10000644 GPIO_DCLR_1 32 GPIO32 to GPIO63 data clear register
OR
MediaTek Confidential © 2014 MediaTek Inc. Page 78 of 347
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
These data set registers are used to clear bits in the
GPIO_DATA_x registers.
EO
GPIO64 to GPIO95 data clear register
10000648 GPIO_DCLR_2 32 These data set registers are used to clear bits in the
US L
GPIO_DATA_x registers.
GPIO0 to GPIO31 rising edge interrupt enable register
GINT_REDGE_
10000650 32
.tw IA
0 These registers are used to enable the condition of rising edge
triggered interrupt.
GPIO32 to GPIO63 rising edge interrupt enable register
GINT_REDGE_
10000654 1 32 These registers are used to enable the condition of rising edge
triggered interrupt.
om NT
GPIO64 to GPIO95 rising edge interrupt enable register
GINT_REDGE_
10000658 2 32 These registers are used to enable the condition of rising edge
triggered interrupt.
GPIO0 to GPIO31 falling edge interrupt enable register
10000660 GINT_FEDGE_ 32
x.c E
0 These registers are used to enable the condition of falling edge
triggered interrupt.
GPIO32 to GPIO63 falling edge interrupt enable register
ne FID
10000664 GINT_FEDGE_ 32
1 These registers are used to enable the condition for falling edge
triggered interrupt.
GPIO64 to GPIO95 falling edge interrupt enable register
10000668 GINT_FEDGE_ 32
2 These registers are used to enable the condition of falling edge
triggered interrupt.
GPIO0 to GPIO31 high level interrupt enable register
syn ON
These registers are used to enable the condition of high level
10000670 GINT_HLVL_0 32 triggered interrupt.
The bit in this register and the corresponded bit in GINT_LLVL_0
can not be set to 1 at the same time.
GPIO32 to GPIO63 high level interrupt enable register
These registers are used to enable the condition of high level
@ C
10000674 GINT_HLVL_1 32 triggered interrupt.
The bit in this register and the corresponded bit in GINT_LLVL_1
can not be set to 1 at the same time.
GPIO64 to GPIO95 high level interrupt enable register
ien K
These registers are used to enable the condition of high level
10000678 GINT_HLVL_2 32 triggered interrupt.
The bit in this register and the corresponded bit in GINT_LLVL_2
ch TE
can not be set to 1 at the same time.
GPIO0 to GPIO31 low level interrupt enable register
These registers are used to enable the condition of low level
10000680 GINT_LLVL_0 32 triggered interrupt.
The bit in this register and the corresponded bit in GINT_HLVL_0
am IA
can not be set to 1 at the same time.
GPIO32 to GPIO63 low level interrupt enable register
These registers are used to enable the condition of low level
10000684 GINT_LLVL_1 32 triggered interrupt.
The bit in this register and the corresponded bit in GINT_HLVL_1
ad ED
can not be set to 1 at the same time.
GPIO64 to GPIO95 low level interrupt enable register
These registers are used to enable the condition of low level
10000688 GINT_LLVL_2 32 triggered interrupt.
The bit in this register and the corresponded bit in GINT_HLVL_2
M
can not be set to 1 at the same time.
GPIO0 to GPIO31 interrupt status register
10000690 GINT_STAT_0 32 These registers are used to record the GPIO current interrupt
status.
GPIO32 to GPIO63 interrupt status register
10000694 GINT_STAT_1 32 These registers are used to record the GPIO current interrupt
status.
10000698 GINT_STAT_2 32 GPIO64 to GPIO95 interrupt status register
OR
MediaTek Confidential © 2014 MediaTek Inc. Page 79 of 347
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
These registers are used to record the GPIO current interrupt
status.
EO
GPIO0 to GPIO31 edge status register
100006A0 GINT_EDGE_0 32 These registers are used to record the GPIO current interrupt's
US L
edge status.
These registers are useful only in edge triggered interrupt.
GPIO32 to GPIO63 edge status register
.tw IA
100006A4 GINT_EDGE_1 32 These registers are used to record the GPIO current interrupt's
edge status.
These registers are useful only in edge triggered interrupt.
GPIO64 to GPIO95 edge status register
om NT
100006A8 GINT_EDGE_2 32 These registers are used to record the GPIO current interrupt's
edge status.
These registers are useful only in edge triggered interrupt.
x.c E
0000000
10000600 GPIO_CTRL_0 GPIO0 to GPIO31 direction control register
0
ne FID
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name GPIOCTRL0[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name GPIOCTRL0[15:0]
syn ON
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:0 GPIOCTRL0 GPIO Pin Direction
@ C
0: GPIO input mode
1: GPIO output mode
ien K
0000000
10000604 GPIO_CTRL_1 GPIO32 to GPIO63 direction control register
ch TE
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name GPIOCTRL1[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
am IA
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name GPIOCTRL1[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ad ED
Bit(s) Name Description
31:0 GPIOCTRL1 GPIO Pin Direction
0: GPIO input mode
1: GPIO output mode
M
0000000
10000608 GPIO_CTRL_2 GPIO64 to GPIO95 direction control register
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name GPIOCTRL2[31:16]
Type RW
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EO
Name GPIOCTRL2[15:0]
Type RW
US L
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
.tw IA
31:0 GPIOCTRL2 GPIO Pin Direction
0: GPIO input mode
1: GPIO output mode
om NT
0000000
10000610 GPIO_POL_0 GPIO0 to GPIO31 polarity control register
0
x.c E
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name GPIOPOL0[31:16]
Type RW
ne FID
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name GPIOPOL0[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
syn ON
Bit(s) Name Description
31:0 GPIOPOL0 GPIO Data Polarity
0: Data is non-inverted
1: Data is inverted
@ C
0000000
10000614 GPIO_POL_1 GPIO32 to GPIO63 polarity control register
0
ien K
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name GPIOPOL1[31:16]
Type
ch TE
RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name GPIOPOL1[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
am IA
Bit(s) Name Description
31:0 GPIOPOL1 GPIO Data Polarity
ad ED
0: Data is non-inverted
1: Data is inverted
M
0000000
10000618 GPIO_POL_2 GPIO64 to GPIO95 polarity control register
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name GPIOPOL2[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name GPIOPOL2[15:0]
Type RW
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
EO
Bit(s) Name Description
31:0 GPIOPOL2 GPIO Data Polarity
US L
0: Data is non-inverted
1: Data is inverted
.tw IA
GPIO_DATA_ 0000000
om NT
10000620 GPIO0 to GPIO31 data register
0 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name GPIODATA0[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
x.c E
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name GPIODATA0[15:0]
Type RW
ne FID
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:0 GPIODATA0 GPIO Data
syn ON
GPIO_DATA_ 0000000
10000624 GPIO32 to GPIO63 data register
1 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name GPIODATA1[31:16]
@ C
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
ien K
GPIODATA1[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ch TE
Bit(s) Name Description
31:0 GPIODATA1 GPIO Data
am IA
GPIO_DATA_ 0000000
10000628 GPIO64 to GPIO95 data register
2 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ad ED
Name GPIODATA2[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name GPIODATA2[15:0]
M
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:0 GPIODATA2 GPIO Data
OR
MediaTek Confidential © 2014 MediaTek Inc. Page 82 of 347
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
FFFFFF
10000630 GPIO_DSET_0 GPIO0 to GPIO31 data set register
EO
FF
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
US L
Name GPIODSET0[31:16]
Type WO
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
.tw IA
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name GPIODSET0[15:0]
Type WO
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
om NT
Bit(s) Name Description
31:0 GPIODSET0 GPIO Data Set
1: Set the GPIO_DATA_0 register
0: No effect
x.c E
10000634
Bit
Name
Type
31 ne FID
GPIO_DSET_1
30 29 28
GPIO32 to GPIO63 data set register
27 26 25 24 23
GPIODSET1[31:16]
WO
22 21 20 19 18
FFFFFF
17
FF
16
syn ON
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name GPIODSET1[15:0]
Type WO
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
@ C
Bit(s) Name Description
31:0 GPIODSET1 GPIO Data Set
1: Set the GPIO_DATA_1 register
ien K
0: No effect
ch TE
FFFFFF
10000638 GPIO_DSET_2 GPIO64 to GPIO95 data set register
FF
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
am IA
Name GPIODSET2[31:16]
Type WO
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name GPIODSET2[15:0]
ad ED
Type WO
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit(s) Name Description
31:0 GPIODSET2 GPIO Data Set
M
1: Set the GPIO_DATA_2 register
0: No effect
GPIO_DCLR_ FFFFFF
10000640 GPIO0 to GPIO31 data clear register
0 FF
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name GPIODCLR0[31:16]
EO
Type WO
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
US L
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name GPIODCLR0[15:0]
Type WO
.tw IA
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit(s) Name Description
31:0 GPIODCLR0 GPIO Data Clear
om NT
1: Clear the GPIO_DATA_0 register
0: No effect
x.c E
GPIO_DCLR_ FFFFFF
10000644 GPIO32 to GPIO63 data clear register
1 FF
ne FID
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name GPIODCLR1[31:16]
Type WO
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name GPIODCLR1[15:0]
Type
syn ON
WO
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit(s) Name Description
31:0 GPIODCLR1 GPIO Data Clear
@ C
1: Clear the GPIO_DATA_1 register
0: No effect
ien K
GPIO_DCLR_ FFFFFF
10000648 GPIO64 to GPIO95 data clear register
2 FF
ch TE
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name GPIODCLR2[31:16]
Type WO
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
am IA
Name GPIODCLR2[15:0]
Type WO
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
ad ED
Bit(s) Name Description
31:0 GPIODCLR2 GPIO Data Clear
1: Clear the GPIO_DATA_2 register
0: No effect
M
GINT_REDGE GPIO0 to GPIO31 rising edge interrupt enable 0000000
10000650
_0 register 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name GINTREDGE0[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
OR
MediaTek Confidential © 2014 MediaTek Inc. Page 84 of 347
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name GINTREDGE0[15:0]
EO
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
US L
Bit(s) Name Description
.tw IA
31:0 GINTREDGE0 GPIO Rising Edge Interrupt Enable
1: Enable rising edge triggered
0: Disable rising edge triggered
om NT
GINT_REDGE GPIO32 to GPIO63 rising edge interrupt enable 0000000
10000654
_1 register 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
x.c E
Name GINTREDGE1[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ne FID
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name GINTREDGE1[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
syn ON
31:0 GINTREDGE1 GPIO Rising Edge Interrupt Enable
1: Enable rising edge triggered
0: Disable rising edge triggered
@ C
GINT_REDGE GPIO64 to GPIO95 rising edge interrupt enable 0000000
10000658
_2 register 0
ien K
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name GINTREDGE2[31:16]
Type RW
Reset
ch TE
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name GINTREDGE2[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
am IA
Bit(s) Name Description
31:0 GINTREDGE2 GPIO Rising Edge Interrupt Enable
1: Enable rising edge triggered
ad ED
0: Disable rising edge triggered
GINT_FEDGE GPIO0 to GPIO31 falling edge interrupt enable 0000000
10000660
M
_0 register 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name GINTFEDGE0[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name GINTFEDGE0[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
OR
MediaTek Confidential © 2014 MediaTek Inc. Page 85 of 347
This document contains information that is proprietary to MediaTek Inc.
Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited.
[email protected],time=2014-12-05 11:55:47,ip=58.250.71.129,doctitle=MT7628_ProgrammingGuide_20140428(E2).docx,company=Synnex Electronics HK Limited 聯強電子_RLT
MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Bit(s) Name Description
EO
31:0 GINTFEDGE0 GPIO Falling Edge Interrupt Enable
US L
1: Enable falling edge triggered
0: Disable falling edge triggered
.tw IA
GINT_FEDGE GPIO32 to GPIO63 falling edge interrupt enable 0000000
10000664
_1 register 0
om NT
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name GINTFEDGE1[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
x.c E
Name GINTFEDGE1[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s)
31:0 ne FID
Name
GINTFEDGE1
Description
GPIO Falling Edge Interrupt Enable
1: Enable falling edge triggered
0: Disable falling edge triggered
syn ON
GINT_FEDGE GPIO64 to GPIO95 falling edge interrupt enable 0000000
10000668
_2 register 0
@ C
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name GINTFEDGE2[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ien K
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name GINTFEDGE2[15:0]
Type RW
Reset
ch TE
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:0 GINTFEDGE2 GPIO Falling Edge Interrupt Enable
1: Enable falling edge triggered
am IA
0: Disable falling edge triggered
ad ED
0000000
10000670 GINT_HLVL_0 GPIO0 to GPIO31 high level interrupt enable register
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name GINTHLVL0[31:16]
Type RW
M
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name GINTHLVL0[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:0 GINTHLVL0 GPIO High Level Interrupt Enable
OR
MediaTek Confidential © 2014 MediaTek Inc. Page 86 of 347
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Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited.
[email protected],time=2014-12-05 11:55:47,ip=58.250.71.129,doctitle=MT7628_ProgrammingGuide_20140428(E2).docx,company=Synnex Electronics HK Limited 聯強電子_RLT
MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Bit(s) Name Description
1: Enable high level triggered
EO
0: Disable high level triggered
US L
.tw IA
0000000
10000674 GINT_HLVL_1 GPIO32 to GPIO63 high level interrupt enable register
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name GINTHLVL1[31:16]
om NT
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name GINTHLVL1[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
x.c E
Bit(s) Name Description
ne FID
31:0 GINTHLVL1 GPIO High Level Interrupt Enable
1: Enable high level triggered
0: Disable high level triggered
syn ON
0000000
10000678 GINT_HLVL_2 GPIO64 to GPIO95 high level interrupt enable register
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name GINTHLVL2[31:16]
Type RW
@ C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name GINTHLVL2[15:0]
Type RW
ien K
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
ch TE
31:0 GINTHLVL2 GPIO High Level Interrupt Enable
1: Enable high level triggered
0: Disable high level triggered
am IA
0000000
10000680 GINT_LLVL_0 GPIO0 to GPIO31 low level interrupt enable register
0
ad ED
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name GINTLLVL0[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M
Name GINTLLVL0[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:0 GINTLLVL0 GPIO Low Level Interrupt Enable
1: Enable low level triggered
0: Disable low level triggered
OR
MediaTek Confidential © 2014 MediaTek Inc. Page 87 of 347
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Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited.
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
EO
0000000
10000684 GINT_LLVL_1 GPIO32 to GPIO63 low level interrupt enable register
US L
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
.tw IA
Name GINTLLVL1[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name GINTLLVL1[15:0]
om NT
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
x.c E
31:0 GINTLLVL1 GPIO Low Level Interrupt Enable
1: Enable low level triggered
0: Disable low level triggered
10000688
ne FID
GINT_LLVL_2 GPIO64 to GPIO95 low level interrupt enable register
0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
syn ON
Name GINTLLVL2[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name GINTLLVL2[15:0]
Type RW
@ C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
ien K
31:0 GINTLLVL2 GPIO Low Level Interrupt Enable
1: Enable low level triggered
0: Disable low level triggered
ch TE
0000000
10000690 GINT_STAT_0 GPIO0 to GPIO31 interrupt status register
0
am IA
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name GINTSTAT0[31:16]
Type W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ad ED
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name GINTSTAT0[15:0]
Type W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
M
Bit(s) Name Description
31:0 GINTSTAT0 GPIO Interrupt Status
1: Interrupt is detected
0: Interrupt is not detected
OR
MediaTek Confidential © 2014 MediaTek Inc. Page 88 of 347
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Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited.
[email protected],time=2014-12-05 11:55:47,ip=58.250.71.129,doctitle=MT7628_ProgrammingGuide_20140428(E2).docx,company=Synnex Electronics HK Limited 聯強電子_RLT
MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
0000000
10000694 GINT_STAT_1 GPIO32 to GPIO63 interrupt status register
EO
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
US L
Name GINTSTAT1[31:16]
Type W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
.tw IA
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name GINTSTAT1[15:0]
Type W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
om NT
Bit(s) Name Description
31:0 GINTSTAT1 GPIO Interrupt Status
1: Interrupt is detected
0: Interrupt is not detected
x.c E
10000698
Bit
Name
Type
31 ne FID
GINT_STAT_2
30 29 28
GPIO64 to GPIO95 interrupt status register
27 26 25 24 23
GINTSTAT2[31:16]
W1C
22 21 20 19 18
0000000
17
0
16
syn ON
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name GINTSTAT2[15:0]
Type W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
@ C
Bit(s) Name Description
31:0 GINTSTAT2 GPIO Interrupt Status
1: Interrupt is detected
ien K
0: Interrupt is not detected
ch TE
GINT_EDGE_ 0000000
100006A0 GPIO0 to GPIO31 edge status register
0 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
am IA
Name GINTEDGE0[31:16]
Type W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name GINTEDGE0[15:0]
ad ED
Type W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:0 GINTEDGE0 GPIO Interrupt Edge Status
M
1: Rising edge
0: Falling edge
GINT_EDGE_ 0000000
100006A4 GPIO32 to GPIO63 edge status register
1 0
OR
MediaTek Confidential © 2014 MediaTek Inc. Page 89 of 347
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Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited.
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name GINTEDGE1[31:16]
EO
Type W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
US L
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name GINTEDGE1[15:0]
Type W1C
.tw IA
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:0 GINTEDGE1 GPIO Interrupt Edge Status
om NT
1: Rising edge
0: Falling edge
x.c E
GINT_EDGE_ 0000000
100006A8 GPIO64 to GPIO95 edge status register
2 0
ne FID
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name GINTEDGE2[31:16]
Type W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name GINTEDGE2[15:0]
Type
syn ON
W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:0 GINTEDGE2 GPIO Interrupt Edge Status
@ C
1: Rising edge
0: Falling edge
ien K
ch TE
am IA
ad ED
OR M
MediaTek Confidential © 2014 MediaTek Inc. Page 90 of 347
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Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited.
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
2.9 SPI Slave
EO
2.9.1 SPI Slave Control
US L
spis_intf Changes LOG
.tw IA
Revision Date Author Change Log
0.1 2013/9/23 Kaiping Yen Initialization
om NT
Module name: spis_intf Base address: (+0h)
Address Name Widt Register Function
h
x.c E
00000000 REG00 32 SPI Slave Register 00
00000004 REG01 32 SPI Slave Register 01
ne FID
00000008 REG02 32 SPI Slave Register 02
0000000C REG03 32 SPI Slave Register 03
00000010 REG04 32 SPI Slave Register 04
syn ON
0000000
00000000 REG00 SPI Slave Register 00
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name bus_read_data[31:16]
Type RO
@ C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name bus_read_data[15:0]
Type RO
ien K
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
ch TE
31:0 bus_read_data SPI Slave Register 00 for bus read data
am IA
0000000
00000004 REG01 SPI Slave Register 01
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name bus_write_data[31:16]
ad ED
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name bus_write_data[15:0]
Type RW
Reset
M
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:0 bus_write_data SPI Slave Register 01 for bus write data
00000008 REG02 SPI Slave Register 02 0000000
OR
MediaTek Confidential © 2014 MediaTek Inc. Page 91 of 347
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EO
Name bus_address[31:16]
Type RW
US L
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
.tw IA
Name bus_address[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
om NT
31:0 bus_address SPI Slave Register 02 for bus address
This address must be physical address
x.c E
0000000
0000000C REG03 SPI Slave Register 03
0
ne FID
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name reg03_31_5[26:11]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
bus
syn ON
reg bus
_pb
Name reg03_31_5[10:0]
_rb
03_ bus_size _r_
3 w
_sel
Type RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
@ C
Bit(s) Name Description
31:5 reg03_31_5 reg03[31:5] reserved bit
4 bus_pb_rb_sel Bus interface selection
ien K
0: Bus transaction is asserted by Rbus master interface, can access DRAM
and peripheral registers
1: Bus transaction is asserted by Pbus master interface, can peripheral
ch TE
registers only
3 reg03_3 reg03[3] reserved bit
2:1 bus_size Bus access size
00: reserved
am IA
01: reserved
10: word (4bytes)
11: reserved
0 bus_r_w Bus access type
ad ED
0: read
1: write
M
0000000
00000010 REG04 SPI Slave Register 04
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
bus
Name _bu
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
sy
Type RO
EO
Reset 0
US L
Bit(s) Name Description
0 bus_busy Bus (Internal Rbus/Pbus Master) interface status
.tw IA
0: SPIS bus interface is idle for next access command
1: SPIS bus interface is busy
om NT
2.9.2 Regsiters
spis_pbslv Changes LOG
Revision Date Author Change Log
x.c E
0.1 2013/9/23 Kaiping Yen Initialization
Address
10000700
ne FID
Module name: spis_pbslv Base address: (+10000700h)
Name
SPIS_REG0
Widt
h
32 SPI Slave Register 0
Register Function
syn ON
10000704 SPIS_REG1 32 SPI Slave Register 1
10000708 SPIS_REG2 32 SPI Slave Register 2
1000070C SPIS_REG3 32 SPI Slave Register 3
10000710 SPIS_REG4 32 SPI Slave Register 4
@ C
10000740 SPIS_CFG 32 SPI Slave Configuration
ien K
0000000
10000700 SPIS_REG0 SPI Slave Register 0
0
ch TE
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name spis_reg0[31:16]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name spis_reg0[15:0]
am IA
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
ad ED
31:0 spis_reg0 SPI Slave Register 0
0000000
M
10000704 SPIS_REG1 SPI Slave Register 1
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name spis_reg1[31:16]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name spis_reg1[15:0]
Type RO
OR
MediaTek Confidential © 2014 MediaTek Inc. Page 93 of 347
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Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited.
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
EO
Bit(s) Name Description
31:0 spis_reg1 SPI Slave Register 1
US L
.tw IA
0000000
10000708 SPIS_REG2 SPI Slave Register 2
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
om NT
Name spis_reg2[31:16]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name spis_reg2[15:0]
x.c E
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ne FID
Bit(s) Name Description
31:0 spis_reg2 SPI Slave Register 2
0000000
syn ON
1000070C SPIS_REG3 SPI Slave Register 3
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name spis_reg3[31:16]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
@ C
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name spis_reg3[15:0]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ien K
Bit(s) Name Description
ch TE
31:0 spis_reg3 SPI Slave Register 3
0000000
am IA
10000710 SPIS_REG4 SPI Slave Register 4
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name spis_reg4[31:16]
Type RO
ad ED
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name spis_reg4[15:0]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
M
Bit(s) Name Description
31:0 spis_reg4 SPI Slave Register 4
10000740 SPIS_CFG SPI Slave Configuration 0000000
OR
MediaTek Confidential © 2014 MediaTek Inc. Page 94 of 347
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EO
Name
Type
US L
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
.tw IA
Name spis_mode
Type RW
Reset 0 0
Bit(s) Name Description
om NT
1:0 spis_mode SPI slave clock polarity and phase configuration
2'b00: CPOL=0, CPHA=0
2'b01: CPOL=0, CPHA=1
2'b10: CPOL=1, CPHA=0
x.c E
2'b11: CPOL=1, CPHA=1
ne FID
syn ON
@ C
ien K
ch TE
am IA
ad ED
OR M
MediaTek Confidential © 2014 MediaTek Inc. Page 95 of 347
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Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited.
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
2
2.10 I C Controller
EO
2.10.1 Features
US L
Programmable I C bus clock rate
2
Supports the Synchronous Inter-Integrated Circuits (I C) serial protocol
2
.tw IA
Bi-directional data transfer
Programmable address width up to 8 bits
Sequential byte read or write capability
Device address and data address can be transmitted for device, page and address selection
om NT
Supports Standard mode and Fast mode
2.10.2 List of Registers
x.c E
I2C Changes LOG
Revision Date Author Change Log
ne FID
0.1 2012/10/3 Evan Chou Initialization
Module name: I2C Base address: (+10000900h)
Address Name Widt Register Function
syn ON
h
10000908 SM0CFG0 32 SERIAL INTERFACE MASTER 0 CONFIG 0 REGISTER
10000910 SM0DOUT 32 SERIAL INTERFACE MASTER 0 DATAOUT REGISTER
10000914 SM0DIN 32 SERIAL INTERFACE MASTER 0 DATAIN REGISTER
@ C
10000918 SM0ST 32 SERIAL INTERFACE MASTER 0 STATUS REGISTER
1000091C SM0AUTO 32 SERIAL INTERFACE MASTER 0 AUTO-MODE REGISTER
10000920 SM0CFG1 32 SERIAL INTERFACE MASTER 0 CONFIG 1 REGISTER
ien K
10000928 SM0CFG2 32 SERIAL INTERFACE MASTER 0 CONFIG 2 REGISTER
10000940 SM0CTL0 32 Serial interface master 0 control 0 register
10000944 SM0CTL1 32 Serial interface master 0 control 1 register
ch TE
10000950 SM0D0 32 Serial interface master 0 data 0 register
10000954 SM0D1 32 Serial interface master 0 data 1 register
1000095C PINTEN 32 Peripheral interrupt enable register
am IA
10000960 PINTST 32 Peripheral interrupt status register
10000964 PINTCL 32 Peripheral interrupt clear register
ad ED
0000000
10000908 SM0CFG0 SERIAL INTERFACE MASTER 0 CONFIG 0 REGISTER
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
M
Type
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name SM0_DEVADDR
Type RW
Reset 0 0 0 0 0 0 0
Bit(s) Name Description
OR
MediaTek Confidential © 2014 MediaTek Inc. Page 96 of 347
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Bit(s) Name Description
6:0 SM0_DEVADDR Device address for transmission
EO
US L
SERIAL INTERFACE MASTER 0 DATAOUT 0000000
.tw IA
10000910 SM0DOUT
REGISTER 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
om NT
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name SM0_DATAOUT
Type RW
Reset 0 0 0 0 0 0 0 0
x.c E
Bit(s) Name Description
ne FID
7:0 SM0_DATAOUT Data out register for auto mode
0000000
10000914 SM0DIN SERIAL INTERFACE MASTER 0 DATAIN REGISTER
0
syn ON
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name SM0_DATAIN
@ C
Type RO
Reset 0 0 0 0 0 0 0 0
Bit(s) Name Description
ien K
7:0 SM0_DATAIN Data in register for auto mode
ch TE
0000000
10000918 SM0ST SERIAL INTERFACE MASTER 0 STATUS REGISTER
2
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
am IA
Name
Type
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ad ED
SM
SM
0_
0_R SM
WD
DA 0_B
Name AT
TA_ US
A_E
RD Y
MP
Y
M
TY
Type RW RW RO
Reset 0 1 0
Bit(s) Name Description
2 SM0_RDATA_RDY I2C read data is ready
1 SM0_WDATA_EMP I2C data output register is empty
TY
OR
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Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
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Bit(s) Name Description
0 SM0_BUSY State machine is busy
EO
US L
SERIAL INTERFACE MASTER 0 AUTO-MODE 0000000
.tw IA
1000091C SM0AUTO
REGISTER 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
om NT
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SM
0_S
Name TA
RT_
x.c E
RW
Type RW
Reset
ne FID
0
Bit(s) Name Description
0 SM0_START_RW Written with 1 to start a read transaction, and 0 to start a write
transaction. This bit is only valid at auto mode.
syn ON
0000000
10000920 SM0CFG1 SERIAL INTERFACE MASTER 0 CONFIG 1 REGISTER
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
@ C
Name
Type
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ien K
Name SM0_BYTECNT
Type RW
Reset 0 0 0 0 0 0
ch TE
Bit(s) Name Description
5:0 SM0_BYTECNT The value + 1 indicateds the number of data bytes for sequential
reads/writes. (word address is included in data bytes)
am IA
0000000
10000928 SM0CFG2 SERIAL INTERFACE MASTER 0 CONFIG 2 REGISTER
0
ad ED
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M
SM
0_I
S_A
Name UT
OM
OD
E
Type RW
Reset 0
OR
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Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
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Bit(s) Name Description
EO
0 SM0_IS_AUTOMOD Set 1 to configure auto mode
US L
E
.tw IA
0000800
10000940 SM0CTL0 Serial interface master 0 control 0 register
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
om NT
SM
0_O
Name DR
RESV0 SM0_CLK_DIV
AIN
Type RW RO RW
Reset
x.c E
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SM SM SM
SM
ne FID
SIF 0_S 0_S 0_S
0_C SM
_VS RE SM0_VSY CL_ DA CL_
Name RESV2 S_S 0_E
YN SV1 NC_MODE ST _ST ST
TAT N
C AT AT RE
US
E E CH
Type RO RO RW RO RO RO RO RW RW
Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
syn ON
Bit(s) Name Description
31 SM0_ODRAIN Open-drain output configuration
0: When SIF output is logic 1, the output is pulled high by outer devices. SIF
output is open-drained.
1: When SIF output is logic 1, the output is pulled high by SIF master 0.
@ C
30:28 RESV0
27:16 SM0_CLK_DIV SIF master 0 clock divide value
ien K
This is used to set the divider to generate expected SCL.
15 SIF_VSYNC
14 RESV1
ch TE
13:12 SM0_VSYNC_MOD Restrict SIF master 0 trigger within VSYNC pulse
E 00: Disable
01: Allow triggered in VSYNC pulse
10: Allow triggered at VSYNC rising edge
am IA
11:5 RESV2
4 SM0_CS_STATUS Clock stretching status
0: no clock stretching
1: clock stretching
ad ED
3 SM0_SCL_STATE SCL value on the bus
2 SM0_SDA_STATE SDA value on the bus
1 SM0_EN SIF master 0 enable bit
0: Disable SIF master 0.
M
1: Enable SIF master 0.
0 SM0_SCL_STRECH Clock stretching enable
0: Not allow slaves hold SCL
1: Allow slaves hold SCL
10000944 SM0CTL1 Serial interface master 0 control 1 register 0000000
OR
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0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EO
Name SM0_ACK
Type RO
US L
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
.tw IA
SM
Name SM0_PGLEN SM0_MODE 0_T
RI
Type RW RW RW
Reset 0 0 0 0 0 0 0
om NT
Bit(s) Name Description
23:16 SM0_ACK Acknowledge bits
ACK[7:0] is acknowledge of 8 bytes of data
x.c E
10:8 SM0_PGLEN Page length
Page length of sequential read/write. The maximum is 8 bytes. Set 0 as 1
byte.
ne FID
6:4 SM0_MODE SIF master mode
001: Start
010: Write data
011: Stop
100: Read data with no ack for final byte
101: Read data with ack
syn ON
0 SM0_TRI Trigger serial interface
0: Read back as serial interface is idle.
1: Set 1 to trigger this serial interface. Read back as serial interface is busy.
@ C
FFFFFF
10000950 SM0D0 Serial interface master 0 data 0 register
FF
ien K
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name SM0_DATA3 SM0_DATA2
Type RW RW
Reset
ch TE
x x x x x x x x x x x x x x x x
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name SM0_DATA1 SM0_DATA0
Type RW RW
Reset x x x x x x x x x x x x x x x x
am IA
Bit(s) Name Description
31:24 SM0_DATA3 Serial interface data byte 3
23:16 SM0_DATA2 Serial interface data byte 2
ad ED
15:8 SM0_DATA1 Serial interface data byte 1
7:0 SM0_DATA0 Serial interface data byte 0
M
FFFFFF
10000954 SM0D1 Serial interface master 0 data 1 register
FF
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name SM0_DATA7 SM0_DATA6
Type RW RW
Reset x x x x x x x x x x x x x x x x
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name SM0_DATA5 SM0_DATA4
OR
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Type RW RW
Reset x x x x x x x x x x x x x x x x
EO
Bit(s) Name Description
US L
31:24 SM0_DATA7 Serial interface data byte 7
23:16 SM0_DATA6 Serial interface data byte 6
.tw IA
15:8 SM0_DATA5 Serial interface data byte 5
7:0 SM0_DATA4 Serial interface data byte 4
om NT
0000000
1000095C PINTEN Peripheral interrupt enable register
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
x.c E
Name
Type
Reset
ne FID
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SM
0_I
Name
NT_
EN
Type RW
Reset 0
syn ON
Bit(s) Name Description
0 SM0_INT_EN Serial interface master 0 interrupt enable
@ C
0000000
10000960 PINTST Peripheral interrupt status register
0
ien K
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
ch TE
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SM
0_I
Name
NT_
ST
am IA
Type WS
Reset 0
Bit(s) Name Description
ad ED
0 SM0_INT_ST Serial interface master 0 interrupt status
M
0000000
10000964 PINTCL Peripheral interrupt clear register
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SM
Name
0_I
OR
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Chip Name
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NL
NT_
CL
EO
W1
Type
C
Reset 0
US L
Bit(s) Name Description
.tw IA
0 SM0_INT_CL Serial interface master 0 interrupt clear
om NT
x.c E
ne FID
syn ON
@ C
ien K
ch TE
am IA
ad ED
OR M
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2.11 I2S Controller
EO
2.11.1 Features
US L
I2S transmitter/receiver, which can be configured as master or slave.
Supports 16-bit data, sampling rates of 8 kHz, 16 kHz, 22.05 kHz, 44.1 kHz, and 48 kHz
.tw IA
Support stereo audio data transfer.
32-byte FIFO are available for data transmission.
Supports GDMA access
Supports 12 Mhz bit clock from external source (when in slave mode)
om NT
2.11.2 Block Diagram
2
The I S transmitter block diagram is shown as below.
x.c E
RBUS
ne FID
CPU SDRAM
RBUS
RBUS
I2S Design CSR
syn ON
Async interface
SD
Parallel- RBUS
PBUS GDMA
WS to-serial FIFO Control
converter PBUS
SCLK
@ C
ien K
2
Figure 2-5 I S Transmitter Block Diagram
ch TE
2
The I S interface consists of two separate cores, a transmitter and a receiver. Both can operate in either master
or slave mode. The transmitter is only shown here in master or slave mode.
am IA
2 2
I S Signal Timing For I S Data Format
ad ED
M
Figure 2-6 I2S Transmit/Receive
OR
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EO
Serial data is transmitted in 2’s complement with the MSB first. The transmitter always sends the MSB of the
next word one clock period after the WS changes. Serial data sent by the transmitter may be synchronized
US L
with either the trailing (HIGH-to-LOW) or the leading (LOW-to-HIGH) edge of the clock signal. However, the
serial data must be latched into the receiver on the leading edge of the serial clock signal, and so there are
.tw IA
some restrictions when transmitting data that is synchronized with the leading edge.
The word select line indicates the channel being transmitted:
WS = 0; channel 1 (left)
om NT
WS = 1; channel 2 (right)
WS may change either on a trailing or leading edge of the serial clock, but it doesn’t need to be symmetrical. In
the slave, this signal is latched on the leading edge of the clock signal. The WS line changes one clock period
before the MSB is transmitted. This allows the slave transmitter to derive synchronous timing of the serial data
x.c E
that will be set up for transmission. Furthermore, it enables the receiver to store the previous word and clear
the input for the next Word.
Revision
ne FID
2.11.3 Registers
I2S Changes LOG
Date Author Change Log
0.1 2014/1/12 Ken Wu Initialization
syn ON
Module name: I2S Base address: (+10000A00h)
Address Name Widt Register Function
@ C
h
I2S Configuration
10000A00 I2S_CFG 32
I2S Tx/Rx Configuration Register
ien K
Interrupt Status
10000A04 INT_STATUS 32
I2S Interrupt Status
Interrupt Enable
10000A08 INT_EN 32
ch TE
I2S Interrupt Enable Control Register
FIFO Status
10000A0C FF_STATUS 32
I2S Tx/Rx FIFO Status
TX_FIFO_WRE Transmit FIFO Write to Register
10000A10 G 32
am IA
Tx Write Data Buffer
RX_FIFO_RRE Receive FIFO Read Register
10000A14 G 32
DRAM PAD CONTROL 3
I2S Configuration 1
10000A18 I2S_CFG1 32
ad ED
I2S Loopback Test Control Register
Integer Part of the Dividor Register 1
10000A20 DIVCOMP_CFG 32
Integer Part of the Dividor Register
Integer Part of the Dividor Register 2
10000A28 DIVINT_CFG 32
Integer Part of the Dividor Register
M
0001404
10000A00 I2S_CFG I2S Configuration
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
I2S DM LIT SY TX_ RX_ NO DA SL
Name _EN A_E TIE S_E EN EN RM TA_ AV
OR
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N _EN NDI _24 24B E_
DIA AN BIT IT MO
EO
N_ DE
DA
TA_
US L
FM
T
Type RW RW RW RW RW RW RW RW RW
.tw IA
Reset 0 0 0 0 0 0 0 0 1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RX_FF_THRES TX_FF_THRES
Type RW RW
om NT
Reset 0 1 0 0 0 1 0 0
Bit(s) Name Description
31 I2S_EN I2S Enable
Enables I2S. When disabled, all I2S control registers are cleared to their
x.c E
initial values.
0: Disable
ne FID
1: Enable
30 DMA_EN DMA Enable
Enables DMA access.
0: Disable
1: Enable
29 LITTIE_ENDIAN_DA Little endian audio data
syn ON
TA_FMT 0: big endian audio data format
1: little endian audio data format
28 SYS_ENDIAN System endian setting.
0: Little endian
1: Big endian
@ C
24 TX_EN Transmitter on/off control
0: Disable
1: Enable
ien K
20 RX_EN Receiver on/off control
0: Disable
1: Enable
ch TE
18 NORM_24BIT 24-bit data format
0: compact data format
1: normal data format
17 DATA_24BIT I2S data width
am IA
0: 16-bit data
1: 24-bit data
16 SLAVE_MODE Sets master or slave mode.
0: Master: using internal clock
ad ED
1: Slave: using external clock
15:12 RX_FF_THRES Rx FIFO Threshold
When the threshold is reached, the host/DMA is notified to fill FIFO.
2<RX_FF_THRES<6
(unit: word)
M
7:4 TX_FF_THRES Tx FIFO Threshold
When the threshold is reached, the host/DMA is notified to fill FIFO.
2<TX_FF_THRES<6
(unit: word)
10000A04 INT_STATUS Interrupt Status 0000000
OR
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0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EO
Name
Type
US L
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
.tw IA
RX_ TX_
RX_ RX_ RX_ TX_ TX_ TX_
DM DM
OV UN TH OV UN TH
Name A_F A_F
RU RU RE RU RU RE
AU AU
N N S N N S
LT LT
om NT
Type RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
Bit(s) Name Description
7 RX_DMA_FAULT Rx DMA Fault Detected Interrupt
x.c E
Asserts when a fault is detected in Rx DMA signals.
6 RX_OVRUN Rx Overrun Interrupt
ne FID
Asserts when the Rx FIFO is overrun.
5 RX_UNRUN Rx Underrun Interrupt
Asserts when the Rx FIFO is underrun.
4 RX_THRES Rx FIFO Below Threshold Interrupt
Asserts when the Rx FIFO is lower than the defined threshold.
syn ON
3 TX_DMA_FAULT Tx DMA Fault Detected Interrupt
Asserts when a fault is detected in Tx DMA signals.
2 TX_OVRUN Tx FIFO Overrun Interrupt
Asserts when the Tx FIFO is overrun.
1 TX_UNRUN Tx FIFO Underrun Interrupt
@ C
Asserts when the Tx FIFO is underrun.
0 TX_THRES Tx FIFO Below Threshold Interrupt
Asserts when the FIFO is lower than the defined threshold.
ien K
ch TE
0000000
10000A08 INT_EN Interrupt Enable
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
am IA
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RX_ RX_ RX_ RX_ TX_ TX_ TX_ TX_
INT INT INT INT INT INT INT INT
Name
ad ED
3_E 2_E 1_E 0_E 3_E 2_E 1_E 0_E
N N N N N N N N
Type RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
Bit(s) Name Description
M
7 RX_INT3_EN INT_STATUS[7] Enable
Enables the Rx DMA Fault Detected Interrupt. This interrupt asserts when a
fault is detected in Rx DMA signals.
6 RX_INT2_EN INT_STATUS[6] Enable
Enables the Rx Overrun Interrupt. This interrupt asserts when the Rx FIFO is
overrun.
5 RX_INT1_EN INT_STATUS[5] Enable
OR
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Bit(s) Name Description
Enables the Rx Underrun Interrupt. This interrupt asserts when the Rx FIFO
EO
is underrun.
4 RX_INT0_EN INT_STATUS[4] Enable
US L
Enables the Rx FIFO Below Threshold Interrupt. This interrupt asserts when
the Rx FIFO is lower than the defined threshold.
.tw IA
3 TX_INT3_EN INT_STATUS[3] Enable
Enables the Tx DMA Fault Detected Interrupt. This interrupt asserts when a
fault is detected in Tx DMA signals.
om NT
2 TX_INT2_EN INT_STATUS[2] Enable
Enables the Tx FIFO Overrun Interrupt. This interrupt asserts when the Tx
FIFO is overrun.
1 TX_INT1_EN INT_STATUS[1] Enable
Enables the Tx FIFO Underrun Interrupt. This interrupt asserts when the Tx
x.c E
FIFO is underrun.
0 TX_INT0_EN INT_STATUS[0] Enable
ne FID
Enables the Tx FIFO Below Threshold Interrupt. This interrupt asserts when
the FIFO is lower than the defined threshold.
0000001
10000A0C FF_STATUS FIFO Status
0
syn ON
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
@ C
Name RX_AVCNT TX_EPCNT
Type RO RO
Reset 0 0 0 0 0 1 0 0 0 0
ien K
Bit(s) Name Description
12:8 RX_AVCNT Rx FIFO Available Space Count
ch TE
Counts the available space for reads in Rx FIFO.
(unit: word)
4:0 TX_EPCNT Tx FIFO Available Space Count
Counts the available space for writes in Tx FIFO.
(unit: word)
am IA
TX_FIFO_WR 0000000
ad ED
10000A10 Transmit FIFO Write to Register
EG 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name TX_FIFO_WDATA[31:16]
Type WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
M
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name TX_FIFO_WDATA[15:0]
Type WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:0 TX_FIFO_WDATA Tx FIFO Write Data Buffer
Buffers data to be written to the Tx FIFO.
OR
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EO
RX_FIFO_RR 0000000
10000A14 Receive FIFO Read Register
US L
EG 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
.tw IA
Name RX_FIFO_RDATA[31:16]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RX_FIFO_RDATA[15:0]
om NT
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
x.c E
31:0 RX_FIFO_RDATA Rx FIFO Read Data Buffer
Buffers data read from the Rx FIFO.
10000A18
Bit 31
ne FID
I2S_CFG1
30 29 28
I2S Configuration 1
27 26 25 24 23 22 21 20 19 18
0000000
17
0
16
EXT
syn ON
LB
_LB
Name K_E
K_E
N
N
Type RW RW
Reset 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
@ C
I2S
Name _F
MT
Type RW
ien K
Reset 0
Bit(s) Name Description
ch TE
31 LBK_EN Enables loopback mode.
0: Normal mode
1: Loopback mode
ASYNC_TXFIFIO -> Tx -> Rx -> ASYNC_RXFIFIO
am IA
30 EXT_LBK_EN Enables external loopback.
0: Normal mode
1: Enables external loop back.
External A/D -> Rx -> Tx -> External D/A
ad ED
0 I2S_FMT I2S audio data format
0: i2s mode
1: left-justified mode
M
DIVCOMP_CF 0000000
10000A20 Integer Part of the Dividor Register 1
G 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CL
Name K_E
N
Type RW
Reset 0
OR
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Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DIVCOMP
EO
Type RW
Reset 0 0 0 0 0 0 0 0 0
US L
Bit(s) Name Description
.tw IA
31 CLK_EN Enables setting of the I2S clock based on DIVCOMP and DIVINT
parameters.
0: Disable
1: Enable
om NT
8:0 DIVCOMP A parameter in an equation which determines FREQOUT. See
DIVINT_CFG.
x.c E
0000000
10000A28 DIVINT_CFG Integer Part of the Dividor Register 2
0
ne FID
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DIVINT
Type RW
syn ON
Reset 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
9:0 DIVINT Integer Divider
A parameter in an equation which determines FREQOUT:
@ C
FREQOUT = FREQIN *(1/2) *
{1 / [DIVINT+DIVCOMP/(512)]}
FREQIN is always fixed to 480 MHz.
ien K
ch TE
am IA
ad ED
OR M
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
2.12 SPI Controller
EO
2.12.1 Features
US L
Supports up to 2 SPI master operations
Programmable clock polarity
.tw IA
Programmable interface clock rate
Programmable bit ordering
Firmware-controlled SPI enable
Programmable payload (address + data) length
om NT
Supports 1/2/4 multi-IO SPI flash memory
Supports command/user mode operation
Supports SPI direct access
Extends the addressable range from 24 bits to 32 bits for memory size larger than 128 Mb.
x.c E
ne FID
2.12.2 Block Diagram
clock
reset TX_FIFO Clock
SPICLK
from System Generator
syn ON
Controller
@ C
CPU SO/SIO1
CPU Interface SERDES
from PalmBus Interface WP/SIO2
Controller
ien K
ch TE
GDMA RX_FIFO SPI Control
FSM
am IA
Figure 2-7 SPI Controller Block Diagram
ad ED
M
2.12.3 Registers
SPI Changes LOG
Revision Date Author Change Log
0.1 2012/8/29 Lancelot Initialization
0.2 2012/11/6 Lancelot 1. Remove 0x38 SW_RST 2. Add CS_POLAR at 0x38
0.3 2012/11/23 Lancelot Fix default value
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
EO
Module name: SPI Base address: (+10000B00h)
US L
Address Name Widt Register Function
h
.tw IA
10000B00 SPI_TRANS 32 SPI transaction control/status register
10000B04 SPI_OP_ADDR 32 SPI opcode/address register
10000B08 SPI_DIDO_0 32 SPI DI/DO data #0 register
10000B0C SPI_DIDO_1 32 SPI DI/DO data #1 register
om NT
10000B10 SPI_DIDO_2 32 SPI DI/DO data #2 register
10000B14 SPI_DIDO_3 32 SPI DI/DO data #3 register
10000B18 SPI_DIDO_4 32 SPI DI/DO data #4 register
10000B1C SPI_DIDO_5 32 SPI DI/DO data #5 register
x.c E
10000B20 SPI_DIDO_6 32 SPI DI/DO data #6 register
10000B24 SPI_DIDO_7 32 SPI DI/DO data #7 register
ne FID
10000B28 SPI_MASTER 32 SPI master mode register
10000B2C SPI_MORE_BU 32 SPI more buf control register
F
SPI_QUEUE_C
10000B30 TL 32 SPI flash queue control register
10000B34 SPI_STATUS 32 SPI controller status register
syn ON
SPI_CS_POLA
10000B38 R 32 SPI chip select polarity
10000B3C SPI_SPACE 32 SPI flash space control register
@ C
0016000
10000B00 SPI_TRANS SPI transaction control/status register
1
ien K
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
spi
_m
ch TE
spi_addr_s ast
Name spi_addr_ext Reserved0 Reserved1
ize er_
bus
y
Type RW RO RW RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0
am IA
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
spi
_m
ast
Name Reserved2
er_
miso_byte_cnt mosi_byte_cnt
ad ED
star
t
Type RO WO RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
M
Bit(s) Name Description
31:24 spi_addr_ext SPI address extention
Address extenstion for 32-bit SPI address size. Usually this field specifies the
first byte of the address phase to transmit to SPI device when
more_buf_mode = 0 and spi_addr_size = 3. And spi_addr[31:24],
spi_addr[23:16], and spi_addr[15:0] are respectively the second, third and
fourth byte of the address phase
20:19 spi_addr_size SPI address size.
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Bit(s) Name Description
0: reserved.
EO
1: spi_addr[15:0] of SPI DI data register are valid (16-bit size).
2: spi_addr[23:0] of SPI DI data register are valid (24-bit size).
US L
3: {spi_addr_ext[7:0], spi_addr[23:0]} of SPI DI data register are valid
(32-bit size)
Note: The spi_addr_size is valid only when more_buf_mode = 0.
.tw IA
16 spi_master_busy Transaction busy indication (Read-only). Writes to this bit are ignored.
0: No SPI transaction is ongoing. Software may start a new SPI transaction
by writing to the SPI transaction start bit within this register.
om NT
1: An SPI transaction presently is underway. Software must not try to start a
new SPI transaction. Software may not alter the value of any field of the SPI
master control registers.
8 spi_master_start SPI transaction start. Only writes to this field are meaningful, reads
always return 0.
x.c E
Writes:
0: No effect
1: Starts SPI transaction.
ne FID
7:4 miso_byte_cnt SPI MISO (rx) byte count.
Determines the number of bytes received from the SPI device from the SPI
opcode/address register and the SPI DI/DO data #0 register. Values of 0 ~ 8
are valid, other values are illegal.
Note: The miso_byte_cnt is valid only when more_buf_mode = 0.
3:0 mosi_byte_cnt SPI MOSI (tx) byte count.
syn ON
Determines the number of bytes transmitted from the SPI opcode/address
register and the SPI DI/DO data #0 register to the SPI device. Values of 1 ~ 8
are valid, other values are illegal.
Note: The mosi_byte_cnt is valid only when more_buf_mode = 0. The
transmitted data sequence is as follows: spi_opcode, spi_addr (conditional)
and d0_byte ~ d3_byte (conditional).
@ C
ien K
SPI_OP_ADD 0000000
10000B04 SPI opcode/address register
R 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ch TE
Name spi_addr[23:8]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name spi_addr[7:0] spi_opcode
am IA
Type RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
ad ED
31:8 spi_addr SPI address. Usually this field specifies the 24-bits address to transmit
to the SPI device when more_buf_mode = 0.
1: (16-bits SPI address size), spi_addr[23:16] is the 1st byte of the address
phase and spi_addr[15:8] is the 2nd byte of the address phase.
2: (24-bits SPI address size), spi_addr[31:24] is the 1st byte of the address
M
phase and spi_addr[23:16] is the 2nd byte of the address phase and
spi_addr[15:8] is the 3rd byte of the address phase.
3: (32-bits SPI address size), spi_addr[31:24] is the 2nd byte of the address
phase and spi_addr[23:16] is the 3rd byte of the address phase and
spi_addr[15:8] is the 4th byte of the address phase
Note: For SPI read transaction and more_buf_mode = 0
Field [15:8] is also used to store the 6-th byte of data read phase.
Field [23:16] is also used to store the 7-th byte of data read phase.
Field [31:24] is also used to store the 8-th byte of data read phase.
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Bit(s) Name Description
7:0 spi_opcode SPI opcode. Usually this field specifies the 8-bits opcode (instruction) to
EO
transmit to the SPI device as the first byte of a SPI transaction when
more_buf_mode = 0.
US L
Note: For SPI read transaction and more_buf_mode = 0, this byte is also
used to store the 5-th byte of data read phase according to the rx byte count
.tw IA
miso_byte_cnt.
om NT
0000000
10000B08 SPI_DIDO_0 SPI DI/DO data #0 register
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name d3_byte d2_byte
Type RW RW
x.c E
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name d1_byte d0_byte
ne FID
Type RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:24 d3_byte The 4th data byte of data read/write phase.
23:16 d2_byte The 3th data byte of data read/write phase.
syn ON
15:8 d1_byte The 2nd data byte of data read/write phase.
7:0 d0_byte The 1st data byte of data read/write phase.
@ C
0000000
10000B0C SPI_DIDO_1 SPI DI/DO data #1 register
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ien K
Name d3_byte d2_byte
Type RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ch TE
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name d1_byte d0_byte
Type RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
am IA
Bit(s) Name Description
31:24 d3_byte The 4th data byte of data read/write phase.
23:16 d2_byte The 3th data byte of data read/write phase.
ad ED
15:8 d1_byte The 2nd data byte of data read/write phase.
7:0 d0_byte The 1st data byte of data read/write phase.
M
0000000
10000B10 SPI_DIDO_2 SPI DI/DO data #2 register
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name d3_byte d2_byte
Type RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name d1_byte d0_byte
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Type RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
EO
Bit(s) Name Description
US L
31:24 d3_byte The 4th data byte of data read/write phase.
23:16 d2_byte The 3th data byte of data read/write phase.
.tw IA
15:8 d1_byte The 2nd data byte of data read/write phase.
7:0 d0_byte The 1st data byte of data read/write phase.
om NT
0000000
10000B14 SPI_DIDO_3 SPI DI/DO data #3 register
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
x.c E
Name d3_byte d2_byte
Type RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ne FID
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name d1_byte d0_byte
Type RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
syn ON
31:24 d3_byte The 4th data byte of data read/write phase.
23:16 d2_byte The 3th data byte of data read/write phase.
15:8 d1_byte The 2nd data byte of data read/write phase.
7:0 d0_byte The 1st data byte of data read/write phase.
@ C
0000000
10000B18 SPI_DIDO_4 SPI DI/DO data #4 register
ien K
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
ch TE
d3_byte d2_byte
Type RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name d1_byte d0_byte
Type RW RW
am IA
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
ad ED
31:24 d3_byte The 4th data byte of data read/write phase.
23:16 d2_byte The 3th data byte of data read/write phase.
15:8 d1_byte The 2nd data byte of data read/write phase.
7:0 d0_byte The 1st data byte of data read/write phase.
M
0000000
10000B1C SPI_DIDO_5 SPI DI/DO data #5 register
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name d3_byte d2_byte
Type RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
OR
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Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name d1_byte d0_byte
EO
Type RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
US L
Bit(s) Name Description
.tw IA
31:24 d3_byte The 4th data byte of data read/write phase.
23:16 d2_byte The 3th data byte of data read/write phase.
15:8 d1_byte The 2nd data byte of data read/write phase.
om NT
7:0 d0_byte The 1st data byte of data read/write phase.
0000000
10000B20 SPI_DIDO_6 SPI DI/DO data #6 register
x.c E
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
ne FID
d3_byte d2_byte
Type RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name d1_byte d0_byte
Type RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
syn ON
Bit(s) Name Description
31:24 d3_byte The 4th data byte of data read/write phase.
23:16 d2_byte The 3th data byte of data read/write phase.
15:8 d1_byte The 2nd data byte of data read/write phase.
@ C
7:0 d0_byte The 1st data byte of data read/write phase.
ien K
0000000
10000B24 SPI_DIDO_7 SPI DI/DO data #7 register
0
ch TE
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name d3_byte d2_byte
Type RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
am IA
Name d1_byte d0_byte
Type RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ad ED
Bit(s) Name Description
31:24 d3_byte The 4th data byte of data read/write phase.
23:16 d2_byte The 3th data byte of data read/write phase.
15:8 d1_byte The 2nd data byte of data read/write phase.
M
7:0 d0_byte The 1st data byte of data read/write phase.
000D888
10000B28 SPI_MASTER SPI master mode register
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name rs_slave_sel clk_ rs_clk_sel
OR
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Chip Name
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mo
de
EO
Type RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
US L
mor
full spi spi
bidi lsb e_b
_du int_ _st _pr cph cpo serial_mod
.tw IA
Name cs_dsel_cnt
ple en art_ efet
r_m
a l
_fir uf_
e
ode st mo
x sel ch
de
Type RW RW RW RW RW RW RW RW RW RW RW
Reset 1 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0
om NT
Bit(s) Name Description
31:29 rs_slave_sel select SPI device
0: select SPI device 0 (default is flash)
1: select SPI device 1
x.c E
...
7: select SPI device 7
ne FID
28 clk_mode This register is used to specify that period of SCLK HIGH is longer or
period of SCLK LOW is longer when clock divisor(clk_sel) is odd.
0: period of SCLK LOW is longer.
1: period of SCLL HIGH is longer.
27:16 rs_clk_sel Register Space SPI clock frequency select.
0: SPI clock frequency is hclk/2. (50% duty cycle, duty cycle is the ratio of the
syn ON
output high time to the total cycle time)
1: SPI clock frequency is hclk/3. (33.33% or 66.67% duty cycle)
2: SPI clock frequency is hclk/4. (50% duty cycle)
3: SPI clock frequency is hclk/5. (40% or 60% duty cycle)
4095: SPI clock frequency is hclk/4097.
15:11 cs_dsel_cnt De-select time of SPI chip select is configured to occupy the number of
@ C
cycles of AHB clock
10 full_duplex Full duplex or half duplex mode.
0: half duplex mode.
ien K
1: full duplex mode.
Full duplex timing diagram
Note: The full_duplex is valid only when more_buf_mode = 1. The
ch TE
transmission is always as half duplex when more_buf_mode = 0;
9 int_en Interrupt enable.
0: disable SPI interrupt.
1: enable SPI interrupt.
am IA
8 spi_start_sel The interval between spi_cs_n and spi_sclk.
0: 3 clk
1: 6 clk
7 spi_prefetch SPI pre-fetch buffer enable
ad ED
0: disable pre-fetch buffer.
1: enable pre-fetch buffer.
6 bidir_mode Bi-direction mode. In this mode, the SPI uses only one serial data pin
for interface with external devices. The MOSI pin becomes the serial
data I/O pin for the SPI transaction and MISO pin is not used. Bi-
M
direction mode is used for the application with only 1 bi-direction serial
pin for SPI transaction.
0: normal mode (both MOSI and MISO pins are used).
1: bi-direction mode (only MOSI pin is used). SPI host controller must operate
in half duplex mode if bidir_mode = 1.
Note: The bidir_mode is valid only when more_buf_mode = 1.
5 cpha (CPHA, clock phase). Initial SPI clock phase for SPI transaction.
There are four SPI modes used to latch data. These SPI modes latch data in
OR
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MT7628
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Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
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Bit(s) Name Description
one of four ways, and are defined by the logic state combinations of the CLK
EO
Polarity (CPOL) in relation to the CLK Phase (CPHA). The valid logic
combinations identify and determine the SPI modes supported by the SPI
US L
device.
SPI mode
.tw IA
At CPOL=0 the base value of the clock is zero
For CPHA=0 (mode 0), data is read on the clock's rising edge and data is
changed on a falling edge.
om NT
For CPHA=1 (mode 1), data is read on the clock's falling edge and data is
changed on a rising edge.
At CPOL=1 the base value of the clock is one (inversion of CPOL=0)
For CPHA=0 (mode 2), data is read on clock's falling edge and data is
changed on a rising edge.
For CPHA=1 (mode 3), data is read on clock's rising edge and data is
x.c E
changed on a falling edge.
4 cpol cpol (CPOL, clock polarity). Initial SPI clock polarity for SPI transaction.
ne FID
3 lsb_first 0: MSB(most significant bit) is transferred first for SPI transaction.
1: LSB(least significant bit) is transferred first for SPI transaction.
2 more_buf_mode Select 2 words buffer or 8 words buffer for SPI transaction.
0: SPI transfer data buffer size is only 2 words. In this mode, SPI DI/DO data
#0 register and SPI opcode/address register are the data buffer for SPI
transaction. And, SPI master follows mosi_byte_cnt and miso_byte_cnt to
syn ON
complete the transmission and reception, respectively. This kind of
transaction must operate in half duplex mode.
1: SPI transfer data buffer size is 8 words. In this mode, SPI opcode/address
register are the data buffer for SPI transaction and follows cmd_bit_cnt to
complete the transaction. SPI DI/DO data #0~#7 register are the data buffer
for SPI transaction and follows do_bit_cnt and di_bit_cnt to complete the
@ C
transmission and reception, respectively. In half duplex mode, transmitted
data are loaded from SPI opcode/address register and SPI DI/DO data #0~#7
registers. And, the received data will overwrite the SPI DI/DO data #0~#7
registers. In full duplex mode, SPI DI/DO data #0~#3 registers are used for
ien K
transmission and SPI DI/DO #4~#7 registers are used for receipt.
1:0 serial_mode This mode is designed for Winbond SPI flash W25Q80/16/32 and
ch TE
W25X10/20/40/80/16/32/64 series.
0: standard serial.
1: dual serial.
2: quad serial.
3: reserved.
Note: The serial_mode is valid only when more_buf_mode = 0. The
am IA
transaction mode is always as standard serial when more_buf_mode = 1.
ad ED
SPI_MORE_B 0000000
10000B2C SPI more buf control register
UF 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name Reserved0 cmd_bit_cnt Reserved1 miso_bit_cnt[8:4]
Type
M
RO RW RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name miso_bit_cnt[3:0] Reserved2 mosi_bit_cnt
Type RW RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Bit(s) Name Description
29:24 cmd_bit_cnt SPI command phase MOSI (tx) bit count. Determines the number of
EO
command bits transmitted from the SPI opcode/address register to the
SPI device. Values of 0 ~ 32 are valid, but other values are illegal.
US L
Note: The cmd_bit_cnt is valid only when more_buf_mode = 1 and the SPI
opcode/address register is treated as a command register.
.tw IA
20:12 miso_bit_cnt SPI data phase MISO (rx) bit count. Determines the number of bits
received from the SPI device into the SPI DI/DO data #0~#7 register.
Values of 0 ~ 256 are valid, but other values are illegal. Maximum value
is 256 for half duplex mode and 128 for full duplex mode. Please note
om NT
that do_bit_cnt must be equal to di_bit_cnt in full duplex mode.
Note: The miso_bit_cnt is valid only when more_buf_mode = 1.
8:0 mosi_bit_cnt SPI data phase MOSI (tx) bit count. Determines the number of data bits
transmitted from the SPI DI/DO data #0~#7 register to the SPI device.
Values of 0 ~ 256 are valid, but other values are illegal. Maximum value
x.c E
is 256 for half duplex mode and 128 for full duplex mode.
Note: The mosi_bit_cnt is valid only when more_buf_mode = 1.
10000B30
Bit 31
ne FID
SPI_QUEUE_
CTL
30 29 28
SPI flash queue control register
27 26 25 24 23 22 21 20 19 18
00000E4
17
0
16
Name
syn ON
fs_page_sel Reserved0[12:3]
Type RW RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
fs_ Res
fs_addr_si fs_addr_si
Name Reserved0[2:0] bus fs_di_ph_byc erv fast_spi_sel
ze_r ze
y ed1
@ C
Type RO RO RO RW RW RO RW
Reset 0 0 0 0 1 1 1 0 0 1 0 0 0 0 0 0
ien K
Bit(s) Name Description
31:26 fs_page_sel Flash Space Page Selection.
0: (Page 0 space) 0x0000_0000 - 0x03ff_ffff
ch TE
1: (Page 1 space) 0x0400_0000 - 0x07ff_ffff
...
63: (Page 63 space) 0xffc0_0000 - 0xffff_ffff
12 fs_busy Transaction busy indication (Read-only) in flash space. Writes to this bit
are ignored.
am IA
0: No SPI flash space access is ongoing. Software may change the
configuration related to flash space.
1: SPI flash space access presently is underway. Software may not alter the
configuration related to flash space.
ad ED
11:10 fs_addr_size_r Latched fs_addr_size indication from internal spimc logic
9:8 fs_addr_size SPI address. This field specifies the 24-bits/16-bits address to transmit
to the SPI device for SPI Flash Space Read operation only.
0: 25-bit SPI address size
1: 16-bit SPI address size Reserved.
M
2: 24-bit SPI address size (default for 3B SPI flash)
3: 26-bit SPI address size (default for 4B SPI flash)
If the change of the fs_addr_size is needed, the sequence below must be
followed. Otherwise, the new fs_addr_size configuration will not be updated
to the internal spimc logic .
Step 1: Set new fs_addr_size.
Step 2: Transmit mode change command (ex. En4B or Ex4B of
MX25L25635E)
Note: 1. The value fs_addr_size is not valid in Register Space.
OR
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Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
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Bit(s) Name Description
2. The Spimc now only supports 3-Byte mode (24 bits) and 4-Byte
EO
mode (25 or 26 bits) switch.
7:4 fs_di_ph_byc Determines the number of data bytes transmitted from the SPI master
US L
controller to the SPI device for SPI Flash Space Read operation. This
field is similar to mosi_byte_cnt in STCSR but is used for setting of
.tw IA
flash space access control path.
Note: this field should
(if fs_addr_size_r = 2, 24-bit fs_addr_size)
= 4 (OP + ADDR) if fast_spi_sel = 0 (0x03)
om NT
= 5 (OP + ADDR + dummy) if fast_spi_sel = 1 (0x0b)
= 5 (OP + ADDR + dummy) if fast_spi_sel = 2 (0x3b)
= 5 (OP + ADDR + M7-0) if fast_spi_sel = 3 (0xbb)
= 5 (OP + ADDR + dummy) if fast_spi_sel = 4 (0x6b)
= 7 (OP + ADDR + M7-0 + dummy) if fast_spi_sel = 5 (0xeb)
= 5 (OP + ADDR + M7-0) if fast_spi_sel = 6 (0xe3)
x.c E
(if fs_addr_size_r = 0 or 3, 25 or 26-bit fs_addr_size)
= 5 (OP + ADDR) if fast_spi_sel = 0 (0x03)
ne FID
= 6 (OP + ADDR + dummy) if fast_spi_sel = 1 (0x0b)
= 6 (OP + ADDR + dummy) if fast_spi_sel = 2 (0x3b)
= 6 (OP + ADDR + M7-0) if fast_spi_sel = 3 (0xbb)
= 6 (OP + ADDR + dummy) if fast_spi_sel = 4 (0x6b)
= 8 (OP + ADDR + M7-0 + dummy) if fast_spi_sel = 5 (0xeb)
= 6 (OP + ADDR + M7-0) if fast_spi_sel = 6 (0xe3)
syn ON
2:0 fast_spi_sel Select SPI flash read instruction for Flash Space
0: standard read data instruction (0x03).
1: standard fast read data instruction (0x0b).
2: fast read dual output instruction defined in Winbond W25Qxx series SPI
flash (0x03b).
3: fast read dual I/O instruction defined in Winbond W25Qxx series SPI flash
@ C
(0xbb).
4: fast read quad output instruction defined in Winbond W25Qxx series SPI
flash (0x6b).
5: fast read quad I/O instruction defined in Winbond W25Qxx series SPI flash
ien K
(0xeb).
6: burst read quad I/O instruction defined in Winbond W25Qxx series SPI
flash (0xe3).
ch TE
Note: serial_mode and more_buf_mode are don't care for this flash space
access control path.
am IA
0000003
10000B34 SPI_STATUS SPI controller status register
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name Reserved0[25:10]
ad ED
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
spi_flash_ spi
Name Reserved0[9:0] Reserved1
mode _ok
Type RO RO RO RC
M
Reset 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0
Bit(s) Name Description
5:4 spi_flash_mode 0: no SPI flash.
1: standard SPI flash.
2: specific SPI flash with dual interface capability.
3: specific SPI flash with quad interface capability.
OR
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Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
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Bit(s) Name Description
0 spi_ok When SPI transaction complete, SPI master controller will set this bit
EO
and assert SPI interrupt to notify software. Reading this register will
clear this bit and de-assert SPI interrupt.
US L
.tw IA
SPI_CS_POL 0000000
10000B38 SPI chip select polarity
AR 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
om NT
Name
Type
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name cs_polar
x.c E
Type RW
Reset 0 0 0 0 0 0 0 0
ne FID
Bit(s) Name Description
7:0 cs_polar Chip select default polarity
set cs_polar[n]=1'b0 for cs[n] low active (SPI Flash)
set cs_polar[n]=1'b1 for cs[n] high active
syn ON
0000003
10000B3C SPI_SPACE SPI flash space control register
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name Reserved[16:1]
@ C
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res
ien K
erv
Name ed[
fs_slave_sel fs_clk_sel
0:0]
ch TE
Type RO RW RW
Reset 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0
Bit(s) Name Description
14:12 fs_slave_sel (Flash Space Slave Select)
am IA
0: select SPI device #0. (default is flash)
1: select SPI device #1.
...
7: select SPI device #7.
ad ED
11:0 fs_clk_sel Flash Space SPI clock frequency select.
0: SPI clock frequency is hclk/2. (50% duty cycle, duty cycle is the ratio of the
output high time to the total cycle time)
1: SPI clock frequency is hclk/3. (33.33% or 66.67% duty cycle)
2: SPI clock frequency is hclk/4. (50% duty cycle)
M
3: SPI clock frequency is hclk/5. (40% or 60% duty cycle)
4095: SPI clock frequency is hclk/4097.
OR
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MT7628
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Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
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2.13 UART Lite
EO
2.13.1 Features
US L
2-pin UART
16550-compatible register set, except for Divisor Latch register
.tw IA
5-8 data bits
1-2 stop bits (1 or 2 stop bits are supported with 5 data bits)
Even, odd, stick or no parity
All standard baud rates up to 345600 b/s
om NT
16-byte receive buffer
16-byte transmit buffer
Receive buffer threshold interrupt
Transmit buffer threshold interrupt
x.c E
False start bit detection in asynchronous mode
Internal diagnostic capabilities
ne FID
Break simulation
Loop-back control for communications link fault isolation
2.13.2 Registers
n = 1; for uart1 only.
syn ON
UARTn+0000h RX Buffer Register UARTn_RBR
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RBR[7:0]
Type RO
@ C
RBR RX Buffer Register. Read-only register. The received data can be read by accessing this register.
Modified when LCR[7] = 0.
ien K
UARTn+0000h TX Holding Register UARTn_THR
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ch TE
Name THR[7:0]
Type WO
THR TX Holding Register. Write-only register. The data to be transmitted is written to this register, and
then sent to the PC via serial communication.
am IA
Modified when LCR[7] = 0.
UARTn+0004h Interrupt Enable Register UARTn_IER
ad ED
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name CTSI RTSI XOFFI X EDSSI ELSI ETBEI ERBFI
Type R/W
Reset 0
M
IER By storing a „1‟ to a specific bit position, the interrupt associated with that bit is enabled. Otherwise,
the interrupt is disabled.
IER[3:0] are modified when LCR[7] = 0.
IER[7:4] are modified when LCR[7] = 0 & EFR[4] = 1.
CTSI Masks an interrupt that is generated when a rising edge is detected on the CTS modem control line.
Note: This interrupt is only enabled when hardware flow control is enabled.
OR
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0 Unmask an interrupt that is generated when a rising edge is detected on the CTS modem control
line.
EO
1 Mask an interrupt that is generated when a rising edge is detected on the CTS modem control line.
US L
RTSI Masks an interrupt that is generated when a rising edge is detected on the RTS modem control line.
Note: This interrupt is only enabled when hardware flow control is enabled.
.tw IA
0 Unmask an interrupt that is generated when a rising edge is detected on the RTS modem control
line.
1 Mask an interrupt that is generated when a rising edge is detected on the RTS modem control line.
om NT
XOFFI Masks an interrupt that is generated when an XOFF character is received.
Note: This interrupt is only enabled when software flow control is enabled.
0 Unmask an interrupt that is generated when an XOFF character is received.
1 Mask an interrupt that is generated when an XOFF character is received.
x.c E
EDSSI When set ("1"), an interrupt is generated if DDCD, TERI, DDSR or DCTS (MSR[4:1]) becomes set.
0 No interrupt is generated if DDCD, TERI, DDSR or DCTS (MSR[4:1]) becomes set.
ne FID
1 An interrupt is generated if DDCD, TERI, DDSR or DCTS (MSR[4:1]) becomes set.
ELSI When set ("1"), an interrupt is generated if BI, FE, PE or OE (LSR[4:1]) becomes set.
0 No interrupt is generated if BI, FE, PE or OE (LSR[4:1]) becomes set.
1 An interrupt is generated if BI, FE, PE or OE (LSR[4:1]) becomes set.
ETBEI When set ("1"), an interrupt is generated if the TX Holding Register is empty or the contents of the TX
syn ON
FIFO
have been reduced to its Trigger Level.
0 No interrupt is generated if the TX Holding Register is empty or the contents of the TX FIFO have
been reduced to its Trigger Level.
@ C
1 An interrupt is generated if the TX Holding Register is empty or the contents of the TX FIFO have
been reduced to its Trigger Level
ERBFI When set ("1"), an interrupt is generated if the RX Buffer contains data.
ien K
0 No interrupt is generated if the RX Buffer contains data.
1 An interrupt is generated if the RX Buffer contains data.
ch TE
UARTn+0008h Interrupt Identification Register UARTn_IIR
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name FIFOE ID4 ID3 ID2 ID1 ID0 NINT
am IA
Type RO
Reset 0 0 0 0 0 0 0 1
IIR Identify if there are pending interrupts; ID4 and ID3 are presented only when EFR[4] = 1.
ad ED
The following table gives the IIR[5:0] codes associated with the possible interrupts:
IIR[5:0] Priority Interrupt Source
Level
000001 - No interrupt pending
M
000110 1 Line Status Interrupt BI, FE, PE or OE set in LSR
000100 2 RX Data Received RX Data received or RX Trigger Level reached.
001100 2 RX Data Timeout Timeout on character in RX FIFO.
000010 3 TX Holding Register TX Holding Register empty or TX FIFO Trigger Level
Empty reached.
000000 4 Modem Status change DDCD, TERI, DDSR or DCTS set in MSR
OR
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MT7628 PROGRAMMING GUIDE Confidential B
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010000 5 Software Flow Control XOFF Character received
100000 6 Hardware Flow Control CTS or RTS Rising Edge
EO
Table 1 The IIR[5:0] codes associated with the possible interrupts
US L
Line Status Interrupt: A RX Line Status Interrupt (IIR[5:0`] == 000110b) is generated if ELSI (IER[2]) is set and
.tw IA
any of BI, FE, PE or OE (LSR[4:1]) becomes set. The interrupt is cleared by reading the Line Status Register.
RX Data Received Interrupt: A RX Received interrupt (IER[5:0] == 000100b) is generated if EFRBI (IER[0]) is set
and either RX Data is placed in the RX Buffer Register or the RX Trigger Level is reached. The interrupt is
cleared by reading the RX Buffer Register or the RX FIFO (if enabled).
om NT
RX Data Timeout Interrupt:
When virtual FIFO mode is disabled, RX Data Timeout Interrupt is generated if all of the following apply:
1. FIFO contains at least one character;
2. The most recent character was received longer than four character periods ago (including all start, parity
x.c E
and stop bits);
ne FID
3. The most recent CPU read of the FIFO was longer than four character periods ago.
The timeout timer is restarted on receipt of a new byte from the RX Shift Register, or on a CPU read from the
RX FIFO.
The RX Data Timeout Interrupt is enabled by setting EFRBI (IER[0]) to 1, and is cleared by reading RX FIFO.
When virtual FIFO mode is enabled, RX Data Timeout Interrupt is generated if all of the following apply:
syn ON
1. FIFO is empty;
2. The most recent character was received longer than four character periods ago (including all start, parity
and stop bits);
@ C
3. The most recent CPU read of the FIFO was longer than four character periods ago.
The timeout timer is restarted on receipt of a new byte from the RX Shift Register.
ien K
RX Holding Register Empty Interrupt: A TX Holding Register Empty Interrupt (IIR[5:0] = 000010b) is generated if
ETRBI (IER[1]) is set and either the TX Holding Register or, if FIFOs are enabled, the TX FIFO becomes empty.
The interrupt is cleared by writing to the TX Holding Register or TX FIFO if FIFO enabled.
ch TE
Modem Status Change Interrupt: A Modem Status Change Interrupt (IIR[5:0] = 000000b) is generated if EDSSI
(IER[3]) is set and either DDCD, TERI, DDSR or DCTS (MSR[3:0]) becomes set. The interrupt is cleared by
reading the Modem Status Register.
Software Flow Control Interrupt: A Software Flow Control Interrupt (IIR[5:0] = 010000b) is generated if
am IA
Software Flow Control is enabled and XOFFI (IER[5]) becomes set, indicating that an XOFF character has been
received. The interrupt is cleared by reading the Interrupt Identification Register.
Hardware Flow Control Interrupt: A Hardware Flow Control Interrupt (IER[5:0] = 100000b) is generated if
Hardware Flow Control is enabled and either RTSI (IER[6]) or CTSI (IER[7]) becomes set indicating that a
ad ED
rising edge has been detected on either the RTS/CTS Modem Control line. The interrupt is cleared by reading
the Interrupt Identification Register.
UARTn+0008h FIFO Control Register UARTn_FCR
M
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RFTL1 RFTL0 TFTL1 TFTL0 DMA1 CLRT CLRR FIFOE
Type WO
FCR FCR is used to control the trigger levels of the FIFOs, or flush the FIFOs.
FCR[7:6] is modified when LCR != BFh
FCR[5:4] is modified when LCR != BFh & EFR[4] = 1
OR
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FCR[4:0] is modified when LCR != BFh
FCR[7:6] RX FIFO trigger threshold
EO
0 1
US L
1 6
2 12
.tw IA
3 RXTRIG
FCR[5:4] TX FIFO trigger threshold
0 1
om NT
1 4
2 8
3 14 (FIFOSIZE - 2)
DMA1 This bit determines the DMA mode, which the TXRDY and RXRDY pins support. TXRDY and
x.c E
RXRDY act to support single-byte transfers between the UART and memory (DMA mode 0) or
multiple byte transfers (DMA mode1). Note that this bit has no effect unless the FIFOE bit is set as
ne FID
well
0 The device operates in DMA Mode 0.
1 The device operates in DMA Mode 1.
TXRDY – mode0: Goes active (low) when the TX FIFO or the TX Holding Register is empty.
Becomes inactive when a byte is written to the Transmit channel.
syn ON
TXRDY – mode1: Goes active (low) when there are no characters in the TX FIFO. Becomes inactive
when the TX FIFO is full.
RXRDY – mode0: Becomes active (low) when at least one character is in the RX FIFO or the RX
Buffer Register is full. Becomes inactive when there are no more characters in the RX FIFO or
@ C
RX Buffer register.
RXRDY – mode1: Becomes active (low) when the RX FIFO Trigger Level is reached or an RX FIFO
Character Timeout occurs. Goes inactive when the RX FIFO is empty.
ien K
CLRT Clear Transmit FIFO. This bit is self-clearing.
0 Leave TX FIFO intact.
ch TE
1 Clear all the bytes in the TX FIFO.
CLRR Clear Receive FIFO. This bit is self-clearing.
0 Leave RX FIFO intact.
1 Clear all the bytes in the RX FIFO.
am IA
FIFOE FIFO Enabled. This bit must be set to 1 for any of the other bits in the registers to have any effect.
0 Disable both the RX and TX FIFOs.
1 Enable both the RX and TX FIFOs.
ad ED
UARTn+000Ch Line Control Register UARTn_LCR
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DLAB SB SP EPS PEN STB WLS1 WLS0
M
Type R/W
Reset 0 0 0 0 0 0 0 0
LCR Line Control Register. Determines characteristics of serial communication signals.
Modified when LCR[7] = 0.
DLAB Divisor Latch Access Bit.
OR
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0 The RX and TX Registers are read/written at Address 0 and the IER register is read/written at
Address 4.
EO
1 The Divisor Latch LS is read/written at Address 0 and the Divisor Latch MS is read/written at
US L
Address 4.
SB Set Break
.tw IA
0 No effect
1 SOUT signal is forced into the “0” state.
SP Stick Parity
om NT
0 No effect.
1 The Parity bit is forced into a defined state, depending on the states of EPS and PEN:
If EPS=1 & PEN=1, the Parity bit is set and checked = 0.
If EPS=0 & PEN=1, the Parity bit is set and checked = 1.
x.c E
EPS Even Parity Select
0 When EPS=0, an odd number of ones is sent and checked.
ne FID
1 When EPS=1, an even number of ones is sent and checked.
PEN Parity Enable
0 The Parity is neither transmitted nor checked.
1 The Parity is transmitted and checked.
STB Number of STOP bits
syn ON
0 One STOP bit is always added.
1 Two STOP bits are added after each character is sent; unless the character length is 5 when 1 STOP
bit is added.
WLS1, 0 Word Length Select.
@ C
0 5 bits
1 6 bits
2 7 bits
ien K
3 8 bits
ch TE
UARTn+0010h Modem Control Register UARTn_MCR
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XOFF
DCM_
Name STATU X OUT2 OUT1 RTS DTR
EN
am IA
S
Type R/W
Reset 0 0 0 0 0 0 0
MCR Modem Control Register. Control interface signals of the UART.
ad ED
MCR[4:0] are modified when LCR[7] = 0,
MCR[7:6] are modified when LCR[7] = 0 & EFR[4] = 1.
XOFF Status This is a read-only bit.
0 When an XON character is received.
M
1 When an XOFF character is received.
DCM_EN UART DCM function enable bit
0 UART DCM is disabled.
1 UART DCM is enabled.
OUT2 Controls the state of the output NOUT2, even in loop mode.
0 NOUT2=1.
OR
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1 NOUT2=0.
OUT1 Controls the state of the output NOUT1, even in loop mode.
EO
0 NOUT1=1.
US L
1 NOUT1=0.
RTS Controls the state of the output NRTS, even in loop mode.
.tw IA
0 NRTS=1.
1 NRTS=0.
DTR Control the state of the output NDTR, even in loop mode.
om NT
0 NDTR=1.
1 NDTR=0.
UARTn+0014h Line Status Register UARTn_LSR
x.c E
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFOE
Name TEMT THRE BI FE PE OE DR
RR
ne FID
Type R/W
Reset 0 1 1 0 0 0 0 0
LSR Line Status Register.
Modified when LCR[7] = 0.
syn ON
FIFOERR RX FIFO Error Indicator.
0 No PE, FE, BI set in the RX FIFO.
1 Set to 1 when there is at least one PE, FE or BI in the RX FIFO.
TEMT TX Holding Register (or TX FIFO) and the TX Shift Register are empty.
0 Empty conditions below are not met.
@ C
1 If FIFOs are enabled, the bit is set whenever the TX FIFO and the TX Shift Register are empty. If
FIFOs are disabled, the bit is set whenever TX Holding Register and TX Shift Register are empty.
ien K
THRE Indicates if there is room for TX Holding Register or TX FIFO is reduced to its Trigger Level.
0 Reset whenever the contents of the TX FIFO are more than its Trigger Level (FIFOs are
ch TE
enabled), or whenever TX Holding Register is not empty(FIFOs are disabled).
1 Set whenever the contents of the TX FIFO are reduced to its Trigger Level (FIFOs are enabled), or
whenever TX Holding Register is empty and ready to accept new data (FIFOs are disabled).
BI Break Interrupt.
am IA
0 Reset by the CPU reading this register
1 If the FIFOs are disabled, this bit is set whenever the SIN is held in the 0 state for more than one
transmission time (START bit + DATA bits + PARITY + STOP bits).
ad ED
If the FIFOs are enabled, this error is associated with a corresponding character in the FIFO and is
flagged when this byte is at the top of the FIFO. When a break occurs, only one zero character is
loaded into the FIFO: the next character transfer is enabled when SIN goes into the marking state
and receives the next valid start bit.
M
FE Framing Error.
0 Reset by the CPU reading this register
1 If the FIFOs are disabled, this bit is set if the received data did not have a valid STOP bit. If the
FIFOs are enabled, the state of this bit is revealed when the byte it refers to is the next to be read.
PE Parity Error
0 Reset by the CPU reading this register
OR
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1 If the FIFOs are disabled, this bit is set if the received data did not have a valid parity bit. If the
FIFOs are enabled, the state of this bit is revealed when the referred byte is the next to be read.
EO
OE Overrun Error.
US L
0 Reset by the CPU reading this register.
1 If the FIFOs are disabled, this bit is set if the RX Buffer was not read by the CPU before new data
.tw IA
from the RX Shift Register overwrote the previous contents.
If the FIFOs are enabled, an overrun error occurs when the RX FIFO is full and the RX Shift
Register becomes full. OE is set as soon as this happens. The character in the Shift Register is
om NT
then overwritten, but not transferred to the FIFO.
DR Data Ready.
0 Cleared by the CPU reading the RX Buffer or by reading all the FIFO bytes.
1 Set by the RX Buffer becoming full or by a byte being transferred into the FIFO.
x.c E
Bit
Name
Type
15
ne FID
UARTn+0018h Modem Status Register
14 13 12 11 10 9 8 7
DCD
R/W R/W
6
RI
5
DSR
R/W
4
CTS
R/W
3
DDCD
R/W
2
UARTn_MSR
TERI
R/W
1
DDSR DCTS
R/W
0
R/W
Reset Input Input Input Input 0 0 0 0
syn ON
Note: After a reset, D4-D7 are inputs. A modem status interrupt can be cleared by writing ‘0’ or set by writing
‘1’ to this register. D0-D3 can be written to.
Modified when LCR[7] = 0.
MSR Modem Status Register
@ C
DCD Data Carry Detect.
When Loop = "0", this value is the complement of the NDCD input signal.
When Loop = "1", this value is equal to the OUT2 bit in the Modem Control Register.
ien K
RI Ring Indicator.
When Loop = "0", this value is the complement of the NRI input signal.
ch TE
When Loop = "1", this value is equal to the OUT1 bit in the Modem Control Register.
DSR Data Set Ready
When Loop = "0", this value is the complement of the NDSR input signal.
When Loop = "1", this value is equal to the DTR bit in the Modem Control Register.
am IA
CTS Clear To Send.
When Loop = "0", this value is the complement of the NCTS input signal.
When Loop = "1", this value is equal to the RTS bit in the Modem Control Register.
ad ED
DDCD Delta Data Carry Detect.
0 The state of DCD has not changed since the Modem Status Register was last read
1 Set if the state of DCD has changed since the Modem Status Register was last read.
TERI Trailing Edge Ring Indicator
M
0 The NRI input does not change since this register was last read.
1 Set if the NRI input changes from “0” to “1” since this register was last read.
DDSR Delta Data Set Ready
0 Cleared if the state of DSR has not changed since this register was last read.
1 Set if the state of DSR has changed since this register was last read.
DCTS Delta Clear To Send
OR
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Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
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0 Cleared if the state of CTS has not changed since this register was last read.
1 Set if the state of CTS has changed since this register was last read.
EO
UARTn+001Ch Scratch Register UARTn_SCR
US L
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
.tw IA
Name SCR[7:0]
Type R/W
A general purpose read/write register. After reset, its value is un-defined.
om NT
Modified when LCR[7] = 0.
UARTn+0000h Divisor Latch (LS) UARTn_DLL
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DLL[7:0]
x.c E
Type R/W
Reset 1
Bit
Name
Type
15 ne FID
UARTn+0004h Divisor Latch (MS)
14 13 12 11 10 9 8 7 6 5 4
DLL[7:0]
R/W
3
UARTn_DLM
2 1 0
Reset 0
syn ON
Note: DLL & DLM can only be updated if DLAB is set (“1”).. Note too that division by 1 generates a BAUD signal
that is constantly high.
Modified when LCR[7] = 1.
The table below shows the divisor needed to generate a given baud rate from CLK inputs of 13, 26 MHz and
@ C
52 MHz. The effective clock enable generated is 16 x the required baud rate.
BAUD 13MHz 26MHz 52MHz
110 7386 14773 29545
ien K
300 2708 5417 10833
1200 677 1354 2708
ch TE
2400 338 677 1354
4800 169 339 677
9600 85 169 339
am IA
19200 42 85 169
38400 21 42 85
57600 14 28 56
ad ED
115200 6 14 28
Table 2 Divisor needed to generate a given baud rate
UARTn+0008h Enhanced Feature Register UARTn_EFR
M
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AUTO AUTO ENABLE
Name D5 SW FLOW CONT[3:0]
CTS RTS -E
Type R/W R/W R/W R/W R/W
Reset 0 0 0 0 0
*NOTE: Only when LCR=BF’h
OR
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MT7628 PROGRAMMING GUIDE Confidential B
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Auto CTS Enables hardware transmission flow control
0 Disabled.
EO
1 Enabled.
US L
Auto RTS Enables hardware reception flow control
0 Disabled.
.tw IA
1 Enabled.
Enable-E Enable enhancement features.
0 Disabled.
om NT
1 Enabled.
CONT[3:0] Software flow control bits.
00xx No TX Flow Control
10xx Transmit XON1/XOFF1 as flow control bytes
x.c E
01xx Transmit XON2/XOFF2 as flow control bytes
11xx Transmit XON1 & XON2 and XOFF1 & XOFF2 as flow control words
ne FID
xx00 No RX Flow Control
xx10 Receive XON1/XOFF1 as flow control bytes
xx01 Receive XON2/XOFF2 as flow control bytes
xx11 Receive XON1 & XON2 and XOFF1 & XOFF2 as flow control words
syn ON
UARTn+0010h XON1 UARTn_XON1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name XON1[7:0]
Type R/W
Reset 0
@ C
ien K
UARTn+0014h XON2 UARTn_XON2
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name XON2[7:0]
ch TE
Type R/W
Reset 0
UARTn+0018h XOFF1 UARTn_XOFF1
am IA
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name XOFF1[7:0]
Type R/W
ad ED
Reset 0
UARTn+001Ch XOFF2 UARTn_XOFF2
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M
Name XOFF2[7:0]
Type R/W
Reset 0
*Note: XON1, XON2, XOFF1, XOFF2 are valid only when LCR=BFh.
OR
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MT7628 PROGRAMMING GUIDE Confidential B
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UARTn+0024h HIGH SPEED UART UARTn_HIGHSPEED
EO
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name SPEED [1:0]
US L
Type R/W
Reset 0
.tw IA
SPEED UART sample counter base
0 based on 16*baud_pulse, baud_rate = system clock frequency/16/{DLH, DLL}
1 based on 8*baud_pulse, baud_rate = system clock frequency/8/{DLH, DLL}
om NT
2 based on 4*baud_pulse, baud_rate = system clock frequency/4/{DLH, DLL}
3 based on sampe_count * baud_pulse, baud_rate = system clock frequency / sampe_count
When HIGHSPEED=3, the value (A * B) means ({DLM, DLL} * SAMPLE_COUNT).
When the Baudrate is more than 115200, it will be more accurate if we set HIGHSPEED=3.
x.c E
The table below shows the divisor needed to generate a given baud rate from CLK inputs of 13M Hz based on
different HIGHSPEED value.
ne FID
BAUD HIGHSPEED = 0 HIGHSPEED = 1 HIGHSPEED = 2 HIGHSPEED = 3
110 7386 14773 29545 7386 * 16
300 2708 7386 14773 2708 * 16
1200 677 2708 7386 677 * 16
syn ON
2400 338 677 2708 338 * 16
4800 169 338 677 169 * 16
9600 85 169 338 85 * 16
19200 42 85 169 9 * 75
@ C
38400 21 42 85 13 * 26
57600 14 21 42 8 * 28
ien K
115200 7 14 21 4 * 28
230400 * 7 14 2 * 28
ch TE
460800 * * 7 1 * 28
921600 * * * 1 * 14
Table 3 Divisor needed to generate a given baud rate from 13MHz based on different HIGHSPEED value
am IA
The table below shows the divisor needed to generate a given baud rate from CLK inputs of 26 MHz based on
different HIGHSPEED value.
ad ED
BAUD HIGHSPEED = 0 HIGHSPEED = 1 HIGHSPEED = 2 HIGHSPEED = 3
110 14773 29545 59091 7386 * 32
300 5417 14773 29545 2708 * 32
1200 1354 5417 14773 677 * 32
M
2400 677 1354 5417 338 * 32
4800 339 677 1354 169 * 32
9600 169 339 667 85 * 32
19200 85 169 339 18 * 75
38400 42 85 169 26 * 26
OR
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MT7628 PROGRAMMING GUIDE Confidential B
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57600 28 42 85 16 * 28
115200 14 28 42 8 * 28
EO
230400 7 14 28 4 * 28
US L
460800 * 7 14 2 * 28
.tw IA
921600 * * 7 1 * 28
Table 4 Divisor needed to generate a given baud rate from 26 MHz based on different HIGHSPEED value
om NT
The table below shows the divisor needed to generate a given baud rate from CLK inputs of 52MHz based on
different HIGHSPEED value.
BAUD HIGHSPEED = 0 HIGHSPEED = 1 HIGHSPEED = 2 HIGHSPEED = 3
110 29545 59091 118182 14773 * 32
x.c E
300 10833 29545 59091 5417 * 32
1200 2708 10833 29545 1354 * 32
ne FID
2400 1354 2708 10833 667 * 32
4800 677 1354 2708 339 * 32
9600 339 677 1354 169 * 32
19200 169 339 677 36 * 75
syn ON
38400 85 169 339 52 * 26
57600 56 85 169 32 * 28
115200 28 56 85 16 * 28
@ C
230400 14 28 56 8 * 28
460800 7 14 28 4 * 28
ien K
921600 * 7 14 2 * 28
Table 5 Divisor needed to generate a given baud rate from 52 MHz based on different HIGHSPEED value
ch TE
UARTn+0028h SAMPLE_COUNT UARTn_SAMPLE_COUNT
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
am IA
Name SAMPLECOUNT [7:0]
Type R/W
Reset 0
ad ED
When HIGHSPEED=3, the sample_count is the threshold value for UART sample counter (sample_num).
Count from 0 to sample_count.
M
UARTn+002Ch SAMPLE_POINT UARTn_SAMPLE_POINT
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name SAMPLEPOINT [7:0]
Type R/W
Reset Ffh
When HIGHSPEED=3, UART gets the input data when sample_count=sample_num.
OR
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MT7628 PROGRAMMING GUIDE Confidential B
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e.g. system clock = 13MHz, 921600 = 13000000 / 14
sample_count = 14 and sample point = 7 (sample the central point to decrease the inaccuracy)
EO
The SAMPLE_POINT is usually (SAMPLE_COUNT/2).
US L
.tw IA
UARTn+0034h Rate Fix Address UARTn_RATEFIX_AD
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RXTE_FIX
Type R/W
om NT
Reset 0
rate_fix When you set "rate_fix"(34H[0]), you can transmit and receive data only if
the input f16m_en is enable.
x.c E
Bit
Name
ne FID
UARTn+003Ch Guard time added register
15 14 13 12 11 10 9 8 7 6 5 4
GUARD_EN
UARTn_GUARD
3 2
GUARD_CNT[3:0]
1 0
Type R/W R/W R/W R/W R/W
syn ON
Reset 0 0 0 0 0
GUARD_CNT Guard interval count value. Guard interval = (1/(system clock / div_step / div )) *
GUARD_CNT.
GUARD_EN Guard interval add enable signal.
@ C
0 No guard interval added.
1 Add guard interval after stop bit.
ien K
UARTn+0040h Escape character register UARTn_ESCAPE_DAT
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ch TE
Name ESCAPE_DAT[7:0]
Type WO
Reset FFh
ESCAPE_DAT Escape character added before software flow control data and escape character, i.e. if tx data is
am IA
xon (31h), with esc_en =1, uart transmits data as esc + CEh (~xon).
UARTn+0044h Escape enable register UARTn_ESCAPE_EN
ad ED
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name ESC_EN
Type R/W
Reset 0
M
ESC_EN Add escape character in transmitter and remove escape character in receiver by UART.
0 Do not deal with the escape character.
1 Add escape character in transmitter and remove escape character in receiver.
UARTn+0048h Sleep enable register UARTn_SLEEP_EN
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name SELLP_EN
OR
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MT7628 PROGRAMMING GUIDE Confidential B
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Type R/W
Reset 0
EO
SLEEP_EN For sleep mode issue
US L
0 Do not deal with sleep mode indicate signal
1 To activate hardware flow control or software control according to software initial setting when
.tw IA
chip enters sleep mode. Releasing hardware flow when chip wakes up; but for software control,
uart sends xon when awaken and when FIFO does not reach threshold level.
om NT
UARTn+004Ch Virtual FIFO enable register UARTn_VFIFO_EN
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name VFIFO_EN
Type R/W
Reset 0
x.c E
VFIFO_EN Virtual FIFO mechanism enable signal.
ne FID
0 Disable VFIFO mode.
1 Enable VFIFO mode. When virtual mode is enabled, the flow control is based on the DMA
threshold, and generates a timeout interrupt for DMA.
UARTn+0050h Rx Trigger Address UARTn_RXTRI_AD
syn ON
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RXTRIG[3:0]
Type R/W
Reset 0
RXTRIG When {rtm,rtl}=2’b11, The Rx FIFO threshold will be Rxtrig.
@ C
UARTn+0054h Fractional Divider LSB Address UARTn_FRACDIV_L
ien K
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name FRACDIV_L
ch TE
Type R/W
Reset 0 0 0 0 0 0 0 0
FRACDIV_L Add sampling count (+1) from state data7 to state data0, in order to contribute fractional
divisor.
am IA
UARTn+0058h Fractional Divider MSB Address UARTn_FRACDIV_M
ad ED
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name FRACDIV_M
Type R/W
Reset 0 0
M
FRACDIV_M Add sampling count in state stop and state parity, in order to contribute fractional divisor.
FRACDIV_L / FRACDIV_L Add one sampling period to each symbol, in order to increase the baud rate
accuracy.
bit_extend register = FRACDIV_L[7:0]
OR
FRACDIV_M[1:0]
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EO
US L
.tw IA
om NT
x.c E
UARTn+005Ch FIFO Control Register UARTn_FCR_RD
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ne FID
Name RFTL1 RFTL0 TFTL1 TFTL0 DMA1 FIFOE
Type RO RO
Read out UARTn_FCR register.
syn ON
UARTn+0060h TX Active Enable Address UARTn_TX_ACTIVE_EN
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name TX_PU_EN TX_OE_EN
Type R/W R/W
@ C
Reset 0 0
TX_OE_EN Enable UART_TX_OE switching function. TX_OE is to control UART_TX output enable.
ien K
TX_PU_EN Enable UART_TX_PU switching function. TX_PU is to control UART_TX pull up enable.
ch TE
am IA
ad ED
OR M
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2.14 PCM Controller
EO
2.14.1 Features
US L
Two clock sources are reserved for PCM circuit. (From internal clock generator, INT_PCM_CLK and
EXT_PCM_CLK)
.tw IA
PCM module can drive a clock out (with fraction-N dividor) to an external codec.
Up to 4 channels PCM are available. 4 to 128 slots are configurable.
Each channel supports a-law (8-bit)/u-law (8-bit)/raw-PCM (8-bit and 16-bit) transfer.
Hardware converter of a-law<->raw-16 and u-law <-> raw-16 are implemented in design.
om NT
Support long (8 cycle)/short (1 cycle)/configurable (intervals are configurable, use to emulate I S
2
interface) FSYNC.
DATA & FSYNC can be driven and sampled by either rising/falling of clock.
Last bit of DTX can be configured as tri-stated on falling edge.
x.c E
Beginning of each slot is configurable by 10-bit registers on each channel.
32-byte FIFO are available for each channel
ne FID
PCM interface can emulate I2S interface (only 16-bit data-width supported ).
MSB/LSB order is configurable.
Supports both a-law/u-law (8-bits) linear PCM(16-bit) and linear PCM(16-bit) a-law/u-law (8-bit)
2.14.2 Block Diagram
PCM Module
syn ON
APBBUS
PCM Control
APBBUS LTF
Status Register
@ C
ien K
RFIFO TFIFO RFIFO TFIFO
(32 bytes) (32 bytes) (32 bytes) (32 bytes)
ch TE
DRAM CH1 CH0
GDMA LTF
am IA
a/ulaw a/ulaw
SYS clock domain
ad ED
PCM clock domain
PCM IF/I2S IF
M
Figure 2-8 PCM Controller Block Diagram
Two clock domains are partitioned in this design. PCM converter (u-law < = > raw-16-bit and A-law < = > raw
16-bit) are implemented in PCM. The threshold of FIFO is configurable. When the threshold is reached, PCM (a)
triggers the DMA interface to notify external DMA engine to transfer data, and (b) triggers an interrupt to the
host.
OR
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The interrupt sources include:
The threshold is reached.
EO
FIFO is under-run or over-run.
A fault is detected at the DMA interface.
US L
The A-law and u-law converter is implemented based on the ITU-G.711 A-law and u-law table. In this design,
both A-law/u-law(8-bit) linear PCM (16-bit) and linear PCM (16-bit) A-law/u-law (8-bit) are supported.
.tw IA
The data-flow from codec to PCM-controller (Rx-flow) is shown as below:
The PCM controller latches the data from DRX at the indicated time slot and then writes it to FIFO. If FIFO
om NT
is full, the data is lost.
When the Rx-FIFO reaches the threshold, two actions may be taken:
When DMA_ENA=1, DMA_REQ is asserted to request a burst transfer. It rechecks the FIFO threshold
after DMA_END is asserted by GDMA. (GDMA should be configured before channel is enabled.)
Assert the interrupt source to notify the host. The host can check RFIFO_AVAIL information then get
x.c E
back the data from FIFO.
ne FID
The data flow from the PCM controller to codec (Tx-flow) is shown below. After GDMA is configured, software
should configure and enable the PCM channel. The empty FIFO should behave as follows.
When DMA_ENA=1, DMA_REQ is triggered to request a burst transfer. It then re-checks the FIFO
threshold after DMA_END is asserted by GDMA (a burst is completed).
The Interrupt source is asserted to notify HOST. HOST writes the data to Tx-FIFO. After that, HOST
rechecks TFIFO_EMPTY information, and then writes more data if available.
syn ON
NOTE: When DMA_ENA=1, the burst size of GDMA should be less than the threshold value.
@ C
2.14.3 List of Registers
2.14.4 PCM Configuration
ien K
PCM Initialization Flow
1. Set PCM_CFG
ch TE
2. Set CH0/1_CFG
3. Write PCM data to FIFO CH0/1_FIFO
4. Set GLB_CFG to enable the PCM and channel.
5. Set dividor clock
6. Enable clock
am IA
7. Monitor FF_STATUS to receive/transmit the other PCM data.
PCM Configuration Examples
ad ED
Below are some examples of PCM configuration.
Case 1:
CFG_FSYNC Register: CFG_FSYNC_EN = 0 (PS: fsync is always driven at SLOT_CNT=1)
CH0_CFG Register: TS_START=1
M
CH1_CFG Register: TS_START=9
PCM_CFG Register: LONG_FSYNC=1’b0, FSYNC_POL=1’b1, DRX_TRI=1’b0, SLOT_MODE=3’b0
OR
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MT7628 PROGRAMMING GUIDE Confidential B
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EO
US L
.tw IA
om NT
Case 2:
CFG_FSYNC Register: CFG_FSYNC_EN = 1, START_LOC=0, interval=16
CH0_CFG Register: TS_START=1
x.c E
CH1_CFG Register: TS_START=17
PCM_CFG Register: LONG_FSYNC=1’b0, FSYNC_POL=1’b1, DRX_TRI=1’b0, SLOT_MODE=3’b0, RAW16-bits
ne FID
syn ON
@ C
ien K
Case 3:
ch TE
CFG_FSYNC Register: CFG_FSYNC_EN = 1, START_LOC=0x1A, interval=2
CH0_CFG Register: TS_START=1 (disable)
CH1_CFG Register: TS_START=0x1A
PCM_CFG Register: LONG_FSYNC=1’b0, FSYNC_POL=1’b0 (LOW active), DRX_TRI=1’b0, SLOT_MODE=3’b0,
am IA
RAW16-bits
ad ED
OR M
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2.14.5 Register
EO
PCM Changes LOG
US L
Revision Date Author Change Log
0.1 2012/10/8 Paddy Wu Initialization
.tw IA
Module name: PCM Base address: (+10002000h)
om NT
Address Name Widt Register Function
h
10002000 GLB_CFG 32 Global Config
10002004 PCM_CFG 32 PCM configuration
x.c E
10002008 INT_STATUS 32 Interrupt status
1000200C INT_EN 32 Interrupt enable
ne FID
CHA0_FF_STA
10002010 TUS 32 Channel A0(represents channel 0) FIFO status
10002014 CHB0_FF_STA 32 Channel B0(represents channel 1) FIFO status
TUS
10002020 CHA0_CFG 32 Channel A0(represents channel 0) Config
10002024 CHB0_CFG 32 Channel B0(represents channel 1) Config
syn ON
10002030 FSYNC_CFG 32 FSYNC config
10002034 CHA0_CFG2 32 Channel A0(represents channel 0) Config
10002038 CHB0_CFG2 32 Channel B0(represents channel 1) Config
10002040 IP_INFO 32 IP version info
10002044 RSV_REG16 32 SPARE REG 16 bits
@ C
10002050 DIVCOMP_CFG 32 Dividor Compensation part config
10002054 DIVINT_CFG 32 Dividor Integer part config
DIGDELAY_CF
ien K
10002060 G 32 Digital delay config
10002080 CH0_FIFO 32 Channel 0 FIFO access point
ch TE
10002084 CH1_FIFO 32 Channel 1 FIFO access point
10002088 CH2_FIFO 32 Channel 2 FIFO access point
1000208C CH3_FIFO 32 Channel 3 FIFO access point
CHA1_FF_STA
10002110 TUS 32 Channel A1(represents channel 3) FIFO status
am IA
10002114 CHB1_FF_STA 32 Channel B1(represents channel 4) FIFO status
TUS
10002120 CHA1_CFG 32 Channel A1(represents channel 3) Config
ad ED
10002124 CHB1_CFG 32 Channel B1(represents channel 1) Config
10002134 CHA1_CFG2 32 Channel A1(represents channel 3) Config
10002138 CHB1_CFG2 32 Channel B1(represents channel 4) Config
M
0044000
10002000 GLB_CFG Global Config
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EXT
PC DM LB
_LB RS
Name M_ A_E K_E RSV0 RFF_THRES TFF_THRES
K_E V1
EN N N
N
OR
MediaTek Confidential © 2014 MediaTek Inc. Page 138 of 347
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Type RW RW RW RW RO RW RO RW
Reset 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0
EO
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RSV2 CH_EN
US L
Type RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
.tw IA
Bit(s) Name Description
31 PCM_EN PCM Enable
When disabled, all FSM of PCM are cleared to their default value.
om NT
0: disable
1: enable
30 DMA_EN DMA Enable
0: Disable the DMA interface, transfer data using software.
1: Enable the DMA interface, transfer data using DMA.
x.c E
0: disable
1: enable
29 LBK_EN loopback enable, loopback path is shown as (Asyn-TXFIFO ->DTX ->
ne FID
DRX->Asyn-RXFIFO)
0: disable
1: enable
28 EXT_LBK_EN loopback enable, loopback path is shown as (Ext-Codec->DRX->DTX-
>Ext-Codec)
0: disable
syn ON
1: enable
27:23 RSV0 Reserved
22:20 RFF_THRES RXFIFO Threshold
When the threshold is reached, the host/DMA is notified to fill FIFO. The
threshold should be >2 and <6.
@ C
When data in FIFO is under the threshold, the following interrupts and GDMA
are triggered.
CH0T_THRES, CH0R_THRES, CH1T_THRES, CH1R_THRES
(unit: word)
ien K
19 RSV1 Reserved
18:16 TFF_THRES TXFIFO Threshold
ch TE
When the threshold is reached, the host/DMA is notified to fill FIFO.
It should be >2 and <6.
When data in FIFO is over the threshold, an interrupt and DMA are triggered.
(unit: word)
15:4 RSV2 Reserved
am IA
3:0 CH_EN Channels 3 to 0 Tx and Rx Enable
0: disable
1: enable
ad ED
0300000
10002004 PCM_CFG PCM configuration
0
M
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CL EXT LO FSY
DT
RS KO _FS NG NC
Name RSV1 X_T RSV2[20:13]
V0 UT_ YN _SY _P
RI
EN C NC OL
Type RO RW RO RW RW RW RW RO
Reset 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RSV2[12:0] SLOT_MODE
Type RO RW
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
EO
Bit(s) Name Description
31 RSV0 Reserved
US L
30 CLKOUT_EN PCM Clock Out Enable
0: A PCM clock is provided from the external Codec/OSC.
.tw IA
1: A PCM clock is provided from the internal dividor.
NOTE: Normally, the register should be asserted to 1. Also, it should be
asserted after configuring the divider and enabling the divider clock.
0: EXT_CLK
om NT
1: INT_DIV
29:28 RSV1 Reserved
27 EXT_FSYNC FSYNC is provided externally
0: FSYNC is generated by internal circuit.
1: FSYNC is provided externally
x.c E
26 LONG_SYNC FSYNC Mode
0: Short FSYNC
ne FID
1: Long FSYNC
25 FSYNC_POL FSYNC Polarity
0: FSYNC is low active
1: FSYNC is high active
24 DTX_TRI DTX Tri-State
syn ON
Tristates DTX when the clock signal on the last bit is has a falling edge.
0: Non- tristate DTX
1: Tristate DTX
23:3 RSV2 Reserved
2:0 SLOT_MODE Sets the number of slots in each PCM frame.
@ C
0: 4 slots, PCM clock out/in should be 256 KHz.
1: 8 slots, PCM clock out/in should be 512 KHz.
2: 16 slots, PCM clock out/in should be 1.024 MHz.
3: 32 slots, PCM clock out/in should be 2.048 MHz.
ien K
4: 64 slots, PCM clock out/in should be 4.096 MHz.
5:128 slots, PCM clock out/in should be 8.192 MHz.
Other: Reserved.
NOTE: When using the external clock, the frequency clock should be equal to
ch TE
PCM_clock out. Otherwise, the PCM_CLKin should be 8.192 MHz.
0: _4_SLOT
1: _8_SLOT
2: _16_SLOT
3: _32_SLOT
am IA
4: _64_SLOT
5: _128_SLOT
ad ED
0000000
10002008 INT_STATUS Interrupt status
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RSV0[23:8]
M
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH
CH CH CH
CH CH CH R_ CH
T_D R_ R_
T_O T_U T_T DM R_T
Name RSV0[7:0] MA
VR NR HR A_F
OV UN
HR
_FA RU RU
UN UN ES AU ES
ULT N N
LT
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
W1 W1 W1 W1 W1 W1 W1 W1
Type RO
C C C C C C C C
Reset
EO
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
US L
Bit(s) Name Description
31:8 RSV0 Reserved
.tw IA
7 CHT_DMA_FAULT Channel Tx DMA Fault Interrupt, Asserts when a fault has been detected
in a CH-Tx DMA signal.
6 CHT_OVRUN Channel Tx FIFO Overrun Interrupt, Asserts when the CH-Tx FIFO is
overrun.
om NT
5 CHT_UNRUN Channel Tx FIFO Underrun Interrupt, Asserts when the CH-Tx FIFO is
underrun.
4 CHT_THRES Channel Tx Threshold Interrupt, Asserts when the CH-Tx FIFO is lower
than the defined threshold.
x.c E
3 CHR_DMA_FAULT Channel Rx DMA Fault Interrupt, Asserts when a fault is detected in a
CH-Rx DMA signal.
2 CHR_OVRUN Channel Rx Overrun Interrupt, Asserts when the CH-Rx FIFO is overrun.
ne FID
1 CHR_UNRUN Channel Rx Underrun Interrupt, Asserts when the CH-Rx FIFO is
underrun.
0 CHR_THRES Channel Rx Threshold Interrupt, Asserts when the CH-Rx FIFO is lower
than the defined threshold.
syn ON
0000000
1000200C INT_EN Interrupt enable
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RSV0[23:8]
@ C
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INT INT INT INT INT INT INT INT
ien K
Name RSV0[7:0] 7_E 6_E 5_E 4_E 3_E 2_E 1_E 0_E
N N N N N N N N
Type RO RW RW RW RW RW RW RW RW
ch TE
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:8 RSV0 Reserved
am IA
7 INT7_EN INT_STATUS[7] Enable,Enables the Channel Tx DMA Fault Interrupt.
This interrupt asserts when a fault has been detected in a CH-Tx DMA
signal.
6 INT6_EN INT_STATUS[6] Enable,Enables the Channel Tx FIFO Overrun Interrupt.
ad ED
This interrupt asserts when the CH-Tx FIFO is overrun.
5 INT5_EN INT_STATUS[5] Enable,Enables the Channel Tx FIFO Underrun
Interrupt. This interrupt asserts when the CH-Tx FIFO is underrun.
4 INT4_EN INT_STATUS[4] Enable,Enables the Channel Tx Threshold Interrupt.
This interrupt when the CH-Tx FIFO is lower than the defined threshold.
M
3 INT3_EN INT_STATUS[3] Enable,Enables the Channel Rx DMA Fault Interrupt.
This interrupt when a fault is detected in a CH-Rx DMA signal.
2 INT2_EN INT_STATUS[2] Enable,Enables the Channel Rx Overrun Interrupt. This
interrupt when the CH-Rx FIFO is overrun.
1 INT1_EN INT_STATUS[1] Enable,Enables the Channel Rx Underrun Interrupt. This
interrupt when the CH-Rx FIFO is under-run.
0 INT0_EN INT_STATUS[0] Enable,Enables the Channel Rx Threshold Interrupt.
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Bit(s) Name Description
This interrupt asserts when the CH-Rx FIFO is lower than the defined
EO
threshold.
US L
.tw IA
CHA0_FF_ST 0010000
10002010 Channel A0(represents channel 0) FIFO status
ATUS 8
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CH CH
om NT
CH CH CH CH CH CH
TX_ RX_
TX_ TX_ TX_ RX_ RX_ RX_
DM DM
Name RSV0 OV UN TH OV UN TH
A_F A_F
RU RU RE RU RU RE
AU AU
N N S N N S
LT LT
W1 W1 W1 W1 W1 W1 W1 W1
Type RO
x.c E
C C C C C C C C
Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ne FID
Name RSV1 CHRFF_AVCNT CHTFF_EPCNT
Type RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
Bit(s) Name Description
31:24 RSV0 Reserved
syn ON
23 CHTX_DMA_FAULT Tx DMA Fault Detected Interrupt,Asserts when a fault is detected in a
Channel A0 Tx DMA signal.
22 CHTX_OVRUN Tx Overrun Interrupt,Asserts when the Channel A0 Tx FIFO is overrun.
21 CHTX_UNRUN Tx FIFO Underrun Interrupt,Asserts when the Channel A0 Tx FIFO is
underrun.
@ C
20 CHTX_THRES Tx FIFO Below Threshold Interrupt,Asserts when the Channel A0 FIFO
is lower than the defined threshold.
19 CHRX_DMA_FAUL Rx DMA Fault Detected Interrupt,Asserts when a fault is detected in a
ien K
T Channel A0 Rx DMA signal.
18 CHRX_OVRUN Rx FIFO Overrun Interrupt,Asserts when the Channel A0 Rx FIFO is
overrun.
ch TE
17 CHRX_UNRUN Rx FIFO Underrun Interrupt,Asserts when the Channel A0 Rx FIFO is
underrun.
16 CHRX_THRES Rx FIFO Below Threshold Interrupt,Asserts when the Channel A0 FIFO
is lower than the defined threshold.
am IA
15:8 RSV1 Reserved
7:4 CHRFF_AVCNT Channel A0 RXFIFO Available Space Count,Counts the available space
for reads in channel A0 RXFIFO.(unit: word)
ad ED
3:0 CHTFF_EPCNT Channel A0 TXFIFO Available Space Count,Counts the available space
for writes in channel A0 TXFIFO.(unit: word)
CHB0_FF_ST 0010000
M
10002014 Channel B0(represents channel 1) FIFO status
ATUS 8
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CH CH
CH CH CH CH CH CH
TX_ RX_
TX_ TX_ TX_ RX_ RX_ RX_
DM DM
Name RSV0
A_F
OV UN TH
A_F
OV UN TH
RU RU RE RU RU RE
AU AU
N N S N N S
LT LT
OR
MediaTek Confidential © 2014 MediaTek Inc. Page 142 of 347
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
W1 W1 W1 W1 W1 W1 W1 W1
Type RO
C C C C C C C C
Reset
EO
0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
US L
RSV1 CHRFF_AVCNT CHTFF_EPCNT
Type RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
.tw IA
Bit(s) Name Description
31:24 RSV0 Reserved
om NT
23 CHTX_DMA_FAULT Tx DMA Fault Detected Interrupt,Asserts when a fault is detected in a
Channel B0 Tx DMA signal.
22 CHTX_OVRUN Tx Overrun Interrupt,Asserts when the Channel B0 Tx FIFO is overrun.
21 CHTX_UNRUN Tx FIFO Underrun Interrupt,Asserts when the Channel B0 Tx FIFO is
underrun.
x.c E
20 CHTX_THRES Tx FIFO Below Threshold Interrupt,Asserts when the Channel B0 FIFO
is lower than the defined threshold.
ne FID
19 CHRX_DMA_FAUL Rx DMA Fault Detected Interrupt,Asserts when a fault is detected in a
T Channel B0 Rx DMA signal.
18 CHRX_OVRUN Rx FIFO Overrun Interrupt,Asserts when the Channel B0 Rx FIFO is
overrun.
17 CHRX_UNRUN Rx FIFO Underrun Interrupt,Asserts when the Channel B0 Rx FIFO is
underrun.
syn ON
16 CHRX_THRES Rx FIFO Below Threshold Interrupt,Asserts when the Channel B0 FIFO
is lower than the defined threshold.
15:8 RSV1 Reserved
7:4 CHRFF_AVCNT Channel B0 RXFIFO Available Space Count,Counts the available space
for reads in channel B0 RXFIFO.(unit: word)
@ C
3:0 CHTFF_EPCNT Channel B0 TXFIFO Available Space Count,Counts the available space
for writes in channel B0 TXFIFO.(unit: word)
ien K
0000000
10002020 CHA0_CFG Channel A0(represents channel 0) Config
ch TE
1
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RSV0 CMP_MODE RSV1[16:6]
Type RO RW RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
am IA
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RSV1[5:0] TS_START
Type RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
ad ED
Bit(s) Name Description
31:30 RSV0 Reserved
29:27 CMP_MODE Compression Mode
Sets the conversion method for the hardware converter to compress raw
M
data.
000: Disable HW converter, linear raw data (16-bit)
010: Disable HW converter, linear raw data (8-bit), A-law or u-law (8-bit)
011: Reserved
100: Enable HW converter, raw data(16-bit) U-law mode (8-bit) (PCM bus in
compressed format)
101: Enable HW converter, u-law mode (8-bit) raw data (16-bit) (PCM bus in
raw, 16-bit format)
110: Enable HW converter, raw data (16-bit) A-law mode (8-bit) (PCM bus in
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Bit(s) Name Description
compressed format)
EO
111: Enable HW converter, A-law mode (8-bit) raw data (16-bit) (PCM bus in
raw, 16-bit format)
US L
0: DIS_CONV16
2: DIS_CONV8
4: EN_ULW2R
.tw IA
5: EN_R2ULW
6: EN_ALW2R
7: EN_R2ALW
26:10 RSV1 Reserved
om NT
9:0 TS_START Timeslot starting location
(unit: clock cycles)
x.c E
0000000
10002024 CHB0_CFG Channel B0(represents channel 1) Config
1
ne FID
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RSV0 CMP_MODE RSV1[16:6]
Type RO RW RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RSV1[5:0] TS_START
syn ON
Type RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Bit(s) Name Description
31:30 RSV0 Reserved
@ C
29:27 CMP_MODE Compression Mode
Sets the conversion method for the hardware converter to compress raw
data.
000: Disable HW converter, linear raw data (16-bit)
ien K
010: Disable HW converter, linear raw data (8-bit), A-law or u-law (8-bit)
011: Reserved
100: Enable HW converter, raw data(16-bit) U-law mode (8-bit) (PCM bus in
ch TE
compressed format)
101: Enable HW converter, u-law mode (8-bit) raw data (16-bit) (PCM bus in
raw, 16-bit format)
110: Enable HW converter, raw data (16-bit) A-law mode (8-bit) (PCM bus in
compressed format)
am IA
111: Enable HW converter, A-law mode (8-bit) raw data (16-bit) (PCM bus in
raw, 16-bit format)
0: DIS_CONV16
2: DIS_CONV8
4: EN_ULW2R
ad ED
5: EN_R2ULW
6: EN_ALW2R
7: EN_R2ALW
26:10 RSV1 Reserved
M
9:0 TS_START Timeslot starting location
(unit: clock cycles)
2800000
10002030 FSYNC_CFG FSYNC config
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
CF PO PO
PO PO
G_F S_C S_D
S_C S_D
EO
Name SY
AP_ RV_
AP_ RV_ RSV0 RSV1[11:6]
NC FSY FSY
DT DT
_EN NC NC
US L
Type RW RW RW RW RW RO RO
Reset 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0
.tw IA
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RSV1[5:0] FSYNC_INTV
Type RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
om NT
Bit(s) Name Description
31 CFG_FSYNC_EN Enables configurable FSYNC.
30 POS_CAP_DT Positive Edge Capture Data, Sets the PCM controller to capture data on
the negative or positive edge of the PCM clock. NOTE: This
x.c E
configuration should be 0 if DTX_TRI=1.
29 POS_DRV_DT Positive Edge Drive Data, Sets the PCM controller to drive data on the
negative or positive edge of the PCM clock.
ne FID
28 POS_CAP_FSYNC Positive Edge Capture FSYNC, Sets the PCM controller to capture
FSYNC on the positive or negative edge of the PCM clock.
27 POS_DRV_FSYNC Positive Edge Driver FSYNC, Sets the PCM controller to drive FSYNC on
the negative or positive edge of the PCM clock.
26:22 RSV0 Reserved
syn ON
21:10 RSV1 Reserved
9:0 FSYNC_INTV Interval when FSYNC may be configured.
(unit: clock cycles)
@ C
0000000
10002034 CHA0_CFG2 Channel A0(represents channel 0) Config
0
ien K
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RSV0[27:12]
Type RO
ch TE
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH CH
_RX _TX CH
RS
Name RSV0[11:0] FF_ FF_ _LS
V1
CL CL B
am IA
R R
Type RO RW RW RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ad ED
Bit(s) Name Description
31:4 RSV0 Reserved
3 CH_RXFF_CLR Channel A0 Rx FIFO Clear
0: Normal operation
1: Clear this bit
M
2 CH_TXFF_CLR Channel A0 Tx FIFO Clear
0: Normal operation
1: Clear this bit
1 RSV1 Reserved
0 CH_LSB Enable CH A0 Tx in LSB order.
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
0000000
10002038 CHB0_CFG2 Channel B0(represents channel 1) Config
EO
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
US L
Name RSV0[27:12]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
.tw IA
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH CH
_RX _TX CH
RS
Name RSV0[11:0] FF_ FF_ _LS
V1
om NT
CL CL B
R R
Type RO RW RW RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
x.c E
31:4 RSV0 Reserved
3 CH_RXFF_CLR Channel B0 Rx FIFO Clear
ne FID
0: Normal operation
1: Clear this bit
2 CH_TXFF_CLR Channel B0 Tx FIFO Clear
0: Normal operation
1: Clear this bit
syn ON
1 RSV1 Reserved
0 CH_LSB Enable CH B0 Tx in LSB order.
0000040
@ C
10002040 IP_INFO IP version info
1
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RSV0
ien K
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ch TE
Name MAX_CH VER
Type RO RO
Reset 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1
Bit(s) Name Description
am IA
31:16 RSV0 Reserved
15:8 MAX_CH Maximum channel number.
7:0 VER Version of this PCM Controller
ad ED
0000000
10002044 RSV_REG16 SPARE REG 16 bits
0
M
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RSV0
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name SPARE_REG
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
OR
MediaTek Confidential © 2014 MediaTek Inc. Page 146 of 347
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Bit(s) Name Description
EO
31:16 RSV0 Reserved
US L
15:0 SPARE_REG Spare register for future use
.tw IA
DIVCOMP_CF 0000000
10002050 Dividor Compensation part config
G 0
om NT
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CL
Name K_E RSV0[22:8]
N
Type RW RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
x.c E
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RSV0[7:0] DIVCOMP
Type RO RW
ne FID
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31 CLK_EN Clock Enable
Enables setting of the PCM interface clock based on DIVCOMP and DIVINT
syn ON
parameters.
30:8 RSV0 Reserved
7:0 DIVCOMP A parameter in an equation which determines FREQOUT. See DIVINT.
@ C
0000000
10002054 DIVINT_CFG Dividor Integer part config
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ien K
Name RSV0[21:6]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ch TE
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RSV0[5:0] DIVINT
Type RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
am IA
Bit(s) Name Description
31:10 RSV0 Reserved
9:0 DIVINT A parameter in an equation which determines FREQOUT.
ad ED
Formula:
FREQOUT = 1/(FREQIN*2*(DIVINT+DIVCOMP /(2^8)))
FREQIN is always fixed to 40 MHz.
M
DIGDELAY_C 0000000
10002060 Digital delay config
FG 2
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TX CH TX CH CH CH
D_ EN_ D_ EN EN EN
RS
Name CL CL RSV0 GL RSV1 N_ RSV2 P_ PD_
V3
R_ R_ T_S GL GL GL
GL GL T T_S T_S T_S
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
T T T T T
Type RW RW RO RW RO RW RO RW RO RW
EO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
US L
TX CH
D_ EN_
DIG DIG
Name RSV4 TXD_DLYVAL RSV5 CHEN_DLYVAL
.tw IA
DL DL
Y_E Y_E
N N
Type RW RO RW RW RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
om NT
Bit(s) Name Description
31 TXD_CLR_GLT TXD Clear Glitch Flag
Clears the glitch detected flag for TXD.
0: No effect.
x.c E
1: Clear the flag.
30 CHEN_CLR_GLT Channel Enable (CHEN) Clear Glitch Flag
ne FID
Clears the glitch detected flag for CHEN.
0: No effect .
1: Clear the flag.
29:27 RSV0 Reserved
26 TXD_GLT_ST TXD Glitch Status
Indicates if a glitch is detected in a TXD signal. It can be cleared by bit[31].
syn ON
0: Not detected.
1: Detected
25:23 RSV1 Reserved
22 CHENN_GLT_ST CHEN Negative Glitch Status
Indicates if a glitch is detected in a CHEN signal. It can be cleared by bit[30]
@ C
(negedge sample).
0: Not detected.
1: Detected
ien K
21:19 RSV2 Reserved
18 CHENP_GLT_ST CHEN Positive Glitch Status
Indicates if a glitch is detected in a CHEN signal. It can be cleared by bit[30]
ch TE
(posedge sample).
0: Not detected.
1: Detected
17 RSV3 Reserved
am IA
16 CHENPD_GLT_ST CHEN Positive Delay Glitch Status
Indicates if a glitch is detected in a CHEN signal. It can be cleared by bit[30]
(posedge sample, delay 1 cycle).
0: Not detected.
ad ED
1: Detected
15 TXD_DIGDLY_EN TXD Digital Delay Enable
Enables digital delay path.
0: Disable
1: Enable
M
14:13 RSV4 Reserved
12:8 TXD_DLYVAL Delay Count Value
The description is the same as the CHEN_DLYVAL field in this register.
CHEN Digital Delay Enable, Enables the digital delay path.
0: Disable
1: Enable
7 CHEN_DIGDLY_EN CHEN Digital Delay Enable
Enables the digital delay path.
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Bit(s) Name Description
0: Disable
EO
1: Enable
6:5 RSV5 Reserved
US L
4:0 CHEN_DLYVAL Delay Count Value
The delay error =
.tw IA
CLK_PERIOD * (SYNC_DELAY + SYNC_DELTA + (DLYCNT_CFG) + 1)
For example,
DLYCNT_CFG = 4,
(SYNC_DELAY is always fixed to 4)
om NT
Final Delay
= CLK_PERIOD * (2 + (-1/0/+1) + (4) + 1)
= CLK_PERIOD * (6/7/8)= CLK_PERIOD * (6 to 8)
= 25 ns to 33.3 ns
NOTE:
Period is 1/240 MHz = 4.1667 ns in MT7620.
x.c E
10002080
Bit
Name
Type
31 ne FID
CH0_FIFO
30 29 28
Channel 0 FIFO access point
27 26 25 24
CH0_FIFO[31:16]
RW
23 22 21 20 19 18
0000000
17
0
16
syn ON
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name CH0_FIFO[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
@ C
Bit(s) Name Description
31:0 CH0_FIFO Channel 0 FIFO access point
ien K
0000000
ch TE
10002084 CH1_FIFO Channel 1 FIFO access point
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name CH1_FIFO[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
am IA
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name CH1_FIFO[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ad ED
Bit(s) Name Description
31:0 CH1_FIFO Channel 1 FIFO access point
M
0000000
10002088 CH2_FIFO Channel 2 FIFO access point
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name CH2_FIFO[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Name CH2_FIFO[15:0]
Type RW
EO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
US L
Bit(s) Name Description
31:0 CH2_FIFO Channel 2 FIFO access point
.tw IA
0000000
1000208C CH3_FIFO Channel 3 FIFO access point
om NT
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name CH3_FIFO[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
x.c E
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name CH3_FIFO[15:0]
Type RW
ne FID
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:0 CH3_FIFO Channel 3 FIFO access point
syn ON
CHA1_FF_ST 0010000
10002110 Channel A1(represents channel 3) FIFO status
ATUS 8
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CH CH
@ C
CH CH CH CH CH CH
TX_ RX_
TX_ TX_ TX_ RX_ RX_ RX_
DM DM
Name RSV0 OV UN TH OV UN TH
A_F A_F
RU RU RE RU RU RE
AU AU
N N S N N S
ien K
LT LT
W1 W1 W1 W1 W1 W1 W1 W1
Type RO
C C C C C C C C
Reset
ch TE
0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RSV1 CHRFF_AVCNT CHTFF_EPCNT
Type RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
am IA
Bit(s) Name Description
31:24 RSV0 Reserved
23 CHTX_DMA_FAULT Tx DMA Fault Detected Interrupt,Asserts when a fault is detected in a
ad ED
Channel A1 Tx DMA signal.
22 CHTX_OVRUN Tx Overrun Interrupt,Asserts when the Channel A0 Tx FIFO is overrun.
21 CHTX_UNRUN Tx FIFO Underrun Interrupt,Asserts when the Channel A1 Tx FIFO is
underrun.
M
20 CHTX_THRES Tx FIFO Below Threshold Interrupt,Asserts when the Channel A0 FIFO
is lower than the defined threshold.
19 CHRX_DMA_FAUL Rx DMA Fault Detected Interrupt,Asserts when a fault is detected in a
T Channel A1 Rx DMA signal.
18 CHRX_OVRUN Rx FIFO Overrun Interrupt,Asserts when the Channel A1 Rx FIFO is
overrun.
17 CHRX_UNRUN Rx FIFO Underrun Interrupt,Asserts when the Channel A1 Rx FIFO is
underrun.
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Bit(s) Name Description
16 CHRX_THRES Rx FIFO Below Threshold Interrupt,Asserts when the Channel A1 FIFO
EO
is lower than the defined threshold.
US L
15:8 RSV1 Reserved
7:4 CHRFF_AVCNT Channel A1 RXFIFO Available Space Count,Counts the available space
for reads in channel A1 RXFIFO.(unit: word)
.tw IA
3:0 CHTFF_EPCNT Channel A1 TXFIFO Available Space Count,Counts the available space
for writes in channel A1 TXFIFO.(unit: word)
om NT
CHB1_FF_ST 0010000
10002114 Channel B1(represents channel 4) FIFO status
ATUS 8
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
x.c E
CH CH
CH CH CH CH CH CH
TX_ RX_
TX_ TX_ TX_ RX_ RX_ RX_
DM DM
Name RSV0 OV UN TH OV UN TH
ne FID
A_F A_F
RU RU RE RU RU RE
AU AU
N N S N N S
LT LT
W1 W1 W1 W1 W1 W1 W1 W1
Type RO
C C C C C C C C
Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
syn ON
Name RSV1 CHRFF_AVCNT CHTFF_EPCNT
Type RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
Bit(s) Name Description
31:24 RSV0 Reserved
@ C
23 CHTX_DMA_FAULT Tx DMA Fault Detected Interrupt,Asserts when a fault is detected in a
Channel B1 Tx DMA signal.
22 CHTX_OVRUN Tx Overrun Interrupt,Asserts when the Channel B0 Tx FIFO is overrun.
ien K
21 CHTX_UNRUN Tx FIFO Underrun Interrupt,Asserts when the Channel B1 Tx FIFO is
underrun.
ch TE
20 CHTX_THRES Tx FIFO Below Threshold Interrupt,Asserts when the Channel B1 FIFO
is lower than the defined threshold.
19 CHRX_DMA_FAUL Rx DMA Fault Detected Interrupt,Asserts when a fault is detected in a
T Channel B1 Rx DMA signal.
18 CHRX_OVRUN Rx FIFO Overrun Interrupt,Asserts when the Channel B1 Rx FIFO is
am IA
overrun.
17 CHRX_UNRUN Rx FIFO Underrun Interrupt,Asserts when the Channel B1 Rx FIFO is
underrun.
ad ED
16 CHRX_THRES Rx FIFO Below Threshold Interrupt,Asserts when the Channel B1 FIFO
is lower than the defined threshold.
15:8 RSV1 Reserved
7:4 CHRFF_AVCNT Channel B1 RXFIFO Available Space Count,Counts the available space
for reads in channel B1 RXFIFO.(unit: word)
M
3:0 CHTFF_EPCNT Channel B1 TXFIFO Available Space Count,Counts the available space
for writes in channel B1 TXFIFO.(unit: word)
0000000
10002120 CHA1_CFG Channel A1(represents channel 3) Config
1
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Name RSV0 CMP_MODE RSV1[16:6]
Type RO RW RO
EO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
US L
Name RSV1[5:0] TS_START
Type RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
.tw IA
Bit(s) Name Description
31:30 RSV0 Reserved
om NT
29:27 CMP_MODE Compression Mode
Sets the conversion method for the hardware converter to compress raw
data.
000: Disable HW converter, linear raw data (16-bit)
010: Disable HW converter, linear raw data (8-bit), A-law or u-law (8-bit)
011: Reserved
x.c E
100: Enable HW converter, raw data(16-bit) U-law mode (8-bit) (PCM bus in
compressed format)
ne FID
101: Enable HW converter, u-law mode (8-bit) raw data (16-bit) (PCM bus in
raw, 16-bit format)
110: Enable HW converter, raw data (16-bit) A-law mode (8-bit) (PCM bus in
compressed format)
111: Enable HW converter, A-law mode (8-bit) raw data (16-bit) (PCM bus in
raw, 16-bit format)
0: DIS_CONV16
syn ON
2: DIS_CONV8
4: EN_ULW2R
5: EN_R2ULW
6: EN_ALW2R
7: EN_R2ALW
26:10 RSV1 Reserved
@ C
9:0 TS_START Timeslot starting location
(unit: clock cycles)
ien K
0000000
ch TE
10002124 CHB1_CFG Channel B1(represents channel 1) Config
1
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RSV0 CMP_MODE RSV1[16:6]
Type RO RW RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
am IA
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RSV1[5:0] TS_START
Type RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
ad ED
Bit(s) Name Description
31:30 RSV0 Reserved
29:27 CMP_MODE Compression Mode
M
Sets the conversion method for the hardware converter to compress raw
data.
000: Disable HW converter, linear raw data (16-bit)
010: Disable HW converter, linear raw data (8-bit), A-law or u-law (8-bit)
011: Reserved
100: Enable HW converter, raw data(16-bit) U-law mode (8-bit) (PCM bus in
compressed format)
101: Enable HW converter, u-law mode (8-bit) raw data (16-bit) (PCM bus in
raw, 16-bit format)
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Bit(s) Name Description
110: Enable HW converter, raw data (16-bit) A-law mode (8-bit) (PCM bus in
EO
compressed format)
111: Enable HW converter, A-law mode (8-bit) raw data (16-bit) (PCM bus in
US L
raw, 16-bit format)
0: DIS_CONV16
2: DIS_CONV8
.tw IA
4: EN_ULW2R
5: EN_R2ULW
6: EN_ALW2R
7: EN_R2ALW
om NT
26:10 RSV1 Reserved
9:0 TS_START Timeslot starting location
(unit: clock cycles)
x.c E
0000000
ne FID
10002134 CHA1_CFG2 Channel A1(represents channel 3) Config
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RSV0[27:12]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
syn ON
CH CH
_RX _TX CH
RS
Name RSV0[11:0] FF_ FF_ _LS
V1
CL CL B
R R
Type RO RW RW RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
@ C
Bit(s) Name Description
31:4 RSV0 Reserved
ien K
3 CH_RXFF_CLR Channel A1 Rx FIFO Clear
0: Normal operation
ch TE
1: Clear this bit
2 CH_TXFF_CLR Channel A1 Tx FIFO Clear
0: Normal operation
1: Clear this bit
1 RSV1 Reserved
am IA
0 CH_LSB Enable CH A1 Tx in LSB order.
ad ED
0000000
10002138 CHB1_CFG2 Channel B1(represents channel 4) Config
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RSV0[27:12]
M
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH CH
_RX _TX CH
RS
Name RSV0[11:0] FF_ FF_ _LS
V1
CL CL B
R R
Type RO RW RW RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Bit(s) Name Description
EO
31:4 RSV0 Reserved
US L
3 CH_RXFF_CLR Channel B1 Rx FIFO Clear
0: Normal operation
1: Clear this bit
.tw IA
2 CH_TXFF_CLR Channel B1 Tx FIFO Clear
0: Normal operation
1: Clear this bit
om NT
1 RSV1 Reserved
0 CH_LSB Enable CH B1 Tx in LSB order.
x.c E
ne FID
syn ON
@ C
ien K
ch TE
am IA
ad ED
OR M
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
2.15 Generic DMA Controller
EO
2.15.1 Features
US L
Supports 16 DMA channels
Supports 32 bit address.
.tw IA
Maximum 65535 byte transfer
Programmable DMA burst size (1, 2, 4, 8, 16 double word burst)
Supports memory to memory, memory to peripheral, peripheral to memory, peripheral to peripheral
transfers.
om NT
Supports continuous mode.
Supports division of target transfer count into 1 to 256 segments
Support for combining different channels into a chain.
Programmable hardware channel priority.
x.c E
Interrupts for each channel.
ne FID
2.15.2 Block Diagram
Rbus Interface Rbus Interface
syn ON
(Master) Rbus Rbus (Master)
Master Master
DMA Engine
@ C
DMA
Interface
ien K
Arbiter
ch TE
Interrupt
Interface Ch0 APBbus
am IA
Interrupt Interface
Controller ABbus (Slave)
Mux
Slave
ad ED
Ch"n"
M
Figure 2-9 Generic DMA Controller Block Diagram
2.15.3 Peripheral Channel Connection
Channel number Peripheral
0 Reserved
1 Reserved
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Channel number Peripheral
2 I2S Controller (TXDMA)
EO
3 I2S Controller (RXDMA)
US L
4 PCM Controller (RDMA, channel-0)
5 PCM Controller (RDMA, channel-1)
.tw IA
6 PCM Controller (TDMA, channel-0)
7 PCM Controller (TDMA, channel-1)
8 PCM Controller (RDMA, channel-2)
om NT
9 PCM Controller (RDMA, channel-3)
10 PCM Controller (TDMA, channel-2)
11 PCM Controller (TDMA, channel-3)
x.c E
12 SPI Controller (RXDMA)
13 SPI Controller (TXDMA)
ne FID
8 to 15 Reserved
2.15.4 Registers
GDMA Changes LOG
syn ON
Revision Date Author Change Log
0.1 2012/10/15 Mark Wang Initialization
Module name: GDMA Base address: (+10002800h)
@ C
Address Name Widt Register Function
h
ien K
10002800 GDMA_SA_0 32 Source Address of GDMA Channel 0
10002804 GDMA_DA_0 32 Destination Address of GDMA Channel 0
10002808 GDMA_CT0_0 32 Control Register 0 of GDMA Channel 0
ch TE
1000280C GDMA_CT1_0 32 Control Register 1 of GDMA Channel 0
10002810 GDMA_SA_1 32 Source Address of GDMA Channel 1
10002814 GDMA_DA_1 32 Destination Address of GDMA Channel 1
10002818 GDMA_CT0_1 32 Control Register 0 of GDMA Channel 1
am IA
1000281C GDMA_CT1_1 32 Control Register 1 of GDMA Channel 1
10002820 GDMA_SA_2 32 Source Address of GDMA Channel 2
10002824 GDMA_DA_2 32 Destination Address of GDMA Channel 2
ad ED
10002828 GDMA_CT0_2 32 Control Register 0 of GDMA Channel 2
1000282C GDMA_CT1_2 32 Control Register 1 of GDMA Channel 2
10002830 GDMA_SA_3 32 Source Address of GDMA Channel 3
10002834 GDMA_DA_3 32 Destination Address of GDMA Channel 3
M
10002838 GDMA_CT0_3 32 Control Register 0 of GDMA Channel 3
1000283C GDMA_CT1_3 32 Control Register 1 of GDMA Channel 3
10002840 GDMA_SA_4 32 Source Address of GDMA Channel 4
10002844 GDMA_DA_4 32 Destination Address of GDMA Channel 4
10002848 GDMA_CT0_4 32 Control Register 0 of GDMA Channel 4
1000284C GDMA_CT1_4 32 Control Register 1 of GDMA Channel 4
10002850 GDMA_SA_5 32 Source Address of GDMA Channel 5
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
10002854 GDMA_DA_5 32 Destination Address of GDMA Channel 5
10002858 GDMA_CT0_5 32 Control Register 0 of GDMA Channel 5
EO
1000285C GDMA_CT1_5 32 Control Register 1 of GDMA Channel 5
US L
10002860 GDMA_SA_6 32 Source Address of GDMA Channel 6
10002864 GDMA_DA_6 32 Destination Address of GDMA Channel 6
.tw IA
10002868 GDMA_CT0_6 32 Control Register 0 of GDMA Channel 6
1000286C GDMA_CT1_6 32 Control Register 1 of GDMA Channel 6
10002870 GDMA_SA_7 32 Source Address of GDMA Channel 7
10002874 GDMA_DA_7 32 Destination Address of GDMA Channel 7
om NT
10002878 GDMA_CT0_7 32 Control Register 0 of GDMA Channel 7
1000287C GDMA_CT1_7 32 Control Register 1 of GDMA Channel 7
10002880 GDMA_SA_8 32 Source Address of GDMA Channel 8
10002884 GDMA_DA_8 32 Destination Address of GDMA Channel 8
x.c E
10002888 GDMA_CT0_8 32 Control Register 0 of GDMA Channel 8
1000288C GDMA_CT1_8 32 Control Register 1 of GDMA Channel 8
ne FID
10002890 GDMA_SA_9 32 Source Address of GDMA Channel 9
10002894 GDMA_DA_9 32 Destination Address of GDMA Channel 9
10002898 GDMA_CT0_9 32 Control Register 0 of GDMA Channel 9
1000289C GDMA_CT1_9 32 Control Register 1 of GDMA Channel 9
100028A0 GDMA_SA_10 32 Source Address of GDMA Channel 10
syn ON
100028A4 GDMA_DA_10 32 Destination Address of GDMA Channel 10
100028A8 GDMA_CT0_10 32 Control Register 0 of GDMA Channel 10
100028AC GDMA_CT1_10 32 Control Register 1 of GDMA Channel 10
100028B0 GDMA_SA_11 32 Source Address of GDMA Channel 11
@ C
100028B4 GDMA_DA_11 32 Destination Address of GDMA Channel 11
100028B8 GDMA_CT0_11 32 Control Register 0 of GDMA Channel 11
100028BC GDMA_CT1_11 32 Control Register 1 of GDMA Channel 11
ien K
100028C0 GDMA_SA_12 32 Source Address of GDMA Channel 12
100028C4 GDMA_DA_12 32 Destination Address of GDMA Channel 12
100028C8 GDMA_CT0_12 32 Control Register 0 of GDMA Channel 12
ch TE
100028CC GDMA_CT1_12 32 Control Register 1 of GDMA Channel 12
100028D0 GDMA_SA_13 32 Source Address of GDMA Channel 13
100028D4 GDMA_DA_13 32 Destination Address of GDMA Channel 13
am IA
100028D8 GDMA_CT0_13 32 Control Register 0 of GDMA Channel 13
100028DC GDMA_CT1_13 32 Control Register 1 of GDMA Channel 13
100028E0 GDMA_SA_14 32 Source Address of GDMA Channel 14
100028E4 GDMA_DA_14 32 Destination Address of GDMA Channel 14
ad ED
100028E8 GDMA_CT0_14 32 Control Register 0 of GDMA Channel 14
100028EC GDMA_CT1_14 32 Control Register 1 of GDMA Channel 14
100028F0 GDMA_SA_15 32 Source Address of GDMA Channel 15
100028F4 GDMA_DA_15 32 Destination Address of GDMA Channel 15
M
100028F8 GDMA_CT0_15 32 Control Register 0 of GDMA Channel 15
100028FC GDMA_CT1_15 32 Control Register 1 of GDMA Channel 15
10002A00 GDMA_UNMAS 32 Unmask Fail Interrupt Status
K_INTSTS
GDMA_DONE_I
10002A04 NTSTS 32 Segment Done Interrupt Status
10002A20 GDMA_GCT 32 Global Control
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
GDMA_PERI_A
10002A30 DDR_START_0 32 Peripheral Region 0 Starting Address
EO
10002A34 GDMA_PERI_A 32 Peripheral Region 0 End Address
DDR_END_0
US L
GDMA_PERI_A
10002A38 DDR_START_1 32 Peripheral Region 1 Starting Address
.tw IA
10002A3C GDMA_PERI_A 32 Peripheral Region 1 End Address
DDR_END_1
GDMA_PERI_A
10002A40 DDR_START_2 32 Peripheral Region 2 Starting Address
om NT
10002A44 GDMA_PERI_A 32 Peripheral Region 2 End Address
DDR_END_2
GDMA_PERI_A
10002A48 DDR_START_3 32 Peripheral Region 3 Starting Address
10002A4C GDMA_PERI_A 32 Peripheral Region 3 End Address
x.c E
DDR_END_3
10002800
Bit
Name
31
ne FID
GDMA_SA_0
30 29 28
Source Address of GDMA Channel 0
27 26 25 24
SOURCE_ADDR[31:16]
23 22 21 20 19 18
0000000
17
0
16
Type RW
syn ON
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name SOURCE_ADDR[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
@ C
Bit(s) Name Description
31:0 SOURCE_ADDR Souce address
ien K
0000000
ch TE
10002804 GDMA_DA_0 Destination Address of GDMA Channel 0
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name DEST_ADDR[31:16]
Type RW
am IA
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DEST_ADDR[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ad ED
Bit(s) Name Description
31:0 DEST_ADDR Destination address
M
0000000
10002808 GDMA_CT0_0 Control Register 0 of GDMA Channel 0
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name TARGET_BYTE_CNT
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SO SE
DE
EO
UR GM
ST_ SW
CE_ EN
AD _M
AD T_D CH
US L
Name CURR_SEGMENT
DR
DR BURST_SIZE
ON _EN
OD
_M E_E
_M E_I
OD N
OD NT_
.tw IA
E
E EN
Type RO RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
om NT
Bit(s) Name Description
31:16 TARGET_BYTE_CN The number of bytes to be transferred
T
15:8 CURR_SEGMENT Indicates the current segment (0 to 255)
x.c E
7 SOURCE_ADDR_M Sets the source address mode
ODE 0: Incremental mode
1: Fix mode
ne FID
6 DEST_ADDR_MOD Sets the destination address mode
E 0: Incremental mode
1: Fix mode
5:3 BURST_SIZE Sets the number of double words in each burst transaction
0: 1 DW
syn ON
1: 2 DWs
2: 4 DWs
3: 8 DWs
4: 16 DWs
5: Undefined
6: Undefined
@ C
7: Undefined
2 SEGMENT_DONE_I Enable the segment done interrupt. This interrupt asserts after transfer
NT_EN of each segment is done.
0: Disable
ien K
1: Enable
1 CH_EN If CONT_MODE_EN=0, this bit is de-asserted by hardware after the
ch TE
number of bytes transfferred reaches the TARGET_BYTE_CNT
0: Disable
1: Enable
0 SW_MODE_EN Software mode enable. If software mode enable is set, the data transfer
starts when the CH_EN bit is set. Otherwise, the data transfer starts
am IA
when the DMA request is asserted.
0: Hardware mode
1: Software mode
ad ED
0000000
1000280C GDMA_CT1_0 Control Register 1 of GDMA Channel 0
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M
Name RESERVED NUM_SEGMENT SOURCE_DMA_REQ
Type RO RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CO CO CH
RE CH
NT_ HE _U
SE _M
Name MO DEST_DMA_REQ NEXT_CH2UNMASK RE NM
RV AS
DE_ NT_ AS
ED K
EN INT K_F
OR
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Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
_EN AIL
_IN
EO
T_E
N
Type RO RW RW RW RW RW RW
US L
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
.tw IA
Bit(s) Name Description
25:22 NUM_SEGMENT the number of segments=2N, where N is the value of this field. Valid
values for this field are N=0 to 8. The segment
size=(TARGET_BYTE_CNT/2N). It the TARGET_BYTE_CNT is not a
om NT
multiple of 2N, the segment size = {(TARGET_BYTE_CNT/2N) + 1}.
21:16 SOURCE_DMA_RE Selects the source DMA request
Q 0: DMA_REQ0
1: DMA_REQ1
2: DMA_REQ2
x.c E
32: The source of the transfer is memory (always ready)
14 CONT_MODE_EN If CONT_MODE_EN=1, HW will NOT clear CH_EN after the number of
ne FID
bytes transferred reachs TARGET_BYTE_CNT. Otherwise, HW will clear
CH_EN will clear the CH_EN.
0: Continuous mode is disabled
1: Continuous mode is enabled
13:8 DEST_DMA_REQ Selects the destination DMA request
0: DMA_REQ0
syn ON
1: DMA_REQ1
2: DMA_REQ2
32: The destination of the transfer is memory (always ready)
7:3 NEXT_CH2UNMAS Selects the channel to clear the CH_MASK bit. When the number of
K bytes transferred reaches the TARGET_BYTE_CNT, the hardware will
clear the CH_MASK field of the NEXT_CH2UNMASK channel. If the
@ C
hardware does not need to clear CH_MASK field of any channel, this
field should be set to the channel itself.
0: Channel 0
1: Channel 1
ien K
n: Channel n
2 COHERENT_INT_E If COHERENT_INT_EN is set, GDMA will issue a dummy read to
ch TE
N destination after the last write to destination to avoid data coherent
problem. Note: DO NOT set this field if the destination is not MEM. (may
corrupt data, if destination is a FIFO)
0: Disable
1: Enable
am IA
1 CH_UNMASK_FAIL If this field is set, an interrupt will be assert when HW detect the
_INT_EN CH_MASK field of NEXT_CH2UNMASK channel is 1'b0 while trying to
clear it.
0: Disable
ad ED
1: Enable
0 CH_MASK When this field is set, the transfer of this channel is gated untill this
field is clear by HW/SW.
0: Channel is not masked
1: Channel is masked
M
0000000
10002810 GDMA_SA_1 Source Address of GDMA Channel 1
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name SOURCE_ADDR[31:16]
Type RW
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EO
Name SOURCE_ADDR[15:0]
Type RW
US L
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
.tw IA
31:0 SOURCE_ADDR Souce address
om NT
0000000
10002814 GDMA_DA_1 Destination Address of GDMA Channel 1
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name DEST_ADDR[31:16]
x.c E
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ne FID
Name DEST_ADDR[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:0 DEST_ADDR Destination address
syn ON
0000000
10002818 GDMA_CT0_1 Control Register 0 of GDMA Channel 1
0
@ C
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name TARGET_BYTE_CNT
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ien K
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SO SE
DE
UR GM
ch TE
ST_ SW
CE_ EN
AD _M
AD T_D CH
Name CURR_SEGMENT DR BURST_SIZE OD
DR ON _EN
_M E_E
_M E_I
OD N
OD NT_
E
E EN
am IA
Type RO RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
ad ED
31:16 TARGET_BYTE_CN The number of bytes to be transferred
T
15:8 CURR_SEGMENT Indicates the current segment (0 to 255)
7 SOURCE_ADDR_M Sets the source address mode
M
ODE 0: Incremental mode
1: Fix mode
6 DEST_ADDR_MOD Sets the destination address mode
E 0: Incremental mode
1: Fix mode
5:3 BURST_SIZE Sets the number of double words in each burst transaction
0: 1 DW
1: 2 DWs
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Bit(s) Name Description
2: 4 DWs
EO
3: 8 DWs
4: 16 DWs
US L
5: Undefined
6: Undefined
7: Undefined
.tw IA
2 SEGMENT_DONE_I Enable the segment done interrupt. This interrupt asserts after transfer
NT_EN of each segment is done.
0: Disable
om NT
1: Enable
1 CH_EN If CONT_MODE_EN=0, this bit is de-asserted by hardware after the
number of bytes transfferred reaches the TARGET_BYTE_CNT
0: Disable
1: Enable
x.c E
0 SW_MODE_EN Software mode enable. If software mode enable is set, the data transfer
starts when the CH_EN bit is set. Otherwise, the data transfer starts
when the DMA request is asserted.
ne FID
0: Hardware mode
1: Software mode
0000000
syn ON
1000281C GDMA_CT1_1 Control Register 1 of GDMA Channel 1
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RESERVED NUM_SEGMENT SOURCE_DMA_REQ
Type RO RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
@ C
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH
_U
CO
CO NM
RE HE CH
NT_ AS
ien K
SE RE _M
Name RV
MO DEST_DMA_REQ NEXT_CH2UNMASK
NT_
K_F
AS
DE_ AIL
ED INT K
EN _IN
_EN
ch TE
T_E
N
Type RO RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
am IA
Bit(s) Name Description
25:22 NUM_SEGMENT the number of segments=2N, where N is the value of this field. Valid
values for this field are N=0 to 8. The segment
size=(TARGET_BYTE_CNT/2N). It the TARGET_BYTE_CNT is not a
ad ED
multiple of 2N, the segment size = {(TARGET_BYTE_CNT/2N) + 1}.
21:16 SOURCE_DMA_RE Selects the source DMA request
Q 0: DMA_REQ0
1: DMA_REQ1
2: DMA_REQ2
M
32: The source of the transfer is memory (always ready)
14 CONT_MODE_EN If CONT_MODE_EN=1, HW will NOT clear CH_EN after the number of
bytes transferred reachs TARGET_BYTE_CNT. Otherwise, HW will clear
CH_EN will clear the CH_EN.
0: Continuous mode is disabled
1: Continuous mode is enabled
13:8 DEST_DMA_REQ Selects the destination DMA request
0: DMA_REQ0
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Bit(s) Name Description
1: DMA_REQ1
EO
2: DMA_REQ2
32: The destination of the transfer is memory (always ready)
US L
7:3 NEXT_CH2UNMAS Selects the channel to clear the CH_MASK bit. When the number of
K bytes transferred reaches the TARGET_BYTE_CNT, the hardware will
.tw IA
clear the CH_MASK field of the NEXT_CH2UNMASK channel. If the
hardware does not need to clear CH_MASK field of any channel, this
field should be set to the channel itself.
0: Channel 0
om NT
1: Channel 1
n: Channel n
2 COHERENT_INT_E If COHERENT_INT_EN is set, GDMA will issue a dummy read to
N destination after the last write to destination to avoid data coherent
problem. Note: DO NOT set this field if the destination is not MEM. (may
corrupt data, if destination is a FIFO)
x.c E
0: Disable
1: Enable
ne FID
1 CH_UNMASK_FAIL If this field is set, an interrupt will be assert when HW detect the
_INT_EN CH_MASK field of NEXT_CH2UNMASK channel is 1'b0 while trying to
clear it.
0: Disable
1: Enable
0 CH_MASK When this field is set, the transfer of this channel is gated untill this
syn ON
field is clear by HW/SW.
0: Channel is not masked
1: Channel is masked
@ C
0000000
10002820 GDMA_SA_2 Source Address of GDMA Channel 2
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ien K
Name SOURCE_ADDR[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ch TE
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name SOURCE_ADDR[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
am IA
Bit(s) Name Description
31:0 SOURCE_ADDR Souce address
ad ED
0000000
10002824 GDMA_DA_2 Destination Address of GDMA Channel 2
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M
Name DEST_ADDR[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DEST_ADDR[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Bit(s) Name Description
31:0 DEST_ADDR Destination address
EO
US L
0000000
.tw IA
10002828 GDMA_CT0_2 Control Register 0 of GDMA Channel 2
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name TARGET_BYTE_CNT
Type RW
om NT
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SO SE
DE
UR GM
ST_ SW
CE_ EN
AD _M
AD T_D CH
x.c E
Name CURR_SEGMENT DR BURST_SIZE OD
DR ON _EN
_M E_E
_M E_I
OD N
OD NT_
ne FID
E
E EN
Type RO RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:16 TARGET_BYTE_CN The number of bytes to be transferred
syn ON
T
15:8 CURR_SEGMENT Indicates the current segment (0 to 255)
7 SOURCE_ADDR_M Sets the source address mode
ODE 0: Incremental mode
1: Fix mode
@ C
6 DEST_ADDR_MOD Sets the destination address mode
E 0: Incremental mode
1: Fix mode
ien K
5:3 BURST_SIZE Sets the number of double words in each burst transaction
0: 1 DW
1: 2 DWs
ch TE
2: 4 DWs
3: 8 DWs
4: 16 DWs
5: Undefined
6: Undefined
am IA
7: Undefined
2 SEGMENT_DONE_I Enable the segment done interrupt. This interrupt asserts after transfer
NT_EN of each segment is done.
0: Disable
ad ED
1: Enable
1 CH_EN If CONT_MODE_EN=0, this bit is de-asserted by hardware after the
number of bytes transfferred reaches the TARGET_BYTE_CNT
0: Disable
1: Enable
M
0 SW_MODE_EN Software mode enable. If software mode enable is set, the data transfer
starts when the CH_EN bit is set. Otherwise, the data transfer starts
when the DMA request is asserted.
0: Hardware mode
1: Software mode
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
0000000
1000282C GDMA_CT1_2 Control Register 1 of GDMA Channel 2
EO
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
US L
Name RESERVED NUM_SEGMENT SOURCE_DMA_REQ
Type RO RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
.tw IA
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH
_U
CO
CO NM
RE HE CH
om NT
NT_ AS
SE RE _M
Name MO DEST_DMA_REQ NEXT_CH2UNMASK K_F
RV NT_ AS
DE_ AIL
ED INT K
EN _IN
_EN
T_E
N
Type RO RW RW RW RW RW RW
x.c E
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ne FID
Bit(s) Name Description
25:22 NUM_SEGMENT the number of segments=2N, where N is the value of this field. Valid
values for this field are N=0 to 8. The segment
size=(TARGET_BYTE_CNT/2N). It the TARGET_BYTE_CNT is not a
multiple of 2N, the segment size = {(TARGET_BYTE_CNT/2N) + 1}.
21:16 SOURCE_DMA_RE Selects the source DMA request
syn ON
Q 0: DMA_REQ0
1: DMA_REQ1
2: DMA_REQ2
32: The source of the transfer is memory (always ready)
14 CONT_MODE_EN If CONT_MODE_EN=1, HW will NOT clear CH_EN after the number of
@ C
bytes transferred reachs TARGET_BYTE_CNT. Otherwise, HW will clear
CH_EN will clear the CH_EN.
0: Continuous mode is disabled
1: Continuous mode is enabled
ien K
13:8 DEST_DMA_REQ Selects the destination DMA request
0: DMA_REQ0
1: DMA_REQ1
ch TE
2: DMA_REQ2
32: The destination of the transfer is memory (always ready)
7:3 NEXT_CH2UNMAS Selects the channel to clear the CH_MASK bit. When the number of
K bytes transferred reaches the TARGET_BYTE_CNT, the hardware will
clear the CH_MASK field of the NEXT_CH2UNMASK channel. If the
am IA
hardware does not need to clear CH_MASK field of any channel, this
field should be set to the channel itself.
0: Channel 0
1: Channel 1
ad ED
n: Channel n
2 COHERENT_INT_E If COHERENT_INT_EN is set, GDMA will issue a dummy read to
N destination after the last write to destination to avoid data coherent
problem. Note: DO NOT set this field if the destination is not MEM. (may
corrupt data, if destination is a FIFO)
M
0: Disable
1: Enable
1 CH_UNMASK_FAIL If this field is set, an interrupt will be assert when HW detect the
_INT_EN CH_MASK field of NEXT_CH2UNMASK channel is 1'b0 while trying to
clear it.
0: Disable
1: Enable
0 CH_MASK When this field is set, the transfer of this channel is gated untill this
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Bit(s) Name Description
field is clear by HW/SW.
EO
0: Channel is not masked
1: Channel is masked
US L
.tw IA
0000000
10002830 GDMA_SA_3 Source Address of GDMA Channel 3
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
om NT
Name SOURCE_ADDR[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name SOURCE_ADDR[15:0]
x.c E
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ne FID
Bit(s) Name Description
31:0 SOURCE_ADDR Souce address
0000000
syn ON
10002834 GDMA_DA_3 Destination Address of GDMA Channel 3
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name DEST_ADDR[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
@ C
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DEST_ADDR[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ien K
Bit(s) Name Description
ch TE
31:0 DEST_ADDR Destination address
0000000
10002838 GDMA_CT0_3 Control Register 0 of GDMA Channel 3
am IA
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name TARGET_BYTE_CNT
Type RW
ad ED
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SO SE
DE
UR GM
ST_ SW
CE_ EN
AD _M
AD T_D CH
M
Name CURR_SEGMENT DR BURST_SIZE OD
DR ON _EN
_M E_E
_M E_I
OD N
OD NT_
E
E EN
Type RO RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Bit(s) Name Description
31:16 TARGET_BYTE_CN The number of bytes to be transferred
EO
T
US L
15:8 CURR_SEGMENT Indicates the current segment (0 to 255)
7 SOURCE_ADDR_M Sets the source address mode
ODE
.tw IA
0: Incremental mode
1: Fix mode
6 DEST_ADDR_MOD Sets the destination address mode
E 0: Incremental mode
om NT
1: Fix mode
5:3 BURST_SIZE Sets the number of double words in each burst transaction
0: 1 DW
1: 2 DWs
2: 4 DWs
x.c E
3: 8 DWs
4: 16 DWs
5: Undefined
ne FID
6: Undefined
7: Undefined
2 SEGMENT_DONE_I Enable the segment done interrupt. This interrupt asserts after transfer
NT_EN of each segment is done.
0: Disable
1: Enable
syn ON
1 CH_EN If CONT_MODE_EN=0, this bit is de-asserted by hardware after the
number of bytes transfferred reaches the TARGET_BYTE_CNT
0: Disable
1: Enable
0 SW_MODE_EN Software mode enable. If software mode enable is set, the data transfer
@ C
starts when the CH_EN bit is set. Otherwise, the data transfer starts
when the DMA request is asserted.
0: Hardware mode
1: Software mode
ien K
ch TE
0000000
1000283C GDMA_CT1_3 Control Register 1 of GDMA Channel 3
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RESERVED NUM_SEGMENT SOURCE_DMA_REQ
am IA
Type RO RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH
_U
ad ED
CO
CO NM
RE HE CH
NT_ AS
SE RE _M
Name RV
MO DEST_DMA_REQ NEXT_CH2UNMASK
NT_
K_F
AS
DE_ AIL
ED INT K
EN _IN
_EN
T_E
M
N
Type RO RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
25:22 NUM_SEGMENT the number of segments=2N, where N is the value of this field. Valid
values for this field are N=0 to 8. The segment
size=(TARGET_BYTE_CNT/2N). It the TARGET_BYTE_CNT is not a
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Bit(s) Name Description
multiple of 2N, the segment size = {(TARGET_BYTE_CNT/2N) + 1}.
EO
21:16 SOURCE_DMA_RE Selects the source DMA request
Q
US L
0: DMA_REQ0
1: DMA_REQ1
2: DMA_REQ2
.tw IA
32: The source of the transfer is memory (always ready)
14 CONT_MODE_EN If CONT_MODE_EN=1, HW will NOT clear CH_EN after the number of
bytes transferred reachs TARGET_BYTE_CNT. Otherwise, HW will clear
CH_EN will clear the CH_EN.
om NT
0: Continuous mode is disabled
1: Continuous mode is enabled
13:8 DEST_DMA_REQ Selects the destination DMA request
0: DMA_REQ0
1: DMA_REQ1
x.c E
2: DMA_REQ2
32: The destination of the transfer is memory (always ready)
ne FID
7:3 NEXT_CH2UNMAS Selects the channel to clear the CH_MASK bit. When the number of
K bytes transferred reaches the TARGET_BYTE_CNT, the hardware will
clear the CH_MASK field of the NEXT_CH2UNMASK channel. If the
hardware does not need to clear CH_MASK field of any channel, this
field should be set to the channel itself.
0: Channel 0
1: Channel 1
syn ON
n: Channel n
2 COHERENT_INT_E If COHERENT_INT_EN is set, GDMA will issue a dummy read to
N destination after the last write to destination to avoid data coherent
problem. Note: DO NOT set this field if the destination is not MEM. (may
corrupt data, if destination is a FIFO)
@ C
0: Disable
1: Enable
1 CH_UNMASK_FAIL If this field is set, an interrupt will be assert when HW detect the
_INT_EN CH_MASK field of NEXT_CH2UNMASK channel is 1'b0 while trying to
ien K
clear it.
0: Disable
1: Enable
ch TE
0 CH_MASK When this field is set, the transfer of this channel is gated untill this
field is clear by HW/SW.
0: Channel is not masked
1: Channel is masked
am IA
0000000
10002840 GDMA_SA_4 Source Address of GDMA Channel 4
ad ED
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name SOURCE_ADDR[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M
Name SOURCE_ADDR[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:0 SOURCE_ADDR Souce address
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
EO
0000000
10002844 GDMA_DA_4 Destination Address of GDMA Channel 4
0
US L
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name DEST_ADDR[31:16]
Type
.tw IA
RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DEST_ADDR[15:0]
Type RW
om NT
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:0 DEST_ADDR Destination address
x.c E
ne FID
0000000
10002848 GDMA_CT0_4 Control Register 0 of GDMA Channel 4
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name TARGET_BYTE_CNT
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
syn ON
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SO SE
DE
UR GM
ST_ SW
CE_ EN
AD _M
AD T_D CH
Name CURR_SEGMENT DR BURST_SIZE OD
DR ON _EN
_M E_E
_M E_I
@ C
OD N
OD NT_
E
E EN
Type RO RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ien K
Bit(s) Name Description
ch TE
31:16 TARGET_BYTE_CN The number of bytes to be transferred
T
15:8 CURR_SEGMENT Indicates the current segment (0 to 255)
7 SOURCE_ADDR_M Sets the source address mode
ODE
am IA
0: Incremental mode
1: Fix mode
6 DEST_ADDR_MOD Sets the destination address mode
E 0: Incremental mode
ad ED
1: Fix mode
5:3 BURST_SIZE Sets the number of double words in each burst transaction
0: 1 DW
1: 2 DWs
2: 4 DWs
M
3: 8 DWs
4: 16 DWs
5: Undefined
6: Undefined
7: Undefined
2 SEGMENT_DONE_I Enable the segment done interrupt. This interrupt asserts after transfer
NT_EN of each segment is done.
0: Disable
1: Enable
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Bit(s) Name Description
1 CH_EN If CONT_MODE_EN=0, this bit is de-asserted by hardware after the
EO
number of bytes transfferred reaches the TARGET_BYTE_CNT
0: Disable
US L
1: Enable
0 SW_MODE_EN Software mode enable. If software mode enable is set, the data transfer
.tw IA
starts when the CH_EN bit is set. Otherwise, the data transfer starts
when the DMA request is asserted.
0: Hardware mode
1: Software mode
om NT
0000000
1000284C GDMA_CT1_4 Control Register 1 of GDMA Channel 4
0
x.c E
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RESERVED NUM_SEGMENT SOURCE_DMA_REQ
ne FID
Type RO RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH
_U
CO
CO NM
RE HE CH
NT_ AS
SE RE _M
Name
syn ON
MO DEST_DMA_REQ NEXT_CH2UNMASK K_F
RV NT_ AS
DE_ AIL
ED INT K
EN _IN
_EN
T_E
N
Type RO RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
@ C
Bit(s) Name Description
25:22 NUM_SEGMENT the number of segments=2N, where N is the value of this field. Valid
ien K
values for this field are N=0 to 8. The segment
size=(TARGET_BYTE_CNT/2N). It the TARGET_BYTE_CNT is not a
multiple of 2N, the segment size = {(TARGET_BYTE_CNT/2N) + 1}.
ch TE
21:16 SOURCE_DMA_RE Selects the source DMA request
Q 0: DMA_REQ0
1: DMA_REQ1
2: DMA_REQ2
32: The source of the transfer is memory (always ready)
am IA
14 CONT_MODE_EN If CONT_MODE_EN=1, HW will NOT clear CH_EN after the number of
bytes transferred reachs TARGET_BYTE_CNT. Otherwise, HW will clear
CH_EN will clear the CH_EN.
0: Continuous mode is disabled
ad ED
1: Continuous mode is enabled
13:8 DEST_DMA_REQ Selects the destination DMA request
0: DMA_REQ0
1: DMA_REQ1
2: DMA_REQ2
M
32: The destination of the transfer is memory (always ready)
7:3 NEXT_CH2UNMAS Selects the channel to clear the CH_MASK bit. When the number of
K bytes transferred reaches the TARGET_BYTE_CNT, the hardware will
clear the CH_MASK field of the NEXT_CH2UNMASK channel. If the
hardware does not need to clear CH_MASK field of any channel, this
field should be set to the channel itself.
0: Channel 0
1: Channel 1
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Bit(s) Name Description
n: Channel n
EO
2 COHERENT_INT_E If COHERENT_INT_EN is set, GDMA will issue a dummy read to
N destination after the last write to destination to avoid data coherent
US L
problem. Note: DO NOT set this field if the destination is not MEM. (may
corrupt data, if destination is a FIFO)
.tw IA
0: Disable
1: Enable
1 CH_UNMASK_FAIL If this field is set, an interrupt will be assert when HW detect the
_INT_EN CH_MASK field of NEXT_CH2UNMASK channel is 1'b0 while trying to
om NT
clear it.
0: Disable
1: Enable
0 CH_MASK When this field is set, the transfer of this channel is gated untill this
field is clear by HW/SW.
x.c E
0: Channel is not masked
1: Channel is masked
10002850
Bit 31
ne FID
GDMA_SA_5
30 29 28
Source Address of GDMA Channel 5
27 26 25 24 23 22 21 20 19 18
0000000
17
0
16
syn ON
Name SOURCE_ADDR[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name SOURCE_ADDR[15:0]
Type RW
@ C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
ien K
31:0 SOURCE_ADDR Souce address
ch TE
0000000
10002854 GDMA_DA_5 Destination Address of GDMA Channel 5
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name DEST_ADDR[31:16]
am IA
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DEST_ADDR[15:0]
ad ED
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:0 DEST_ADDR Destination address
M
0000000
10002858 GDMA_CT0_5 Control Register 0 of GDMA Channel 5
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name TARGET_BYTE_CNT
Type RW
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EO
SO SE
DE
UR GM
ST_ SW
US L
CE_ EN
AD _M
AD T_D CH
Name CURR_SEGMENT
DR
DR BURST_SIZE
ON _EN
OD
_M E_E
.tw IA
_M E_I
OD N
OD NT_
E
E EN
Type RO RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
om NT
Bit(s) Name Description
31:16 TARGET_BYTE_CN The number of bytes to be transferred
T
15:8 CURR_SEGMENT Indicates the current segment (0 to 255)
x.c E
7 SOURCE_ADDR_M Sets the source address mode
ODE 0: Incremental mode
ne FID
1: Fix mode
6 DEST_ADDR_MOD Sets the destination address mode
E 0: Incremental mode
1: Fix mode
5:3 BURST_SIZE Sets the number of double words in each burst transaction
syn ON
0: 1 DW
1: 2 DWs
2: 4 DWs
3: 8 DWs
4: 16 DWs
5: Undefined
@ C
6: Undefined
7: Undefined
2 SEGMENT_DONE_I Enable the segment done interrupt. This interrupt asserts after transfer
NT_EN of each segment is done.
ien K
0: Disable
1: Enable
ch TE
1 CH_EN If CONT_MODE_EN=0, this bit is de-asserted by hardware after the
number of bytes transfferred reaches the TARGET_BYTE_CNT
0: Disable
1: Enable
0 SW_MODE_EN Software mode enable. If software mode enable is set, the data transfer
am IA
starts when the CH_EN bit is set. Otherwise, the data transfer starts
when the DMA request is asserted.
0: Hardware mode
1: Software mode
ad ED
0000000
1000285C GDMA_CT1_5 Control Register 1 of GDMA Channel 5
0
M
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RESERVED NUM_SEGMENT SOURCE_DMA_REQ
Type RO RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RE CO CO CH CH
SE NT_ HE _U _M
Name RV MO
DEST_DMA_REQ NEXT_CH2UNMASK
RE NM AS
ED DE_ NT_ AS K
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
EN INT K_F
_EN AIL
EO
_IN
T_E
N
US L
Type RO RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
.tw IA
Bit(s) Name Description
25:22 NUM_SEGMENT the number of segments=2N, where N is the value of this field. Valid
values for this field are N=0 to 8. The segment
om NT
size=(TARGET_BYTE_CNT/2N). It the TARGET_BYTE_CNT is not a
multiple of 2N, the segment size = {(TARGET_BYTE_CNT/2N) + 1}.
21:16 SOURCE_DMA_RE Selects the source DMA request
Q 0: DMA_REQ0
1: DMA_REQ1
x.c E
2: DMA_REQ2
32: The source of the transfer is memory (always ready)
ne FID
14 CONT_MODE_EN If CONT_MODE_EN=1, HW will NOT clear CH_EN after the number of
bytes transferred reachs TARGET_BYTE_CNT. Otherwise, HW will clear
CH_EN will clear the CH_EN.
0: Continuous mode is disabled
1: Continuous mode is enabled
13:8 DEST_DMA_REQ Selects the destination DMA request
syn ON
0: DMA_REQ0
1: DMA_REQ1
2: DMA_REQ2
32: The destination of the transfer is memory (always ready)
7:3 NEXT_CH2UNMAS Selects the channel to clear the CH_MASK bit. When the number of
K bytes transferred reaches the TARGET_BYTE_CNT, the hardware will
@ C
clear the CH_MASK field of the NEXT_CH2UNMASK channel. If the
hardware does not need to clear CH_MASK field of any channel, this
field should be set to the channel itself.
0: Channel 0
ien K
1: Channel 1
n: Channel n
2 COHERENT_INT_E If COHERENT_INT_EN is set, GDMA will issue a dummy read to
ch TE
N destination after the last write to destination to avoid data coherent
problem. Note: DO NOT set this field if the destination is not MEM. (may
corrupt data, if destination is a FIFO)
0: Disable
1: Enable
am IA
1 CH_UNMASK_FAIL If this field is set, an interrupt will be assert when HW detect the
_INT_EN CH_MASK field of NEXT_CH2UNMASK channel is 1'b0 while trying to
clear it.
0: Disable
ad ED
1: Enable
0 CH_MASK When this field is set, the transfer of this channel is gated untill this
field is clear by HW/SW.
0: Channel is not masked
1: Channel is masked
M
0000000
10002860 GDMA_SA_6 Source Address of GDMA Channel 6
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name SOURCE_ADDR[31:16]
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
EO
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name SOURCE_ADDR[15:0]
US L
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
.tw IA
Bit(s) Name Description
31:0 SOURCE_ADDR Souce address
om NT
0000000
10002864 GDMA_DA_6 Destination Address of GDMA Channel 6
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
x.c E
Name DEST_ADDR[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ne FID
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DEST_ADDR[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
syn ON
31:0 DEST_ADDR Destination address
0000000
10002868 GDMA_CT0_6 Control Register 0 of GDMA Channel 6
@ C
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name TARGET_BYTE_CNT
Type RW
ien K
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SO SE
ch TE
DE
UR GM
ST_ SW
CE_ EN
AD _M
AD T_D CH
Name CURR_SEGMENT
DR
DR BURST_SIZE
ON _EN
OD
_M E_E
_M E_I
OD N
OD NT_
am IA
E
E EN
Type RO RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ad ED
Bit(s) Name Description
31:16 TARGET_BYTE_CN The number of bytes to be transferred
T
15:8 CURR_SEGMENT Indicates the current segment (0 to 255)
M
7 SOURCE_ADDR_M Sets the source address mode
ODE 0: Incremental mode
1: Fix mode
6 DEST_ADDR_MOD Sets the destination address mode
E 0: Incremental mode
1: Fix mode
5:3 BURST_SIZE Sets the number of double words in each burst transaction
0: 1 DW
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Bit(s) Name Description
1: 2 DWs
EO
2: 4 DWs
3: 8 DWs
US L
4: 16 DWs
5: Undefined
6: Undefined
.tw IA
7: Undefined
2 SEGMENT_DONE_I Enable the segment done interrupt. This interrupt asserts after transfer
NT_EN of each segment is done.
om NT
0: Disable
1: Enable
1 CH_EN If CONT_MODE_EN=0, this bit is de-asserted by hardware after the
number of bytes transfferred reaches the TARGET_BYTE_CNT
0: Disable
x.c E
1: Enable
0 SW_MODE_EN Software mode enable. If software mode enable is set, the data transfer
starts when the CH_EN bit is set. Otherwise, the data transfer starts
ne FID
when the DMA request is asserted.
0: Hardware mode
1: Software mode
syn ON
0000000
1000286C GDMA_CT1_6 Control Register 1 of GDMA Channel 6
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RESERVED NUM_SEGMENT SOURCE_DMA_REQ
Type RO RW RW
@ C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH
_U
CO
ien K
CO NM
RE HE CH
NT_ AS
SE RE _M
Name MO DEST_DMA_REQ NEXT_CH2UNMASK K_F
RV NT_ AS
DE_ AIL
ch TE
ED INT K
EN _IN
_EN
T_E
N
Type RO RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
am IA
Bit(s) Name Description
25:22 NUM_SEGMENT the number of segments=2N, where N is the value of this field. Valid
values for this field are N=0 to 8. The segment
ad ED
size=(TARGET_BYTE_CNT/2N). It the TARGET_BYTE_CNT is not a
multiple of 2N, the segment size = {(TARGET_BYTE_CNT/2N) + 1}.
21:16 SOURCE_DMA_RE Selects the source DMA request
Q 0: DMA_REQ0
1: DMA_REQ1
M
2: DMA_REQ2
32: The source of the transfer is memory (always ready)
14 CONT_MODE_EN If CONT_MODE_EN=1, HW will NOT clear CH_EN after the number of
bytes transferred reachs TARGET_BYTE_CNT. Otherwise, HW will clear
CH_EN will clear the CH_EN.
0: Continuous mode is disabled
1: Continuous mode is enabled
13:8 DEST_DMA_REQ Selects the destination DMA request
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Bit(s) Name Description
0: DMA_REQ0
EO
1: DMA_REQ1
2: DMA_REQ2
US L
32: The destination of the transfer is memory (always ready)
7:3 NEXT_CH2UNMAS Selects the channel to clear the CH_MASK bit. When the number of
.tw IA
K bytes transferred reaches the TARGET_BYTE_CNT, the hardware will
clear the CH_MASK field of the NEXT_CH2UNMASK channel. If the
hardware does not need to clear CH_MASK field of any channel, this
field should be set to the channel itself.
om NT
0: Channel 0
1: Channel 1
n: Channel n
2 COHERENT_INT_E If COHERENT_INT_EN is set, GDMA will issue a dummy read to
N destination after the last write to destination to avoid data coherent
problem. Note: DO NOT set this field if the destination is not MEM. (may
x.c E
corrupt data, if destination is a FIFO)
0: Disable
ne FID
1: Enable
1 CH_UNMASK_FAIL If this field is set, an interrupt will be assert when HW detect the
_INT_EN CH_MASK field of NEXT_CH2UNMASK channel is 1'b0 while trying to
clear it.
0: Disable
1: Enable
syn ON
0 CH_MASK When this field is set, the transfer of this channel is gated untill this
field is clear by HW/SW.
0: Channel is not masked
1: Channel is masked
@ C
0000000
10002870 GDMA_SA_7 Source Address of GDMA Channel 7
0
ien K
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name SOURCE_ADDR[31:16]
Type RW
ch TE
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name SOURCE_ADDR[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
am IA
Bit(s) Name Description
31:0 SOURCE_ADDR Souce address
ad ED
0000000
10002874 GDMA_DA_7 Destination Address of GDMA Channel 7
0
M
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name DEST_ADDR[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DEST_ADDR[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Bit(s) Name Description
31:0 DEST_ADDR Destination address
EO
US L
0000000
.tw IA
10002878 GDMA_CT0_7 Control Register 0 of GDMA Channel 7
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name TARGET_BYTE_CNT
Type RW
om NT
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SO SE
DE
UR GM
ST_ SW
CE_ EN
AD _M
AD T_D CH
x.c E
Name CURR_SEGMENT DR BURST_SIZE OD
DR ON _EN
_M E_E
_M E_I
OD N
OD NT_
ne FID
E
E EN
Type RO RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:16 TARGET_BYTE_CN The number of bytes to be transferred
syn ON
T
15:8 CURR_SEGMENT Indicates the current segment (0 to 255)
7 SOURCE_ADDR_M Sets the source address mode
ODE 0: Incremental mode
1: Fix mode
@ C
6 DEST_ADDR_MOD Sets the destination address mode
E 0: Incremental mode
1: Fix mode
ien K
5:3 BURST_SIZE Sets the number of double words in each burst transaction
0: 1 DW
1: 2 DWs
ch TE
2: 4 DWs
3: 8 DWs
4: 16 DWs
5: Undefined
6: Undefined
am IA
7: Undefined
2 SEGMENT_DONE_I Enable the segment done interrupt. This interrupt asserts after transfer
NT_EN of each segment is done.
0: Disable
ad ED
1: Enable
1 CH_EN If CONT_MODE_EN=0, this bit is de-asserted by hardware after the
number of bytes transfferred reaches the TARGET_BYTE_CNT
0: Disable
1: Enable
M
0 SW_MODE_EN Software mode enable. If software mode enable is set, the data transfer
starts when the CH_EN bit is set. Otherwise, the data transfer starts
when the DMA request is asserted.
0: Hardware mode
1: Software mode
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
0000000
1000287C GDMA_CT1_7 Control Register 1 of GDMA Channel 7
EO
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
US L
Name RESERVED NUM_SEGMENT SOURCE_DMA_REQ
Type RO RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
.tw IA
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH
_U
CO
CO NM
RE HE CH
om NT
NT_ AS
SE RE _M
Name MO DEST_DMA_REQ NEXT_CH2UNMASK K_F
RV NT_ AS
DE_ AIL
ED INT K
EN _IN
_EN
T_E
N
Type RO RW RW RW RW RW RW
x.c E
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ne FID
Bit(s) Name Description
25:22 NUM_SEGMENT the number of segments=2N, where N is the value of this field. Valid
values for this field are N=0 to 8. The segment
size=(TARGET_BYTE_CNT/2N). It the TARGET_BYTE_CNT is not a
multiple of 2N, the segment size = {(TARGET_BYTE_CNT/2N) + 1}.
21:16 SOURCE_DMA_RE Selects the source DMA request
syn ON
Q 0: DMA_REQ0
1: DMA_REQ1
2: DMA_REQ2
32: The source of the transfer is memory (always ready)
14 CONT_MODE_EN If CONT_MODE_EN=1, HW will NOT clear CH_EN after the number of
@ C
bytes transferred reachs TARGET_BYTE_CNT. Otherwise, HW will clear
CH_EN will clear the CH_EN.
0: Continuous mode is disabled
1: Continuous mode is enabled
ien K
13:8 DEST_DMA_REQ Selects the destination DMA request
0: DMA_REQ0
1: DMA_REQ1
ch TE
2: DMA_REQ2
32: The destination of the transfer is memory (always ready)
7:3 NEXT_CH2UNMAS Selects the channel to clear the CH_MASK bit. When the number of
K bytes transferred reaches the TARGET_BYTE_CNT, the hardware will
clear the CH_MASK field of the NEXT_CH2UNMASK channel. If the
am IA
hardware does not need to clear CH_MASK field of any channel, this
field should be set to the channel itself.
0: Channel 0
1: Channel 1
ad ED
n: Channel n
2 COHERENT_INT_E If COHERENT_INT_EN is set, GDMA will issue a dummy read to
N destination after the last write to destination to avoid data coherent
problem. Note: DO NOT set this field if the destination is not MEM. (may
corrupt data, if destination is a FIFO)
M
0: Disable
1: Enable
1 CH_UNMASK_FAIL If this field is set, an interrupt will be assert when HW detect the
_INT_EN CH_MASK field of NEXT_CH2UNMASK channel is 1'b0 while trying to
clear it.
0: Disable
1: Enable
0 CH_MASK When this field is set, the transfer of this channel is gated untill this
OR
MediaTek Confidential © 2014 MediaTek Inc. Page 178 of 347
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Bit(s) Name Description
field is clear by HW/SW.
EO
0: Channel is not masked
1: Channel is masked
US L
.tw IA
0000000
10002880 GDMA_SA_8 Source Address of GDMA Channel 8
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
om NT
Name SOURCE_ADDR[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name SOURCE_ADDR[15:0]
x.c E
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ne FID
Bit(s) Name Description
31:0 SOURCE_ADDR Souce address
0000000
syn ON
10002884 GDMA_DA_8 Destination Address of GDMA Channel 8
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name DEST_ADDR[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
@ C
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DEST_ADDR[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ien K
Bit(s) Name Description
ch TE
31:0 DEST_ADDR Destination address
0000000
10002888 GDMA_CT0_8 Control Register 0 of GDMA Channel 8
am IA
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name TARGET_BYTE_CNT
Type RW
ad ED
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SO SE
DE
UR GM
ST_ SW
CE_ EN
AD _M
AD T_D CH
M
Name CURR_SEGMENT DR BURST_SIZE OD
DR ON _EN
_M E_E
_M E_I
OD N
OD NT_
E
E EN
Type RO RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Bit(s) Name Description
31:16 TARGET_BYTE_CN The number of bytes to be transferred
EO
T
US L
15:8 CURR_SEGMENT Indicates the current segment (0 to 255)
7 SOURCE_ADDR_M Sets the source address mode
ODE
.tw IA
0: Incremental mode
1: Fix mode
6 DEST_ADDR_MOD Sets the destination address mode
E 0: Incremental mode
om NT
1: Fix mode
5:3 BURST_SIZE Sets the number of double words in each burst transaction
0: 1 DW
1: 2 DWs
2: 4 DWs
x.c E
3: 8 DWs
4: 16 DWs
5: Undefined
ne FID
6: Undefined
7: Undefined
2 SEGMENT_DONE_I Enable the segment done interrupt. This interrupt asserts after transfer
NT_EN of each segment is done.
0: Disable
1: Enable
syn ON
1 CH_EN If CONT_MODE_EN=0, this bit is de-asserted by hardware after the
number of bytes transfferred reaches the TARGET_BYTE_CNT
0: Disable
1: Enable
0 SW_MODE_EN Software mode enable. If software mode enable is set, the data transfer
@ C
starts when the CH_EN bit is set. Otherwise, the data transfer starts
when the DMA request is asserted.
0: Hardware mode
1: Software mode
ien K
ch TE
0000000
1000288C GDMA_CT1_8 Control Register 1 of GDMA Channel 8
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RESERVED NUM_SEGMENT SOURCE_DMA_REQ
am IA
Type RO RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH
_U
ad ED
CO
CO NM
RE HE CH
NT_ AS
SE RE _M
Name RV
MO DEST_DMA_REQ NEXT_CH2UNMASK
NT_
K_F
AS
DE_ AIL
ED INT K
EN _IN
_EN
T_E
M
N
Type RO RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
25:22 NUM_SEGMENT the number of segments=2N, where N is the value of this field. Valid
values for this field are N=0 to 8. The segment
size=(TARGET_BYTE_CNT/2N). It the TARGET_BYTE_CNT is not a
OR
MediaTek Confidential © 2014 MediaTek Inc. Page 180 of 347
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Bit(s) Name Description
multiple of 2N, the segment size = {(TARGET_BYTE_CNT/2N) + 1}.
EO
21:16 SOURCE_DMA_RE Selects the source DMA request
Q
US L
0: DMA_REQ0
1: DMA_REQ1
2: DMA_REQ2
.tw IA
32: The source of the transfer is memory (always ready)
14 CONT_MODE_EN If CONT_MODE_EN=1, HW will NOT clear CH_EN after the number of
bytes transferred reachs TARGET_BYTE_CNT. Otherwise, HW will clear
CH_EN will clear the CH_EN.
om NT
0: Continuous mode is disabled
1: Continuous mode is enabled
13:8 DEST_DMA_REQ Selects the destination DMA request
0: DMA_REQ0
1: DMA_REQ1
x.c E
2: DMA_REQ2
32: The destination of the transfer is memory (always ready)
ne FID
7:3 NEXT_CH2UNMAS Selects the channel to clear the CH_MASK bit. When the number of
K bytes transferred reaches the TARGET_BYTE_CNT, the hardware will
clear the CH_MASK field of the NEXT_CH2UNMASK channel. If the
hardware does not need to clear CH_MASK field of any channel, this
field should be set to the channel itself.
0: Channel 0
1: Channel 1
syn ON
n: Channel n
2 COHERENT_INT_E If COHERENT_INT_EN is set, GDMA will issue a dummy read to
N destination after the last write to destination to avoid data coherent
problem. Note: DO NOT set this field if the destination is not MEM. (may
corrupt data, if destination is a FIFO)
@ C
0: Disable
1: Enable
1 CH_UNMASK_FAIL If this field is set, an interrupt will be assert when HW detect the
_INT_EN CH_MASK field of NEXT_CH2UNMASK channel is 1'b0 while trying to
ien K
clear it.
0: Disable
1: Enable
ch TE
0 CH_MASK When this field is set, the transfer of this channel is gated untill this
field is clear by HW/SW.
0: Channel is not masked
1: Channel is masked
am IA
0000000
10002890 GDMA_SA_9 Source Address of GDMA Channel 9
ad ED
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name SOURCE_ADDR[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M
Name SOURCE_ADDR[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:0 SOURCE_ADDR Souce address
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
EO
0000000
10002894 GDMA_DA_9 Destination Address of GDMA Channel 9
0
US L
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name DEST_ADDR[31:16]
Type
.tw IA
RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DEST_ADDR[15:0]
Type RW
om NT
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:0 DEST_ADDR Destination address
x.c E
ne FID
0000000
10002898 GDMA_CT0_9 Control Register 0 of GDMA Channel 9
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name TARGET_BYTE_CNT
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
syn ON
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SO SE
DE
UR GM
ST_ SW
CE_ EN
AD _M
AD T_D CH
Name CURR_SEGMENT DR BURST_SIZE OD
DR ON _EN
_M E_E
_M E_I
@ C
OD N
OD NT_
E
E EN
Type RO RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ien K
Bit(s) Name Description
ch TE
31:16 TARGET_BYTE_CN The number of bytes to be transferred
T
15:8 CURR_SEGMENT Indicates the current segment (0 to 255)
7 SOURCE_ADDR_M Sets the source address mode
ODE
am IA
0: Incremental mode
1: Fix mode
6 DEST_ADDR_MOD Sets the destination address mode
E 0: Incremental mode
ad ED
1: Fix mode
5:3 BURST_SIZE Sets the number of double words in each burst transaction
0: 1 DW
1: 2 DWs
2: 4 DWs
M
3: 8 DWs
4: 16 DWs
5: Undefined
6: Undefined
7: Undefined
2 SEGMENT_DONE_I Enable the segment done interrupt. This interrupt asserts after transfer
NT_EN of each segment is done.
0: Disable
1: Enable
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Bit(s) Name Description
1 CH_EN If CONT_MODE_EN=0, this bit is de-asserted by hardware after the
EO
number of bytes transfferred reaches the TARGET_BYTE_CNT
0: Disable
US L
1: Enable
0 SW_MODE_EN Software mode enable. If software mode enable is set, the data transfer
.tw IA
starts when the CH_EN bit is set. Otherwise, the data transfer starts
when the DMA request is asserted.
0: Hardware mode
1: Software mode
om NT
0000000
1000289C GDMA_CT1_9 Control Register 1 of GDMA Channel 9
0
x.c E
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RESERVED NUM_SEGMENT SOURCE_DMA_REQ
ne FID
Type RO RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH
_U
CO
CO NM
RE HE CH
NT_ AS
SE RE _M
Name
syn ON
MO DEST_DMA_REQ NEXT_CH2UNMASK K_F
RV NT_ AS
DE_ AIL
ED INT K
EN _IN
_EN
T_E
N
Type RO RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
@ C
Bit(s) Name Description
25:22 NUM_SEGMENT the number of segments=2N, where N is the value of this field. Valid
ien K
values for this field are N=0 to 8. The segment
size=(TARGET_BYTE_CNT/2N). It the TARGET_BYTE_CNT is not a
multiple of 2N, the segment size = {(TARGET_BYTE_CNT/2N) + 1}.
ch TE
21:16 SOURCE_DMA_RE Selects the source DMA request
Q 0: DMA_REQ0
1: DMA_REQ1
2: DMA_REQ2
32: The source of the transfer is memory (always ready)
am IA
14 CONT_MODE_EN If CONT_MODE_EN=1, HW will NOT clear CH_EN after the number of
bytes transferred reachs TARGET_BYTE_CNT. Otherwise, HW will clear
CH_EN will clear the CH_EN.
0: Continuous mode is disabled
ad ED
1: Continuous mode is enabled
13:8 DEST_DMA_REQ Selects the destination DMA request
0: DMA_REQ0
1: DMA_REQ1
2: DMA_REQ2
M
32: The destination of the transfer is memory (always ready)
7:3 NEXT_CH2UNMAS Selects the channel to clear the CH_MASK bit. When the number of
K bytes transferred reaches the TARGET_BYTE_CNT, the hardware will
clear the CH_MASK field of the NEXT_CH2UNMASK channel. If the
hardware does not need to clear CH_MASK field of any channel, this
field should be set to the channel itself.
0: Channel 0
1: Channel 1
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Bit(s) Name Description
n: Channel n
EO
2 COHERENT_INT_E If COHERENT_INT_EN is set, GDMA will issue a dummy read to
N destination after the last write to destination to avoid data coherent
US L
problem. Note: DO NOT set this field if the destination is not MEM. (may
corrupt data, if destination is a FIFO)
.tw IA
0: Disable
1: Enable
1 CH_UNMASK_FAIL If this field is set, an interrupt will be assert when HW detect the
_INT_EN CH_MASK field of NEXT_CH2UNMASK channel is 1'b0 while trying to
om NT
clear it.
0: Disable
1: Enable
0 CH_MASK When this field is set, the transfer of this channel is gated untill this
field is clear by HW/SW.
x.c E
0: Channel is not masked
1: Channel is masked
100028A0
Bit 31
ne FID
GDMA_SA_10
30 29 28
Source Address of GDMA Channel 10
27 26 25 24 23 22 21 20 19 18
0000000
17
0
16
syn ON
Name SOURCE_ADDR[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name SOURCE_ADDR[15:0]
Type RW
@ C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
ien K
31:0 SOURCE_ADDR Souce address
ch TE
0000000
100028A4 GDMA_DA_10 Destination Address of GDMA Channel 10
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name DEST_ADDR[31:16]
am IA
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DEST_ADDR[15:0]
ad ED
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:0 DEST_ADDR Destination address
M
GDMA_CT0_1 0000000
100028A8 Control Register 0 of GDMA Channel 10
0 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name TARGET_BYTE_CNT
Type RW
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EO
SO SE
DE
UR GM
ST_ SW
US L
CE_ EN
AD _M
AD T_D CH
Name CURR_SEGMENT
DR
DR BURST_SIZE
ON _EN
OD
_M E_E
.tw IA
_M E_I
OD N
OD NT_
E
E EN
Type RO RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
om NT
Bit(s) Name Description
31:16 TARGET_BYTE_CN The number of bytes to be transferred
T
15:8 CURR_SEGMENT Indicates the current segment (0 to 255)
x.c E
7 SOURCE_ADDR_M Sets the source address mode
ODE 0: Incremental mode
ne FID
1: Fix mode
6 DEST_ADDR_MOD Sets the destination address mode
E 0: Incremental mode
1: Fix mode
5:3 BURST_SIZE Sets the number of double words in each burst transaction
syn ON
0: 1 DW
1: 2 DWs
2: 4 DWs
3: 8 DWs
4: 16 DWs
5: Undefined
@ C
6: Undefined
7: Undefined
2 SEGMENT_DONE_I Enable the segment done interrupt. This interrupt asserts after transfer
NT_EN of each segment is done.
ien K
0: Disable
1: Enable
ch TE
1 CH_EN If CONT_MODE_EN=0, this bit is de-asserted by hardware after the
number of bytes transfferred reaches the TARGET_BYTE_CNT
0: Disable
1: Enable
0 SW_MODE_EN Software mode enable. If software mode enable is set, the data transfer
am IA
starts when the CH_EN bit is set. Otherwise, the data transfer starts
when the DMA request is asserted.
0: Hardware mode
1: Software mode
ad ED
GDMA_CT1_1 0000000
100028AC Control Register 1 of GDMA Channel 10
0 0
M
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RESERVED NUM_SEGMENT SOURCE_DMA_REQ
Type RO RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RE CO CO CH CH
SE NT_ HE _U _M
Name RV MO
DEST_DMA_REQ NEXT_CH2UNMASK
RE NM AS
ED DE_ NT_ AS K
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
EN INT K_F
_EN AIL
EO
_IN
T_E
N
US L
Type RO RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
.tw IA
Bit(s) Name Description
25:22 NUM_SEGMENT the number of segments=2N, where N is the value of this field. Valid
values for this field are N=0 to 8. The segment
om NT
size=(TARGET_BYTE_CNT/2N). It the TARGET_BYTE_CNT is not a
multiple of 2N, the segment size = {(TARGET_BYTE_CNT/2N) + 1}.
21:16 SOURCE_DMA_RE Selects the source DMA request
Q 0: DMA_REQ0
1: DMA_REQ1
x.c E
2: DMA_REQ2
32: The source of the transfer is memory (always ready)
ne FID
14 CONT_MODE_EN If CONT_MODE_EN=1, HW will NOT clear CH_EN after the number of
bytes transferred reachs TARGET_BYTE_CNT. Otherwise, HW will clear
CH_EN will clear the CH_EN.
0: Continuous mode is disabled
1: Continuous mode is enabled
13:8 DEST_DMA_REQ Selects the destination DMA request
syn ON
0: DMA_REQ0
1: DMA_REQ1
2: DMA_REQ2
32: The destination of the transfer is memory (always ready)
7:3 NEXT_CH2UNMAS Selects the channel to clear the CH_MASK bit. When the number of
K bytes transferred reaches the TARGET_BYTE_CNT, the hardware will
@ C
clear the CH_MASK field of the NEXT_CH2UNMASK channel. If the
hardware does not need to clear CH_MASK field of any channel, this
field should be set to the channel itself.
0: Channel 0
ien K
1: Channel 1
n: Channel n
2 COHERENT_INT_E If COHERENT_INT_EN is set, GDMA will issue a dummy read to
ch TE
N destination after the last write to destination to avoid data coherent
problem. Note: DO NOT set this field if the destination is not MEM. (may
corrupt data, if destination is a FIFO)
0: Disable
1: Enable
am IA
1 CH_UNMASK_FAIL If this field is set, an interrupt will be assert when HW detect the
_INT_EN CH_MASK field of NEXT_CH2UNMASK channel is 1'b0 while trying to
clear it.
0: Disable
ad ED
1: Enable
0 CH_MASK When this field is set, the transfer of this channel is gated untill this
field is clear by HW/SW.
0: Channel is not masked
1: Channel is masked
M
0000000
100028B0 GDMA_SA_11 Source Address of GDMA Channel 11
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name SOURCE_ADDR[31:16]
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
EO
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name SOURCE_ADDR[15:0]
US L
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
.tw IA
Bit(s) Name Description
31:0 SOURCE_ADDR Souce address
om NT
0000000
100028B4 GDMA_DA_11 Destination Address of GDMA Channel 11
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
x.c E
Name DEST_ADDR[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ne FID
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DEST_ADDR[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
syn ON
31:0 DEST_ADDR Destination address
GDMA_CT0_1 0000000
100028B8 Control Register 0 of GDMA Channel 11
@ C
1 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name TARGET_BYTE_CNT
Type RW
ien K
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SO SE
ch TE
DE
UR GM
ST_ SW
CE_ EN
AD _M
AD T_D CH
Name CURR_SEGMENT
DR
DR BURST_SIZE
ON _EN
OD
_M E_E
_M E_I
OD N
OD NT_
am IA
E
E EN
Type RO RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ad ED
Bit(s) Name Description
31:16 TARGET_BYTE_CN The number of bytes to be transferred
T
15:8 CURR_SEGMENT Indicates the current segment (0 to 255)
M
7 SOURCE_ADDR_M Sets the source address mode
ODE 0: Incremental mode
1: Fix mode
6 DEST_ADDR_MOD Sets the destination address mode
E 0: Incremental mode
1: Fix mode
5:3 BURST_SIZE Sets the number of double words in each burst transaction
0: 1 DW
OR
MediaTek Confidential © 2014 MediaTek Inc. Page 187 of 347
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Bit(s) Name Description
1: 2 DWs
EO
2: 4 DWs
3: 8 DWs
US L
4: 16 DWs
5: Undefined
6: Undefined
.tw IA
7: Undefined
2 SEGMENT_DONE_I Enable the segment done interrupt. This interrupt asserts after transfer
NT_EN of each segment is done.
om NT
0: Disable
1: Enable
1 CH_EN If CONT_MODE_EN=0, this bit is de-asserted by hardware after the
number of bytes transfferred reaches the TARGET_BYTE_CNT
0: Disable
x.c E
1: Enable
0 SW_MODE_EN Software mode enable. If software mode enable is set, the data transfer
starts when the CH_EN bit is set. Otherwise, the data transfer starts
ne FID
when the DMA request is asserted.
0: Hardware mode
1: Software mode
syn ON
GDMA_CT1_1 0000000
100028BC Control Register 1 of GDMA Channel 11
1 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RESERVED NUM_SEGMENT SOURCE_DMA_REQ
Type RO RW RW
@ C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH
_U
CO
ien K
CO NM
RE HE CH
NT_ AS
SE RE _M
Name MO DEST_DMA_REQ NEXT_CH2UNMASK K_F
RV NT_ AS
DE_ AIL
ch TE
ED INT K
EN _IN
_EN
T_E
N
Type RO RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
am IA
Bit(s) Name Description
25:22 NUM_SEGMENT the number of segments=2N, where N is the value of this field. Valid
values for this field are N=0 to 8. The segment
ad ED
size=(TARGET_BYTE_CNT/2N). It the TARGET_BYTE_CNT is not a
multiple of 2N, the segment size = {(TARGET_BYTE_CNT/2N) + 1}.
21:16 SOURCE_DMA_RE Selects the source DMA request
Q 0: DMA_REQ0
1: DMA_REQ1
M
2: DMA_REQ2
32: The source of the transfer is memory (always ready)
14 CONT_MODE_EN If CONT_MODE_EN=1, HW will NOT clear CH_EN after the number of
bytes transferred reachs TARGET_BYTE_CNT. Otherwise, HW will clear
CH_EN will clear the CH_EN.
0: Continuous mode is disabled
1: Continuous mode is enabled
13:8 DEST_DMA_REQ Selects the destination DMA request
OR
MediaTek Confidential © 2014 MediaTek Inc. Page 188 of 347
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Bit(s) Name Description
0: DMA_REQ0
EO
1: DMA_REQ1
2: DMA_REQ2
US L
32: The destination of the transfer is memory (always ready)
7:3 NEXT_CH2UNMAS Selects the channel to clear the CH_MASK bit. When the number of
.tw IA
K bytes transferred reaches the TARGET_BYTE_CNT, the hardware will
clear the CH_MASK field of the NEXT_CH2UNMASK channel. If the
hardware does not need to clear CH_MASK field of any channel, this
field should be set to the channel itself.
om NT
0: Channel 0
1: Channel 1
n: Channel n
2 COHERENT_INT_E If COHERENT_INT_EN is set, GDMA will issue a dummy read to
N destination after the last write to destination to avoid data coherent
problem. Note: DO NOT set this field if the destination is not MEM. (may
x.c E
corrupt data, if destination is a FIFO)
0: Disable
ne FID
1: Enable
1 CH_UNMASK_FAIL If this field is set, an interrupt will be assert when HW detect the
_INT_EN CH_MASK field of NEXT_CH2UNMASK channel is 1'b0 while trying to
clear it.
0: Disable
1: Enable
syn ON
0 CH_MASK When this field is set, the transfer of this channel is gated untill this
field is clear by HW/SW.
0: Channel is not masked
1: Channel is masked
@ C
0000000
100028C0 GDMA_SA_12 Source Address of GDMA Channel 12
0
ien K
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name SOURCE_ADDR[31:16]
Type RW
ch TE
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name SOURCE_ADDR[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
am IA
Bit(s) Name Description
31:0 SOURCE_ADDR Souce address
ad ED
0000000
100028C4 GDMA_DA_12 Destination Address of GDMA Channel 12
0
M
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name DEST_ADDR[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DEST_ADDR[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
OR
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Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited.
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Bit(s) Name Description
31:0 DEST_ADDR Destination address
EO
US L
GDMA_CT0_1 0000000
.tw IA
100028C8 Control Register 0 of GDMA Channel 12
2 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name TARGET_BYTE_CNT
Type RW
om NT
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SO SE
DE
UR GM
ST_ SW
CE_ EN
AD _M
AD T_D CH
x.c E
Name CURR_SEGMENT DR BURST_SIZE OD
DR ON _EN
_M E_E
_M E_I
OD N
OD NT_
ne FID
E
E EN
Type RO RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:16 TARGET_BYTE_CN The number of bytes to be transferred
syn ON
T
15:8 CURR_SEGMENT Indicates the current segment (0 to 255)
7 SOURCE_ADDR_M Sets the source address mode
ODE 0: Incremental mode
1: Fix mode
@ C
6 DEST_ADDR_MOD Sets the destination address mode
E 0: Incremental mode
1: Fix mode
ien K
5:3 BURST_SIZE Sets the number of double words in each burst transaction
0: 1 DW
1: 2 DWs
ch TE
2: 4 DWs
3: 8 DWs
4: 16 DWs
5: Undefined
6: Undefined
am IA
7: Undefined
2 SEGMENT_DONE_I Enable the segment done interrupt. This interrupt asserts after transfer
NT_EN of each segment is done.
0: Disable
ad ED
1: Enable
1 CH_EN If CONT_MODE_EN=0, this bit is de-asserted by hardware after the
number of bytes transfferred reaches the TARGET_BYTE_CNT
0: Disable
1: Enable
M
0 SW_MODE_EN Software mode enable. If software mode enable is set, the data transfer
starts when the CH_EN bit is set. Otherwise, the data transfer starts
when the DMA request is asserted.
0: Hardware mode
1: Software mode
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
GDMA_CT1_1 0000000
100028CC Control Register 1 of GDMA Channel 12
EO
2 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
US L
Name RESERVED NUM_SEGMENT SOURCE_DMA_REQ
Type RO RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
.tw IA
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH
_U
CO
CO NM
RE HE CH
om NT
NT_ AS
SE RE _M
Name MO DEST_DMA_REQ NEXT_CH2UNMASK K_F
RV NT_ AS
DE_ AIL
ED INT K
EN _IN
_EN
T_E
N
Type RO RW RW RW RW RW RW
x.c E
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ne FID
Bit(s) Name Description
25:22 NUM_SEGMENT the number of segments=2N, where N is the value of this field. Valid
values for this field are N=0 to 8. The segment
size=(TARGET_BYTE_CNT/2N). It the TARGET_BYTE_CNT is not a
multiple of 2N, the segment size = {(TARGET_BYTE_CNT/2N) + 1}.
21:16 SOURCE_DMA_RE Selects the source DMA request
syn ON
Q 0: DMA_REQ0
1: DMA_REQ1
2: DMA_REQ2
32: The source of the transfer is memory (always ready)
14 CONT_MODE_EN If CONT_MODE_EN=1, HW will NOT clear CH_EN after the number of
@ C
bytes transferred reachs TARGET_BYTE_CNT. Otherwise, HW will clear
CH_EN will clear the CH_EN.
0: Continuous mode is disabled
1: Continuous mode is enabled
ien K
13:8 DEST_DMA_REQ Selects the destination DMA request
0: DMA_REQ0
1: DMA_REQ1
ch TE
2: DMA_REQ2
32: The destination of the transfer is memory (always ready)
7:3 NEXT_CH2UNMAS Selects the channel to clear the CH_MASK bit. When the number of
K bytes transferred reaches the TARGET_BYTE_CNT, the hardware will
clear the CH_MASK field of the NEXT_CH2UNMASK channel. If the
am IA
hardware does not need to clear CH_MASK field of any channel, this
field should be set to the channel itself.
0: Channel 0
1: Channel 1
ad ED
n: Channel n
2 COHERENT_INT_E If COHERENT_INT_EN is set, GDMA will issue a dummy read to
N destination after the last write to destination to avoid data coherent
problem. Note: DO NOT set this field if the destination is not MEM. (may
corrupt data, if destination is a FIFO)
M
0: Disable
1: Enable
1 CH_UNMASK_FAIL If this field is set, an interrupt will be assert when HW detect the
_INT_EN CH_MASK field of NEXT_CH2UNMASK channel is 1'b0 while trying to
clear it.
0: Disable
1: Enable
0 CH_MASK When this field is set, the transfer of this channel is gated untill this
OR
MediaTek Confidential © 2014 MediaTek Inc. Page 191 of 347
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Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited.
[email protected],time=2014-12-05 11:55:47,ip=58.250.71.129,doctitle=MT7628_ProgrammingGuide_20140428(E2).docx,company=Synnex Electronics HK Limited 聯強電子_RLT
MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Bit(s) Name Description
field is clear by HW/SW.
EO
0: Channel is not masked
1: Channel is masked
US L
.tw IA
0000000
100028D0 GDMA_SA_13 Source Address of GDMA Channel 13
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
om NT
Name SOURCE_ADDR[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name SOURCE_ADDR[15:0]
x.c E
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ne FID
Bit(s) Name Description
31:0 SOURCE_ADDR Souce address
0000000
syn ON
100028D4 GDMA_DA_13 Destination Address of GDMA Channel 13
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name DEST_ADDR[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
@ C
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DEST_ADDR[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ien K
Bit(s) Name Description
ch TE
31:0 DEST_ADDR Destination address
GDMA_CT0_1 0000000
100028D8 Control Register 0 of GDMA Channel 13
am IA
3 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name TARGET_BYTE_CNT
Type RW
ad ED
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SO SE
DE
UR GM
ST_ SW
CE_ EN
AD _M
AD T_D CH
M
Name CURR_SEGMENT DR BURST_SIZE OD
DR ON _EN
_M E_E
_M E_I
OD N
OD NT_
E
E EN
Type RO RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
OR
MediaTek Confidential © 2014 MediaTek Inc. Page 192 of 347
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Bit(s) Name Description
31:16 TARGET_BYTE_CN The number of bytes to be transferred
EO
T
US L
15:8 CURR_SEGMENT Indicates the current segment (0 to 255)
7 SOURCE_ADDR_M Sets the source address mode
ODE
.tw IA
0: Incremental mode
1: Fix mode
6 DEST_ADDR_MOD Sets the destination address mode
E 0: Incremental mode
om NT
1: Fix mode
5:3 BURST_SIZE Sets the number of double words in each burst transaction
0: 1 DW
1: 2 DWs
2: 4 DWs
x.c E
3: 8 DWs
4: 16 DWs
5: Undefined
ne FID
6: Undefined
7: Undefined
2 SEGMENT_DONE_I Enable the segment done interrupt. This interrupt asserts after transfer
NT_EN of each segment is done.
0: Disable
1: Enable
syn ON
1 CH_EN If CONT_MODE_EN=0, this bit is de-asserted by hardware after the
number of bytes transfferred reaches the TARGET_BYTE_CNT
0: Disable
1: Enable
0 SW_MODE_EN Software mode enable. If software mode enable is set, the data transfer
@ C
starts when the CH_EN bit is set. Otherwise, the data transfer starts
when the DMA request is asserted.
0: Hardware mode
1: Software mode
ien K
ch TE
GDMA_CT1_1 0000000
100028DC Control Register 1 of GDMA Channel 13
3 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RESERVED NUM_SEGMENT SOURCE_DMA_REQ
am IA
Type RO RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH
_U
ad ED
CO
CO NM
RE HE CH
NT_ AS
SE RE _M
Name RV
MO DEST_DMA_REQ NEXT_CH2UNMASK
NT_
K_F
AS
DE_ AIL
ED INT K
EN _IN
_EN
T_E
M
N
Type RO RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
25:22 NUM_SEGMENT the number of segments=2N, where N is the value of this field. Valid
values for this field are N=0 to 8. The segment
size=(TARGET_BYTE_CNT/2N). It the TARGET_BYTE_CNT is not a
OR
MediaTek Confidential © 2014 MediaTek Inc. Page 193 of 347
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Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited.
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Bit(s) Name Description
multiple of 2N, the segment size = {(TARGET_BYTE_CNT/2N) + 1}.
EO
21:16 SOURCE_DMA_RE Selects the source DMA request
Q
US L
0: DMA_REQ0
1: DMA_REQ1
2: DMA_REQ2
.tw IA
32: The source of the transfer is memory (always ready)
14 CONT_MODE_EN If CONT_MODE_EN=1, HW will NOT clear CH_EN after the number of
bytes transferred reachs TARGET_BYTE_CNT. Otherwise, HW will clear
CH_EN will clear the CH_EN.
om NT
0: Continuous mode is disabled
1: Continuous mode is enabled
13:8 DEST_DMA_REQ Selects the destination DMA request
0: DMA_REQ0
1: DMA_REQ1
x.c E
2: DMA_REQ2
32: The destination of the transfer is memory (always ready)
ne FID
7:3 NEXT_CH2UNMAS Selects the channel to clear the CH_MASK bit. When the number of
K bytes transferred reaches the TARGET_BYTE_CNT, the hardware will
clear the CH_MASK field of the NEXT_CH2UNMASK channel. If the
hardware does not need to clear CH_MASK field of any channel, this
field should be set to the channel itself.
0: Channel 0
1: Channel 1
syn ON
n: Channel n
2 COHERENT_INT_E If COHERENT_INT_EN is set, GDMA will issue a dummy read to
N destination after the last write to destination to avoid data coherent
problem. Note: DO NOT set this field if the destination is not MEM. (may
corrupt data, if destination is a FIFO)
@ C
0: Disable
1: Enable
1 CH_UNMASK_FAIL If this field is set, an interrupt will be assert when HW detect the
_INT_EN CH_MASK field of NEXT_CH2UNMASK channel is 1'b0 while trying to
ien K
clear it.
0: Disable
1: Enable
ch TE
0 CH_MASK When this field is set, the transfer of this channel is gated untill this
field is clear by HW/SW.
0: Channel is not masked
1: Channel is masked
am IA
0000000
100028E0 GDMA_SA_14 Source Address of GDMA Channel 14
ad ED
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name SOURCE_ADDR[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M
Name SOURCE_ADDR[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:0 SOURCE_ADDR Souce address
OR
MediaTek Confidential © 2014 MediaTek Inc. Page 194 of 347
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Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited.
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
EO
0000000
100028E4 GDMA_DA_14 Destination Address of GDMA Channel 14
0
US L
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name DEST_ADDR[31:16]
Type
.tw IA
RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DEST_ADDR[15:0]
Type RW
om NT
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:0 DEST_ADDR Destination address
x.c E
ne FID
GDMA_CT0_1 0000000
100028E8 Control Register 0 of GDMA Channel 14
4 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name TARGET_BYTE_CNT
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
syn ON
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SO SE
DE
UR GM
ST_ SW
CE_ EN
AD _M
AD T_D CH
Name CURR_SEGMENT DR BURST_SIZE OD
DR ON _EN
_M E_E
_M E_I
@ C
OD N
OD NT_
E
E EN
Type RO RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ien K
Bit(s) Name Description
ch TE
31:16 TARGET_BYTE_CN The number of bytes to be transferred
T
15:8 CURR_SEGMENT Indicates the current segment (0 to 255)
7 SOURCE_ADDR_M Sets the source address mode
ODE
am IA
0: Incremental mode
1: Fix mode
6 DEST_ADDR_MOD Sets the destination address mode
E 0: Incremental mode
ad ED
1: Fix mode
5:3 BURST_SIZE Sets the number of double words in each burst transaction
0: 1 DW
1: 2 DWs
2: 4 DWs
M
3: 8 DWs
4: 16 DWs
5: Undefined
6: Undefined
7: Undefined
2 SEGMENT_DONE_I Enable the segment done interrupt. This interrupt asserts after transfer
NT_EN of each segment is done.
0: Disable
1: Enable
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Bit(s) Name Description
1 CH_EN If CONT_MODE_EN=0, this bit is de-asserted by hardware after the
EO
number of bytes transfferred reaches the TARGET_BYTE_CNT
0: Disable
US L
1: Enable
0 SW_MODE_EN Software mode enable. If software mode enable is set, the data transfer
.tw IA
starts when the CH_EN bit is set. Otherwise, the data transfer starts
when the DMA request is asserted.
0: Hardware mode
1: Software mode
om NT
GDMA_CT1_1 0000000
100028EC Control Register 1 of GDMA Channel 14
4 0
x.c E
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RESERVED NUM_SEGMENT SOURCE_DMA_REQ
ne FID
Type RO RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH
_U
CO
CO NM
RE HE CH
NT_ AS
SE RE _M
Name
syn ON
MO DEST_DMA_REQ NEXT_CH2UNMASK K_F
RV NT_ AS
DE_ AIL
ED INT K
EN _IN
_EN
T_E
N
Type RO RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
@ C
Bit(s) Name Description
25:22 NUM_SEGMENT the number of segments=2N, where N is the value of this field. Valid
ien K
values for this field are N=0 to 8. The segment
size=(TARGET_BYTE_CNT/2N). It the TARGET_BYTE_CNT is not a
multiple of 2N, the segment size = {(TARGET_BYTE_CNT/2N) + 1}.
ch TE
21:16 SOURCE_DMA_RE Selects the source DMA request
Q 0: DMA_REQ0
1: DMA_REQ1
2: DMA_REQ2
32: The source of the transfer is memory (always ready)
am IA
14 CONT_MODE_EN If CONT_MODE_EN=1, HW will NOT clear CH_EN after the number of
bytes transferred reachs TARGET_BYTE_CNT. Otherwise, HW will clear
CH_EN will clear the CH_EN.
0: Continuous mode is disabled
ad ED
1: Continuous mode is enabled
13:8 DEST_DMA_REQ Selects the destination DMA request
0: DMA_REQ0
1: DMA_REQ1
2: DMA_REQ2
M
32: The destination of the transfer is memory (always ready)
7:3 NEXT_CH2UNMAS Selects the channel to clear the CH_MASK bit. When the number of
K bytes transferred reaches the TARGET_BYTE_CNT, the hardware will
clear the CH_MASK field of the NEXT_CH2UNMASK channel. If the
hardware does not need to clear CH_MASK field of any channel, this
field should be set to the channel itself.
0: Channel 0
1: Channel 1
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Bit(s) Name Description
n: Channel n
EO
2 COHERENT_INT_E If COHERENT_INT_EN is set, GDMA will issue a dummy read to
N destination after the last write to destination to avoid data coherent
US L
problem. Note: DO NOT set this field if the destination is not MEM. (may
corrupt data, if destination is a FIFO)
.tw IA
0: Disable
1: Enable
1 CH_UNMASK_FAIL If this field is set, an interrupt will be assert when HW detect the
_INT_EN CH_MASK field of NEXT_CH2UNMASK channel is 1'b0 while trying to
om NT
clear it.
0: Disable
1: Enable
0 CH_MASK When this field is set, the transfer of this channel is gated untill this
field is clear by HW/SW.
x.c E
0: Channel is not masked
1: Channel is masked
100028F0
Bit 31
ne FID
GDMA_SA_15
30 29 28
Source Address of GDMA Channel 15
27 26 25 24 23 22 21 20 19 18
0000000
17
0
16
syn ON
Name SOURCE_ADDR[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name SOURCE_ADDR[15:0]
Type RW
@ C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
ien K
31:0 SOURCE_ADDR Souce address
ch TE
0000000
100028F4 GDMA_DA_15 Destination Address of GDMA Channel 15
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name DEST_ADDR[31:16]
am IA
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DEST_ADDR[15:0]
ad ED
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:0 DEST_ADDR Destination address
M
GDMA_CT0_1 0000000
100028F8 Control Register 0 of GDMA Channel 15
5 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name TARGET_BYTE_CNT
Type RW
OR
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Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EO
SO SE
DE
UR GM
ST_ SW
US L
CE_ EN
AD _M
AD T_D CH
Name CURR_SEGMENT
DR
DR BURST_SIZE
ON _EN
OD
_M E_E
.tw IA
_M E_I
OD N
OD NT_
E
E EN
Type RO RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
om NT
Bit(s) Name Description
31:16 TARGET_BYTE_CN The number of bytes to be transferred
T
15:8 CURR_SEGMENT Indicates the current segment (0 to 255)
x.c E
7 SOURCE_ADDR_M Sets the source address mode
ODE 0: Incremental mode
ne FID
1: Fix mode
6 DEST_ADDR_MOD Sets the destination address mode
E 0: Incremental mode
1: Fix mode
5:3 BURST_SIZE Sets the number of double words in each burst transaction
syn ON
0: 1 DW
1: 2 DWs
2: 4 DWs
3: 8 DWs
4: 16 DWs
5: Undefined
@ C
6: Undefined
7: Undefined
2 SEGMENT_DONE_I Enable the segment done interrupt. This interrupt asserts after transfer
NT_EN of each segment is done.
ien K
0: Disable
1: Enable
ch TE
1 CH_EN If CONT_MODE_EN=0, this bit is de-asserted by hardware after the
number of bytes transfferred reaches the TARGET_BYTE_CNT
0: Disable
1: Enable
0 SW_MODE_EN Software mode enable. If software mode enable is set, the data transfer
am IA
starts when the CH_EN bit is set. Otherwise, the data transfer starts
when the DMA request is asserted.
0: Hardware mode
1: Software mode
ad ED
GDMA_CT1_1 0000000
100028FC Control Register 1 of GDMA Channel 15
5 0
M
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RESERVED NUM_SEGMENT SOURCE_DMA_REQ
Type RO RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RE CO CO CH CH
SE NT_ HE _U _M
Name RV MO
DEST_DMA_REQ NEXT_CH2UNMASK
RE NM AS
ED DE_ NT_ AS K
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
EN INT K_F
_EN AIL
EO
_IN
T_E
N
US L
Type RO RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
.tw IA
Bit(s) Name Description
25:22 NUM_SEGMENT the number of segments=2N, where N is the value of this field. Valid
values for this field are N=0 to 8. The segment
om NT
size=(TARGET_BYTE_CNT/2N). It the TARGET_BYTE_CNT is not a
multiple of 2N, the segment size = {(TARGET_BYTE_CNT/2N) + 1}.
21:16 SOURCE_DMA_RE Selects the source DMA request
Q 0: DMA_REQ0
1: DMA_REQ1
x.c E
2: DMA_REQ2
32: The source of the transfer is memory (always ready)
ne FID
14 CONT_MODE_EN If CONT_MODE_EN=1, HW will NOT clear CH_EN after the number of
bytes transferred reachs TARGET_BYTE_CNT. Otherwise, HW will clear
CH_EN will clear the CH_EN.
0: Continuous mode is disabled
1: Continuous mode is enabled
13:8 DEST_DMA_REQ Selects the destination DMA request
syn ON
0: DMA_REQ0
1: DMA_REQ1
2: DMA_REQ2
32: The destination of the transfer is memory (always ready)
7:3 NEXT_CH2UNMAS Selects the channel to clear the CH_MASK bit. When the number of
K bytes transferred reaches the TARGET_BYTE_CNT, the hardware will
@ C
clear the CH_MASK field of the NEXT_CH2UNMASK channel. If the
hardware does not need to clear CH_MASK field of any channel, this
field should be set to the channel itself.
0: Channel 0
ien K
1: Channel 1
n: Channel n
2 COHERENT_INT_E If COHERENT_INT_EN is set, GDMA will issue a dummy read to
ch TE
N destination after the last write to destination to avoid data coherent
problem. Note: DO NOT set this field if the destination is not MEM. (may
corrupt data, if destination is a FIFO)
0: Disable
1: Enable
am IA
1 CH_UNMASK_FAIL If this field is set, an interrupt will be assert when HW detect the
_INT_EN CH_MASK field of NEXT_CH2UNMASK channel is 1'b0 while trying to
clear it.
0: Disable
ad ED
1: Enable
0 CH_MASK When this field is set, the transfer of this channel is gated untill this
field is clear by HW/SW.
0: Channel is not masked
1: Channel is masked
M
GDMA_UNMA 0000000
10002A00 Unmask Fail Interrupt Status
SK_INTSTS 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name UNMASK_FAIL_INTSTS[31:16]
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Type W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
EO
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name UNMASK_FAIL_INTSTS[15:0]
US L
Type W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
.tw IA
Bit(s) Name Description
31:0 UNMASK_FAIL_INT This field is the bit-map of unmask fail interrupt status of each channel.
STS The unmask fail interrupt will assert when HW detect the CH_MASK field
of NEXT_CH2UNMASK channel is 1'b0 while trying to clear it.
om NT
GDMA_DONE 0000000
10002A04 Segment Done Interrupt Status
_INTSTS 0
x.c E
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name SEGMENT_DONE_INTSTS[31:16]
ne FID
Type W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name SEGMENT_DONE_INTSTS[15:0]
Type W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
syn ON
Bit(s) Name Description
31:0 SEGMENT_DONE_I This field is the bit-map of segment done interrupt status of each
NTSTS channel. The segment done interrupt will assert when each segment is
transferred completely.
@ C
0000000
10002A20 GDMA_GCT Global Control
ien K
E
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RESERVED[26:11]
ch TE
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AR
TOTAL_C B_
Name RESERVED[10:0] IP_VER
am IA
H_NUM MO
DE
Type RO RO RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0
ad ED
Bit(s) Name Description
4:3 TOTAL_CH_NUM Total channel number supported
0: 8 channels
1: 16 channels
2: 32 channels
M
3: Undefined
2:1 IP_VER GDMA core version
0 ARB_MODE Arbitration mode selection
0: channel 0 has highest priority and others are round-robin
1: All channel are round-robin
OR
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MT7628
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Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
GDMA_PERI_
1000000
EO
10002A30 ADDR_START Peripheral Region 0 Starting Address
0
_0
US L
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name PERI_ADDR_START_0[31:16]
Type
.tw IA
RW
Reset 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name PERI_ADDR_START_0[15:0]
Type RW
om NT
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:0 PERI_ADDR_STAR GDMA request will direct to peripheral bus if the request address >=
T_0 PERI_ADDR_START_x & < PERI_ADDR_END_x
x.c E
10002A34
Bit
Name
Type
31 ne FID
GDMA_PERI_
ADDR_END_0
30 29 28
Peripheral Region 0 End Address
27 26 25 24 23
PERI_ADDR_END_0[31:16]
RW
22 21 20 19 18
2000000
17
0
16
syn ON
Reset 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name PERI_ADDR_END_0[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
@ C
Bit(s) Name Description
31:0 PERI_ADDR_END_ GDMA request will direct to peripheral bus if the request address >=
0 PERI_ADDR_START_x & < PERI_ADDR_END_x
ien K
ch TE
GDMA_PERI_
2000000
10002A38 ADDR_START Peripheral Region 1 Starting Address
0
_1
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
am IA
Name PERI_ADDR_START_1[31:16]
Type RW
Reset 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name PERI_ADDR_START_1[15:0]
ad ED
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:0 PERI_ADDR_STAR GDMA request will direct to peripheral bus if the request address >=
M
T_1 PERI_ADDR_START_x & < PERI_ADDR_END_x
GDMA_PERI_ 3000000
10002A3C Peripheral Region 1 End Address
ADDR_END_1 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name PERI_ADDR_END_1[31:16]
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Type RW
Reset 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0
EO
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name PERI_ADDR_END_1[15:0]
US L
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
.tw IA
Bit(s) Name Description
31:0 PERI_ADDR_END_ GDMA request will direct to peripheral bus if the request address >=
1 PERI_ADDR_START_x & < PERI_ADDR_END_x
om NT
GDMA_PERI_
1000000
10002A40 ADDR_START Peripheral Region 2 Starting Address
0
_2
x.c E
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name PERI_ADDR_START_2[31:16]
ne FID
Type RW
Reset 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name PERI_ADDR_START_2[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
syn ON
Bit(s) Name Description
31:0 PERI_ADDR_STAR GDMA request will direct to peripheral bus if the request address >=
T_2 PERI_ADDR_START_x & < PERI_ADDR_END_x
@ C
GDMA_PERI_ 2000000
10002A44 Peripheral Region 2 End Address
ADDR_END_2 0
ien K
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name PERI_ADDR_END_2[31:16]
Type RW
ch TE
Reset 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name PERI_ADDR_END_2[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
am IA
Bit(s) Name Description
31:0 PERI_ADDR_END_ GDMA request will direct to peripheral bus if the request address >=
2 PERI_ADDR_START_x & < PERI_ADDR_END_x
ad ED
GDMA_PERI_
6000000
10002A48 ADDR_START Peripheral Region 3 Starting Address
M
0
_3
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name PERI_ADDR_START_3[31:16]
Type RW
Reset 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name PERI_ADDR_START_3[15:0]
Type RW
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
EO
Bit(s) Name Description
31:0
US L
PERI_ADDR_STAR GDMA request will direct to peripheral bus if the request address >=
T_3 PERI_ADDR_START_x & < PERI_ADDR_END_x
.tw IA
GDMA_PERI_ 7000000
10002A4C Peripheral Region 3 End Address
ADDR_END_3 0
om NT
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name PERI_ADDR_END_3[31:16]
Type RW
Reset 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
x.c E
Name PERI_ADDR_END_3[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s)
31:0 ne FID
Name
PERI_ADDR_END_
3
Description
GDMA request will direct to peripheral bus if the request address >=
PERI_ADDR_START_x & < PERI_ADDR_END_x
syn ON
@ C
ien K
ch TE
am IA
ad ED
OR M
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
2.16 AES Controller
EO
2.16.1 Registers
US L
AES Changes LOG
.tw IA
Revision Date Author Change Log
0.1 2013/4/30 Morrie Lin Initialization
0.2 2013/6/5 Morrie Lin Add desc_5dw_info_en register
0.3 2013/6/7 Morrie Lin Update AES base address
om NT
Module name: AES Base address: (+10004000h)
Address Name Widt Register Function
x.c E
h
TX_BASE_PTR TX_BASE_PTR0
ne FID
10004000 32
0 Used for DMA base address of TX ring0
TX_MAX_CNT0
10004004 TX_MAX_CNT0 32
Used for DMA max number of TX ring0
TX_CTX_IDX0
10004008 TX_CTX_IDX0 32
Used for CPU pointer of TX ring0
TX_DTX_IDX0
syn ON
1000400C TX_DTX_IDX0 32
Used for DMA pointer of TX ring0
RX_BASE_PTR RX_BASE_PTR0
10004100 0 32
Used for DMA base address of RX ring0
RX_MAX_CNT0
10004104 RX_MAX_CNT0 32
Used for DMA max number of RX ring0
@ C
RX_CALC_IDX RX_CALC_IDX0
10004108 32
0 Used for CPU pointer of RX ring0
FS_DRX_IDX0
ien K
1000410C FS_DRX_IDX0 32
Used for DMA pointer of RX ring0
PDMA_INFO
10004200 PDMA_INFO 32
ch TE
used for PDMA information
PDMA_GLO_C PDMA_GLO_CFG
10004204 FG 32
used for PDMA setting
PDMA_RST_ID PDMA_RST_IDX
10004208 X 32
used for PDMA setting
am IA
DELAY_INT_CF DELAY_INT_CFG
1000420C G 32
used for PDMA setting
PDMA_Q_CFG
10004210 PDMA_Q_CFG 32
ad ED
used for PDMA setting
PDMA_INT_ST PDMA_INT_STA
10004220 A 32
used for PDMA setting
PDMA_INT_MS PDMA_INT_MSK
10004228 K 32
used for PDMA setting
M
TX_BASE_PT 0000000
10004000 TX_BASE_PTR0
R0 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RESV
Type RO
OR
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Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EO
Name TX_BASE_PTR0
Type RW
US L
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
.tw IA
31:16 RESV Reserved
15:0 TX_BASE_PTR0 Tx Base Pointer 0
Points to the base address of TX_Ring 0
om NT
(If enable desc_5dw_info_en 8-DWORD aligned address, else 4-DWORD
aligned address).
x.c E
TX_MAX_CNT 0000000
10004004 TX_MAX_CNT0
0 0
ne FID
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RESV
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name TX_MAX_CNT0
Type RW
syn ON
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:16 RESV Reserved
15:0 TX_MAX_CNT0 Tx Maximum TXD Count 0
@ C
The maximum TXD count in TXD_Ring 0.
ien K
0000000
10004008 TX_CTX_IDX0 TX_CTX_IDX0
0
ch TE
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RESV
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
am IA
Name TX_MAX_CNT0
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ad ED
Bit(s) Name Description
31:16 RESV Reserved
15:0 TX_MAX_CNT0 Tx CPU TXD Index n
Points to the next TXD to be used by the CPU.
(If enable desc_5dw_info_en, 8-DWORD aligned address, else 4-DWORD
M
aligned address).
0000000
1000400C TX_DTX_IDX0 TX_DTX_IDX0
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RESV[23:8]
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
EO
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RESV[7:0] TX_DTX_IDX0
US L
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
.tw IA
Bit(s) Name Description
31:8 RESV Reserved
7:0 TX_DTX_IDX0 Tx DMA TXD Index n
om NT
Points to the next TXD to be used by the DMA.
(If enable desc_5dw_info_en, 8-DWORD aligned address, else 4-DWORD
aligned address).
x.c E
RX_BASE_PT 0000000
10004100 RX_BASE_PTR0
R0 0
ne FID
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RESV
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RX_BASE_PTR0
syn ON
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:16 RESV Reserved
@ C
15:0 RX_BASE_PTR0 Rx Base Pointer 0
Points to the base address of RXD Ring 0
(If enable desc_5dw_info_en, 8-DWORD aligned address, else 4-DWORD
aligned address).
ien K
ch TE
RX_MAX_CNT 0000000
10004104 RX_MAX_CNT0
0 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RESV
am IA
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RX_MAX_CNT0
Type RW
ad ED
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:16 RESV Reserved
M
15:0 RX_MAX_CNT0 Rx Maximum Count 0
The maximum RXD count in RXD Ring 0.
RX_CALC_ID 0000000
10004108 RX_CALC_IDX0
X0 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Name RESV
Type RO
EO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
US L
Name RX_CALI_IDX0
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
.tw IA
Bit(s) Name Description
31:16 RESV Reserved
om NT
15:0 RX_CALI_IDX0 Rx CPU RXD Index 0
Points to the next RXD the CPU will allocate to RXD Ring 0.
(If enable desc_5dw_info_en, 8-DWORD aligned address, else 4-DWORD
aligned address).
x.c E
0000000
ne FID
1000410C FS_DRX_IDX0 FS_DRX_IDX0
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RESV[23:8]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
syn ON
Name RESV[7:0] RX_DRX_IDX0
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
@ C
31:8 RESV Reserved
7:0 RX_DRX_IDX0 Rx DMA RXD Index n
Points to the next RXD that the DMA will use in FDS Ring 0.
(If enable desc_5dw_info_en, 8-DWORD aligned address, else 4-DWORD
ien K
aligned address).
ch TE
4C00010
10004200 PDMA_INFO PDMA_INFO
1
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
am IA
Name VERSION INDEX_WIDTH BASE_PTR_WIDTH
Type RO RO RO
Reset 0 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ad ED
Name RX_RING_NUM TX_RING_NUM
Type RO RO
Reset 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1
Bit(s) Name Description
M
31:28 VERSION PDMA controller version.
27:24 INDEX_WIDTH RX Ring index width
23:16 BASE_PTR_WIDTH Base Pointer Width
15:8 RX_RING_NUM Rx ring number
7:0 TX_RING_NUM Tx ring number
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
PDMA_GLO_ 0000045
10004204 PDMA_GLO_CFG
EO
CFG 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
US L
RX_ CL
BY
2B_ KG
TE_
Name OF AT RESV[16:4]
.tw IA
SW
FSE E_B
AP
T YP
Type RW RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
om NT
des TX_ RX_ TX_
mul sha des BIG RX_ TX_
c_5 WB DM DM
ti_d re_f c_3 _EN WPDMA_B DM DM
Name RESV[3:0] dw_ _D A_ A_
ma ifo_ 2b_ DIA T_SIZE A_E A_E
info DO BU BU
_en en en N N N
_en NE SY SY
Type RO RW RW RW RW RW RW RW RO RW RO RW
x.c E
Reset 0 0 0 0 0 1 0 0 0 1 0 1 0 0 0 0
ne FID
Bit(s) Name Description
31 RX_2B_OFFSET Rx 2 Byte Offset
Sets the byte size of the Rx buffer offset.
0: 4 bytes
1: 2 bytes. 0
30 CLKGATE_BYP Clock Gating Control Status Register
syn ON
Controls gating of the PDMA clock.
0: PDMA clock operates in freerun mode.
1: PDMA clock is gated when idle.
29 BYTE_SWAP Byte Swap
The DMA applies the endian rule to convert the descriptor.
@ C
0: Byte swap not applied.
1: Apply byte swap.
28:12 RESV Reserved
ien K
11 desc_5dw_info_en Support extension tx_info/rx_info to to 20 byte and the total length of
descriptor is 32 byte.
0: Disable
ch TE
1: Enable
10 multi_dma_en
9 share_fifo_en
8 desc_32b_en Support 32 Byte alignment descriptor
am IA
Enables support for 32 Byte alignment PDMA descriptors.
0: Disable
1: Enable
7 BIG_ENDIAN Selects the Endian mode for the SoC platform section.
ad ED
DMA applies the endian rule to convert payload and Tx/Rx information. DMA
does not apply the endian rule to registers or descriptors.
0: Little endian
1: Big endian
6 TX_WB_DDONE Tx Write Back DDONE
M
Enables TX_DMA writing back DDONE into TXD.
0: Disable
1: Enable
5:4 WPDMA_BT_SIZE PDMA Burst Size
Defines the burst size of PDMA.
0 : 4 DWORD (16bytes).
1 : 8 DWORD (32 bytes).
2 : 16 DWORD (64 bytes).
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Bit(s) Name Description
3 : 32 DWORD (128 bytes)
EO
3 RX_DMA_BUSY 1 : RX_DMA is busy. 0 : RX_DMA is not busy
US L
2 RX_DMA_EN Rx DMA Enable
Enables Rx DMA. When disabled, Rx DMA finishes the current receiving
packet, and then stops.
.tw IA
0: Disable
1: Enable
1 TX_DMA_BUSY Indicates whether Tx DMA is busy.
om NT
0: Not busy
1: Busy
0 TX_DMA_EN Tx DMA Enable
Enables Tx DMA. When disabled, Tx DMA finishes the current sending
packet, and then stops.
x.c E
0: Disable
1: Enable
10004208
Bit 31
ne FID
PDMA_RST_I
DX
30 29 28
PDMA_RST_IDX
27 26 25 24 23 22 21 20 19 18
0000000
17
0
16
Name RESV[31:16]
syn ON
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RESV[15:0]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
@ C
Bit(s) Name Description
31:0 RESV Reserved
ien K
ch TE
DELAY_INT_C 0000000
1000420C DELAY_INT_CFG
FG 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TX
am IA
DL
Name Y_I TXMAX_PINT TXMAX_PTIME
NT_
EN
Type RW RW RW
ad ED
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RX
DL
Name Y_I RXMAX_PINT RXMAX_PTIME
NT_
M
EN
Type RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31 TXDLY_INT_EN Tx Delay Interrupt Enable
Enables the Tx delayed interrupt mechanism.
0: Disable
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Bit(s) Name Description
1: Enable
EO
30:24 TXMAX_PINT Tx Maximum Pending Interrupts
US L
Specifies the maximum number of pending interrupts. When the number of
pending interrupts is equal to or greater than the value specified here or the
interrupt pending time has reached the limit (see below), a final TX_DLY_INT
.tw IA
is generated.
0: Disable this feature.
23:16 TXMAX_PTIME Tx Maximum Pending Time
Specifies the maximum pending time for the internal TX_DONE_INT0 and
om NT
TX_DONE_INT1. When the pending time is equal to or greater than
TXMAX_PTIME x 20us or the number of pended TX_DONE_INT0 and
TX_DONE_INT1 is equal to or greater than TXMAX_PINT (see above), a
final TX_DLY_INT is generated
0: Disable this feature.
x.c E
15 RXDLY_INT_EN Rx Delay Interrupt Enable
Enables the Rx delayed interrupt mechanism.
0: Disable
ne FID
1: Enable
14:8 RXMAX_PINT Rx Maximum Pending Interrupts
Specifies the maximum number of pending interrupts. When the number of
pended interrupts is equal to or greater than the value specified here or the
interrupt pending time has reached the limit (see below), a final RX_DLY_INT
is generated.
syn ON
0: Disable this feature.
7:0 RXMAX_PTIME Rx Maximum Pending Time
Specifies the maximum pending time for the internal RX_DONE_INT. When
the pending time is equal to or greater than RXMAX_PTIME x 20 us, or the
number of pended RX_DONE_INT is equal to or greater than RXMAX_PCNT
@ C
(see above), a final RX_DLY_INT is generated.
0: Disable this feature.
ien K
PDMA_Q_CF 0000000
10004210 PDMA_Q_CFG
G 0
ch TE
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RESV[27:12]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
am IA
Name RESV[11:0] RST_DRX_IDX1
Type RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ad ED
Bit(s) Name Description
31:4 RESV
3:0 RST_DRX_IDX1 Will stop to block interface as RX-descriptors reach this threshold
M
PDMA_INT_S 0000000
10004220 PDMA_INT_STA
TA 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RX_ RX_ TX_ TX_ RX_
CO DL CO DL DO
Name RESV1
HE Y_I HE Y_I NE_
RE NT RE NT INT
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
NT NT
Type RW RW RW RW RO RW
EO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
US L
TX_
DO
Name RESV
NE_
.tw IA
INT
Type RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
om NT
Bit(s) Name Description
31 RX_COHERENT Rx Coherent Interrupt
Asserts when the Rx DMA is ready to handle a queue, but cannot access the
queue because the driver is not ready.
30 RX_DLY_INT Rx Delay Interrupt
x.c E
Asserts when the number of pended Rx interrupts has reached a specified
level, or when the pending time is reached. Configure this interrupt using the
ne FID
DELAY_INT_CFG register.
29 TX_COHERENT Tx Coherent Interrupt
Asserts when the Tx DMA is ready to handle a queue, but cannot access the
queue because the driver is not ready.
28 TX_DLY_INT Tx Delay Interrupt
Asserts when the number of pended Tx interrupts has reached a specified
syn ON
level, or when the pending time is reached. Configure this interrupt using the
DELAY_INT_CFG register.
27:17 RESV1
16 RX_DONE_INT Rx Queue 0 Done Interrupt
Asserts when an Rx packet is received on Queue 0.
@ C
15:1 RESV
0 TX_DONE_INT Tx Queue 0 Done Interrupt
Asserts when a Tx Queue 0 packet is transmitted.
ien K
ch TE
PDMA_INT_M 0000000
10004228 PDMA_INT_MSK
SK 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TX_
RX_
RX_ CO TX_ RX_
am IA
CO
DL HE DL DO
HE
Name Y_I RE Y_I RESV1 NE_
RE
NT_ NT_ NT_ INT
NT_
EN INT EN _EN
EN
ad ED
_EN
Type RW RW RW RW RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TX_
DO
M
Name RESV NE_
INT
_EN
Type RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31 RX_COHERENT_E Masks the Rx Coherent interrupt. This interrupt asserts when the Rx
N DMA is ready to handle a queue, but cannot access the queue because
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Bit(s) Name Description
the driver is not ready.
EO
30 RX_DLY_INT_EN Masks the Rx Delay interrupt. This interrupt asserts when the number of
pending Rx interrupts has reached a specified level, or when the
US L
pending time is reached.
29 TX_COHERENT_IN Masks the Tx Coherent interrupt. This interrupt asserts when the Tx
.tw IA
T_EN DMA is ready to handle a queue, but cannot access the queue because
the driver is not ready.
28 TX_DLY_INT_EN Masks the Tx Delay interrupt. This interrupt asserts when the number of
pending Tx interrupts has reached a specified level, or when the
om NT
pending time is reached.
27:17 RESV1
16 RX_DONE_INT_EN Masks the Rx Queue 0 Done interrupt. This interrupt asserts when an Rx
packet is received on Queue 0.
x.c E
15:1 RESV
0 TX_DONE_INT_EN Masks the Tx Queue 0 Done interrupt. This interrupt asserts when a Tx
packet is transmitted on Queue 0.
ne FID
syn ON
@ C
ien K
ch TE
am IA
ad ED
OR M
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
EO
US L
.tw IA
om NT
x.c E
ne FID
syn ON
@ C
ien K
ch TE
am IA
ad ED
OR M
MediaTek Confidential © 2014 MediaTek Inc. Page 213 of 347
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
2.17 PWM (Pulse Width Modulation)
EO
2.17.1 Registers
US L
PWM Changes LOG
.tw IA
Revision Date Author Change Log
1 2013/11/26 Rick Ho Initial Version
om NT
Module name: PWM Base address: (+10005000h)
Address Name Widt Register Function
h
10005000 PWM_ENABLE 32 PWM Enable register
x.c E
10005010 PWM0_CON 32 PWM0 Control register
10005014 PWM0_HDURA 32 PWM0 High Duration register
ne FID
TION
PWM0_LDURA
10005018 TION 32 PWM0 Low Duration register
1000501C PWM0_GDURA 32 PWM0 Guard Duration register
TION
PWM0_SEND_
10005030 32 PWM0 Send Data0 register
syn ON
DATA0
10005034 PWM0_SEND_ 32 PWM0 Send Data1 register
DATA1
PWM0_WAVE_
10005038 NUM 32 PWM0 Wave Number register
@ C
1000503C PWM0_DATA_ 32 PWM0 Data Width register
WIDTH
PWM0_THRES
10005040 H 32 PWM0 Thresh register
ien K
10005044 PWM0_SEND_ 32 PWM0 Send Wave Number register
WAVENUM
10005050 PWM1_CON 32 PWM1 Control register
ch TE
10005054 PWM1_HDURA 32 PWM1 High Duration register
TION
PWM1_LDURA
10005058 TION 32 PWM1 Low Duration register
am IA
1000505C PWM1_GDURA 32 PWM1 Guard Duration register
TION
PWM1_SEND_
10005070 DATA0 32 PWM1 Send Data0 register
ad ED
10005074 PWM1_SEND_ 32 PWM1 Send Data1 register
DATA1
PWM1_WAVE_
10005078 NUM 32 PWM1 Wave Number register
1000507C PWM1_DATA_ 32 PWM1 Data Width register
M
WIDTH
PWM1_THRES
10005080 H 32 PWM1 Thresh register
10005084 PWM1_SEND_ 32 PWM1 Send Wave Number register
WAVENUM
10005090 PWM2_CON 32 PWM2 Control register
10005094 PWM2_HDURA 32 PWM2 High Duration register
TION
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
PWM2_LDURA
10005098 TION 32 PWM2 Low Duration register
EO
1000509C PWM2_GDURA 32 PWM2 Guard Duration register
TION
US L
PWM2_SEND_
100050B0 DATA0 32 PWM2 Send Data0 register
.tw IA
100050B4 PWM2_SEND_ 32 PWM2 Send Data1 register
DATA1
PWM2_WAVE_
100050B8 NUM 32 PWM2 Wave Number register
om NT
100050BC PWM2_DATA_ 32 PWM2 Data Width register
WIDTH
PWM2_THRES
100050C0 H 32 PWM2 Thresh register
100050C4 PWM2_SEND_ 32 PWM2 Send Wave Number register
x.c E
WAVENUM
100050D0 PWM3_CON 32 PWM3 Control register
ne FID
100050D4 PWM3_HDURA 32 PWM3 High Duration register
TION
PWM3_LDURA
100050D8 TION 32 PWM3 Low Duration register
100050DC PWM3_GDURA 32 PWM3 Guard Duration register
TION
PWM3_SEND_
syn ON
100050F0 DATA0 32 PWM3 Send Data0 register
100050F4 PWM3_SEND_ 32 PWM3 Send Data1 register
DATA1
PWM3_WAVE_
100050F8 NUM 32 PWM3 Wave Number register
@ C
100050FC PWM3_DATA_ 32 PWM3 Data Width register
WIDTH
PWM3_THRES
10005100 H 32 PWM3 Thresh register
ien K
10005104 PWM3_SEND_ 32 PWM3 Send Wave Number register
WAVENUM
ch TE
PWM_EN_STA
1000520C TUS 32 PWM Enable Status register
am IA
PWM_ENABL 0000000
10005000 PWM Enable register
E 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RESV[27:12]
ad ED
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PW PW PW PW
Name RESV[11:0] M3_ M2_ M1_ M0_
EN EN EN EN
M
Type RO RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:4 RESV RESERVED
3 PWM3_EN 0: disabe PWM3
1: enable PWM3
OR
MediaTek Confidential © 2014 MediaTek Inc. Page 215 of 347
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Bit(s) Name Description
2 PWM2_EN 0: disabe PWM2
EO
1: enable PWM2
US L
1 PWM1_EN 0: disabe PWM1
1: enable PWM1
0 PWM0_EN 0: disabe PWM0
.tw IA
1: enable PWM0
om NT
00007E0
10005010 PWM0_CON PWM0 Control register
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RESV0
Type RO
x.c E
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ne FID
OL
GU
D_P IDL
AR CL
WM E_V
Name STOP_BITPOS D_V RESV1 KS CLKDIV
_M AL
AL EL
OD UE
UE
E
Type RW RW RW RW RO RW RW
Reset 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0
syn ON
Bit(s) Name Description
31:16 RESV0 RESERVED
15 OLD_PWM_MODE 0: New PWM mode
@ C
1: Old PWM mode
14:9 STOP_BITPOS The stop bit position for source data in periodical mode. In FIFO mode,
it's used to indicate the stop bit position in total 64 bits. In Memory
mode, it's for the stop bit position in the last 32 bits.
ien K
8 GUARD_VALUE PWM0 output value when guard time.
7 IDLE_VALUE PWM0 output value when idle state.
ch TE
6:4 RESV1 RESERVED
3 CLKSEL Select PWM0 clock
0: CLK= 100KHz
1: CLK= 40MHz
am IA
2:0 CLKDIV Select PWM0 clock scale.
000: CLK Hz
001: CLK/2 Hz
010: CLK/4 Hz
011: CLK/8 Hz
ad ED
100: CLK/16 Hz
101: CLK/32 Hz
110: CLK/64 Hz
111: CLK/128 Hz
M
PWM0_HDUR 0000000
10005014 PWM0 High Duration register
ATION 1
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RESV
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name HDURATION
EO
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
US L
Bit(s) Name Description
.tw IA
31:16 RESV RESERVED
15:0 HDURATION PWM0 pulse duration based on the current clock when PWM output is
high. If duration =N, need to program N-1 in this register.
Note: The duration of PWM must not be 0.
om NT
PWM0_LDUR 0000000
10005018 PWM0 Low Duration register
ATION 1
x.c E
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RESV
ne FID
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name LDURATION
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
syn ON
Bit(s) Name Description
31:16 RESV RESERVED
15:0 LDURATION PWM0 pulse duration based on the current clock when PWM output is
low. If duration =N, need to program N-1 in this register.
Note: The duration of PWM must not be 0.
@ C
ien K
PWM0_GDUR 0000000
1000501C PWM0 Guard Duration register
ATION 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ch TE
Name RESV
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name GUARD_DURATION
am IA
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
ad ED
31:16 RESV RESERVED
15:0 GUARD_DURATIO
N
M
PWM0_SEND 0000000
10005030 PWM0 Send Data0 register
_DATA0 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name SEND_DATA0[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Name SEND_DATA0[15:0]
Type RW
EO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
US L
Bit(s) Name Description
31:0 SEND_DATA0 PWM0 local buffer0 of pulse sequence data to be generated.
.tw IA
Note: This value should be written only in periodically FIFO mode. In other
mode, this buffer is for internal memory access.
om NT
PWM0_SEND 0000000
10005034 PWM0 Send Data1 register
_DATA1 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name SEND_DATA1[31:16]
x.c E
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ne FID
Name SEND_DATA1[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:0 SEND_DATA1 PWM0 local buffer0 of pulse sequence data to be generated.
syn ON
Note: This value should be written only in periodically FIFO mode. In other
mode, this buffer is for internal memory access.
@ C
PWM0_WAVE 0000000
10005038 PWM0 Wave Number register
_NUM 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ien K
Name RESV
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ch TE
Name WAVE_NUM
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
am IA
Bit(s) Name Description
31:16 RESV RESERVED
15:0 WAVE_NUM The number by which PWM0 will generate from the pulse data
repeatedly.
ad ED
Note: If WAVE_NUM=0, the waveform generation will not stop until it is
disabled.
M
PWM0_DATA 0000000
1000503C PWM0 Data Width register
_WIDTH 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RESV[18:3]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RESV[2:0] DATA_WIDTH
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Type RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
EO
Bit(s) Name Description
US L
31:13 RESV RESERVED
12:0 DATA_WIDTH The PWM0 pulse data width in the old PWM mode.
.tw IA
PWM0_THRE 0000000
om NT
10005040 PWM0 Thresh register
SH 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RESV[18:3]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
x.c E
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RESV[2:0] THRESH
Type
ne FID
RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:13 RESV RESERVED
12:0 THRESH The PWM0 pulse data high/low switching threshold in the old PWM
syn ON
mode.
PWM0_SEND 0000000
10005044 PWM0 Send Wave Number register
_WAVENUM 0
@ C
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RESV
Type RO
ien K
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name SEND_WAVENUM
ch TE
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:16 RESV RESERVED
am IA
15:0 SEND_WAVENUM The number by which PWM0 has already generated from the specified
data source in the periodical mode.
ad ED
00007E0
10005050 PWM1_CON PWM1 Control register
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M
Name RESV0
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OL
GU
D_P IDL
AR CL
WM E_V
Name _M
STOP_BITPOS D_V
AL
RESV1 KS CLKDIV
AL EL
OD UE
UE
E
OR
MediaTek Confidential © 2014 MediaTek Inc. Page 219 of 347
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Type RW RW RW RW RO RW RW
Reset 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0
EO
Bit(s) Name Description
US L
31:16 RESV0 RESERVED
15 OLD_PWM_MODE Use old PWM mode
.tw IA
Note: Using old PWM mode also means periodical mode. So SRCSEL and
MODE is ignored in this situation. Only old PWM mode with 32 KHz clock
source (however could not work in the system sleep-mode).
0: New PWM mode
om NT
1: Old PWM mode
14:9 STOP_BITPOS Note: Using old PWM mode also means periodical mode. So SRCSEL
and MODE is ignored in this situation. Only old PWM mode with 32 KHz
clock source (however could not work in the system sleep-mode).
8 GUARD_VALUE PWM1 output value when guard time.
x.c E
7 IDLE_VALUE PWM1 output value when idle state.
6:4 RESV1 Select Random Generator mode
ne FID
3 CLKSEL Select PWM1 clock
0: CLK= 100KHz
1: CLK= 40MHz
2:0 CLKDIV Select PWM1 clock scale.
000: CLK Hz
syn ON
001: CLK/2 Hz
010: CLK/4 Hz
011: CLK/8 Hz
100: CLK/16 Hz
101: CLK/32 Hz
110: CLK/64 Hz
111: CLK/128 Hz
@ C
ien K
PWM1_HDUR 0000000
10005054 PWM1 High Duration register
ATION 1
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ch TE
Name RESV
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name HDURATION
am IA
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Bit(s) Name Description
ad ED
31:16 RESV RESERVED
15:0 HDURATION PWM1 pulse duration based on the current clock when PWM output is
high. If duration =N, need to program N-1 in this register.
Note: The duration of PWM must not be 0.
M
PWM1_LDUR 0000000
10005058 PWM1 Low Duration register
ATION 1
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RESV
Type RO
OR
MediaTek Confidential © 2014 MediaTek Inc. Page 220 of 347
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EO
Name LDURATION
Type RW
US L
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Bit(s) Name Description
.tw IA
31:16 RESV RESERVED
15:0 LDURATION PWM1 pulse duration based on the current clock when PWM output is
low. If duration =N, need to program N-1 in this register.
om NT
Note: The duration of PWM must not be 0.
PWM1_GDUR 0000000
1000505C PWM1 Guard Duration register
x.c E
ATION 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ne FID
Name RESV
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name GUARD_DURATION
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
syn ON
Bit(s) Name Description
31:16 RESV RESERVED
15:0 GUARD_DURATIO
N
@ C
ien K
PWM1_SEND 0000000
10005070 PWM1 Send Data0 register
_DATA0 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ch TE
Name SEND_DATA0[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name SEND_DATA0[15:0]
am IA
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
ad ED
31:0 SEND_DATA0 PWM1 local buffer0 of pulse sequence data to be generated.
Note: This value should be written only in periodically FIFO mode. In other
mode, this buffer is for internal memory access.
M
PWM1_SEND 0000000
10005074 PWM1 Send Data1 register
_DATA1 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name SEND_DATA1[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Name SEND_DATA1[15:0]
Type RW
EO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
US L
Bit(s) Name Description
31:0 SEND_DATA1 PWM1 local buffer0 of pulse sequence data to be generated.
.tw IA
Note: This value should be written only in periodically FIFO mode. In other
mode, this buffer is for internal memory access.
om NT
PWM1_WAVE 0000000
10005078 PWM1 Wave Number register
_NUM 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RESV
x.c E
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ne FID
Name WAVE_NUM
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:16 RESV RESERVED
syn ON
15:0 WAVE_NUM The number by which PWM1 will generate from the pulse data
repeatedly.
Note: If WAVE_NUM=0, the waveform generation will not stop until it is
disabled.
@ C
PWM1_DATA 0000000
1000507C PWM1 Data Width register
ien K
_WIDTH 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RESV[18:3]
ch TE
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RESV[2:0] DATA_WIDTH
Type RO RW
Reset
am IA
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:13 RESV RESERVED
ad ED
12:0 DATA_WIDTH The PWM1 pulse data width in the old PWM mode.
PWM1_THRE 0000000
M
10005080 PWM1 Thresh register
SH 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RESV[18:3]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RESV[2:0] THRESH
Type RO RW
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
EO
Bit(s) Name Description
31:13 RESV RESERVED
US L
12:0 THRESH The PWM1 pulse data high/low switching threshold in the old PWM
mode.
.tw IA
PWM1_SEND 0000000
om NT
10005084 PWM1 Send Wave Number register
_WAVENUM 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RESV
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
x.c E
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name SEND_WAVENUM
ne FID
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:16 RESV RESERVED
15:0 SEND_WAVENUM The number by which PWM1 has already generated from the specified
syn ON
data source in the periodical mode.
00007E0
10005090 PWM2_CON PWM2 Control register
0
@ C
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RESV0
Type RO
ien K
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OL
GU
ch TE
D_P IDL
AR CL
WM E_V
Name STOP_BITPOS D_V RESV1 KS CLKDIV
_M AL
AL EL
OD UE
UE
E
Type RW RW RW RW RO RW RW
am IA
Reset 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:16 RESV0 RESERVED
ad ED
15 OLD_PWM_MODE Use old PWM mode
Note: Using old PWM mode also means periodical mode. So SRCSEL and
MODE is ignored in this situation. Only old PWM mode with 32 KHz clock
source (however could not work in the system sleep-mode).
0: New PWM mode
M
1: Old PWM mode
14:9 STOP_BITPOS Note: Using old PWM mode also means periodical mode. So SRCSEL
and MODE is ignored in this situation. Only old PWM mode with 32 KHz
clock source (however could not work in the system sleep-mode).
8 GUARD_VALUE PWM2 output value when guard time.
7 IDLE_VALUE PWM2 output value when idle state.
6:4 RESV1 Select Random Generator mode
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Bit(s) Name Description
3 CLKSEL Select PWM2 clock
EO
0: CLK= 100KHz
1: CLK= 40MHz
US L
2:0 CLKDIV Select PWM2 clock scale.
000: CLK Hz
.tw IA
001: CLK/2 Hz
010: CLK/4 Hz
011: CLK/8 Hz
100: CLK/16 Hz
om NT
101: CLK/32 Hz
110: CLK/64 Hz
111: CLK/128 Hz
x.c E
PWM2_HDUR 0000000
10005094 PWM2 High Duration register
ATION 1
ne FID
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RESV
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name HDURATION
syn ON
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Bit(s) Name Description
31:16 RESV RESERVED
@ C
15:0 HDURATION PWM2 pulse duration based on the current clock when PWM output is
high. If duration =N, need to program N-1 in this register.
Note: The duration of PWM must not be 0.
ien K
ch TE
PWM2_LDUR 0000000
10005098 PWM2 Low Duration register
ATION 1
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RESV
Type RO
am IA
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name LDURATION
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
ad ED
Bit(s) Name Description
31:16 RESV RESERVED
15:0 LDURATION PWM2 pulse duration based on the current clock when PWM output is
M
low. If duration =N, need to program N-1 in this register.
Note: The duration of PWM must not be 0.
PWM2_GDUR 0000000
1000509C PWM2 Guard Duration register
ATION 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OR
MediaTek Confidential © 2014 MediaTek Inc. Page 224 of 347
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Name RESV
Type RO
EO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
US L
Name GUARD_DURATION
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
.tw IA
Bit(s) Name Description
31:16 RESV RESERVED
om NT
15:0 GUARD_DURATIO
N
x.c E
PWM2_SEND 0000000
100050B0 PWM2 Send Data0 register
_DATA0 0
ne FID
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name SEND_DATA0[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name SEND_DATA0[15:0]
Type RW
syn ON
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:0 SEND_DATA0 PWM2 local buffer0 of pulse sequence data to be generated.
Note: This value should be written only in periodically FIFO mode. In other
@ C
mode, this buffer is for internal memory access.
ien K
PWM2_SEND 0000000
100050B4 PWM2 Send Data1 register
_DATA1 0
ch TE
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name SEND_DATA1[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name SEND_DATA1[15:0]
am IA
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
ad ED
31:0 SEND_DATA1 PWM2 local buffer0 of pulse sequence data to be generated.
Note: This value should be written only in periodically FIFO mode. In other
mode, this buffer is for internal memory access.
M
PWM2_WAVE 0000000
100050B8 PWM2 Wave Number register
_NUM 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RESV
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OR
MediaTek Confidential © 2014 MediaTek Inc. Page 225 of 347
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Name WAVE_NUM
Type RW
EO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
US L
Bit(s) Name Description
31:16 RESV RESERVED
.tw IA
15:0 WAVE_NUM The number by which PWM2 will generate from the pulse data
repeatedly.
Note: If WAVE_NUM=0, the waveform generation will not stop until it is
disabled.
om NT
PWM2_DATA 0000000
100050BC PWM2 Data Width register
_WIDTH 0
x.c E
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RESV[18:3]
ne FID
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RESV[2:0] DATA_WIDTH
Type RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
syn ON
Bit(s) Name Description
31:13 RESV RESERVED
12:0 DATA_WIDTH The PWM2 pulse data width in the old PWM mode.
@ C
PWM2_THRE 0000000
100050C0 PWM2 Thresh register
SH 0
ien K
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RESV[18:3]
Type RO
ch TE
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RESV[2:0] THRESH
Type RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
am IA
Bit(s) Name Description
31:13 RESV RESERVED
ad ED
12:0 THRESH The PWM2 pulse data high/low switching threshold in the old PWM
mode.
PWM2_SEND 0000000
M
100050C4 PWM2 Send Wave Number register
_WAVENUM 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RESV
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name SEND_WAVENUM
Type RO
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
EO
Bit(s) Name Description
31:16 RESV RESERVED
US L
15:0 SEND_WAVENUM The number by which PWM2 has already generated from the specified
data source in the periodical mode.
.tw IA
00007E0
om NT
100050D0 PWM3_CON PWM3 Control register
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RESV0
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
x.c E
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OL
GU
ne FID
D_P IDL
AR CL
WM E_V
Name STOP_BITPOS D_V RESV1 KS CLKDIV
_M AL
AL EL
OD UE
UE
E
Type RW RW RW RW RO RW RW
Reset 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0
syn ON
Bit(s) Name Description
31:16 RESV0 RESERVED
15 OLD_PWM_MODE Use old PWM mode
Note: Using old PWM mode also means periodical mode. So SRCSEL and
@ C
MODE is ignored in this situation. Only old PWM mode with 32 KHz clock
source (however could not work in the system sleep-mode).
0: New PWM mode
1: Old PWM mode
ien K
14:9 STOP_BITPOS Note: Using old PWM mode also means periodical mode. So SRCSEL
and MODE is ignored in this situation. Only old PWM mode with 32 KHz
clock source (however could not work in the system sleep-mode).
ch TE
8 GUARD_VALUE PWM3 output value when guard time.
7 IDLE_VALUE PWM3 output value when idle state.
6:4 RESV1 Select Random Generator mode
3 CLKSEL Select PWM3 clock
am IA
0: CLK= 100KHz
1: CLK= 40MHz
2:0 CLKDIV Select PWM3 clock scale.
ad ED
000: CLK Hz
001: CLK/2 Hz
010: CLK/4 Hz
011: CLK/8 Hz
100: CLK/16 Hz
101: CLK/32 Hz
M
110: CLK/64 Hz
111: CLK/128 Hz
PWM3_HDUR 0000000
100050D4 PWM3 High Duration register
ATION 1
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Name RESV
Type RO
EO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
US L
Name HDURATION
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
.tw IA
Bit(s) Name Description
31:16 RESV RESERVED
om NT
15:0 HDURATION PWM3 pulse duration based on the current clock when PWM output is
high. If duration =N, need to program N-1 in this register.
Note: The duration of PWM must not be 0.
x.c E
PWM3_LDUR 0000000
100050D8 PWM3 Low Duration register
ATION 1
ne FID
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RESV
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name LDURATION
syn ON
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Bit(s) Name Description
31:16 RESV RESERVED
@ C
15:0 LDURATION PWM3 pulse duration based on the current clock when PWM output is
low. If duration =N, need to program N-1 in this register.
Note: The duration of PWM must not be 0.
ien K
ch TE
PWM3_GDUR 0000000
100050DC PWM3 Guard Duration register
ATION 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RESV
Type RO
am IA
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name GUARD_DURATION
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ad ED
Bit(s) Name Description
31:16 RESV RESERVED
15:0 GUARD_DURATIO
M
PWM3_SEND 0000000
100050F0 PWM3 Send Data0 register
_DATA0 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name SEND_DATA0[31:16]
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
EO
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name SEND_DATA0[15:0]
US L
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
.tw IA
Bit(s) Name Description
31:0 SEND_DATA0 PWM3 local buffer0 of pulse sequence data to be generated.
Note: This value should be written only in periodically FIFO mode. In other
om NT
mode, this buffer is for internal memory access.
PWM3_SEND 0000000
100050F4 PWM3 Send Data1 register
_DATA1 0
x.c E
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name SEND_DATA1[31:16]
ne FID
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name SEND_DATA1[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
syn ON
Bit(s) Name Description
31:0 SEND_DATA1 PWM3 local buffer0 of pulse sequence data to be generated.
Note: This value should be written only in periodically FIFO mode. In other
mode, this buffer is for internal memory access.
@ C
PWM3_WAVE 0000000
100050F8 PWM3 Wave Number register
ien K
_NUM 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
ch TE
RESV
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name WAVE_NUM
Type RW
am IA
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
ad ED
31:16 RESV RESERVED
15:0 WAVE_NUM The number by which PWM3 will generate from the pulse data
repeatedly.
Note: If WAVE_NUM=0, the waveform generation will not stop until it is
disabled.
M
PWM3_DATA 0000000
100050FC PWM3 Data Width register
_WIDTH 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RESV[18:3]
Type RO
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EO
Name RESV[2:0] DATA_WIDTH
Type RO RW
US L
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
.tw IA
31:13 RESV RESERVED
12:0 DATA_WIDTH The PWM3 pulse data width in the old PWM mode.
om NT
PWM3_THRE 0000000
10005100 PWM3 Thresh register
SH 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
x.c E
Name RESV[18:3]
Type RO
Reset
ne FID
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RESV[2:0] THRESH
Type RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
syn ON
31:13 RESV RESERVED
12:0 THRESH The PWM3 pulse data high/low switching threshold in the old PWM
mode.
@ C
PWM3_SEND 0000000
10005104 PWM3 Send Wave Number register
_WAVENUM 0
ien K
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RESV
Type RO
ch TE
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name SEND_WAVENUM
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
am IA
Bit(s) Name Description
31:16 RESV RESERVED
15:0 SEND_WAVENUM The number by which PWM3 has already generated from the specified
ad ED
data source in the periodical mode.
PWM_EN_ST 0000000
M
1000520C PWM Enable Status register
ATUS 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RESV[27:12]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PW PW PW PW
Name RESV[11:0]
M3_ M2_ M1_ M0_
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
EN_ EN_ EN_ EN_
ST ST ST ST
EO
Type RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
US L
Bit(s) Name Description
.tw IA
31:4 RESV RESERVED
3 PWM3_EN_ST PWM3 enable status
2 PWM2_EN_ST PWM2 enable status
1 PWM1_EN_ST PWM1 enable status
om NT
0 PWM0_EN_ST PWM0 enable status
x.c E
ne FID
syn ON
@ C
ien K
ch TE
am IA
ad ED
OR M
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
2.18 Frame Engine
EO
2.18.1 Registers
US L
SDM Changes LOG
.tw IA
Revision Date Author Change Log
0.1 2013/5/27 PeterCT WU Initialization
om NT
Module name: SDM Base address: (+10100000h)
Address Name Widt Register Function
h
10100800 TX_BASE_PTR 32 TX Ring #0 Base Pointer
x.c E
_0
TX_MAX_CNT_
10100804 0 32 TX Ring #0 Maximum Count
ne FID
10100808 TX_CTX_IDX_0 32 TX Ring #0 CPU pointer
1010080C TX_DTX_IDX_0 32 TX Ring #0 DMA poitner
10100810 TX_BASE_PTR 32 TX Ring #1 Base Pointer
_1
TX_MAX_CNT_
10100814 32 TX Ring #1 Maximum Count
syn ON
1
10100818 TX_CTX_IDX_1 32 TX Ring #1 CPU pointer
1010081C TX_DTX_IDX_1 32 TX Ring #1 DMA poitner
10100820 TX_BASE_PTR 32 TX Ring #2 Base Pointer
_2
@ C
TX_MAX_CNT_
10100824 2 32 TX Ring #2 Maximum Count
10100828 TX_CTX_IDX_2 32 TX Ring #2 CPU pointer
ien K
1010082C TX_DTX_IDX_2 32 TX Ring #2 DMA poitner
10100830 TX_BASE_PTR 32 TX Ring #3 Base Pointer
_3
ch TE
TX_MAX_CNT_
10100834 3 32 TX Ring #3 Maximum Count
10100838 TX_CTX_IDX_3 32 TX Ring #3 CPU pointer
1010083C TX_DTX_IDX_3 32 TX Ring #3 DMA poitner
am IA
10100900 RX_BASE_PTR 32 RX Ring #0 Base Pointer
_0
RX_MAX_CNT_
10100904 0 32 RX Ring #0 Maximum Count
ad ED
10100908 RX_CRX_IDX_0 32 RX Ring #0 CPU pointer
1010090C RX_DRX_IDX_0 32 RX Ring #0 DMA poitner
10100910 RX_BASE_PTR 32 RX Ring #1 Base Pointer
_1
RX_MAX_CNT_
M
10100914 1 32 RX Ring #1 Maximum Count
10100918 RX_CRX_IDX_1 32 RX Ring #1 CPU pointer
1010091C RX_DRX_IDX_1 32 RX Ring #1 DMA poitner
10100A00 PDMA_INFO 32 PDMA Information
PDMA_GLO_C
10100A04 FG 32 PDMA Global Configuration
10100A0C DELAY_INT_CF 32 Delay Interrupt Configuration
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
G
10100A10 FREEQ_THRES 32 Free Queue Threshold
EO
10100A20 INT_STATUS 32 Interrupt Status
US L
10100A28 INT_MASK 32 Interrupt Mask
10100A80 PDMA_SCH 32 Scheduler Configuration for Q0&Q1
.tw IA
10100A84 PDMA_WRR 32 Scheduler Configuration for Q2&Q3
10100C00 SDM_CON 32 Switch DMA Control
10100C04 SDM_RING 32 Switch DMA Rx Ring
10100C08 SDM_TRING 32 Switch DMA TX Ring
om NT
SDM_MAC_AD
10100C0C RL 32 Switch MAC Address LSB
10100C10 SDM_MAC_AD 32 Switch MAC Address MSB
RH
10100D00 SDM_TPCNT 32 Switch DMA Tx Packet Count
x.c E
10100D04 SDM_TBCNT 32 Switch DMA TX Byte Count
10100D08 SDM_RPCNT 32 Switch DMA RX Packet Count
ne FID
10100D0C SDM_RBCNT 32 Switch DMA RX Byte Count
10100D10 SDM_CS_ERR 32 Switch DMA RX Checksum Error
syn ON
TX_BASE_PT 0000000
10100800 TX Ring #0 Base Pointer
R_0 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name TX_BASE_PTR[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
@ C
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name TX_BASE_PTR[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ien K
Bit(s) Name Description
ch TE
31:0 TX_BASE_PTR Point to the base address of TX Ring #0 (4-DW aligned address)
TX_MAX_CNT 0000000
am IA
10100804 TX Ring #0 Maximum Count
_0 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
ad ED
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name TX_MAX_CNT
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0
M
Bit(s) Name Description
11:0 TX_MAX_CNT The maximum number of TXD count in TX Ring #0
10100808 TX_CTX_IDX_ TX Ring #0 CPU pointer 0000000
OR
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Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
0 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EO
Name
Type
US L
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
.tw IA
Name TX_CTX_IDX
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
om NT
11:0 TX_CTX_IDX Point to the next TXD CPU wants to use
x.c E
TX_DTX_IDX_ 0000000
1010080C TX Ring #0 DMA poitner
0 0
ne FID
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name TX_DTX_IDX
Type RO
syn ON
Reset 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
11:0 TX_DTX_IDX Point to the next TXD DMA wants to use
@ C
TX_BASE_PT 0000000
10100810 TX Ring #1 Base Pointer
R_1 0
ien K
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name TX_BASE_PTR[31:16]
ch TE
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name TX_BASE_PTR[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
am IA
Bit(s) Name Description
31:0 TX_BASE_PTR Point to the base address of TX Ring #0 (4-DW aligned address)
ad ED
TX_MAX_CNT 0000000
10100814 TX Ring #1 Maximum Count
_1 0
M
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name TX_MAX_CNT
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Bit(s) Name Description
11:0 TX_MAX_CNT The maximum number of TXD count in TX Ring #0
EO
US L
TX_CTX_IDX_ 0000000
.tw IA
10100818 TX Ring #1 CPU pointer
1 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
om NT
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name TX_CTX_IDX
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0
x.c E
Bit(s) Name Description
ne FID
11:0 TX_CTX_IDX Point to the next TXD CPU wants to use
TX_DTX_IDX_ 0000000
1010081C TX Ring #1 DMA poitner
1 0
syn ON
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name TX_DTX_IDX
@ C
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
ien K
11:0 TX_DTX_IDX Point to the next TXD DMA wants to use
ch TE
TX_BASE_PT 0000000
10100820 TX Ring #2 Base Pointer
R_2 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
am IA
Name TX_BASE_PTR[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ad ED
Name TX_BASE_PTR[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
M
31:0 TX_BASE_PTR Point to the base address of TX Ring #0 (4-DW aligned address)
TX_MAX_CNT 0000000
10100824 TX Ring #2 Maximum Count
_2 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Type
Reset
EO
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name TX_MAX_CNT
US L
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0
.tw IA
Bit(s) Name Description
11:0 TX_MAX_CNT The maximum number of TXD count in TX Ring #0
om NT
TX_CTX_IDX_ 0000000
10100828 TX Ring #2 CPU pointer
2 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
x.c E
Name
Type
Reset
ne FID
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name TX_CTX_IDX
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
syn ON
11:0 TX_CTX_IDX Point to the next TXD CPU wants to use
TX_DTX_IDX_ 0000000
1010082C TX Ring #2 DMA poitner
@ C
2 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
ien K
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name TX_DTX_IDX
ch TE
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
am IA
11:0 TX_DTX_IDX Point to the next TXD DMA wants to use
ad ED
TX_BASE_PT 0000000
10100830 TX Ring #3 Base Pointer
R_3 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name TX_BASE_PTR[31:16]
Type RW
M
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name TX_BASE_PTR[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:0 TX_BASE_PTR Point to the base address of TX Ring #0 (4-DW aligned address)
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
EO
TX_MAX_CNT 0000000
10100834 TX Ring #3 Maximum Count
US L
_3 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
.tw IA
Name
Type
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name TX_MAX_CNT
om NT
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
x.c E
11:0 TX_MAX_CNT The maximum number of TXD count in TX Ring #0
10100838
Bit
Name
31
ne FID
TX_CTX_IDX_
3
30 29 28
TX Ring #3 CPU pointer
27 26 25 24 23 22 21 20 19 18
0000000
17
0
16
Type
syn ON
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name TX_CTX_IDX
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0
@ C
Bit(s) Name Description
11:0 TX_CTX_IDX Point to the next TXD CPU wants to use
ien K
TX_DTX_IDX_ 0000000
ch TE
1010083C TX Ring #3 DMA poitner
3 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
Reset
am IA
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name TX_DTX_IDX
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0
ad ED
Bit(s) Name Description
11:0 TX_DTX_IDX Point to the next TXD DMA wants to use
M
RX_BASE_PT 0000000
10100900 RX Ring #0 Base Pointer
R_0 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RX_BASE_PTR[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Name RX_BASE_PTR[15:0]
Type RW
EO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
US L
Bit(s) Name Description
31:0 RX_BASE_PTR Point to the base address of RX Ring #0 (4-DW aligned address)
.tw IA
RX_MAX_CNT 0000000
10100904 RX Ring #0 Maximum Count
om NT
_0 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
Reset
x.c E
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name TX_MAX_CNT
Type RW
ne FID
Reset 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
11:0 TX_MAX_CNT The maximum number of RXD count in RX Ring #0
syn ON
RX_CRX_IDX_ 0000000
10100908 RX Ring #0 CPU pointer
0 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
@ C
Type
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name TX_CTX_IDX
ien K
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0
ch TE
Bit(s) Name Description
11:0 TX_CTX_IDX Point to the next RXD CPU wants to use
am IA
RX_DRX_IDX_ 0000000
1010090C RX Ring #0 DMA poitner
0 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ad ED
Name
Type
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RX_DRX_IDX
M
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
11:0 RX_DRX_IDX Point to the next RXD DMA wants to use
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
RX_BASE_PT 0000000
10100910 RX Ring #1 Base Pointer
EO
R_1 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
US L
Name RX_BASE_PTR[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
.tw IA
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RX_BASE_PTR[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
om NT
Bit(s) Name Description
31:0 RX_BASE_PTR Point to the base address of RX Ring #0 (4-DW aligned address)
x.c E
RX_MAX_CNT 0000000
10100914 RX Ring #1 Maximum Count
ne FID
_1 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
syn ON
Name TX_MAX_CNT
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
11:0 TX_MAX_CNT The maximum number of RXD count in RX Ring #0
@ C
ien K
RX_CRX_IDX_ 0000000
10100918 RX Ring #1 CPU pointer
1 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ch TE
Name
Type
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name TX_CTX_IDX
am IA
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
ad ED
11:0 TX_CTX_IDX Point to the next RXD CPU wants to use
RX_DRX_IDX_ 0000000
M
1010091C RX Ring #1 DMA poitner
1 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RX_DRX_IDX
Type RO
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Reset 0 0 0 0 0 0 0 0 0 0 0 0
EO
Bit(s) Name Description
11:0 RX_DRX_IDX Point to the next RXD DMA wants to use
US L
.tw IA
1C00020
10100A00 PDMA_INFO PDMA Information
4
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
om NT
Name INDEX_WIDTH BASE_PTR_WIDTH
Type RO RO
Reset 1 1 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RX_RING_NUM TX_RING_NUM
x.c E
Type RO RO
Reset 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0
ne FID
Bit(s) Name Description
27:24 INDEX_WIDTH Point to the next RXD CPU wants to use
23:16 BASE_PTR_WIDTH Base pointer width, x
Base_addr[31:32-x] is shared with all ring base adderss. Only ring #0 base
address[31:32-x] field Is writabl.
syn ON
[note]: "0" means no bit of base_address is shared.
15:8 RX_RING_NUM Rx ring number
7:0 TX_RING_NUM Tx ring number
@ C
PDMA_GLO_ 0000005
10100A04 PDMA Global Configuration
CFG 0
ien K
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name HDR_SEG_LEN
Type RW
Reset
ch TE
0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TX_ RX_ TX_
BIG RX_ TX_
WB DM DM
_EN PDMA_BT DM DM
Name _D A_ A_
DIA _SIZE A_E A_E
DO BU BU
N N N
am IA
NE SY SY
Type RW RW RW RO RW RO RW
Reset 0 1 0 1 0 0 0 0
ad ED
Bit(s) Name Description
29:16 HDR_SEG_LEN Header Segment Length
Specify the header segment size in byte to supoprt RX header/payload
scattering fucntion, when set to a non-zero value.
When set to zero, the header/payload scattering feature is disabled.
M
7 BIG_ENDIAN Big endian
0: PDMA will not do byte swapping for TX/RX packet header and payload
1: PDMA will do byte swaping for TX/RX packet header and payload
6 TX_WB_DDONE 0: Disable TX_DMA writing back DDONE into TXD
1: Enable TX_DMA writing back DDONE into TXD
5:4 PDMA_BT_SIZE The burst size of PDMA
0: 4 DWORDs (16-bytes)
1: 8 DWORDs (32-bytes)
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Bit(s) Name Description
2: 16 DWORDs (64-bytes)
EO
3: Reserved
3 RX_DMA_BUSY 0: RX_DMA is not busy
US L
1: RX_DMA is busy
2 RX_DMA_EN 0: Diable RX_DMA (when disabled, RX_DMA will finish the current receiving
.tw IA
packet, then stop)
1: Enable RX_DMA
1 TX_DMA_BUSY 0: TX_DMA is not busy
1: TX_DMA is busy
om NT
0 TX_DMA_EN 0: Disable TX_DMA (when disabled, TX_DMA will finish the current sending
packet, then stop)
1: Enable TX_DMA
x.c E
DELAY_INT_C 0000000
10100A0C Delay Interrupt Configuration
ne FID
FG 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TX
DL
Name Y_I TXMAX_PINT TXMAX_PTIME
NT_
EN
syn ON
Type RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RX
DL
Name Y_I RXMAX_PINT RXMAX_PTIME
@ C
NT_
EN
Type RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ien K
Bit(s) Name Description
31 TXDLY_INT_EN Delay interrupt mechanism
ch TE
0: Disable TX delayed interrupt mechanism
1: Enable Tx delayed interrupt mechanism
30:24 TXMAX_PINT Specified Max. number of pended interrupts
When the number of pended interrupts is equal or greater than the value
am IA
specified here or interupt pending time reach the limit (see below), an final
TX_DLY_INT is generated.
[Note] reset to 0 can disable pending interrupt count check.
23:16 TXMAX_PTIME Specified Max. pended time
ad ED
When the pending time is equal or greater than TXMAX_PTIME x 20us or the
number of pended TX_DONE is equal or greater than TXMAX_PINT 9see
above), an final TX_DLY_INT is generated.
[Note] reset to 0 can disable pending interrupt time check.
15 RXDLY_INT_EN 0: Disable Rx delayed interrupt mechanism
M
1: Enable Rx delayed interrupt mechanism
14:8 RXMAX_PINT Specified Max. number of pended interrupts
When the number of pended interrupts is equal or greater than the value
specified here or interupt pending time reach the limit (see below), an final
RX_DLY_INT is generated.
[Note] reset to 0 can disable pending interrupt count check.
7:0 RXMAX_PTIME Specified Max. pended time
When the pending time is equal or greater than RXMAX_PTIME x 20us or the
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Bit(s) Name Description
number of pended RX_DONE is equal or greater than RXMAX_PINT 9see
EO
above), an finalRX_DLY_INT is generated.
[Note] reset to 0 can disable pending interrupt time check.
US L
.tw IA
FREEQ_THRE 0000000
10100A10 Free Queue Threshold
S 2
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
om NT
Name
Type
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name FREEQ_THRES
Type RW
x.c E
Reset 0 0 1 0
ne FID
Bit(s) Name Description
3:0 FREEQ_THRES Rx free queue threshold
PDMA will stop DMA interface when left RX descriptors reach this threshold
syn ON
0000000
10100A20 INT_STATUS Interrupt Status
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RX_ TX_ RX_ RX_
RX_ TX_
CO CO DO DO
DL DL
@ C
Name HE HE NE_ NE_
Y_I Y_I
RE RE INT INT
NT NT
NT NT 1 0
W1 W1 W1 W1 W1 W1
Type
ien K
C C C C C C
Reset 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TX_ TX_ TX_ TX_
ch TE
DO DO DO DO
Name NE_ NE_ NE_ NE_
INT INT INT INT
3 2 1 0
W1 W1 W1 W1
Type
am IA
C C C C
Reset 0 0 0 0
Bit(s) Name Description
ad ED
31 RX_COHERENT RX_DMA finds data coherent event while checking ddone bit.
30 RX_DLY_INT Summary of the whole PDMA Rx related interrupts.
29 TX_COHERENT TX_DMA finds data coherent event while checking ddone bit.
28 TX_DLY_INT Summary of the whole PDMA Tx related interrupts.
M
17 RX_DONE_INT1 Rx ring #1 packet receive interrupt
16 RX_DONE_INT0 Rx ring #0 packet receive interrupt
3 TX_DONE_INT3 Tx ring #3 packet transmit interrupt
2 TX_DONE_INT2 Tx ring #2 packet transmit interrupt
1 TX_DONE_INT1 Tx ring #1 packet transmit interrupt
0 TX_DONE_INT0 Tx ring #0 packet transmit interrupt
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
EO
0000000
10100A28 INT_MASK Interrupt Mask
0
US L
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RX_ TX_ RX_ RX_
RX_ TX_
.tw IA
CO CO DO DO
DL DL
Name HE
Y_I
HE
Y_I
NE_ NE_
RE RE INT INT
NT NT
NT NT 1 0
Type RW RW RW RW RW RW
om NT
Reset 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TX_ TX_ TX_ TX_
DO DO DO DO
Name NE_ NE_ NE_ NE_
INT INT INT INT
x.c E
3 2 1 0
Type RW RW RW RW
Reset 0 0 0 0
Bit(s)
31
ne FID
Name
RX_COHERENT
Description
Interrupt enable for RX_DMA data coherent vent
0: Disable interrupt
1: Enable interrupt
syn ON
30 RX_DLY_INT Summary of the whole PDMA Rx related interrupts.
0: Disable interrupt
1: Enable interrupt
29 TX_COHERENT Interrupt enable for TX_DMA data coherent vent
0: Disable interrupt
1: Enable interrupt
@ C
28 TX_DLY_INT Summary of the whole PDMA Tx related interrupts.
0: Disable interrupt
1: Enable interrupt
ien K
17 RX_DONE_INT1 Rx ring #1 packet receive interrupt
0: Disable interrupt
1: Enable interrupt
ch TE
16 RX_DONE_INT0 Rx ring #0 packet receive interrupt
0: Disable interrupt
1: Enable interrupt
3 TX_DONE_INT3 Tx ring #3 packet transmit interrupt
am IA
0: Disable interrupt
1: Enable interrupt
2 TX_DONE_INT2 Tx ring #2 packet transmit interrupt
0: Disable interrupt
ad ED
1: Enable interrupt
1 TX_DONE_INT1 Tx ring #1 packet transmit interrupt
0: Disable interrupt
1: Enable interrupt
M
0 TX_DONE_INT0 Tx ring #0 packet transmit interrupt
0: Disable interrupt
1: Enable interrupt
0000000
10100A80 PDMA_SCH Scheduler Configuration for Q0&Q1
0
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SCH_MOD
Name
EO
E
Type RW
Reset
US L
0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
.tw IA
Type
Reset
Bit(s) Name Description
om NT
25:24 SCH_MODE Scheduling Mode
00: WRR
01: Strict priority, Q3>Q2,Q1>Q0
10: Mixed mode, Q3>WRR(Q2,Q1,Q0)
11: Mixed mode, Q3>Q2>WRR(Q1,Q0)
x.c E
ne FID
0000000
10100A84 PDMA_WRR Scheduler Configuration for Q2&Q3
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
Reset
syn ON
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name SCH_WT_Q3 SCH_WT_Q2 SCH_WT_Q1 SCH_WT_Q0
Type RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0
@ C
Bit(s) Name Description
14:12 SCH_WT_Q3 Scheduling Weight of TX Q3
10:8 SCH_WT_Q2 Scheduling Weight of TX Q2
ien K
6:4 SCH_WT_Q1 Scheduling Weight of TX Q1
2:0 SCH_WT_Q0 Scheduling Weight of TX Q0
ch TE
0007810
10100C00 SDM_CON Switch DMA Control
0
am IA
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UN
PO
PD LO TC _D UD TC
RT_ IPC
Name REV0 MA
MA
OP O_8 RO PC PC
S
_FC _EN 1xx P_E S S
ad ED
P
N
Type RO RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name EXT_VLAN
M
Type RW
Reset 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:24 REV0 Reserved
23 PDMA_FC TX PDMA Flow Cotnrol Enable
When this bit is set, the downstream fow control is enabled on PDMA 4 TX
Ring (SDM_TRGING)
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Bit(s) Name Description
0: Disable
EO
1: Enable
22 PORT_MAP RX Ring Selection
US L
The received frame will be collected into the corresponding PDMA RX Ring
based on the source port priority tag.
.tw IA
0: Priority Tag (SDMRRING[7:0])
1: Source Port (SDM_RRING[12:8])
21 LOOP_EN Frame Engine Loop-back Mode Enable
20 TCO_81xx Special tag Recongization Enable
om NT
When this bit is set, PDI(0x81xx) is recognized by the first byte (0x81) only.
The second byte could be used for the specilqa purpose like the incoming
source port.
19 UN_DROP_EN Drop Unknonwn MAC Address
x.c E
0: Disable
1: Enable
18 UDPCS UDP Packet Checksum RX Offload Enable
ne FID
0: disable, checksum result is showed on RX descriptor
1: enable, drop checksum error packet
17 TCPCS TCP Packet Checksum RX Offload Enable
0: disable, checksum result is showed on RX descriptor
1: enable, drop checksum error packet
syn ON
16 IPCS IP Header Checksum RX Offload Enable
0: disable, checksum result is showed on RX descriptor
1: enable, drop checksum error packet
15:0 EXT_VLAN Outer VLAN Protocol ID
The specific vlaue is used to recognize the outer VLAN protocol ID only. Per
inner VLAN or the general VLAN-tagged frame, the value PID=0x8100 is the
@ C
uniqe protocol ID.
ien K
0000000
10100C04 SDM_RING Switch DMA Rx Ring
0
ch TE
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
QU QU QU QU
E3_ E2_ E1_ E0_
Name REV0 RIN RIN RIN RIN
G_F G_F G_F G_F
am IA
C C C C
Type RO RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PO PO PO PO PO PRI
ad ED
PRI PRI PRI PRI PRI PRI PRI
RT4 RT3 RT2 RT1 RT0 10_
Name _RI _RI _RI _RI _RI
7_R 6_R 5_R 4_R 3_R 2_R 1_R
RIN
ING ING ING ING ING ING ING
NG NG NG NG NG G
Type RW RW RW RW RW RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0
M
Bit(s) Name Description
31:20 REV0 Reserved
19 QUE3_RING_FC Pause Switch Queue 3 by RX Ring##
When RX Ring# reaches the reserved free threshold(FREEQ_THRES), the
queue 3 to CPU will be paused.
1: RX Ring #0
0: RX Ring #1
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Bit(s) Name Description
18 QUE2_RING_FC Pause Switch Queue 2 by RX Ring##
EO
When RX Ring# reaches the reserved free threshold(FREEQ_THRES), the
queue 3 to CPU will be paused.
US L
1: RX Ring #0
0: RX Ring #1
.tw IA
17 QUE1_RING_FC Pause Switch Queue 1 by RX Ring##
When RX Ring# reaches the reserved free threshold(FREEQ_THRES), the
queue 3 to CPU will be paused.
1: RX Ring #0
om NT
0: RX Ring #1
16 QUE0_RING_FC Pause Switch Queue 0 by RX Ring##
When RX Ring# reaches the reserved free threshold(FREEQ_THRES), the
queue 3 to CPU will be paused.
1: RX Ring #0
x.c E
0: RX Ring #1
12 PORT4_RING Source Port 4 to RX Ring##
ne FID
The received frames from the source port 4 will be sent to RX Ring#
[Note] To use the source port, the special tag between FE and SW should be
enabled.
1: RX Ring #0
0: RX Ring #1
11 PORT3_RING Source Port 3 to RX Ring##
syn ON
The received frames from the source port 4 will be sent to RX Ring#
[Note] To use the source port, the special tag between FE and SW should be
enabled.
1: RX Ring #0
0: RX Ring #1
10 PORT2_RING Source Port 2 to RX Ring##
@ C
The received frames from the source port 4 will be sent to RX Ring#
[Note] To use the source port, the special tag between FE and SW should be
enabled.
1: RX Ring #0
ien K
0: RX Ring #1
9 PORT1_RING Source Port 1 to RX Ring##
ch TE
The received frames from the source port 4 will be sent to RX Ring#
[Note] To use the source port, the special tag between FE and SW should be
enabled.
1: RX Ring #0
0: RX Ring #1
am IA
8 PORT0_RING Source Port 0 to RX Ring##
The received frames from the source port 4 will be sent to RX Ring#
[Note] To use the source port, the special tag between FE and SW should be
enabled.
1: RX Ring #0
ad ED
0: RX Ring #1
7 PRI7_RING Priority 7 to RX Ring##
The received frames with priority tag 7 will be sent to RX Ring#
1: RX Ring #0
0: RX Ring #1
M
6 PRI6_RING Priority 6 to RX Ring##
The received frames with priority tag 6 will be sent to RX Ring#
1: RX Ring #0
0: RX Ring #1
5 PRI5_RING Priority 5 to RX Ring##
The received frames with priority tag 5 will be sent to RX Ring#
1: RX Ring #0
OR
MediaTek Confidential © 2014 MediaTek Inc. Page 246 of 347
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Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited.
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Bit(s) Name Description
0: RX Ring #1
EO
4 PRI4_RING Priority 4 to RX Ring##
US L
The received frames with priority tag 4 will be sent to RX Ring#
1: RX Ring #0
0: RX Ring #1
.tw IA
3 PRI3_RING Priority 3 to RX Ring##
The received frames with priority tag 3 will be sent to RX Ring#
1: RX Ring #0
0: RX Ring #1
om NT
2 PRI2_RING Priority 2 to RX Ring##
The received frames with priority tag 2 will be sent to RX Ring#
1: RX Ring #0
0: RX Ring #1
x.c E
1 PRI1_RING Priority 1to RX Ring##
The received frames with priority tag 1 will be sent to RX Ring#
1: RX Ring #0
ne FID
0: RX Ring #1
0 PRI10_RING Priority 0 to RX Ring##
The received frames with priority tag 0 will be sent to RX Ring#
1: RX Ring #0
0: RX Ring #1
syn ON
0000000
10100C08 SDM_TRING Switch DMA TX Ring
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
@ C
Name RING3_WAN_FC RING2_WAN_FC RING1_WAN_FC RING0_WAN_FC
Type RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ien K
Name RING3_LAN_FC RING2_LAN_FC RING1_LAN_FC RING0_LAN_FC
Type RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ch TE
Bit(s) Name Description
31:28 RING3_WAN_FC Pause TX Ring 3 by WAN Port
TX Ring# will be paused when the corresponding switch egress queue on
WAN port is congested.
am IA
Bit.3: WAN port Queue#3
Bit.2: WAN port Queue#2
Bit.1: WAN port Queue#1
Bit.0: WAN port Queue#0
ad ED
27:24 RING2_WAN_FC Pause TX Ring 2 by WAN Port
TX Ring# will be paused when the corresponding switch egress queue on
WAN port is congested.
Bit.3: WAN port Queue#3
Bit.2: WAN port Queue#2
M
Bit.1: WAN port Queue#1
Bit.0: WAN port Queue#0
23:20 RING1_WAN_FC Pause TX Ring 1 by WAN Port
TX Ring# will be paused when the corresponding switch egress queue on
WAN port is congested.
Bit.3: WAN port Queue#3
Bit.2: WAN port Queue#2
Bit.1: WAN port Queue#1
OR
MediaTek Confidential © 2014 MediaTek Inc. Page 247 of 347
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Bit(s) Name Description
Bit.0: WAN port Queue#0
EO
19:16 RING0_WAN_FC Pause TX Ring 0 by WAN Port
US L
TX Ring# will be paused when the corresponding switch egress queue on
WAN port is congested.
Bit.3: WAN port Queue#3
.tw IA
Bit.2: WAN port Queue#2
Bit.1: WAN port Queue#1
Bit.0: WAN port Queue#0
15:12 RING3_LAN_FC Pause TX Ring 3 by LAN Port
om NT
TX Ring# will be paused when the corresponding switch egress queue on
WAN port is congested.
Bit.3: LAN port Queue#3
Bit.2: LAN port Queue#2
Bit.1: LAN port Queue#1
x.c E
Bit.0: LAN port Queue#0
11:8 RING2_LAN_FC Pause TX Ring 2 by LAN Port
TX Ring# will be paused when the corresponding switch egress queue on
ne FID
WAN port is congested.
Bit.3: LAN port Queue#3
Bit.2: LAN port Queue#2
Bit.1: LAN port Queue#1
Bit.0: LAN port Queue#0
7:4 RING1_LAN_FC Pause TX Ring 1 by LAN Port
syn ON
TX Ring# will be paused when the corresponding switch egress queue on
WAN port is congested.
Bit.3: LAN port Queue#3
Bit.2: LAN port Queue#2
Bit.1: LAN port Queue#1
Bit.0: LAN port Queue#0
@ C
3:0 RING0_LAN_FC Pause TX Ring 0 by LAN Port
TX Ring# will be paused when the corresponding switch egress queue on
WAN port is congested.
ien K
Bit.3: LAN port Queue#3
Bit.2: LAN port Queue#2
Bit.1: LAN port Queue#1
ch TE
Bit.0: LAN port Queue#0
SDM_MAC_A 0000000
10100C0C Switch MAC Address LSB
am IA
DRL 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name MAC_ADDR_LSB[31:16]
Type RW
ad ED
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name MAC_ADDR_LSB[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
M
Bit(s) Name Description
31:0 MAC_ADDR_LSB MAC Address bit[31:0]
SDM_MAC_A 0000000
10100C10 Switch MAC Address MSB
DRH 0
OR
MediaTek Confidential © 2014 MediaTek Inc. Page 248 of 347
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
EO
Type
Reset
US L
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name MAC_ADDR_MSB
Type RW
.tw IA
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
15:0 MAC_ADDR_MSB MAC Address bit[47:32]
om NT
0000000
10100D00 SDM_TPCNT Switch DMA Tx Packet Count
0
x.c E
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name TX_PCNT[31:16]
ne FID
Type RC
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name TX_PCNT[15:0]
Type RC
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
syn ON
Bit(s) Name Description
31:0 TX_PCNT Transmit Packet Count
@ C
0000000
10100D04 SDM_TBCNT Switch DMA TX Byte Count
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ien K
Name TX_BCNT[31:16]
Type RC
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ch TE
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name TX_BCNT[15:0]
Type RC
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
am IA
Bit(s) Name Description
31:0 TX_BCNT Transmit Byte Count
ad ED
0000000
10100D08 SDM_RPCNT Switch DMA RX Packet Count
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M
Name RX_PCNT[31:16]
Type RC
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RX_PCNT[15:0]
Type RC
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
OR
MediaTek Confidential © 2014 MediaTek Inc. Page 249 of 347
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Bit(s) Name Description
31:0 RX_PCNT Receive Packet Count
EO
US L
0000000
.tw IA
10100D0C SDM_RBCNT Switch DMA RX Byte Count
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RX_BCNT[31:16]
Type RC
om NT
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RX_BCNT[15:0]
Type RC
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
x.c E
Bit(s) Name Description
ne FID
31:0 RX_BCNT Receive Byte Count
0000000
10100D10 SDM_CS_ERR Switch DMA RX Checksum Error
0
syn ON
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name CS_ERR_CNT[31:16]
Type RC
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name CS_ERR_CNT[15:0]
@ C
Type RC
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
ien K
31:0 CS_ERR_CNT Receive Checksum Error Count
ch TE
am IA
ad ED
OR M
MediaTek Confidential © 2014 MediaTek Inc. Page 250 of 347
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Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited.
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
2.19 Switch Controller
EO
2.19.1 Registers
US L
ESW Changes LOG
.tw IA
Revision Date Author Change Log
0.1 2013/5/29 PeterCT WU Initialization
om NT
Module name: ESW Base address: (+10110000h)
Address Name Widt Register Function
h
10110000 ISR 32 Interrupt Status
x.c E
10110004 IMR 32 Interrupt Mask
10110008 FCT0 32 Flow Control Threshold 0
ne FID
1011000C FCT1 32 Flow Control Threshold 1
10110010 PFC0 32 Priority Flow Control 0
10110014 PFC1 32 Priority Flow Control 1
10110018 PFC2 32 Priority Flow Control 2
1011001C GQS0 32 Global Queue Status 0
syn ON
10110020 GQS1 32 Global Queue Status 1
10110024 ATS 32 Address Table Search
10110028 ATS0 32 Address Table Status 0
1011002C ATS1 32 Address Table Status 1
@ C
10110030 ATS2 32 Address Table Status 2
10110034 WMAD0 32 WT_MAC_AD0
10110038 WMAD1 32 WT_MAC_AD1
ien K
1011003C WMAD2 32 WT_MAC_AD2
10110040 PVIDC0 32 PVID Configuration 0
10110044 PVIDC1 32 PVID Configuration 1
ch TE
10110048 PVIDC2 32 PVID Configuration 2
1011004C PVIDC3 32 PVID Configuration 3
10110050 VLANI0 32 VLAN Identifier 0
10110054 VLANI1 32 VLAN Identifier 1
am IA
10110058 VLANI2 32 VLAN Identifier 2
1011005C VLANI3 32 VLAN Identifier 3
10110060 VLANI4 32 VLAN Identifier 4
ad ED
10110064 VLANI5 32 VLAN Identifier 5
10110068 VLANI6 32 VLAN Identifier 6
1011006C VLANI7 32 VLAN Identifier 7
10110070 VMSC0 32 VLAN Member Port Configuration 0
M
10110074 VMSC1 32 VLAN Member Port Configuration 1
10110078 VMSC2 32 VLAN Member Port Configuration 2
1011007C VMSC3 32 VLAN Member Port Configuration 3
10110080 POA 32 Port Ability Offset
10110084 FPA 32 Force Port4 - Port0 Ability
10110088 PTS 32 Port Status
1011008C SOCPC 32 SoC Port Control
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
10110090 POC0 32 Port Control 0
10110094 POC1 32 Port Control 1
EO
10110098 POC2 32 Port Control 2
US L
1011009C SGC 32 Switch Global Control
101100A0 STRT 32 Switch Reset
.tw IA
101100A4 LEDP0 32 LED Port0
101100A8 LEDP1 32 LED Port1
101100AC LEDP2 32 LED Port2
101100B0 LEDP3 32 LED Port3
om NT
101100B4 LEDP4 32 LED Port4
101100B8 WDTR 32 Watch Dog Trigger Reset
101100BC DES 32 Debug Signal
101100C0 PCR0 32 PHY Control Register 0
x.c E
101100C4 PCR1 32 PHY Control Register 1
101100C8 FPA1 32 Force P5P6 Ability
ne FID
101100CC FCT2 32 Flow Control Threshold 2
101100D0 QSS0 32 Queue Status 0
101100D4 QSS1 32 Queue Status 1
101100D8 DEC 32 Debug Control
101100DC MTI 32 Memory Test Information
syn ON
101100E0 PPC 32 Packet Counter
101100E4 SGC2 32 Switch Global Control 2
101100E8 P0PC 32 Port 0 Packet Counter
101100EC P1PC 32 Port 1 Packet Counter
@ C
101100F0 P2PC 32 Port 2 Packet Counter
101100F4 P3PC 32 Port 3 Packet Counter
101100F8 P4PC 32 Port 4 Packet Counter
ien K
101100FC P5PC 32 Port 5 Packet Counter
10110100 VUB0 32 VLAN Untag Block 0
10110104 VUB1 32 VLAN Untag Block 1
ch TE
10110108 VUB2 32 VLAN Untag Block 2
1011010C VUB3 32 VLAN Untag Block 3
10110110 BMU_CTRL 32 BC/MC/UN Rate Limit Control
am IA
10110114 BMU_LMT_NU 32 BC/MC/UN Rate Limit Frame Number
M1
BMU_LMT_NU
10110118 M2 32 BC/MC/UN Rate Limit Frame Number
ad ED
1011011C P01_ING_CTRL 32 Port 0&1 Ingress Rate Limit Control
10110120 P23_ING_CTRL 32 Port 2&3 Ingress Rate Limit Control
10110124 P45_ING_CTRL 32 Port 4&5 Ingress Rate Limit Control
P0_ING_THRE
10110128 S 32 Port 0 Ingress Rate Limit Threshold
M
1011012C P1_ING_THRE 32 Port 1 Ingress Rate Limit Threshold
S
P2_ING_THRE
10110130 S 32 Port 2 Ingress Rate Limit Threshold
10110134 P3_ING_THRE 32 Port 3 Ingress Rate Limit Threshold
S
P4_ING_THRE
10110138 S 32 Port 4 Ingress Rate Limit Threshold
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
P5_ING_THRE
1011013C S 32 Port 5 Ingress Rate Limit Threshold
EO
10110140 P01_EG_CTRL 32 Port 0/1 Egress Rate Limit Control
10110144 P23_EG_CTRL 32 Port 2/3 Egress Rate Limit Control
US L
10110148 P45_EG_CTRL 32 Port 4/5 Egress Rate Limit Control
1011014C PCRI 32 Packet Counter Recycle Indication
.tw IA
10110150 P0TPC 32 Port 0 TX Packet Counter
10110154 P1TPC 32 Port 1 TX Packet Counter
10110158 P2TPC 32 Port 2 TX Packet Counter
om NT
1011015C P3TPC 32 Port 3 TX Packet Counter
10110160 P4TPC 32 Port 4 TX Packet Counter
10110164 P5TPC 32 Port 5 TX Packet Counter
10110168 LEDC 32 LED Control
x.c E
ne FID
0000000
10110000 ISR Interrupt Status
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WA WA
TC TC
HA MU GL LA LA LA LA LA
HD HD PO
syn ON
S_I BC ST_ OB N_ N_ N_ N_ N_
OG OG RT_
NT _ST DR AL_ QU QU QU QU QU
Name REV0 1_T 0_T
RU
ST_
OR OP QU E_F E_F E_F E_F E_F
MR MR CH
DE M _LA E_F ULL ULL ULL ULL ULL
_EX _EX G
R N ULL _6 _5 _4 _3 _2
PIR PIR
ED ED
W1 W1 W1 W1 W1 W1 W1 W1 W1 W1 W1 W1
@ C
Type RO
C C C C C C C C C C C C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LA LA
ien K
N_ N_
QU QU
Name
E_F E_F
ch TE
ULL ULL
_1 _0
W1 W1
Type C C
Reset 0 0
am IA
Bit(s) Name Description
31:30 REV0 Reserved
29 WATCHDOG1_TMR P5 no transmit packet alert.
ad ED
_EXPIRED This bit indicating that P5 don't transmit packet for 3 seconds when P5 need
to transmit packet. Write one clear.
[Note] This feature is only valid when port 5 Giga MAC is implemented.
28 WATCHDOG0_TMR Abnormal Alert
_EXPIRED This bit indicating that global queue block counts is less
M
than buf_starvation_th for 3 seconds. Write one clear.
27 HAS_INTRUDER Intruder Alert
This bit indicating that an unsecured packet is coming into a secured port.
Write one clear.
26 PORT_ST_CHG Port status change
Any port from link status change. Write one clear.
25 BC_STORM BC storm
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Bit(s) Name Description
The device is undergoing broadcast storm. Write one clear.
EO
24 MUST_DROP_LAN Queue exhausted
US L
The global queue is used up and all packets are dropped. Write one clear.
23 GLOBAL_QUE_FUL Global Queue Full.
L
.tw IA
Write one clear.
20 LAN_QUE_FULL_6 Port 6 out queue full. Write one clear.
[Note]: This feature is only valid when port 5 Giga MAC is implemented.
19 LAN_QUE_FULL_5 Port 5 out queue full. Write one clear.
om NT
18 LAN_QUE_FULL_4 Port 4 out queue full. Write one clear.
17 LAN_QUE_FULL_3 Port 3 out queue full. Write one clear.
16 LAN_QUE_FULL_2 Port 2 out queue full. Write one clear.
15 LAN_QUE_FULL_1 Port 1 out queue full. Write one clear.
x.c E
14 LAN_QUE_FULL_0 Port 0 out queue full. Write one clear.
10110004
Bit 31
ne FID
IMR
30 29 28
Interrupt Mask
27 26 25 24 23 22 21 20 19 18
FFFFFF
17
FF
16
WA WA
syn ON
TC TC
HA MU GL LA LA LA LA LA
HD HD PO
S_I BC ST_ OB N_ N_ N_ N_ N_
OG OG RT_
NT _ST DR AL_ QU QU QU QU QU
Name 1_T 0_T
RU
ST_
OR OP QU
REV1
E_F E_F E_F E_F E_F
MR MR CH
DE M _LA E_F ULL ULL ULL ULL ULL
_EX _EX G
R N ULL _6 _5 _4 _3 _2
PIR PIR
@ C
ED ED
Type RW RW RW RW RW RW RW RW RW RW RW RW RW
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ien K
LA LA
N_ N_
QU QU
Name
ch TE
E_F E_F
ULL ULL
_1 _0
Type RW RW
Reset 1 1
am IA
Bit(s) Name Description
29 WATCHDOG1_TMR P5 no transmit packet alert.
_EXPIRED This bit indicating that P5 don't transmit packet for 3 seconds when P5 need
ad ED
to transmit packet. Write one clear.
[Note]: This feature is only valid when port 5 Giga MAC is implemented.
28 WATCHDOG0_TMR Abnormal Alert
_EXPIRED This bit indicating that global queue block counts is less
than buf_starvation_th for 3 seconds. Write one clear.
M
27 HAS_INTRUDER Intruder Alert
This bit indicating that an unsecured packet is coming into a secured port.
Write one clear.
26 PORT_ST_CHG Port status change
Any port from link status change. Write one clear.
25 BC_STORM BC storm
The device is undergoing broadcast storm. Write one clear.
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Bit(s) Name Description
24 MUST_DROP_LAN Queue exhausted
EO
The global queue is used up and all packets are dropped. Write one clear.
US L
23 GLOBAL_QUE_FUL Global Queue Full.
L Write one clear.
.tw IA
22:21 REV1 Port 6 out queue full. Write one clear.
[Note]: This feature is only valid when port 5 Giga MAC is implemented.
20 LAN_QUE_FULL_6 Port 6 out queue full. Write one clear.
[Note]: This feature is only valid when port 5 Giga MAC is implemented.
om NT
19 LAN_QUE_FULL_5 Port 5 out queue full. Write one clear.
18 LAN_QUE_FULL_4 Port 4 out queue full. Write one clear.
17 LAN_QUE_FULL_3 Port 3 out queue full. Write one clear.
16 LAN_QUE_FULL_2 Port 2 out queue full. Write one clear.
x.c E
15 LAN_QUE_FULL_1 Port 1 out queue full. Write one clear.
14 LAN_QUE_FULL_0 Port 0 out queue full. Write one clear.
10110008
ne FID
FCT0 Flow Control Threshold 0
FFC86E
5A
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
syn ON
Name FC_RLS_TH FC_SET_TH
Type RW RW
Reset 1 1 1 1 1 1 1 1 1 1 0 0 1 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DRO_RLS_TH DROP_SET_TH
Type RW RW
@ C
Reset 0 1 1 0 1 1 1 0 0 1 0 1 1 0 1 0
Bit(s) Name Description
ien K
31:24 FC_RLS_TH Flow Control Release Threshold
Flow control will be disabled when the global queue block counts is greater
than the release threshold
ch TE
23:16 FC_SET_TH Flow Control Set Threshold
Flow control will be enabled when the global queue block counts is less than
the set threshold
15:8 DRO_RLS_TH Drop Release Threshold
am IA
Switch will stop dropping packets when the global queue block counts is
greater than the drop-release threshold
7:0 DROP_SET_TH Drop Set Threshold
Switch will start dropping packets when the global queue block counts is less
ad ED
than the drop-set threshold.
0000001
M
1011000C FCT1 Flow Control Threshold 1
4
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name PORT_TH
Type RW
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Reset 0 0 0 1 0 1 0 0
EO
Bit(s) Name Description
7:0 PORT_TH Per Port Output Threshold
US L
When the global queue reaches the flow control or drop threshold on register
FCT0, per port output threshold will be checked to enable flow-control or
.tw IA
packet-dop depending on per queue minimum reserved blocks of the register
PFC2.
om NT
0F00000
10110010 PFC0 Priority Flow Control 0
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name MTCC_LMT TURN_OFF_FC
x.c E
Type RW RW
Reset 1 1 1 1 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ne FID
Name VO_NUM CL_NUM BE_NUM BK_NUM
Type RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
27:24 MTCC_LMT MTCC LIMIT
syn ON
The maximum Back-off count limit to drop excessive collision packets.
22:16 TURN_OFF_FC Turn off FC When Receiving High Packet
Auto-turn-off FC when the programmed ports receive one of the highest
priority packet.
0: DIsable
@ C
1: Enable
15:12 VO_NUM The proportional number of WRR for Voice Queue
After transmit exactly the number of packets then proceed to next queue. If
ien K
equal to 0, only this queue is forced to the strict priority mode
11:8 CL_NUM The proportional number of WRR for Control-Load Queue
After transmit exactly the number of packet then proceed to next queue.
ch TE
7:4 BE_NUM The proportional number of WRR for Best-Effort Queue
After transmit exactly the number of packet then proceed to next queue.
3:0 BK_NUM The proportional number of WRR for Background Queue After transmit
exactly the number of packet then proceed to next queue.
am IA
0000155
10110014 PFC1 Priority Flow Control 1
ad ED
5
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CP
IGM
U_
P_T
US
Name EN_TOS O_ EN_VLAN
M
E_
CP
Q1_
U
EN
Type RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI
ORI PORT_PRI PORT_PRI PORT_PRI PORT_PRI PORT_PRI PORT_PRI PORT_PRI
Name
TY_ 6 5 4 3 2 1 0
OP
OR
MediaTek Confidential © 2014 MediaTek Inc. Page 256 of 347
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Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited.
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
TIO
N
EO
Type RW RW RW RW RW RW RW RW
Reset 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1
US L
Bit(s) Name Description
.tw IA
31 CPU_USE_Q1_EN CPU Port only use q1 enable
0: default priority resolution
1: packets forwarded to CPU port uses Best-Effor Queue
30:24 EN_TOS Port6 ~ port0 TOS_en.
om NT
Check TOS field of IP packets for priority resolution.
[Note] Port 5 function is only vlaid when port 5 Giga MAC is implemented
0: Disable
1: Enable
23 IGMP_TO_CPU IGMP forward to CPU enable
x.c E
0: IGMP message will be floode to all ports
1: IGMP message will be forwarded to CPU port only.
ne FID
22:16 EN_VLAN Enable per port VLAN-tag VID membership and priority tag check.
[Note] Port 5 function is only vlaid when port 5 Giga MAC is implemented
0: disable.
1: enable
15 PRIORITY_OPTION Priority Resolution Option
0: 802.1p -> TOS -> Per port
syn ON
1: TOS -> 802.1p -> Per port
13:12 PORT_PRI6 Port priority
By setting this register to assign per port's default priority queue.
11:10 PORT_PRI5 Port priority
By setting this register to assign per port's default priority queue.
@ C
[Note] This feature is only valid when port 6 Giga MAC is implemented
9:8 PORT_PRI4 Port priority
By setting this register to assign per port's default priority queue.
ien K
7:6 PORT_PRI3 Port priority
By setting this register to assign per port's default priority queue.
5:4 PORT_PRI2 Port priority
ch TE
By setting this register to assign per port's default priority queue.
3:2 PORT_PRI1 Port priority
By setting this register to assign per port's default priority queue.
1:0 PORT_PRI0 Port priority
am IA
By setting this register to assign per port's default priority queue.
ad ED
0303030
10110018 PFC2 Priority Flow Control 2
3
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name PRI_TH_VO PRI_TH_CL
Type RW RW
M
Reset 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name PRI_TH_BE PRI_TH_BK
Type RW RW
Reset 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1
Bit(s) Name Description
31:24 PRI_TH_VO Voice Threshold (Highest Priority)
OR
MediaTek Confidential © 2014 MediaTek Inc. Page 257 of 347
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Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited.
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Bit(s) Name Description
The minimum reserved packet block count which outout queue can store
EO
when the flow-control /drop threshold of registers FTC0 and FCT1 is reached.
If the queued blocks exceed the threshold, the incoming packet will be
US L
paused or dropped.
23:16 PRI_TH_CL Control Load Threshold
.tw IA
The minimum reserved packet block count which outout queue can store
when the flow-control/drop threshold of registers FTC0 and FCT1 is reached.
If the queued blocks exceed the threshold, the incoming packet will be
paused or dropped.
om NT
15:8 PRI_TH_BE Best Effort threshold
The minimum reserved packet block count which outout queue can store
when the flow-control/drop threshold of registers FTC0 and FCT1 is reached.
If the queued blocks exceed the threshold, the incoming packet will be
paused or dropped.
x.c E
7:0 PRI_TH_BK Background Threshold (Lowest Priority)
The minimum reserved packet block count which outout queue can store
when the flow-control/drop threshold of registers FTC0 and FCT1 is reached.
ne FID
If the queued blocks exceed the threshold, the incoming packet will be
paused or dropped.
FA41016
syn ON
1011001C GQS0 Global Queue Status 0
E
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name PRI7_QUE PRI6_QUE PRI5_QUE PRI4_QUE PRI3_QUE PRI2_QUE PRI1_QUE PRI0_QUE
Type RW RW RW RW RW RW RW RW
Reset 1 1 1 1 1 0 1 0 0 1 0 0 0 0 0 1
@ C
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name EMPTY_CNT
Type RO
Reset 1 0 1 1 0 1 1 1 0
ien K
Bit(s) Name Description
31:30 PRI7_QUE Queue mapping for Priority Tag #7
ch TE
29:28 PRI6_QUE Queue mapping for Priority Tag #6
27:26 PRI5_QUE Queue mapping for Priority Tag #5
25:24 PRI4_QUE Queue mapping for Priority Tag #4
am IA
23:22 PRI3_QUE Queue mapping for Priority Tag #3
21:20 PRI2_QUE Queue mapping for Priority Tag #2
19:18 PRI1_QUE Queue mapping for Priority Tag #1
17:16 PRI0_QUE Queue mapping for Priority Tag #0
ad ED
8:0 EMPTY_CNT Global Queue Block Counts
This field indicates the number of block count left in the global free queue.
M
0000000
10110020 GQS1 Global Queue Status 1
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name OUTQUE_FULL_VO OUTQUE_FULL_CL
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OR
MediaTek Confidential © 2014 MediaTek Inc. Page 258 of 347
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Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited.
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Name OUTQUE_FULL_BE OUTQUE_FULL_BK
Type RO RO
EO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
US L
Bit(s) Name Description
31:24 OUTQUE_FULL_VO Congested Voice Queue
.tw IA
The corresponding queue is congested
23:16 OUTQUE_FULL_CL Congested Control Load Queue
The corresponding queue is congested
om NT
15:8 OUTQUE_FULL_BE Congested Best Effort Queue
The corresponding queue is congested
7:0 OUTQUE_FULL_BK Congested Background Queue
The corresponding queue is congested
x.c E
0000000
ne FID
10110024 ATS Address Table Search
4
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
syn ON
BE
SE
GIN
AT_ AR
_SE
LK CH
AR
Name UP_ _NX
CH
IDL T_A
_A
E DD
@ C
DD
R
R
W1 W1
Type RO
C C
Reset 1 0 0
ien K
Bit(s) Name Description
ch TE
2 AT_LKUP_IDLE Address Lookup Idle
This field indicates that Adress Table engine is in IDLE state.
1 SEARCH_NXT_AD Search For The Next Address (Self_Clear)
DR
am IA
0 BEGIN_SEARCH_A Start Searching The Address Table (Self_Clear)
DDR
ad ED
0000000
10110028 ATS0 Address Table Status 0
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R_PORT_MAP[6:4
Name HASH_ADD_LU
M
]
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R_
AT_ SE
MC
TA AR
_IN
Name R_PORT_MAP[3:0] R_VLD R_AGE_FIELD
GR
BL CH
E_E _R
ES
ND DY
S
OR
MediaTek Confidential © 2014 MediaTek Inc. Page 259 of 347
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Type RO RO RO RO RO RC
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0
EO
Bit(s) Name Description
US L
31:22 HASH_ADD_LU Address table lookup address
18:12 R_PORT_MAP Port map
.tw IA
The MAC existing in the bit =1.
10:7 R_VLD VLAN index
6:4 R_AGE_FIELD Aging field
om NT
2 R_MC_INGRESS MC Ingress
1 AT_TABLE_END Search to the end of address table
0 SEARCH_RDY Data is ready (read clear)
x.c E
0000000
ne FID
1011002C ATS1 Address Table Status 1
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
syn ON
Name MAC_AD_SER0
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
@ C
15:0 MAC_AD_SER0 Read MAC Address [15:0]
ien K
0000000
10110030 ATS2 Address Table Status 2
0
ch TE
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name MAC_AD_SER0[31:16]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name MAC_AD_SER0[15:0]
am IA
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
ad ED
31:0 MAC_AD_SER0 Read MAC Address [31:16]
M
0008000
10110034 WMAD0 WT_MAC_AD0
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AT_
CF
W_PORT_MAP[6:
Name HASH_ADD_LU G_I
4]
DL
E
Type RO RO RW
OR
MediaTek Confidential © 2014 MediaTek Inc. Page 260 of 347
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Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited.
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Reset 0 0 0 0 0 0 0 0 0 0 1 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EO
W_
W_ W_
SA_ MC
MA MA
US L
FIL _IN
Name W_PORT_MAP[3:0] W_INDEX W_AGE_FIELD
TE GR
C_ C_
DO CM
R ES
NE D
.tw IA
S
Type RW RW RW RW RW RO WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
om NT
31:22 HASH_ADD_LU Address table configuration address
19 AT_CFG_IDLE Address Table Configuration SM IDLE
18:12 W_PORT_MAP Write Port map
10:7 W_INDEX VLAN index
x.c E
0: VLAN 0
1-14: ...
ne FID
15: VLAN 15
6:4 W_AGE_FIELD Write Aging field
3'b111: static address,
3'b001 - 3'b110: the entry is valid and will be aged out
2'b000: default, entry is invalid
3 SA_FILTER SA_FILTER
syn ON
0: default
1: The corresponding packet will be dropped when the SA is matched
2 W_MC_INGRESS Write MC Ingress
1 W_MAC_DONE MAC Write Done
0: default
@ C
1: MAC address write OK (read clear)
0 W_MAC_CMD MAC Address write Command
0: default
ien K
1: the MAC write data is ready and write to MAC table now(self_clear)
ch TE
0000000
10110038 WMAD1 WT_MAC_AD1
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
am IA
Name
Type
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name W_MAC_15_0
ad ED
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
15:0 W_MAC_15_0 Write MAC Address[15:0]
M
0000000
1011003C WMAD2 WT_MAC_AD2
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name W_MAC_47_16[31:16]
Type RW
OR
MediaTek Confidential © 2014 MediaTek Inc. Page 261 of 347
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EO
Name W_MAC_47_16[15:0]
Type RW
US L
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
.tw IA
31:0 W_MAC_47_16 Write MAC Address[47:16]
om NT
0000100
10110040 PVIDC0 PVID Configuration 0
1
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name P1_PVID[11:4]
x.c E
Type RW
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ne FID
Name P1_PVID[3:0] P0_PVID
Type RW RW
Reset 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1
Bit(s) Name Description
23:12 P1_PVID Port1 PVID Setting
syn ON
11:0 P0_PVID Port0 PVID Setting
0000100
10110044 PVIDC1 PVID Configuration 1
@ C
1
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name P3_PVID[11:4]
ien K
Type RW
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ch TE
Name P3_PVID[3:0] P2_PVID
Type RW RW
Reset 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1
Bit(s) Name Description
am IA
23:12 P3_PVID Port3 PVID Setting
11:0 P2_PVID Port2 PVID Setting
ad ED
0000100
10110048 PVIDC2 PVID Configuration 2
1
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
M
P5_PVID[11:4]
Type RW
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name P5_PVID[3:0] P4_PVID
Type RW RW
Reset 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1
Bit(s) Name Description
OR
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Bit(s) Name Description
23:12 P5_PVID Port5 PVID Setting
EO
[Note] This feature is only valid when port 5 Giga MAC is implemented.
US L
11:0 P4_PVID Port4 PVID Setting
.tw IA
7502000
1011004C PVIDC3 PVID Configuration 3
1
om NT
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name QUE3_PRIT QUE2_PRIT QUE1_PRIT QUE0_PRIT
Type RW RW RW RW
Reset 1 1 1 1 0 1 0 0 0 0 1 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name P6_PVID
x.c E
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 1
ne FID
Bit(s) Name Description
30:28 QUE3_PRIT Priority Tag Egress Mapping for Voice Queue#3
26:24 QUE2_PRIT Priority Tag Egress Mapping for Control Load Queue#2
22:20 QUE1_PRIT Priority Tag Egress Mapping for Best Effort Queue#1
syn ON
18:16 QUE0_PRIT Priority Tag Egress Mapping for Back Ground Queue#0
11:0 P6_PVID Port6 PVID Setting
0000200
@ C
10110050 VLANI0 VLAN Identifier 0
1
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name VID1[11:4]
ien K
Type RW
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ch TE
Name VID1[3:0] VID0
Type RW RW
Reset 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1
Bit(s) Name Description
am IA
23:12 VID1 VLAN Field Identifier for VLAN 1
11:0 VID0 VLAN Field Identifier for VLAN 0
ad ED
0000400
10110054 VLANI1 VLAN Identifier 1
3
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M
Name VID3[11:4]
Type RW
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name VID3[3:0] VID2
Type RW RW
Reset 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1
OR
MediaTek Confidential © 2014 MediaTek Inc. Page 263 of 347
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Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited.
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Bit(s) Name Description
23:12 VID3 VLAN Field Identifier for VLAN 3
EO
11:0 VID2 VLAN Field Identifier for VLAN 2
US L
.tw IA
0000600
10110058 VLANI2 VLAN Identifier 2
5
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
om NT
Name VID5[11:4]
Type RW
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name VID5[3:0] VID4
Type RW RW
x.c E
Reset 0 1 1 0 0 0 0 0 0 0 0 0 0 1 0 1
ne FID
Bit(s) Name Description
23:12 VID5 VLAN Field Identifier for VLAN 5
11:0 VID4 VLAN Field Identifier for VLAN 4
syn ON
0000800
1011005C VLANI3 VLAN Identifier 3
7
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name VID7[11:4]
Type RW
@ C
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name VID7[3:0] VID6
Type RW RW
ien K
Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1
Bit(s) Name Description
ch TE
23:12 VID7 VLAN Field Identifier for VLAN 7
11:0 VID6 VLAN Field Identifier for VLAN 6
am IA
0000A00
10110060 VLANI4 VLAN Identifier 4
9
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ad ED
Name VID9[11:4]
Type RW
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name VID9[3:0] VID8
M
Type RW RW
Reset 1 0 1 0 0 0 0 0 0 0 0 0 1 0 0 1
Bit(s) Name Description
23:12 VID9 VLAN Field Identifier for VLAN 9
11:0 VID8 VLAN Field Identifier for VLAN 8
OR
MediaTek Confidential © 2014 MediaTek Inc. Page 264 of 347
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Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited.
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
EO
0000C00
10110064 VLANI5 VLAN Identifier 5
B
US L
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name VID11[11:4]
Type
.tw IA
RW
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name VID11[3:0] VID10
Type RW RW
om NT
Reset 1 1 0 0 0 0 0 0 0 0 0 0 1 0 1 1
Bit(s) Name Description
23:12 VID11 VLAN Field Identifier for VLAN 11
x.c E
11:0 VID10 VLAN Field Identifier for VLAN 10
10110068
Bit
Name
31
ne FID
VLANI6
30 29 28
VLAN Identifier 6
27 26 25 24 23 22 21 20
VID13[11:4]
19 18
0000E00
17
D
16
Type RW
syn ON
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name VID13[3:0] VID12
Type RW RW
Reset 1 1 1 0 0 0 0 0 0 0 0 0 1 1 0 1
@ C
Bit(s) Name Description
23:12 VID13 VLAN Field Identifier for VLAN 13
ien K
11:0 VID12 VLAN Field Identifier for VLAN 12
ch TE
0001000
1011006C VLANI7 VLAN Identifier 7
F
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name VID15[11:4]
am IA
Type RW
Reset 0 0 0 0 0 0 0 1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name VID15[3:0] VID14
ad ED
Type RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1
Bit(s) Name Description
23:12 VID15 VLAN Field Identifier for VLAN 15
M
11:0 VID14 VLAN Field Identifier for VLAN 14
FFFFFF
10110070 VMSC0 VLAN Member Port Configuration 0
FF
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name VLAN_MEMSET_3 VLAN_MEMSET_2
OR
MediaTek Confidential © 2014 MediaTek Inc. Page 265 of 347
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Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited.
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Type RW RW
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
EO
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name VLAN_MEMSET_1 VLAN_MEMSET_0
US L
Type RW RW
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
.tw IA
Bit(s) Name Description
31:24 VLAN_MEMSET_3 VLAN 3 Member Port
23:16 VLAN_MEMSET_2 VLAN 2 Member Port
om NT
15:8 VLAN_MEMSET_1 VLAN 1 Member Port
7:0 VLAN_MEMSET_0 VLAN 0 Member Port
x.c E
FFFFFF
10110074 VMSC1 VLAN Member Port Configuration 1
FF
ne FID
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name VLAN_MEMSET_7 VLAN_MEMSET_6
Type RW RW
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name VLAN_MEMSET_5 VLAN_MEMSET_4
Type RW RW
syn ON
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit(s) Name Description
31:24 VLAN_MEMSET_7 VLAN 7 Member Port
@ C
23:16 VLAN_MEMSET_6 VLAN 6 Member Port
15:8 VLAN_MEMSET_5 VLAN 5 Member Port
7:0 VLAN_MEMSET_4 VLAN 4 Member Port
ien K
ch TE
FFFFFF
10110078 VMSC2 VLAN Member Port Configuration 2
FF
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name VLAN_MEMSET_11 VLAN_MEMSET_10
Type RW RW
am IA
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name VLAN_MEMSET_9 VLAN_MEMSET_8
Type RW RW
ad ED
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit(s) Name Description
31:24 VLAN_MEMSET_11 VLAN 11 Member Port
23:16 VLAN_MEMSET_10 VLAN 10 Member Port
M
15:8 VLAN_MEMSET_9 VLAN 9 Member Port
7:0 VLAN_MEMSET_8 VLAN 8 Member Port
FFFFFF
1011007C VMSC3 VLAN Member Port Configuration 3
FF
OR
MediaTek Confidential © 2014 MediaTek Inc. Page 266 of 347
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Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited.
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name VLAN_MEMSET_15 VLAN_MEMSET_14
EO
Type RW RW
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
US L
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name VLAN_MEMSET_13 VLAN_MEMSET_12
Type RW RW
.tw IA
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit(s) Name Description
31:24 VLAN_MEMSET_15 VLAN 15 Member Port
om NT
23:16 VLAN_MEMSET_14 VLAN 14 Member Port
15:8 VLAN_MEMSET_13 VLAN 13 Member Port
7:0 VLAN_MEMSET_12 VLAN 12 Member Port
x.c E
ne FID
0000000
10110080 POA Port Ability Offset
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
G1_ G0_
Name LIN LIN LINK G1_TXC G0_TXC XFC
K K
Type RO RO RO RO RO RO
syn ON
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DUPLEX G1_SPD G0_SPD SPEED
Type RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
@ C
Bit(s) Name Description
31 G1_LINK Port 6 Link Status
1: Link up
ien K
0: Link down
30 G0_LINK Port 5 Link Status
ch TE
[Note] This feature is only valid when port 5 giga MAC is implemented.
1: Link up
0: Link down
29:25 LINK Port 4 ~ port0 Link Status
1: Link up
am IA
0: Link down
24:23 G1_TXC Flow Control Status fo Port6
The flow control capability status bit after Auto-negotiation or force mode.
1xb: full duplex and tx flow control ON
ad ED
x1b: full duplex and rx flow control ON
00b: flow control off
22:21 G0_TXC Flow Control Status fo Port5
The flow control capability status bit after Auto-negotiation or force mode.
[Note] This feature is only valid when port 5 giga MAC is implemented.
M
1xb: full duplex and tx flow control ON
x1b: full duplex and rx flow control ON
00b: flow control off
20:16 XFC Flow Control Status of port 0 ~ 4
The flow control capability status bit after Auto-negotiation or force mode.
0: flow control off
1: full duplex and 802.3x flow control ON (after AN or forced)
15:9 DUPLEX Port6 ~ port0 Duplex Mode
OR
MediaTek Confidential © 2014 MediaTek Inc. Page 267 of 347
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Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited.
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MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Bit(s) Name Description
[Note]: Port5 funciton is only valid when port 5 Giga MAC is implemented.
EO
0: half duplex
1: full duplex
US L
8:7 G1_SPD MII port 6 Speed:Mode
10: 1000M
.tw IA
01: 100M
00: 10M
6:5 G0_SPD MII port 5 Speed:Mode
[Note] This feature is only valid when port 5 Giga MAC is implemented
om NT
10: 1000M
01: 100M
00: 10M
4:0 SPEED Port4 ~ port0 Speed Mode
0: 10M
x.c E
1: 100M
10110084
Bit
Name
31
ne FID
FPA
30 29
FORCE_MODE
28
Force Port4 - Port0 Ability
27 26 25 24
FORCE_LINK
23 22 21 20 19 18
FORCE_XFC
0000000
17
0
16
syn ON
Type RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XT
AL_
Name FORCE_DPX FORCE_SPD
CO
MP
@ C
Type RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0
ien K
Bit(s) Name Description
31:27 FORCE_MODE Port4 ~ port 0 force mode
0: default
ch TE
1: force mode. Auto-negotiation status is ignored. All the port ability are
forced according to the following fields of the register FPA.
26:22 FORCE_LINK Port 4 ~ port 0 PHY Link
This field is valid only FORCE_MDOE is set. The final resolution is reported
am IA
to POA register.
1: Link up
0: Link down
20:16 FORCE_XFC Port 4 ~ port 0 Flow control of PHY port
ad ED
This field is valid only FORCE_MDOE is set. The final resolution is reported
to POA register.
0: default OFF
1: 802.3x flow control ON
12:8 FORCE_DPX Flow Control Status of port 0 ~ 4
M
The flow control capability status bit after Auto-negotiation or force mode.
0: flow control off
1: full duplex and 802.3x flow control ON (after AN or forced)
5 XTAL_COMP Crystal rate compensation
0: Disable
1: When the switch has transmitted 20000 bytes, the switch will compensate
for the loss of crystal rate.
4:0 FORCE_SPD Port4 ~ port0 Speed:
OR
MediaTek Confidential © 2014 MediaTek Inc. Page 268 of 347
This document contains information that is proprietary to MediaTek Inc.
Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited.
[email protected],time=2014-12-05 11:55:47,ip=58.250.71.129,doctitle=MT7628_ProgrammingGuide_20140428(E2).docx,company=Synnex Electronics HK Limited 聯強電子_RLT
MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Bit(s) Name Description
This field is valid only FORCE_MDOE is set. The final resolution is reported
EO
to POA register.
1: 100M
US L
0: 10M
.tw IA
0000000
10110088 PTS Port Status
0
om NT
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
x.c E
G1_ G0_
TX TX
Name C_S C_S SECURED_ST
ne FID
TAT TAT
US US
Type RO RO RO
Reset 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
9 G1_TXC_STATUS Port 6 TXC status
syn ON
0: no alert
1: error, no TXC
8 G0_TXC_STATUS Port 5 TXC status
[Note] This feature is only valid when port 5 Giga MAC is implemented.
0: no alert
@ C
1: error, no TXC
6:0 SECURED_ST Security Status
0: no alert
ien K
1: has intruder coming if turn on the SA_secured mode, read clear
ch TE
027F7F7
1011008C SOCPC SoC Port Control
F
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CR
am IA
C_P
CPU_SELE
Name AD DISBC2CPU
CTION
DIN
G
Type
ad ED
RW RW RW
Reset 1 0 0 1 1 1 1 1 1 1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DISMC2CPU DISUN2CPU
Type RW RW
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1
M
Bit(s) Name Description
25 CRC_PADDING CRC padding from CPU
If this bit is set , all packets from CPU don't need to append CRC and the
outgoing LAN/WAN port will calculate and append CRC.
0: packets from CPU need CRC appending
1: packets from CPU without CRC appending
OR
MediaTek Confidential © 2014 MediaTek Inc. Page 269 of 347
This document contains information that is proprietary to MediaTek Inc.
Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited.
[email protected],time=2014-12-05 11:55:47,ip=58.250.71.129,doctitle=MT7628_ProgrammingGuide_20140428(E2).docx,company=Synnex Electronics HK Limited 聯強電子_RLT
MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Bit(s) Name Description
24:23 CPU_SELECTION CPU Selection
EO
00b: Port 6
01b: Port 0
US L
10b: Port 4
11b: Port 5
.tw IA
22:16 DISBC2CPU Disable BC to CPU
When this bit = 1, BC frames from the corresponding port will not be forward
to CPU.
[Note] Port5 funciton is only valid when port 5 Giga MAC is implemented.
om NT
0: Includes CPU port.
1: Excludes CPU port
14:8 DISMC2CPU Disable MC to CPU
When this bit =1, MC frames from the corresponding port will not forward to
CPU.
x.c E
[Note] Port5 funciton is only valid when port 5 Giga MAC is implemented.
0: Includes CPU port.
1: Excludes CPU port
ne FID
6:0 DISUN2CPU Disable UN to CPU
When this bit =1, Unkonwn frames from the corresponding port will not
forward to CPU.
[Note] Port5 funciton is only valid when port 5 Giga MAC is implemented.
0: Includes CPU port.
1: Excludes CPU port
syn ON
3F807F7
10110090 POC0 Port Control 0
F
@ C
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DIS DIS
_G _G
HASH_AD MII_ MII_
Name DIS_PORT DISRMC2_CPU
ien K
DR_SHIFT PO PO
RT_ RT_
1 0
Type RW RW RW RW RW
ch TE
Reset 0 0 1 1 1 1 1 1 1 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
C_F
CP_
Name EN_FC EN_BP
am IA
OP
TIO
N
Type RW RW RW
Reset 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1
ad ED
Bit(s) Name Description
31:30 HASH_ADDR_SHIF Address table hashing algorithm option for member set index
T
M
29 DIS_GMII_PORT_1 Disable port 6
0: port enable
1: port disable
28 DIS_GMII_PORT_0 Disable port 5
[Note] This feature is only valid when port 5 Giga MAC is implemented.
0: port enable
1: port disable
27:23 DIS_PORT Disable phy port
OR
MediaTek Confidential © 2014 MediaTek Inc. Page 270 of 347
This document contains information that is proprietary to MediaTek Inc.
Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited.
[email protected],time=2014-12-05 11:55:47,ip=58.250.71.129,doctitle=MT7628_ProgrammingGuide_20140428(E2).docx,company=Synnex Electronics HK Limited 聯強電子_RLT
MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Bit(s) Name Description
0: port enable
EO
1: port disable
22:16 DISRMC2_CPU Unknown Reserved Multicast Frame Excludes CPU
US L
[Note] Port5 funciton is only valid when port 5 Giga MAC is implemented.
0: Unknown Reserved Multicast Forward Rule (SGC.RMC_RULE)
.tw IA
1: Excludes CPU port
14:8 EN_FC Apply 802.3x status after Auto-negotiation
This field can individually control the 802.3x capability after Auto-negotiation
is done.
om NT
[Note] Port5 funciton is only valid when port 5 Giga MAC is implemented.
0: ignore the AN stats for 802.3x capability
1: follow the AN status for 802.3x capability
7 MAC_FCP_OPTION Multicast Flow control/Backpressure option
0: When all ports are fc/bp disable, the switch will use drop_threshold to drop
x.c E
frames only. If not, the switch will use fc_threshold and drop_threshold.
1: When only the destination TX port is fc/bp disable, the switch will use
drop_threshold to drop frames only . If not, that TX port uses fc_threshold and
ne FID
drop_threshold.
6:0 EN_BP Apply back pressure capability
[Note] Port5 funciton is only valid when port 5 Giga MAC is implemented.
0: ignore the back pressure mode (default OFF)
1: apply back pressure based on SGC.BP_MODE.
syn ON
0000000
10110094 POC1 Port Control 1
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
@ C
Name DISIPMC2CPU BLOCKING_STATE
Type RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ien K
Name DIS_LRNING SA_SECURED_PORT
Type RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ch TE
Bit(s) Name Description
29:23 DISIPMC2CPU Unknown IP Multicast Frame Excludes CPU
0: Unknown IP Multicast Forward Rule (SGC.IP_MULT_RULE)
am IA
1: Excludes CPU port
22:16 BLOCKING_STATE Port State for Spanning Tree Protocol
[Note]: Port5 funciton is only valid when port 5 Giga MAC is implemented.
0: normal state
ad ED
1: blocking state, forwarding rmc packet to cpu(need programming
address table
14:8 DIS_LRNING Disable SA learning
[Note] Port5 funciton is only valid when port 5 Giga MAC is implemented.
0: default enabled
M
1: disable Source MAC learning
6:0 SA_SECURED_PO SA secured mode
RT [Note*1]: Must set dis_learn and sa_secured at the same time.
[Note*2] Port5 funciton is only valid when port 5 Giga MAC is implemented.
0: don't care SA match,
1: the packets' SA needs match, otherwise discard the packets
OR
MediaTek Confidential © 2014 MediaTek Inc. Page 271 of 347
This document contains information that is proprietary to MediaTek Inc.
Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited.
[email protected],time=2014-12-05 11:55:47,ip=58.250.71.129,doctitle=MT7628_ProgrammingGuide_20140428(E2).docx,company=Synnex Electronics HK Limited 聯強電子_RLT
MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
00007F0
10110098 POC2 Port Control 2
EO
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
US L
G1_ G0_
ML
TX TX
D2
C_ C_ IPV6_MUL
.tw IA
Name CH CH
CP
T_RULE
DIS_UC_PAUSE
U_E
EC EC
N
K K
Type RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0
om NT
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PE
R_V
LA
N_
Name UN
ENAGING_PORT UNTAG_EN
x.c E
TA
G_
EN
ne FID
Type RW RW RW
Reset 0 1 1 1 1 1 1 1 0 0 0 0 0 0 0
Bit(s) Name Description
30 G1_TXC_CHECK Check the port 6 TXC
syn ON
if no txc clock, then disable MII port
0: disable
1: enable, check TXC
29 G0_TXC_CHECK Check the port 5 TXC
if no txc clock, then disable MII port
[Note] This feature is only valid when port 5 Giga MAC is implemented.
@ C
0: disable
1: enable, check TXC
25 MLD2CPU_EN MLD Message Packets forward to CPU
ien K
0: MLD message will be flooded
1: MLD message will be forward to CPU port only
24:23 IPV6_MULT_RULE Unknown IPV6 Multicast Frame Forward Rule
ch TE
If no match in the address table, then folloing the rule
00: BC
01: to CPU
10: drop
11: Reserved
am IA
22:16 DIS_UC_PAUSE Disable Unicast Pause Frame
[Note] Port5 funciton is only valid when port 5 Giga MAC is implemented.
0: switch will consider pause frame when DA!=0180c20001 but unicast to
CPU,
ad ED
1: switch will not consider pause frame when DA!= 0180c20001 and unicast
to CPU
15 PER_VLAN_UNTAG Per port per vlan untag enable
_EN VLAN tag removal option.
0: Use per port UNTAG_EN
M
1: Use untag enable bitmap in VLAN table
14:8 ENAGING_PORT Port aging
[Note] Port5 funciton is only valid when port 5 Giga MAC is implemented.
0: disable aging that the MAC address is belong to programmed port(s)
1: enable aging
6:0 UNTAG_EN Per Port VLAN Tag Temoval
[Note] Port5 funciton is only valid when port 5 Giga MAC is implemented.
0: disable
OR
MediaTek Confidential © 2014 MediaTek Inc. Page 272 of 347
This document contains information that is proprietary to MediaTek Inc.
Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited.
[email protected],time=2014-12-05 11:55:47,ip=58.250.71.129,doctitle=MT7628_ProgrammingGuide_20140428(E2).docx,company=Synnex Electronics HK Limited 聯強電子_RLT
MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Bit(s) Name Description
1: enable VLAN tag field removal.
EO
US L
6008A04
1011009C SGC Switch Global Control
.tw IA
1
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LE
BK
N_E BIS
OF IP_MULT_ RMC_RUL LED_FLAS DISMIIPOR
om NT
Name F_A
RR
RULE E H_TIME
BISH_TH H_ BP_MODE
T_WASTX
_C DIS
LG
HK
Type RW RW RW RW RW RW RW RW RW
Reset 1 1 0 0 0 0 0 0 0 0 0 1 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
x.c E
DIS
AB DIS
LE_ _PK
ne FID
ADDRESS
TX_ T_T PKT_MAX BC_STOR
Name BP_JAM_CNT S_HASH_ AGING_INTERNAL
BA X_A _LEN M_PROT
ALG
CK BO
OF RT
F
Type RW RW RW RW RW RW RW
Reset 1 0 1 0 0 0 0 0 0 1 0 0 0 0 0 1
syn ON
Bit(s) Name Description
30 BKOFF_ALG Backoff Algorithm Option
0: default
1: comply with UNH test
@ C
29 LEN_ERR_CHK Length of Received Frame Check Enable
When the bit is set, the received packet length will be checked for length
encapsulated frames.
0: default disabled
ien K
1: comply with UNH test
28:27 IP_MULT_RULE Unknown IP Multicase Frame Forward Rule
ch TE
If no match in the address table, then following the rules.
00: BC
01: to cpu
10: drop
11: reserved
am IA
26:25 RMC_RULE Unknown Reserved Multicast Frame Forward Rule
If no match in the address table, then follow the rules.
00: to all port(not include blocking state port)
01: to cpu
ad ED
10: drop
11: reserved
24:23 LED_FLASH_TIME The Frequency Of LED Flash
00: 30ms
01: 60ms
M
10: 240ms
11: 480ms
22:21 BISH_TH The Threshold Of Memory Bisshop
11: skip if fail 8 blocks, 0
00: skip if fail 16 (default, from pins)
01: skip if fail 48
10: skip if fail 64
20 BISH_DIS Build In Self Hop
OR
MediaTek Confidential © 2014 MediaTek Inc. Page 273 of 347
This document contains information that is proprietary to MediaTek Inc.
Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited.
[email protected],time=2014-12-05 11:55:47,ip=58.250.71.129,doctitle=MT7628_ProgrammingGuide_20140428(E2).docx,company=Synnex Electronics HK Limited 聯強電子_RLT
MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Bit(s) Name Description
0: enable skip function
EO
1: disable
19:18 BP_MODE Back Pressure Mode
US L
00: disable
01: BP jam, the jam number is set by bp_num
.tw IA
10: BP jamALL, jam packet until the BP condition is released(default),
11: BP carrier, use carrier insertion to do back pressure
17:16 DISMIIPORT_WAST GMII Port Disable Was_Transmit
X [Note] This feature is only valid when port 5 Giga MAC is implemented.
om NT
1: disable was_transmit (good for late CRS PHY, like HPNA2.0 or power-
LAN),
0: enable
15:12 BP_JAM_CNT Back Pressure Jam Number
The consecutive jam count when back pressure is enabled, The default is 10
x.c E
packet jam then one no-jam packet.
11 DISABLE_TX_BAC Disable The Collision Back Off Timer
ne FID
KOFF 0: default
1: re-transmit immediately after collision
10:9 ADDRESSS_HASH MAC Address Hashing Algorithm
_ALG 00: direct mode, using last 10-bit as hashing address
01: XOR48 mode
10: XOR32 mode
syn ON
11: reserved
8 DIS_PKT_TX_ABO Disable Packet TX Abort
RT 1: Disable collision 16 packet abort and late collision abort
0: enable both abort
7:6 PKT_MAX_LEN Maximum Packet Length
@ C
Untaged / VLAN-taged
00: 1536 Bytes / 1536 Bytes
01: 1518 Bytes / 1522 Bytes
10: 1522 Bytes / 1526 Bytes
ien K
11: Reserved / Reserved
5:4 BC_STORM_PROT Global Broadcast Storm Protection
BC will be blocked, if the following number of BC blocks in in output queues
ch TE
00: disable
01: 64
10: 96
11: 128
3:0 AGING_INTERNAL Aging Timer
am IA
0000: disable age
0001: 300sec
0010 - 0111: 600 ~ 38400sec
1xxx: Fast Age (60sec)
ad ED
0000000
101100A0 STRT Switch Reset
0
M
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RESET_SW[31:16]
Type WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RESET_SW[15:0]
Type WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
OR
MediaTek Confidential © 2014 MediaTek Inc. Page 274 of 347
This document contains information that is proprietary to MediaTek Inc.
Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited.
[email protected],time=2014-12-05 11:55:47,ip=58.250.71.129,doctitle=MT7628_ProgrammingGuide_20140428(E2).docx,company=Synnex Electronics HK Limited 聯強電子_RLT
MT7628
Y
Chip Name
MT7628 PROGRAMMING GUIDE Confidential B
NL
Bit(s) Name Description
EO
31:0 RESET_SW Reset switch engine, data, address, link memory , cpu port and ahb
US L
interface when writing data to the STRT register.
.tw IA
0000000
101100A4 LEDP0 LED Port0
5
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
om NT
Name
Type
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name P0_LED
x.c E
Type RW
Reset 0 1 0 1
ne FID
Bit(s) Name Description
3:0 P0_LED port0 LED state, default = link/activity
0000: link
0001: 100M speed
0010: duplex
0011: activity
syn ON
0100: collision
0101: link/activity
0110: duplex/collsion
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