8086 microprocessor

Intel 8086
o Intel 8086 microprocessor is the enhanced version of Intel 8085
microprocessor. It was designed by Intel in 1976.
o The 8086 microprocessor is a16-bit, N-channel, HMOS microprocessor. Where
the HMOS is used for "High-speed Metal Oxide Semiconductor".
o Intel 8086 is built on a single semiconductor chip and packaged in a 40-pin IC
package. The type of package is DIP (Dual Inline Package).
o Intel 8086 uses 20 address lines and 16 data- lines. It can directly address up
to 220 = 1 Mbyte of memory.
o It consists of a powerful instruction set, which provides operation like division
and multiplication very quickly.
o 8086 is designed to operate in two modes, i.e., Minimum and Maximum
mode.

8086 pins configuration

The description of the pins of 8086 is as follows:

AD0-AD15 (Address Data Bus): Bidirectional address/data lines. These are low
order address bus. They are multiplexed with data.

When these lines are used to transmit memory address, the symbol A is used instead
of AD, for example, A0- A15.

A16 - A19 (Output): High order address lines. These are multiplexed with status
signals.

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A16/S3, A17/S4: A16 and A17 are multiplexed with segment identifier signals S3
and S4.

A18/S5: A18 is multiplexed with interrupt status S5.

A19/S6: A19 is multiplexed with status signal S6.

BHE/S7 (Output): Bus High Enable/Status. During T1, it is low. It enables the
data onto the most significant half of data bus, D8-D15. 8-bit device connected

is multiplexed
to upper half of the data bus use BHE signal. It

with status signal S7. S7 signal is available

during T3 and T4.
RD (Read): For read operation. It is an output signal. It is active when LOW.

Ready (Input): The addressed memory or I/O sends acknowledgment through this
pin. When HIGH, it denotes that the peripheral is ready to transfer data.

RESET (Input): System reset. The signal is active HIGH.

CLK (input): Clock 5, 8 or 10 MHz.

INTR: Interrupt Request.

NMI (Input): Non-maskable interrupt request.

TEST (Input): Wait for test control. When LOW the microprocessor continues
execution otherwise waits.

VCC: Power supply +5V dc.

GND: Ground.

Operating Modes of 8086

There are two operating modes of operation for Intel 8086, namely the minimum
mode and the maximum mode.

When only one 8086 CPU is to be used in a microprocessor system, the 8086 is used
in the Minimum mode of operation.

In a multiprocessor system 8086 operates in the Maximum mode.

Pin Description for Minimum Mode

In this minimum mode of operation, the pin MN/ MX is connected to 5V D.C. supply
i.e. MN/MX = VCC.

The description about the pins from 24 to 31 for the minimum mode is as
follows:

INTA (Output): Pin number 24 interrupts acknowledgement. On receiving interrupt

signal, the processor issues an interrupt acknowledgment signal. It is active LOW.

ALE (Output): Pin no. 25. Address latch enable. It goes HIGH during T1. The
microprocessor 8086 sends this signal to latch the address into the Intel 8282/8283
latch.

DEN (Output): Pin no. 26. Data Enable. When Intel 8287/8286 octal bus transceiver
is used this signal. It is active LOW.

DT/R (output): Pin No. 27 data Transmit/Receives. When Intel 8287/8286 octal bus
transceiver is used this signal controls the direction of data flow through the
transceiver. When it is HIGH, data is sent out. When it is LOW, data is received.

M/IO (Output): Pin no. 28, Memory or I/O access. When this signal is HIGH, the CPU
wants to access memory. When this signal is LOW, the CPU wants to access I/O
device.

WR (Output): Pin no. 29, Write. When this signal is LOW, the CPU performs memory
or I/O write operation.

HLDA (Output): Pin no. 30, Hold Acknowledgment. It is sent by the processor when
it receives HOLD signal. It is active HIGH signal. When HOLD is removed HLDA goes
LOW.
HOLD (Input): Pin no. 31, Hold. When another device in microcomputer system
wants to use the address and data bus, it sends HOLD request to CPU through this
pin. It is an active HIGH signal.

Functional units of 8086

8086 contains two independent functional units: a Bus Interface Unit (BIU) and
an Execution Unit (EU).

Fig: Block Diagram of Intel 8086 Microprocessor (8086 Architecture)

Bus Interface Unit (BIU)

The segment registers, instruction pointer and 6-byte instruction queue are
associated with the bus interface unit (BIU).
The BIU:

o Handles transfer of data and addresses,

o Fetches instruction codes, stores fetched instruction codes in first-in-first-out
register set called a queue,
o Reads data from memory and I/O devices,
o Writes data to memory and I/O devices,
o It relocates addresses of operands since it gets un-relocated operand
addresses from EU. The EU tells the BIU from where to fetch instructions or
where to read data.

It has the following functional parts:

o Instruction Queue: When EU executes instructions, the BIU gets 6-bytes of

the next instruction and stores them in the instruction queue and this process
is known as instruction pre fetch. This process increases the speed of the
processor.
o Segment Registers: A segment register contains the addresses of instructions
and data in memory which are used by the processor to access memory
locations. It points to the starting address of a memory segment currently
being used.
There are 4 segment registers in 8086 as given below:
o Code Segment Register (CS): Code segment of the memory holds
instruction codes of a program.
o Data Segment Register (DS): The data, variables and constants given
in the program are held in the data segment of the memory.
o Stack Segment Register (SS): Stack segment holds addresses and
data of subroutines. It also holds the contents of registers and memory
locations given in PUSH instruction.
o Extra Segment Register (ES): Extra segment holds the destination
addresses of some data of certain string instructions.

o Instruction Pointer (IP): The instruction pointer in the 8086 microprocessor

acts as a program counter. It indicates to the address of the next instruction to
be executed.

Execution Unit (EU)

 o The EU receives opcode of an instruction from the queue, decodes it and then
executes it. While Execution, unit decodes or executes an instruction, then the
BIU fetches instruction codes from the memory and stores them in the queue.
o The BIU and EU operate in parallel independently. This makes processing
faster.
o General purpose registers, stack pointer, base pointer and index registers,
ALU, flag registers (FLAGS), instruction decoder and timing and control unit
constitute execution unit (EU). Let's discuss them:

o General Purpose Registers: There are four 16-bit general purpose registers:
AX (Accumulator Register), BX (Base Register), CX (Counter) and DX. Each of
these 16-bit registers are further subdivided into 8-bit registers as shown
below:

16-bit registers 8-bit high-order registers 8-bit low-order registers

AX AH AL

BX BH BL

CX CH CL

DX DH DL

o Index Register: The following four registers are in the group of pointer and
index registers:
o Stack Pointer (SP)
o Base Pointer (BP)
o Source Index (SI)
o Destination Index (DI)
o ALU: It handles all arithmetic and logical operations. Such as addition,
subtraction, multiplication, division, AND, OR, NOT operations.
o Flag Register: It is a 16?bit register which exactly behaves like a flip-flop,
means it changes states according to the result stored in the accumulator. It
has 9 flags and they are divided into 2 groups i.e. conditional and control
flags.
o Conditional Flags: This flag represents the result of the last arithmetic
or logical instruction executed. Conditional flags are:
 o Carry Flag
o Auxiliary Flag
o Parity Flag
o Zero Flag
o Sign Flag
o Overflow Flag
o Control Flags: It controls the operations of the execution unit. Control
flags are:
o Trap Flag
o Interrupt Flag
o Direction Flag

Interrupts
Interrupt is a process of creating a temporary halt during program execution and
allows peripheral devices to access the microprocessor.

Microprocessor responds to these interrupts with an interrupt service routine (ISR),

which is a short program or subroutine to instruct the microprocessor on how to
handle the interrupt.

There are different types of interrupt in 8086:

Hardware Interrupts
Hardware interrupts are that type of interrupt which are caused by any peripheral
device by sending a signal through a specified pin to the microprocessor.

The Intel 8086 has two hardware interrupt pins:

o NMI (Non-Maskbale Interrupt)

o INTR (Interrupt Request) Maskable Interrupt.

NMI: NMI is a single Non-Maskable Interrupt having higher priority than the
maskable interrupt.

o It cannot be disabled (masked) by user using software.

o It is used by the processor to handle emergency conditions.
For example: It can be used to save program and data in case of power
failure. An external electronic circuitry is used to detect power failure, and to
send an interrupt signal to 8086 through NMI line.

INTR: The INTR is a maskable interrupt. It can be enabled/disabled using interrupt

flag (IF). After receiving INTR from external device, the 8086 acknowledges through
INTA signal.

It executes two consecutive interrupt acknowledge bus cycles.

Software Interrupt
A microprocessor can also be interrupted by internal abnormal conditions such as
overflow; division by zero; etc. A programmer can also interrupt microprocessor by
inserting INT instruction at the desired point in the program while debugging a
program. Such an interrupt is called a software interrupt.

The interrupt caused by an internal abnormal conditions also came under the
heading of software interrupt.

Example of software interrupts are:

o TYPE 0 (division by zero)

o TYPE 1 (single step execution for debugging a program)
o TYPE 2 represents NMI (power failure condition)
o TYPE 3 (break point interrupt)
 o TYPE 4 (overflow interrupt)

Interrupt pointer table for 8086

Fig: Interrupt pointer table for 8086

The 8086 can handle up to 256, hardware and software interrupts.

1KB memory acts as a table to contain interrupt vectors (or interrupt pointers), and it
is called interrupt vector table or interrupt pointer table. The 256 interrupt pointers
have been numbered from 0 to 255 (FF hex). The number assigned to an interrupt
pointer is known as type of that interrupt. For example, Type 0, Type 1, Type
2,...........Type 255 interrupt.

Addressing modes of 8086

The way for which an operand is specified for an instruction in the accumulator, in a
general purpose register or in memory location, is called addressing mode.

The 8086 microprocessors have 8 addressing modes. Two addressing modes have
been provided for instructions which operate on register or immediate data.

These two addressing modes are:

Register Addressing: In register addressing, the operand is placed in one of the 16-
bit or 8-bit general purpose registers.

Example

o MOV AX, CX
o ADD AL, BL
o ADD CX, DX

Immediate Addressing: In immediate addressing, the operand is specified in the

instruction itself.

Example

o MOV AL, 35H

o MOV BX, 0301H
o MOV [0401], 3598H
o ADD AX, 4836H

The remaining 6 addressing modes specify the location of an operand which is

placed in a memory.

These 6 addressing modes are:

Direct Addressing: In direct addressing mode, the operand?s offset is given in the
instruction as an 8-bit or 16-bit displacement element.

Example

o ADD AL, [0301]

The instruction adds the content of the offset address 0301 to AL. the operand is
placed at the given offset (0301) within the data segment DS.
Register Indirect Addressing: The operand's offset is placed in any one of the
registers BX, BP, SI or DI as specified in the instruction.

Example

o MOV AX, [BX]

It moves the contents of memory locations addressed by the register BX to the

register AX.

Based Addressing: The operand's offset is the sum of an 8-bit or 16-bit

displacement and the contents of the base register BX or BP. BX is used as base
register for data segment, and the BP is used as a base register for stack segment.

Effective address (Offset) = [BX + 8-bit or 16-bit displacement].

Example

o MOV AL, [BX+05]; an example of 8-bit displacement.

o MOV AL, [BX + 1346H]; example of 16-bit displacement.

Indexed Addressing: The offset of an operand is the sum of the content of an index
register SI or DI and an 8-bit or 16-bit displacement.

Offset (Effective Address) = [SI or DI + 8-bit or 16-bit displacement]

Example

o MOV AX, [SI + 05]; 8-bit displacement.

o MOV AX, [SI + 1528H]; 16-bit displacement.

Based Indexed Addressing: The offset of operand is the sum of the content of a
base register BX or BP and an index register SI or DI.

Effective Address (Offset) = [BX or BP] + [SI or DI]

Here, BX is used for a base register for data segment, and BP is used as a base
register for stack segment.

Example

o ADD AX, [BX + SI]

o MOV CX, [BX + SI]
Based Indexed with Displacement: In this mode of addressing, the operand's offset
is given by:

Effective Address (Offset) = [BX or BP] + [SI or DI] + 8-bit or 16-bit displacement

Example

o MOV AX, [BX + SI + 05]; 8-bit displacement

o MOV AX, [BX + SI + 1235H]; 16-bit displacement

RISC and CISC Processors

RISC stands for Reduced Instruction Set Computer and

CISC stands for Complex Instruction Set Computer.

There are two approaches of the design of the control unit of a microprocessor i.e.-

o Hardware approach and

o Software approach.

RISC Processors:- To execute an instruction, a number of steps are required. By the

control unit of the processor, a number of control signals are generated for each
step. To execute each instruction, if there is a separate electronic circuitry in the
control unit, which produces all the necessary signals, this approach of the design of
the control section of the processor is called RISC design. It is hardware approach. It
is also called hard-wired approach.

Examples of RISC processors are:

o DEC's Alpha 21064, 21164 and 21264 processors;

o SUN's SPARC and ULTRA SPARC;
o PowerPC processors etc.

CISC Processors:- If the control unit contains a number of micro electronic circuitry
to generate a set of control signals and each micro circuitry is activated by a
microcode, this design approach is called CISC design. This is a software approach of
designing a control unit of the processor.

Examples of CISC processors are:

 o Intel 386, 486;
o Pentium Pro, Pentium, Pentium II, Pentium III, Pentium 4;
o Motorola's 68000, 68020, 68030, 68040, etc.

Difference between RISC and CISC

S.No. RISC CISC

1. Simple instruction set Complex instruction set

2. Consists of Large number of registers. Less number of registers

3. Larger Program Smaller program

4. Simple processor circuitry (small number of Complex processor circuitry (more num
transistors) of transistors)

5. More RAM usage Little Ram usage

6. Simple addressing modes Variety of addressing modes

7. Fixed length instructions Variable length instructions

8. Fixed number of clock cycles for executing Variable number of clock cycles for
one instruction instructions

8086 Microprocessor
Following are the features of 8086 microprocessor:
• Data Bus Width: 16
• Addressed Memory Size of: 1M
80286 Microprocessor
Following are the features of 80286 microprocessor:
• Data bus width: 16
• Addressed Memory size of : 16M
• Clock speed is higher and hence some instructions are executed in as little
as 250ns.
• As shown in the figure, 80286 does not have multiplexed address/data bus
lines.

Figure-1 depicts pin diagram of 8086 and 80286.

80386 Microprocessor
Following are the features of 80386 microprocessor:
• 32-bit data bus and 32-bit memory address
• It addresses up to 4G bytes of memory.
• 80386SX: address 16M bytes of memory.
• 80386SL: address 32M bytes of memory.
• 80386SLC: address 32M bytes of memory.It contain internal cache memory
which allowed it to process data at higher rates
Figure-2 depicts pin diagrams of 80386DX and 80386SX.

80486 Microprocessor
Following are the features of 80486 microprocessor:
• Data Bus Width: 32 bit
• Address bus : 32 bit
• Memory Size: 4G +16K cache
• The 80486 architecture has been ungraded such that half of its instructions
are executed in 1 clock cycle instead of two clock cycles.
• It has 80386 like microprocessor and 80387 like numeric coprocessor.
Following table compares 80286 vs 80386 vs 80486 and mentions difference
between them.

Specifications 80286 80386

 CPU Speed 6 to 25 MHz 12 to 40 MHz 16 to 100

Cores 1 1 1

RAM 16MB 4GB 4GB

Functional Units 4 6 9

Pipeline stages 3 3 5

Cache off chip 0 YES (Support) YES (Supp

Cache on chip 0 0 8 KB

Transistors 134,000 275,000 >1000000

The Pentium family of processors originated from the 80486 microprocessor. The term
''Pentium processor'' refers to a family of microprocessors that share a common
architecture and instruction set. It runs at a clock frequency of either 60 or 66 MHz and has
3.1 million transistors. Some of the features of Pentium architecture are:

 Complex Instruction Set Computer (CISC) architecture with Reduced Instruction

Set Computer (RISC) performance.
 64-Bit Bus
 Upward code compatibility.
 Pentium processor uses Superscalar architecture and hence can issue multiple
instructions per cycle.
 Multiple Instruction Issue (MII) capability.
 Pentium processor executes instructions in five stages. This staging, or pipelining,
allows the processor to overlap multiple instructions so that it takes less time to
execute two instructions in a row.
 The Pentium processor fetches the branch target instruction before it executes the
branch instruction.
  The Pentium processor has two separate 8-kilobyte (KB) caches on chip, one for
instructions and one for data. It allows the Pentium processor to fetch data and
instructions from the cache simultaneously.
 When data is modified, only the data in the cache is changed. Memory data is
changed only when the Pentium processor replaces the modified data in the cache
with a different set of data
 The Pentium processor has been optimized to run critical instructions in fewer
clock cycles than the 80486 processor.

The Pentium processor has two primary operating modes -

1. Protected Mode - In this mode all instructions and architectural features are
available, providing the highest performance and capability. This is the
recommended mode that all new applications and operating systems should
target.
2. Real-Address Mode - This mode provides the programming environment of the
Intel 8086 processor, with a few extensions. Reset initialization places the
processor in real mode where, with a single instruction, it can switch to protected
mode.

The Pentium's basic integer pipeline is five stages long, with the stages broken down as
follows:

1. Pre-fetch/Fetch: Instructions are fetched from the instruction cache and aligned in
pre-fetch buffers for decoding.
2. Decode1: Instructions are decoded into the Pentium's internal instruction format.
Branch prediction also takes place at this stage.
3. Decode2: Same as above, and microcode ROM kicks in here, if necessary. Also,
address computations take place at this stage.
 4. Execute: The integer hardware executes the instruction.
5. Write-back: The results of the computation are written back to the register file.

Floating Point Unit:

There are 8 general-purpose 80-bit Floating point registers. Floating point unit has 8
stages of pipelining. First five are similar to integer unit. Since the possibility of error is
more in Floating Point unit (FPU) than in integer unit, additional error checking stage is
there in FPU. The floating point unit is shown as below

Where, FRD - Floating Point Rounding

FDD - Floating Point Division
FADD - Floating Point Addition
FEXP - Floating Point Exponent
FAND - Floating Point And
FMUL - Floating Point Multiply