Karnaugh Map Method

 The Karnaugh map method is a graphical technique for simplifying Boolean functions.
 It is a two-dimensional of a Truth Table. It provides a simpler method for minimizing logic expressions.
 The map method is ideally suited for four or less variables.
 A Karnaugh map for n variables is made up of 2n squares.
 Each square designates a product term of a Boolean expression.
 For product terms which are present in the expression, 1s are written in the corresponding squares; 0s
are written in those squares which correspond to product terms not present in the expression.

Consider a map of two variables:

A A A 0 1
B

B A B AB 0 A B AB

B A B AB 1 A B AB

In the map, 0 represents A , and 1 represents A. Similarly, for variable B.

For example, for the Boolean functions Y = A B + AB

0 1

1
0

1 1

Example : simplify Y= A B +A B

0 1

0 1 1 B

Two adjacent squares containing 1 have been grouped together. To show the
grouping, they have been encircled. For simplification we have to see that which variable isBcommon to both squares. In
st
this case Bis common to both as the 1 row is for .
So their simplification will result Y = B
This can be verified also algebraically as follows:
Y= A B +A B

= B (A + A)
=
B

So the variable which is common to adjacent squares is selected, and the variable which is not common is discarded.

Example : simplify Y= A B + AB +B
A
0 1
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 0 1 1 A

1 B
1 1

Simplification result Y= A B + AB +B
A =B+A

The result obtained by map method can also be verified algebraically as follows:

Y= A B + AB +B
A

= A B + AB + AB +A B

= B (A + A) + A ( B + B )
= B+A

Karnaugh Map for Three variables:

A B A B A B A B
C
A B C A B C A B C AB C

C
A B C A B C ABC A BC

The ordering of the variables, ie., 00,01,11,10 is in gray code.

AB
C 00 01 11 10

0 A B C A B C A B C AB C

1
A B C A B C ABC A BC

Example: simplifying the function Y = AB C + ABC

AB
C 00 01 11 10

0 1 AB

1
1

The simplified function will be Y = AB

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 Example: simplifying the function Y = A B C + A B C + A B C

AB
C 00 01 11 10

0 1 1 AC

1 A B
1

The simplified function will be Y = A B + A C

Summmary of Rule of simplication:

1. No zeros allowed.
2. No diagonals.
3. Only power of 2 number of cells in each group.
4. Groups should be as large as possible.
5. Everyone must be in at least one group.
6. Overlapping allowed.
7. Fewest number of groups possible.

Combinational and Sequential circuits

 There are two types of logic circuits – combinational and sequential.
Combinational circuit
 A combinational circuit is one in which the state of the output at any instant is entirely determined by the states of
the inputs at that time.
 Combinational circuits are those logic circuits whose operations can be completely described by a truth table /
Boolean expression.
 A combinational circuit is realized using AND, OR, NOT gates (or NAND OR NOR gates).
 Examples of combinational circuits are: adder, subtractors, code converters, decoders, encoders, programmable
logic arrays (PLAs), ROMs etc.,
Sequential circuit
 A sequential circuit consists of a combinational logic and storage elements.
 The output of a sequential circuit is not only a function of a present inputs but also of past inputs.
 The state of the storage elements depends upon the preceding inputs and the preceding states of the elements.
Therefore, the output of a sequential circuit becomes a function of both the present inputs and the present internal
states of the sequential circuit.
 To realize sequential circuits in addition to AND, OR and NOT gates, flip-flops are also required.
 Examples of sequential circuits are: registers, shift registers, counters, etc.,

Sum of product forms

 A sum-of-products representation is a logical sum (OR) of products (terms using the AND operator)
Consider a equation

E = ((A. B) + (A .C) + (B . C))

Arithmetic Circuits
Arithmetic operations, such as addition, subtraction, multiplication, division etc., are performed by a digital computer,
calculator or other digital system. Logic circuits for some important arithmetic operations are half-adder and full adder.
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HALF ADDER:
A logic circuit which performs addition of two binary bits is called a half-adder.
Truth table for the addition of two binary bits.
Inputs Outputs
A B Sum S Carry C
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

It is concluded that the sum is equal to A XOR B. It means that the outputs of an EXCLUSIVE-OR gate will give the sum.
The carry is equal to A AND B. The output of an AND gate will give the carry.

S= A B + A B
A Sum
=A B
Sum
S S
S HALF
C=AB B A
ADDER
Carry
B
C
Carry
C

Full Adder

A logic circuit which performs addition of three binary bits is called a Full-adder.
A full adder can be built using two half adders and an OR gate.

Inputs Outputs
A B C Sum S Carry C
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

A Carry
HALF
ADDER Carry

B Sum A
Y
HALF Carry
ADDER
Sum

--Full Adder—

Register transfer notation

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* Provides a formal means of describing machine structure and function.
*It can be used to describe WHAT a machine does.
Using RTN can describe
1.Static properties
2.Dynamic properties
Static properties
* Specifying register – IR(31 . . 0) specifies a register named IR having 32 bits numbered 31 to 0
* ―Naming‖ using the := naming operator.
Eg: - OP(4 .. 0) := IR(31 .. 27) - it tells that the 5msbs of IR be called OP, with bits 4 .. 0

Dynamic properties:
* Condition Expression-
(op=12) -> R[ra] <- R[rb] + R[rc]
It says when the OP field of IR =12, will store in the register specified by the ra field, which has addition of rb and rc.
Physical consideration:
FAN-IN
*Fan-in is the number of input a gate can handle.
*Physical logic gates with a large fan-in tend to be slower than those with a smaller fan-in.
*This is because the complexity of the input circuitry increases the input capacitance of the device.
*Using logic gate with higher fan-in will help reducing the depth of the logic circuit.
*For instance the Fan-in for the AND gate:

Fan-out:
Fan out of the logic gate output is the number of gate inputs it can feed or connect to.

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