Features

• Single 2.7V - 3.6V Supply

• Serial Interface Architecture
• Page Program Operation
– Single Cycle Reprogram (Erase and Program)
– 512 Pages (264 Bytes/Page) Main Memory
• Optional Page and Block Erase Operations
• One 264-Byte SRAM Data Buffer
• Internal Program and Control Timer
• Fast Page Program Time – 7 ms Typical
• 120 µs Typical Page to Buffer Transfer Time 1-Megabit
• Low-Power Dissipation
– 4 mA Active Read Current Typical
– 2 µA CMOS Standby Current Typical 2.7-volt Only
• 13 MHz Max Clock Frequency
• Hardware Data Protection Feature Serial
• Serial Peripheral Interface (SPI) Compatible – Modes 0 and 3
• CMOS and TTL Compatible Inputs and Outputs DataFlash®
• Commercial and Industrial Temperature Ranges

Description AT45DB011
The AT45DB011 is a 2.7-volt only, serial interface Flash memory suitable for in-sys-
tem reprogramming. Its 1,081,344 bits of memory are organized as 512 pages of 264 Preliminary
bytes each. In addition to the main memory, the AT45DB011 also contains one SRAM
data buffer of 264 bytes. Unlike conventional Flash memories that are accessed ran-
domly with multiple address lines and a parallel interface, the DataFlash uses a serial
interface to sequentially access its data. The simple serial interface facilitates hard-
(continued)
Pin Configurations SOIC
Pin Name Function
SI 1 8 SO
CS Chip Select SCK 2 7 GND
SCK Serial Clock RESET 3 6 VCC
CS 4 5 WP
SI Serial Input
SO Serial Output
Hardware Page AT45DB011
WP
Write Protect Pin
RESET Chip Reset
Preliminary 16-
RDY/BUSY Ready/Busy Megabit 2.7-volt
PLCC TSSOP Top View
Type 1
Only Serial
GND
VCC

DataFlash
NC
NC

NC
NC
CS

RDY/BUSY 1 14 CS
4
3
2
1
32
31
30

SCK 5 29 WP
RESET 2 13 NC
SI 6 28 RESET
SO 7 27 RDY/BUSY WP 3 12 NC
NC 8 26 NC VCC 4 11 NC
NC 9 25 NC
GND 5 10 NC
NC 10 24 NC
NC 11 23 NC SCK 6 9 NC
NC 12 22 NC SO 7 8 SI
NC 13 21 NC
14
15
16
17
18
19
20
NC
NC
DC
DC
NC
NC
NC

Rev. 1103C–08/98

Note: PLCC package pins 16

and 17 are DON’T CONNECT

1
ware layout, increases system reliability, minimizes switch- To allow for simple in-system reprogrammability, the
ing noise, and reduces package size and active pin count. AT45DB011 does not require high input voltages for pro-
The device is optimized for use in many commercial and gramming. The device operates from a single power sup-
industrial applications where high density, low pin count, p ly , 2. 7V to 3. 6V , f o r b o th t he pr o g r am an d r e a d
low voltage, and low power are essential. Typical applica- operations. The AT45DB011 is enabled through the chip
tions for the DataFlash are digital voice storage, image select pin (CS) and accessed via a three-wire interface
storage, and data storage. The device operates at clock consisting of the Serial Input (SI), Serial Output (SO), and
frequencies up to 13 MHz with a typical active read current the Serial Clock (SCK).
consumption of 4 mA. All programming cycles are self-timed, and no separate
erase cycle is required before programming.

Block Diagram
WP FLASH MEMORY ARRAY

PAGE (264 BYTES)

BUFFER (264 BYTES)

SCK
CS I/O INTERFACE
RESET
VCC
GND
RDY/BUSY SI SO

Memory Array
To provide optimal flexibility, the memory array of the details the number of pages per sector and block. All pro-
AT45DB011 is divided into three levels of granularity com- gram operations to the DataFlash occur on a page by page
prising of sectors, blocks, and pages. The Memory Archi- basis; however, the optional erase operations can be per-
tecture Diagram illustrates the breakdown of each level and formed at the block or page level.

2 AT45DB011
 AT45DB011

Memory Architecture Diagram

SECTOR ARCHITECTURE BLOCK ARCHITECTURE PAGE ARCHITECTURE
SECTOR 0 PAGE 0
SECTOR 0 = 2112 BYTES (2K + 64) BLOCK 0 8 Pages
BLOCK 1 PAGE 1

BLOCK 0
BLOCK 2
BLOCK 3

SECTOR 1
PAGE 6
SECTOR 1 = 65,472 BYTES (62K + 1984) PAGE 7
PAGE 8
BLOCK 29 PAGE 9

BLOCK 1
BLOCK 30
BLOCK 31
BLOCK 32
PAGE 14
BLOCK 33
PAGE 15
BLOCK 34
PAGE 16
PAGE 17
SECTOR 2

PAGE 18
SECTOR 2 = 67,584 BYTES (64K + 2K)

BLOCK 61 PAGE 509

BLOCK 62 PAGE 510
BLOCK 63 PAGE 511

Block = 2112 bytes Page = 264 bytes

(2K + 64) (256 + 8)

Device Operation
The device operation is controlled by instructions from the bits are sent to initialize the read operation. Following the
host processor. The list of instructions and their associated 32 don’t care bits, additional pulses on SCK result in serial
opcodes are contained in Tables 1 and 2. A valid instruc- data being output on the SO (serial output) pin. The CS pin
tion starts with the falling edge of CS followed by the appro- must remain low during the loading of the opcode, the
priate 8-bit opcode and the desired buffer or main memory address bits, and the reading of data. When the end of a
address location. While the CS pin is low, toggling the SCK page in main memory is reached during a main memory
pin controls the loading of the opcode and the desired page read, the device will continue reading at the beginning
buffer or main memory address location through the SI of the same page. A low to high transition on the CS pin will
(serial input) pin. All instructions, addresses, and data are terminate the read operation and tri-state the SO pin.
transferred with the most significant bit (MSB) first. BUFFER READ: Data can be read from the data buffer
Read using an opcode of 54H. To perform a buffer read, the eight
bits of the opcode must be followed by 15 don’t care bits,
By specifying the appropriate opcode, data can be read
nine address bits, and eight don't care bits. Since the buffer
from the main memory or from the data buffer.
size is 264-bytes, nine address bits (BFA8-BFA0) are
MAIN MEMORY PAGE READ: A main memory read allows required to specify the first byte of data to be read from the
the user to read data directly from any one of the 512 buffer. The CS pin must remain low during the loading of
pages in the main memory, bypassing the data buffer and the opcode, the address bits, the don’t care bits, and the
leaving the contents of the buffer unchanged. To start a reading of data. When the end of the buffer is reached, the
page read, the 8-bit opcode, 52H, is followed by 24 device will continue reading back at the beginning of the
address bits and 32 don’t care bits. In the AT45DB011, the buffer. A low to high transition on the CS pin will terminate
first six address bits are reserved for larger density devices the read operation and tri-state the SO pin.
(see Notes on page 9), the next nine address bits (PA8-
MAIN MEMORY PAGE TO BUFFER TRANSFER: A page
PA0) specify the page address, and the next nine address
of data can be transferred from the main memory to buffer.
bits (BA8-BA0) specify the starting byte address within the
An 8-bit opcode of 53H is followed by the six reserved bits,
page. The 32 don’t care bits which follow the 24 address
nine address bits (PA8-PA0) which specify the page in

3
main memory that is to be transferred, and nine don’t care page are internally self timed and should take place in a
bits. The CS pin must be low while toggling the SCK pin to maximum time of tEP. During this time, the status register
load the opcode, the address bits, and the don’t care bits will indicate that the part is busy.
from the SI pin. The transfer of the page of data from the BUFFER TO MAIN MEMORY PAGE PROGRAM WITH-
main memory to the buffer will begin when the CS pin tran- OUT BUILT-IN ERASE: A previously erased page within
sitions from a low to a high state. During the transfer of a main memory can be programmed with the contents of the
page of data (tXFR), the status register can be read to deter- buffer. An 8-bit opcode of 88H is followed by the six
mine whether the transfer has been completed or not. reserved bits, nine address bits (PA8-PA0) that specify the
MAIN MEMORY PAGE TO BUFFER COMPARE: A page of page in the main memory to be written, and nine additional
data in main memory can be compared to the data in the don’t care bits. When a low to high transition occurs on the
buffer. An 8-bit opcode of 60H is followed by 24 address CS pin, the part will program the data stored in the buffer
bits consisting of the six reserved bits, nine address bits into the specified page in the main memory. It is necessary
(PA8-PA0) which specify the page in the main memory that that the page in main memory that is being programmed
is to be compared to the buffer, and nine don’t care bits. has been previously erased. The programming of the page
The loading of the opcode and the address bits is the same is internally self timed and should take place in a maximum
as described previously. The CS pin must be low while tog- time of tP. During this time, the status register will indicate
gling the SCK pin to load the opcode, the address bits, and that the part is busy.
the don't care bits from the SI pin. On the low to high transi- PAGE ERASE: The optional Page Erase command can be
tion of the CS pin, the 264 bytes in the selected main mem- used to individually erase any page in the main memory
ory page will be compared with the 264 bytes in the buffer. array allowing the Buffer to Main Memory Page Program
During this time (tXFR), the status register will indicate that without Built-In Erase command to be utilized at a later
the part is busy. On completion of the compare operation, time. To perform a Page Erase, an opcode of 81H must be
bit 6 of the status register is updated with the result of the loaded into the device, followed by six reserved bits, nine
compare. address bits (PA8-PA0), and nine don’t care bits. The nine
Program address bits are used to specify which page of the memory
array is to be erased. When a low to high transition occurs
BUFFER WRITE: Data can be shifted in from the SI pin
on the CS pin, the part will erase the selected page to 1s.
into the data buffer. To load data into the buffer, an 8-bit
The erase operation is internally self-timed and should take
opcode of 84H is followed by 15 don’t care bits and nine
place in a maximum time of tPE. During this time, the status
address bits (BFA8-BFA0). The nine address bits specify
register will indicate that the part is busy.
the first byte in the buffer to be written. The data is entered
following the address bits. If the end of the data buffer is BLOCK ERASE: A block of eight pages can be erased at
reached, the device will wrap around back to the beginning one time allowing the Buffer to Main Memory Page Pro-
of the buffer. Data will continue to be loaded into the buffer gram without Built-In Erase command to be utilized to
until a low to high transition is detected on the CS pin. reduce programming times when writing large amounts of
data to the device. To perform a Block Erase, an opcode of
BUFFER TO MAIN MEMORY PAGE PROGRAM WITH
50H must be loaded into the device, followed by six
BUILT-IN ERASE: Data written into the buffer can be pro-
reserved bits, six address bits (PA8-PA3), and 12 don’t
grammed into the main memory. An 8-bit opcode of 83H is
care bits. The six address bits are used to specify which
followed by the six reserved bits, nine address bits (PA8-
block of eight pages is to be erased. When a low to high
PA0) that specify the page in the main memory to be writ-
transition occurs on the CS pin, the part will erase the
ten, and nine additional don’t care bits. When a low to high
selected block of eight pages to 1s. The erase operation is
transition occurs on the CS pin, the part will first erase the
internally self-timed and should take place in a maximum
selected page in main memory to all 1s and then program
time of tBE. During this time, the status register will indicate
the data stored in the buffer into the specified page in the
that the part is busy.
main memory. Both the erase and the programming of the

4 AT45DB011
 AT45DB011

Block Erase Addressing

PA8 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 Block
0 0 0 0 0 0 X X X 0
0 0 0 0 0 1 X X X 1
0 0 0 0 1 0 X X X 2
0 0 0 0 1 1 X X X 3
• • • • • • • • • •
• • • • • • • • • •
• • • • • • • • • •
1 1 1 1 0 0 X X X 60
1 1 1 1 0 1 X X X 61
1 1 1 1 1 0 X X X 62
1 1 1 1 1 1 X X X 63

MAIN MEMORY PAGE PROGRAM: This operation is a self-timed and should take place in a maximum time of tEP.
combination of the Buffer Write and Buffer to Main Memory During this time, the status register will indicate that the
Page Program with Built-In Erase operations. Data is first part is busy.
shifted into the buffer from the SI pin and then programmed If a sector is programmed or reprogrammed sequentially
into a specified page in the main memory. An 8-bit opcode page by page, then the programming algorithm shown in
of 82H is followed by the six reserved bits and 18 address Figure 1 is recommended. Otherwise, if multiple bytes in a
bits. The nine most significant address bits (PA8-PA0) page or several pages are programmed randomly in a sec-
select the page in the main memory where data is to be tor, then the programming algorithm shown in Figure 2 is
written, and the next nine address bits (BFA8-BFA0) select recommended.
the first byte in the buffer to be written. After all address bits
STATUS REGISTER: The status register can be used to
are shifted in, the part will take data from the SI pin and
determine the device’s ready/busy status, the result of a
store it in the data buffer. If the end of the buffer is reached,
Main Memory Page to Buffer Compare operation, or the
the device will wrap around back to the beginning of the
device density. To read the status register, an opcode of
buffer. When there is a low to high transition on the CS pin,
57H must be loaded into the device. After the last bit of the
the part will first erase the selected page in main memory to
opcode is shifted in, the eight bits of the status register,
all 1s and then program the data stored in the buffer into
starting with the MSB (bit 7), will be shifted out on the SO
the specified page in the main memory. Both the erase and
pin during the next eight clock cycles. The five most-signifi-
the programming of the page are internally self timed and
cant bits of the status register will contain device informa-
should take place in a maximum of time tEP. During this
tion, while the remaining three least-significant bits are
time, the status register will indicate that the part is busy.
reserved for future use and will have undefined values.
AUTO PAGE REWRITE: This mode is only needed if multi- After bit 0 of the status register has been shifted out, the
ple bytes within a page or multiple pages of data are modi- sequence will repeat itself (as long as CS remains low and
fied in a random fashion. This mode is a combination of two SCK is being toggled) starting again with bit 7. The data in
operations: Main Memory Page to Buffer Transfer and the status register is constantly updated, so each repeating
Buffer to Main Memory Page Program with Built-In Erase. sequence will output new data.
A page of data is first transferred from the main memory to
Ready/busy status is indicated using bit 7 of the status reg-
the data buffer, and then the same data (from the buffer) is
ister. If bit 7 is a 1, then the device is not busy and is ready
programmed back into its original page of main memory.
to accept the next command. If bit 7 is a 0, then the device
An 8-bit opcode of 58H is followed by the six reserved bits,
is in a busy state. The user can continuously poll bit 7 of the
nine address bits (PA8-PA0) that specify the page in main
status register by stopping SCK once bit 7 has been output.
memory to be rewritten, and nine additional don’t care bits.
The status of bit 7 will continue to be output on the SO pin,
When a low to high transition occurs on the CS pin, the part
and once the device is no longer busy, the state of SO will
will first transfer data from the page in main memory to the
change from 0 to 1. There are eight operations which can
buffer and then program the data from the buffer back into
cause the device to be in a busy state: Main Memory Page
same page of main memory. The operation is internally
to Buffer Transfer, Main Memory Page to Buffer Compare,

5
Buffer to Main Memory Page Program with Built-In Erase, machine to an idle state. The device will remain in the reset
Buffer to Main Memory Page Program without Built-In condition as long as a low level is present on the RESET
Erase, Page Erase, Block Erase, Main Memory Page Pro- pin. Normal operation can resume once the RESET pin is
gram, and Auto Page Rewrite. brought back to a high level.
The result of the most recent Main Memory Page to Buffer The device incorporates an internal power-on reset circuit,
Compare operation is indicated using bit 6 of the status so there are no restrictions on the RESET pin during
register. If bit 6 is a 0, then the data in the main memory power-on sequences. The RESET pin is also internally
page matches the data in the buffer. If bit 6 is a 1, then at pulled high; therefore, in low pin count applications, con-
least one bit of the data in the main memory page does not nection of the RESET pin is not necessary if this pin and
match the data in the buffer. feature will not be utilized. However, it is recommended
The device density is indicated using bits 5, 4, and 3 of the that the RESET pin be driven high externally whenever
status register. For the AT45DB011, the three bits are 0, 0, possible.
and 1. The decimal value of these three binary bits does READY/BUSY: This open drain output pin will be driven
not equate to the device density; the three bits represent a low when the device is busy in an internally self-timed oper-
combinational code relating to differing densities of Serial ation. This pin, which is normally in a high state (through an
DataFlash devices, allowing a total of eight different density external pull-up resistor), will be pulled low during program-
configurations. ming operations, compare operations, and during page-to-
HARDWARE PAGE WRITE PROTECT: If the WP pin is buffer transfers.
held low, the first 256 pages of the main memory cannot be The busy status indicates that the Flash memory array and
reprogrammed. The only way to reprogram the first 256 the buffer cannot be accessed.
pages is to first drive the protect pin high and then use the
program commands previously mentioned. The WP pin is Power On/Reset State
internally pulled high; therefore, in low pin count applica- When power is first applied to the device, or when recover-
tions, connection of the WP pin is not necessary if this pin ing from a reset condition, the device will default to SPI
and feature will not be utilized. However, it is recom- mode 3. In addition, the SO pin will be in a high impedance
mended that the WP pin be driven high externally when- state, and a high to low transition on the CS pin will be
ever possible. required to start a valid instruction. The SPI mode will be
RESET: A low state on the reset pin (RESET) will terminate automatically selected on every falling edge of CS by sam-
the operation in progress and reset the internal state pling the inactive clock state.
Status Register Format
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

RDY/BUSY COMP 0 0 1 X X X

Absolute Maximum Ratings*

Temperature Under Bias ................................ -55°C to +125°C *NOTICE: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
Storage Temperature ..................................... -65°C to +150°C age to the device. This is a stress rating only and
functional operation of the device at these or any
All Input Voltages other conditions beyond those indicated in the
(including NC Pins) operational sections of this specification is not
with Respect to Ground ...................................-0.6V to +6.25V implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
All Output Voltages reliability.
with Respect to Ground .............................-0.6V to VCC + 0.6V

DC and AC Operating Range

AT45DB011

Com. 0°C to 70°C

Operating Temperature (Case)
Ind. -40°C to 85°C
(1)
VCC Power Supply 2.7V to 3.6V
Note: 1. After power is applied and VCC is at the minimum specified data sheet value, the system should wait 20 ms before an oper-
ational mode is started.

6 AT45DB011
 AT45DB011

DC Characteristics
Symbol Parameter Condition Min Typ Max Units

CS, RESET, WP = VIH, all inputs

ISB Standby Current 2 10 µA
at CMOS levels

Active Current, Read f = 13 MHz; IOUT = 0 mA;

ICC1 4 10 mA
Operation VCC = 3.6V

Active Current, Program/Erase

ICC2 VCC = 3.6V 10 25 mA
Operation

ILI Input Load Current VIN = CMOS levels 1 µA

ILO Output Leakage Current VI/O = CMOS levels 1 µA

VIL Input Low Voltage 0.6 V

VIH Input High Voltage 2.0 V

VOL Output Low Voltage IOL = 1.6 mA; VCC = 2.7V 0.4 V

VOH Output High Voltage IOH = -100 µA VCC - 0.2V V

AC Characteristics
Symbol Parameter Min Typ Max Units

fSCK SCK Frequency 13 MHz

tWH SCK High Time 35 ns

tWL SCK Low Time 35 ns

tCS Minimum CS High Time 250 ns

tCSS CS Setup Time 250 ns

tCSH CS Hold Time 250 ns

tCSB CS High to RDY/BUSY Low 200 ns

tSU Data In Setup Time 10 ns

tH Data In Hold Time 20 ns

tHO Output Hold Time 0 ns

tDIS Output Disable Time 25 ns

tV Output Valid 30 ns

tXFR Page to Buffer Transfer/Compare Time 120 200 µs

tEP Page Erase and Programming Time 10 20 ms

tP Page Programming Time 7 15 ms

tPE Page Erase Time 6 10 ms

tBE Block Erase Time 7 15 ms

tRST RESET Pulse Width 10 µs

tREC RESET Recovery Time 1 µs

Input Test Waveforms and Output Test Load

Measurement Levels DEVICE
UNDER
AC 2.4V AC
2.0 TEST
DRIVING MEASUREMENT
30 pF
LEVELS 0.8 LEVEL
0.45V

tR, tF < 5 ns (10% to 90%)

7
AC Waveforms
Two different timing diagrams are shown below. Waveform times for the SI signal are referenced to the low-to-high
1 shows the SCK signal being low when CS makes a high- transition on the SCK signal.
to-low transition, and Waveform 2 shows the SCK signal Waveform 1 shows timing that is also compatible with SPI
being high when CS makes a high-to-low transition. Both Mode 0, and Waveform 2 shows timing that is compatible
waveforms show valid timing diagrams. The setup and hold with SPI Mode 3.
Waveform 1 – Inactive Clock Polarity Low
tCS
CS

tCSS tWH tWL tCSH

SCK

tV tHO tDIS
HIGH IMPEDANCE HIGH IMPEDANCE
SO VALID OUT

tSU tH

SI VALID IN

Waveform 2 – Inactive Clock Polarity High

tCS
CS

tCSS tWL tWH tCSH

SCK

tV tHO tDIS
HIGH Z HIGH IMPEDANCE
SO VALID OUT

tSU tH

SI VALID IN

8 AT45DB011
 AT45DB011

Reset Timing (Inactive Clock Polarity Low Shown)

CS
tREC tCSS

SCK
tRST

RESET

HIGH IMPEDANCE HIGH IMPEDANCE

SO

SI

Command Sequence for Read/Write Operations (Except Status Register Read)

SI CMD 8 bits 8 bits 8 bits

MSB r r r r r r XX XXXX XXXX XXXX XXXX LSB

Reserved for Page Address Byte/Buffer Address

larger densities (PA8-PA0) (BA8-BA0/BFA8-BFA0)

Notes: 1. “r” designates bits reserved for larger densities.

2. It is recommended that “r” be a logical “0”.
3. For densities larger than 1M bit, the “r” bits become the most significant Page Address bit for the appropriate density.

9
Write Operations
The following block diagram and waveforms illustrate the various write sequences available.

FLASH MEMORY ARRAY

PAGE (264 BYTES)

BUFFER TO
MAIN MEMORY
PAGE PROGRAM

BUFFER (264 BYTES)

MAIN MEMORY PAGE
BUFFER PROGRAM THROUGH
WRITE BUFFER

I/O INTERFACE

SI

Main Memory Page Program through Buffer

· Completes writing into buffer
· Starts self-timed erase/program operation

CS

SI CMD r ···r , PA8-7 PA6-0, BFA8 BFA7-0 n n+1 Last Byte

Buffer Write
· Completes writing into buffer

CS

SI CMD X X···X, BFA8 BFA7-0 n n+1 Last Byte

Buffer to Main Memory Page Program

(Data from Buffer Programmed into Flash Page)
Starts self-timed erase/program operation

CS

SI CMD r ···r , PA8-7 PA6-0, X X

n = 1st byte written

Each transition represents
8 bits and 8 clock cycles n+1 = 2nd byte written

10 AT45DB011
 AT45DB011

Read Operations
The following block diagram and waveforms illustrate the various read sequences available.

FLASH MEMORY ARRAY

PAGE (264 BYTES)

MAIN MEMORY
PAGE TO
BUFFER

BUFFER (264 BYTES) MAIN MEMORY

PAGE READ
BUFFER
READ

I/O INTERFACE

SO

Main Memory Page Read

CS

SI CMD r ···r , PA8-7 PA6-0, BA8 BA7-0 X X X X

SO n n+1

Main Memory Page to Buffer Transfer (Data from Flash Page Read into Buffer)
Starts reading page data into buffer

CS

SI CMD r ···r , PA8-7 PA6-0, X X

SO

Buffer Read
CS

SI CMD X X···X, BFA8 BFA7-0 X

SO n n+1

n = 1st byte read

Each transition represents
8 bits and 8 clock cycles n+1 = 2nd byte read

11
Detailed Bit-Level Read Timing – Inactive Clock Polarity Low
Main Memory Page Read
CS

SCK 1 2 3 4 5 60 61 62 63 64 65 66 67

tSU
COMMAND OPCODE
SI 0 1 0 1 0 X X X X X

tV
DATA OUT
HIGH-IMPEDANCE
SO D7 D6 D5
MSB

Buffer Read
CS

SCK 1 2 3 4 5 36 37 38 39 40 41 42 43

tSU
COMMAND OPCODE
SI 0 1 0 1 0 X X X X X

tV
DATA OUT
HIGH-IMPEDANCE
SO D7 D6 D5
MSB

Status Register Read

CS

SCK 1 2 3 4 5 6 7 8 9 10 11 12 16 17

tSU
COMMAND OPCODE
SI 0 1 0 1 0 1 1 1

tV
STATUS REGISTER OUTPUT
HIGH-IMPEDANCE
SO D7 D6 D5 D1 D0 D7
MSB LSB MSB

12 AT45DB011
 AT45DB011

Detailed Bit-Level Read Timing – Inactive Clock Polarity High

Main Memory Page Read
CS

SCK 1 2 3 4 5 61 62 63 64 65 66 67 68

tSU
COMMAND OPCODE
SI 0 1 0 1 0 X X X X X

tV
DATA OUT
HIGH-IMPEDANCE
SO D7 D6 D5 D4
MSB

Buffer Read
CS

SCK 1 2 3 4 5 37 38 39 40 41 42 43 44

tSU
COMMAND OPCODE
SI 0 1 0 1 0 X X X X X

tV
DATA OUT
HIGH-IMPEDANCE
SO D7 D6 D5 D4
MSB

Status Register Read

CS

SCK 1 2 3 4 5 6 7 8 9 10 11 12 17 18

tSU
COMMAND OPCODE
SI 0 1 0 1 0 1 1 1

tV
STATUS REGISTER OUTPUT
HIGH-IMPEDANCE
SO D7 D6 D5 D4 D0 D7 D6
MSB LSB MSB

13
 Table 1
Main Memory Buffer Main Memory Page Main Memory Page Buffer
Page Read Read to Buffer Transfer to Buffer Compare Write
Opcode
52H 54H 53H 60H 84H
0 0 0 0 1
1 1 1 1 0
0 0 0 1 0
1 1 1 0 0
0 0 0 0 0
0 1 0 0 1
1 0 1 0 0
0 0 1 0 0
r X r r X
r X r r X
r X r r X
r X r r X
r X r r X
r X r r X
PA8 X PA8 PA8 X
PA7 X PA7 PA7 X
PA6 X PA6 PA6 X
PA5 X PA5 PA5 X
PA4 X PA4 PA4 X
PA3 X PA3 PA3 X
PA2 X PA2 PA2 X
PA1 X PA1 PA1 X
PA0 X PA0 PA0 X
BA8 BFA8 X X BFA8
BA7 BFA7 X X BFA7
BA6 BFA6 X X BFA6
BA5 BFA5 X X BFA5
BA4 BFA4 X X BFA4
BA3 BFA3 X X BFA3
BA2 BFA2 X X BFA2
BA1 BFA1 X X BFA1
BA0 BFA0 X X BFA0
X X
X X
X (Don’t Care)
X X
r (reserved bits)
X X
X X
X X
X X
X X
•
•
•
X (64th bit)

14 AT45DB011
 AT45DB011

Table 2
Buffer to
Buffer to Main Memory
Main Memory Page Program Main Memory Auto Page
Page Program without Built-In Page Block Page Program Rewrite Status
with Built-In Erase Erase Erase Erase Through Buffer Through Buffer Register
Opcode
83H 88H 81H 50H 82H 58H 57H
1 1 1 0 1 0 0
0 0 0 1 0 1 1
0 0 0 0 0 0 0
0 0 0 1 0 1 1
0 1 0 0 0 1 0
0 0 0 0 0 0 1
1 0 0 0 1 0 1
1 0 1 0 0 0 1
r r r r r r
r r r r r r
r r r r r r
r r r r r r
r r r r r r
r r r r r r
PA8 PA8 PA8 PA8 PA8 PA8
PA7 PA7 PA7 PA7 PA7 PA7
PA6 PA6 PA6 PA6 PA6 PA6
PA5 PA5 PA5 PA5 PA5 PA5
PA4 PA4 PA4 PA4 PA4 PA4
PA3 PA3 PA3 PA3 PA3 PA3
PA2 PA2 PA2 X PA2 PA2
PA1 PA1 PA1 X PA1 PA1
PA0 PA0 PA0 X PA0 PA0
X X X X BFA8 X
X X X X BFA7 X
X X X X BFA6 X
X X X X BFA5 X
X X X X BFA4 X
X X X X BFA3 X
X X X X BFA2 X
X X X X BFA1 X
X X X X BFA0 X

X (Don’t Care)
r (reserved bits)

15
Figure 1. Algorithm for Programming or Reprogramming of the Entire Array Sequentially

START
provide address
and data

BUFFER WRITE
(84H)

MAIN MEMORY PAGE PROGRAM

(82H)

BUFFER to MAIN
MEMORY PAGE PROGRAM
(83H)

END

Notes: 1. This type of algorithm is used for applications in which the entire array is programmed sequentially, filling the array page-by-
page.
2. A page can be written using either a Main Memory Page Program operation or a Buffer Write operation followed by a Buffer
to Main Memory Page Program operation.
3. The algorithm above shows the programming of a single page. The algorithm will be repeated sequentially for each page
within the entire array.

16 AT45DB011
 AT45DB011

Figure 2. Algorithm for Randomly Modifying Data

START

provide address of
page to modify

MAIN MEMORY PAGE If planning to modify multiple

to BUFFER TRANSFER bytes currently stored within
(53H) a page of the Flash array

BUFFER WRITE
(84H)

MAIN MEMORY PAGE PROGRAM

(82H)

BUFFER to MAIN
MEMORY PAGE PROGRAM
(83H)

(2)
Auto Page Rewrite
(58H)

INCREMENT PAGE
(2)
ADDRESS POINTER

END

Notes: 1. To preserve data integrity, each page of a DataFlash

sector must be updated/rewritten at least once Sector Addressing
within every 10,000 cumulative page erase/program
operations within that sector. PA2-
PA8 PA7 PA6 PA5 PA4 PA3 PA0 Sector
2. A Page Address Pointer must be maintained to indi-
cate which page is to be rewritten. The Auto Page 0 0 0 0 0 0 X 0
Rewrite command must use the address specified
by the Page Address Pointer. 0 X X X X X X 1

3. Other algorithms can be used to rewrite portions of 1 X X X X X X 2

the Flash array. Low power applications may choose
to wait until 10,000 cumulative page erase/program
operations have accumulated before rewriting all
pages of the sector. See application note AN-4
(“Using Atmel’s Serial DataFlash”) for more details.

17
Ordering Information
ICC (mA)
fSCK (MHz) Active Standby Ordering Code Package Operation Range
13 10 0.01 AT45DB011-JC 32J Commercial
AT45DB011-SC 8S2 (0°C to 70°C)
AT45DB011-XC 14X
13 10 0.01 AT45DB011-JI 32J Industrial
AT45DB011-SI 8S2 (-40°C to 85°C)
AT45DB011-XI 14X

Package Type
32J 32-Lead, Plastic J-Leaded Chip Carrier (PLCC)
8S2 8-Lead, 0.210" Wide, Plastic Gull Wing Small Outline (EIAJ SOIC)
14X 14-Lead, 0.170" Wide, Plastic Thin Shrink Small Outline Package (TSSOP)

18 AT45DB011
 AT45DB011

Packaging Information
32J, 32-Lead, Plastic J-Leaded Chip Carrier (PLCC) 8S2, 8-Lead, 0.210" Wide, Plastic Gull Wing Small
Dimensions in Inches and (Millimeters) Outline (EIAJ SOIC)
JEDEC STANDARD MS-016 AE Dimensions in Inches and (Millimeters)

.045(1.14) X 45° PIN NO. 1 .025(.635) X 30° - 45° .020 (.508)

.012(.305) .012 (.305)
IDENTIFY
.008(.203)

.530(13.5) .213 (5.41) .330 (8.38)

.553(14.0)
.490(12.4) .205 (5.21) .300 (7.62)
.032(.813) .547(13.9) PIN 1
.595(15.1) .021(.533)
.026(.660)
.585(14.9) .013(.330)
.050 (1.27) BSC
.050(1.27) TYP .030(.762)
.300(7.62) REF .015(3.81)
.430(10.9) .095(2.41) .212 (5.38)
.390(9.90) .203 (5.16)
.060(1.52)
.080 (2.03)
AT CONTACT .140(3.56) .070 (1.78)
POINTS .120(3.05)

.013 (.330)
.004 (.102)
.022(.559) X 45° MAX (3X)
0
.453(11.5) 8
REF .010 (.254)
.447(11.4) .007 (.178)
.495(12.6)
.035 (.889)
.485(12.3) .020 (.508)

14X, 14-Lead, 0.170" Wide, Thin Shrink Small

Outline Package (TSSOP)
Dimensions in Millimeters and (Inches)*

INDEX MARK
PIN
1

4.50 (.177) 6.50 (.256)

4.30 (.169) 6.25 (.246)

5.10 (.201)
4.90 (.193) 1.20 (.047) MAX

.650 (.026) BSC

0.15 (.006) SEATING
0.30 (.012) 0.05 (.002) PLANE
0.19 (.007)

0 0.20 (.008)
REF 0.09 (.004)
8

0.75 (.030)
0.45 (.018)

*Controlling dimension: millimeters

19