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One-instruction set computer

A one-instruction set computer (OISC), sometimes called an ultimate reduced instruction set
computer (URISC), is an abstract machine that uses only one instruction – obviating the need for
a machine language opcode.[1][2][3] With a judicious choice for the single instruction and given
infinite resources, an OISC is capable of being a universal computer in the same manner as
traditional computers that have multiple instructions.[2]: 55 OISCs have been recommended as
aids in teaching computer architecture[1]: 327 [2]: 2 and have been used as computational models in
structural computing research.[3] The first carbon nanotube computer is a 1-bit one-instruction
set computer (and has only 178 transistors).[4]

Machine architecture

In a Turing-complete model, each memory location can store an arbitrary integer, and –
depending on the model – there may be arbitrarily many locations. The instructions themselves
reside in memory as a sequence of such integers.

There exists a class of universal computers with a single instruction based on bit manipulation
such as bit copying or bit inversion. Since their memory model is finite, as is the memory
structure used in real computers, those bit manipulation machines are equivalent to real
computers rather than to Turing machines.[5]

Currently known OISCs can be roughly separated into three broad categories:

Bit-manipulating machines

Transport triggered architecture machines

Arithmetic-based Turing-complete machines

Bit-manipulating machines

Bit-manipulating machines are the simplest class.

FlipJump

The FlipJump (https://esolangs.org/wiki/FlipJump) machine has 1 instruction, a;b - flips the bit
a, then jumps to b. This is the most primitive OISC, but it's still useful. It can successfully do
Math/Logic calculations, branching, pointers, and calling functions with the help of its standard
library.

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BitBitJump

A bit copying machine,[5] called BitBitJump, copies one bit in memory and passes the execution
unconditionally to the address specified by one of the operands of the instruction. This process
turns out to be capable of universal computation (i.e. being able to execute any algorithm and to
interpret any other universal machine) because copying bits can conditionally modify the code
that will be subsequently executed.

Toga computer

Another machine, called the Toga Computer (https://esolangs.org/wiki/TOGA_computer) ,

inverts a bit and passes the execution conditionally depending on the result of inversion. The
unique instruction is TOGA(a,b) which stands for TOGgle a And branch to b if the result of the
toggle operation is true.

Multi-bit copying machine

Similar to BitBitJump, a multi-bit copying machine copies several bits at the same time. The
problem of computational universality is solved in this case by keeping predefined jump tables in
the memory.

Transport triggered architecture

Transport triggered architecture (TTA) is a design in which computation is a side effect of data
transport. Usually, some memory registers (triggering ports) within common address space
perform an assigned operation when the instruction references them. For example, in an OISC
using a single memory-to-memory copy instruction, this is done by triggering ports that perform
arithmetic and instruction pointer jumps when written to.

Arithmetic-based Turing-complete machines

Arithmetic-based Turing-complete machines use an arithmetic operation and a conditional jump.

Like the two previous universal computers, this class is also Turing-complete. The instruction
operates on integers which may also be addresses in memory.

Currently there are several known OISCs of this class, based on different arithmetic operations:

addition (addleq, add and branch if less than or equal to zero)[6]

decrement (DJN, Decrement and branch (Jump) if Nonzero)[7]

increment (P1eq, Plus 1 and branch if equal to another value)[8]

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subtraction (subleq, subtract and branch if less than or equal to zero)[9][10]

positive subtraction when possible, else branch (Arithmetic machine)[11]

Instruction types

Common choices for the single instruction are:

Subtract and branch if less than or equal to zero

Subtract and branch if negative

Subtract if positive else branch

Reverse subtract and skip if borrow

Move (used as part of a transport triggered architecture)[12]

Subtract and branch if non zero (SBNZ a, b, c, destination)

Cryptoleq (heterogeneous encrypted and unencrypted computation)

Only one of these instructions is used in a given implementation. Hence, there is no need for an
opcode to identify which instruction to execute; the choice of instruction is inherent in the design
of the machine, and an OISC is typically named after the instruction it uses (e.g., an SBN
OISC,[2]: 41 the SUBLEQ language,[3]: 4 etc.). Each of the above instructions can be used to
construct a Turing-complete OISC.

This article presents only subtraction-based instructions among those that are not transport
triggered. However, it is possible to construct Turing complete machines using an instruction
based on other arithmetic operations, e.g., addition. For example, one variation known as DLN
(Decrement and jump if not zero) has only two operands and uses decrement as the base
operation. For more information see Subleq derivative languages [1] (http://esolangs.org/wiki/Su
bleq) .

Subtract and branch if not equal to zero

The SBNZ a, b, c, d instruction ("subtract and branch if not equal to zero") subtracts the
contents at address a from the contents at address b, stores the result at address c, and then, if
the result is not 0, transfers control to address d (if the result is equal to zero, execution proceeds
to the next instruction in sequence).[3]

Subtract and branch if less than or equal to zero

The subleq instruction ("subtract and branch if less than or equal to zero") subtracts the contents
at address a from the contents at address b, stores the result at address b, and then, if the result
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is not positive, transfers control to address c (if the result is positive, execution proceeds to the
next instruction in sequence).[3]: 4–7 Pseudocode:

Instruction subleq a, b, c
Mem[b] = Mem[b] - Mem[a]
if (Mem[b] ≤ 0)
goto c

Conditional branching can be suppressed by setting the third operand equal to the address of
the next instruction in sequence. If the third operand is not written, this suppression is implied.

A variant is also possible with two operands and an internal accumulator, where the accumulator
is subtracted from the memory location specified by the first operand. The result is stored in
both the accumulator and the memory location, and the second operand specifies the branch
address:

Instruction subleq2 a, b
Mem[a] = Mem[a] - ACCUM
ACCUM = Mem[a]
if (Mem[a] ≤ 0)
goto b

Although this uses only two (instead of three) operands per instruction, correspondingly more
instructions are then needed to effect various logical operations.

Synthesized instructions

It is possible to synthesize many types of higher-order instructions using only the subleq
instruction.[3]: 9–10

Unconditional branch:

JMP c

subleq Z, Z, c

Addition can be performed by repeated subtraction, with no conditional branching; e.g., the
following instructions result in the content at location a being added to the content at location b:

ADD a, b

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subleq a, Z
subleq Z, b
subleq Z, Z

The first instruction subtracts the content at location a from the content at location Z (which is 0)
and stores the result (which is the negative of the content at a) in location Z. The second
instruction subtracts this result from b, storing in b this difference (which is now the sum of the
contents originally at a and b); the third instruction restores the value 0 to Z.

A copy instruction can be implemented similarly; e.g., the following instructions result in the
content at location b getting replaced by the content at location a, again assuming the content
at location Z is maintained as 0:

MOV a, b

subleq b, b
subleq a, Z
subleq Z, b
subleq Z, Z

Any desired arithmetic test can be built. For example, a branch-if-zero condition can be
assembled from the following instructions:

BEQ b, c

subleq b, Z, L1
subleq Z, Z, OUT
L1:
subleq Z, Z
subleq Z, b, c
OUT:
...

Subleq2 can also be used to synthesize higher-order instructions, although it generally requires
more operations for a given task. For example, no fewer than 10 subleq2 instructions are
required to flip all the bits in a given byte:

NOT a

subleq2 tmp ; tmp = 0 (tmp = temporary register)

subleq2 tmp

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subleq2 one ; acc = -1

subleq2 a ; a' = a + 1
subleq2 Z ; Z = - a - 1
subleq2 tmp ; tmp = a + 1
subleq2 a ; a' = 0
subleq2 tmp ; load tmp into acc
subleq2 a ; a' = - a - 1 ( = ~a )
subleq2 Z ; set Z back to 0

Emulation

The following program (written in pseudocode) emulates the execution of a subleq-based OISC:

int memory[], program_counter, a, b, c

program_counter = 0
while (program_counter >= 0):
a = memory[program_counter]
b = memory[program_counter+1]
c = memory[program_counter+2]
if (a < 0 or b < 0):
program_counter = -1
else:
memory[b] = memory[b] - memory[a]
if (memory[b] > 0):
program_counter += 3
else:
program_counter = c

This program assumes that memory[] is indexed by nonnegative integers. Consequently, for a
subleq instruction (a, b, c), the program interprets a < 0, b < 0, or an executed branch to c <
0 as a halting condition. Similar interpreters written in a subleq-based language (i.e., self-
interpreters, which may use self-modifying code as allowed by the nature of the subleq
instruction) can be found in the external links below.

A general purpose SMP-capable 64-bit operating system called Dawn OS has been implemented
in an emulated Subleq machine. The OS contains a C-like compiler. Some memory areas in the
virtual machine are used for peripherals like the keyboard, mouse, hard drives, network card, etc.
Basic applications written for it include a media player, painting tool, document reader and
scientific calculator.[13]

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A 32-bit Subleq computer with a graphic display and a keyboard called Izhora has been
constructed by Yoel Matveyev as a large cellular automation pattern.[14][15]

Compilation

There is a compiler called Higher Subleq written by Oleg Mazonka that compiles a simplified C
program into subleq code.[16]

Subtract and branch if negative

The subneg instruction ("subtract and branch if negative"), also called SBN, is defined similarly to
subleq:[2]: 41, 51–52

Instruction subneg a, b, c
Mem[b] = Mem[b] - Mem[a]
if (Mem[b] < 0)
goto c

Conditional branching can be suppressed by setting the third operand equal to the address of
the next instruction in sequence. If the third operand is not written, this suppression is implied.

Synthesized instructions

It is possible to synthesize many types of higher-order instructions using only the subneg
instruction. For simplicity, only one synthesized instruction is shown here to illustrate the
difference between subleq and subneg.

Unconditional branch:[2]: 88–89

JMP c

subneg POS, Z, c

where Z and POS are locations previously set to contain 0 and a positive integer, respectively;

Unconditional branching is assured only if Z initially contains 0 (or a value less than the integer
stored in POS). A follow-up instruction is required to clear Z after the branching, assuming that
the content of Z must be maintained as 0.

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subneg4

A variant is also possible with four operands – subneg4. The reversal of minuend and subtrahend
eases implementation in hardware. The non-destructive result simplifies the synthetic
instructions.

Instruction subneg s, m, r, j
(* subtrahend, minuend, result and jump addresses *)
Mem[r] = Mem[m] - Mem[s]
if (Mem[r] < 0)
goto j

Arithmetic machine

In an attempt to make Turing machine more intuitive, Z. A. Melzak consider the task of
computing with positive numbers. The machine has an infinite abacus, an infinite number of
counters (pebbles, tally sticks) initially at a special location S. The machine is able to do one
operation:

Take from location X as many counters as there are in location Y and transfer
them to location Z and proceed to instruction y.

If this operation is not possible because there is not enough counters in Y, then
leave the abacus as it is and proceed to instruction n. [17]

In order to keep all numbers positive and mimic a human operator computing on a real world
abacus, the test is performed before any subtraction. Pseudocode:

Instruction melzak X, Y, Z, n, y
if (Mem[Y] < Mem[X])
goto n
Mem[X] -= Mem[Y]
Mem[Z] += Mem[Y]
goto y

After giving a few programs: multiplication, gcd, computing the n-th prime number,
representation in base b of an arbitrary number, sorting in order of magnitude, Melzak shows
explicitly how to simulate an arbitrary Turing machine on his arithmetic machine.

MUL p, q

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multiply:
melzak P, ONE, S, stop ; Move 1 counter from P to S. If
not possible, move to stop.
melzak S, Q, ANS, multiply, multiply ; Move q counters from S to ANS.
Move to the first instruction.
stop:

where the memory location P is p, Q is q, ONE is 1, ANS is initially 0 and at the end pq, and S is a
large number.

He mentions that it can easily be shown using the elements of recursive functions that every
number calculable on the arithmetic machine is computable. A proof of which was given by
Lambek[18] on an equivalent two instruction machine : X+ (increment X) and X− else T
(decrement X if it not empty, else jump to T).

Reverse subtract and skip if borrow

In a reverse subtract and skip if borrow (RSSB) instruction, the accumulator is subtracted from the
memory location and the next instruction is skipped if there was a borrow (memory location was
smaller than the accumulator). The result is stored in both the accumulator and the memory
location. The program counter is mapped to memory location 0. The accumulator is mapped to
memory location 1.[2]

Instruction rssb x
ACCUM = Mem[x] - ACCUM
Mem[x] = ACCUM
if (ACCUM < 0)
goto PC + 2

Example

To set x to the value of y minus z:

# First, move z to the destination location x.

RSSB temp # Three instructions required to clear acc, temp [See Note 1]
RSSB temp
RSSB temp
RSSB x # Two instructions clear acc, x, since acc is already clear
RSSB x

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RSSB y # Load y into acc: no borrow

RSSB temp # Store -y into acc, temp: always borrow and skip
RSSB temp # Skipped
RSSB x # Store y into x, acc
# Second, perform the operation.
RSSB temp # Three instructions required to clear acc, temp
RSSB temp
RSSB temp
RSSB z # Load z
RSSB x # x = y - z [See Note 2]

[Note 1] If the value stored at "temp" is initially a negative value and the instruction that
executed right before the first "RSSB temp" in this routine borrowed, then four "RSSB temp"
instructions will be required for the routine to work.

[Note 2] If the value stored at "z" is initially a negative value then the final "RSSB x" will be
skipped and thus the routine will not work.

Transport triggered architecture

A transport triggered architecture uses only the move instruction, hence it was originally called a
"move machine". This instruction moves the contents of one memory location to another
memory location combining with the current content of the new location:[2]: 42 [19]

Instruction movx a, b (also written a -> b)

OP = GetOperation(Mem[b])
Mem[b] := OP(Mem[a], Mem[b])

The operation performed is defined by the destination memory cell. Some cells are specialized in
addition, some other in multiplication, etc. So memory cells are not simple store but coupled
with an arithmetic logic unit (ALU) setup to perform only one sort of operation with the current
value of the cell. Some of the cells are control flow instructions to alter the program execution
with jumps, conditional execution, subroutines, if-then-else, for-loop, etc...

A commercial transport triggered architecture microcontroller has been produced called MAXQ,
which hides the apparent inconvenience of an OISC by using a "transfer map" that represents all
possible destinations for the move instructions.[20]

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Cryptoleq

Cryptoleq processor made at NYU

Abu Dhabi

Cryptoleq[21] is a language consisting of one eponymous instruction, is capable of performing

general-purpose computation on encrypted programs and is a close relative to Subleq.
Cryptoleq works on continuous cells of memory using direct and indirect addressing, and
performs two operations O1 and O2 on three values A, B, and C:

Instruction cryptoleq a, b, c
Mem[b] = O1(Mem[a], Mem[b])
if O2(Mem[b]) ≤ 0
IP = c
else
IP = IP + 3

where a, b and c are addressed by the instruction pointer, IP, with the value of IP addressing a, IP
+ 1 point to b and IP + 2 to c.

In Cryptoleq operations O1 and O2 are defined as follows:

The main difference with Subleq is that in Subleq, O1(x,y) simply subtracts y from x and O2(x)
equals to x. Cryptoleq is also homomorphic to Subleq, modular inversion and multiplication is
homomorphic to subtraction and the operation of O2 corresponds the Subleq test if the values
were unencrypted. A program written in Subleq can run on a Cryptoleq machine, meaning
backwards compatibility. Cryptoleq though, implements fully homomorphic calculations and
since the model is be able to do multiplications. Multiplication on an encrypted domain is
assisted by a unique function G that is assumed to be difficult to reverse engineer and allows re-
encryption of a value based on the O2 operation:

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where is the re-encrypted value of y and is encrypted zero. x is the encrypted value of a
variable, let it be m, and equals .

The multiplication algorithm is based on addition and subtraction, uses the function G and does
not have conditional jumps nor branches. Cryptoleq encryption is based on Paillier cryptosystem.

See also

FRACTRAN

Minimal axioms for Boolean algebra

Register machine

Turing tarpit

Reduced instruction set computer

Complex instruction set computer

Zero instruction set computer

References

1. Mavaddat, F.; Parhami, B. (October 1988). "URISC: The Ultimate Reduced Instruction Set Computer" (htt
p://www.ece.ucsb.edu/~parhami/pubs_folder/parh88-ijeee-ultimate-risc.pdf) (PDF). International
Journal of Electrical Engineering Education. Manchester University Press. 25 (4): 327–334.
doi:10.1177/002072098802500408 (https://doi.org/10.1177%2F002072098802500408) .
S2CID 61797084 (https://api.semanticscholar.org/CorpusID:61797084) . Retrieved 2010-10-04. This
paper considers "a machine with a single 3-address instruction as the ultimate in RISC design (URISC)".
Without giving a name to the instruction, it describes a SBN OISC and its associated assembly
language, emphasising that this is a universal (i.e., Turing-complete) machine whose simplicity makes it
ideal for classroom use.

2. Gilreath, William F.; Laplante, Phillip A. (2003). Computer Architecture: A Minimalist Perspective (https://
web.archive.org/web/20090613042342/http://www.caamp.info/) . Springer Science+Business Media.
ISBN 978-1-4020-7416-5. Archived from the original (http://www.caamp.info) on 2009-06-13.
Intended for researchers, computer system engineers, computational theorists and students, this book
provides an in-depth examination of various OISCs, including SBN and MOVE. It attributes SBN to W. L.
van der Poel (1956).

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3. Nürnberg, Peter J.; Wiil, Uffe K.; Hicks, David L. (September 2003), "A Grand Unified Theory for
Structural Computing" (https://books.google.com/books?id=uxjigT31ns4C&pg=PA1) ,
Metainformatics: International Symposium, MIS 2003 (http://www.informatik.uni-trier.de/~ley/db/conf/
metainformatics/metainformatics2003.html) , Graz, Austria: Springer Science+Business Media, pp. 1–
16, ISBN 978-3-540-22010-7 This research paper focusses entirely on a SUBLEQ OISC and its
associated assembly language, using the name SUBLEQ for "both the instruction and any language
based upon it".

4. "First computer made of carbon nanotubes is unveiled" (https://www.bbc.co.uk/news/science-environ

ment-24232896) . BBC. 26 September 2013. Retrieved 26 September 2013.

5. Oleg Mazonka, "Bit Copying: The Ultimate Computational Simplicity" (http://www.complex-systems.co

m/pdf/19-3-5.pdf) , Complex Systems Journal 2011, Vol 19, N3, pp. 263–285

6. "Addleq" (https://esolangs.org/wiki/Addleq) . Esolang Wiki. Retrieved 2017-09-16.

7. "DJN OISC" (https://esolangs.org/wiki/DJN_OISC) . Esolang Wiki. Retrieved 2017-09-16.

8. "P1eq" (https://esolangs.org/wiki/P1eq) . Esolang Wiki. Retrieved 2017-09-16.

9. Mazonka, Oleg (October 2009). "SUBLEQ" (https://web.archive.org/web/20170629094925/http://mazo

nka.com/subleq/index.html) . Archived from the original (http://mazonka.com/subleq/index.html)
on 2017-06-29. Retrieved 2017-09-16.

10. "Subleq" (https://esolangs.org/wiki/Subleq) . Esolang Wiki. Retrieved 2017-09-16.

11. Z. A. Melzak (1961). "An informal arithmetical approach to computability and computation" (https://do
i.org/10.4153%2FCMB-1961-031-9) . Canadian Mathematical Bulletin. 4 (3): 279–293.
doi:10.4153/CMB-1961-031-9 (https://doi.org/10.4153%2FCMB-1961-031-9) .

12. xoreaxeaxeax. "movfuscator" (https://github.com/xoreaxeaxeax/movfuscator) . GitHub. Retrieved

2022-11-12.

13. "Dawn for SUBLEQ" (http://users.atw.hu/gerigeri/DawnOS/index.html) .

14. https://www.gazetaeao.ru/zanimatelnaya-nauka-vchera-segodnya-zavtra/ A Russian article on

popular science in Birobidzhaner Shtern with a brief discussion of Yoel Matveyev's Izhora computer

15. https://habr.com/ru/post/584596/ A description of the virtual computer Izhora on Habr (in Russian)

16. Oleg Mazonka A Simple Multi-Processor Computer Based on Subleq (https://arxiv.org/abs/1106.259

3)

17. Z. A. Melzak (2018-11-20) [1961-09]. "An informal arithmetical approach to computability and
computation" (https://doi.org/10.4153%2FCMB-1961-032-6) . Canadian Mathematical Bulletin. 4 (3):
279–293. doi:10.4153/CMB-1961-032-6 (https://doi.org/10.4153%2FCMB-1961-032-6) .

18. J. Lambek (2018-11-20) [1961-09]. "How to program an infinite abacus" (https://doi.org/10.4153%2FC

MB-1961-032-6) . Canadian Mathematical Bulletin. 4 (3): 295–302. doi:10.4153/CMB-1961-032-6 (htt
ps://doi.org/10.4153%2FCMB-1961-032-6) .

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19. Jones, Douglas W. (June 1988). "The Ultimate RISC" (http://www.cs.uiowa.edu/~jones/arch/risc/) .

ACM SIGARCH Computer Architecture News. New York: ACM. 16 (3): 48–55. doi:10.1145/48675.48683 (h
ttps://doi.org/10.1145%2F48675.48683) . S2CID 9481528 (https://api.semanticscholar.org/CorpusID:9
481528) . Retrieved 2010-10-04. "Reduced instruction set computer architectures have attracted
considerable interest since 1980. The ultimate RISC architecture presented here is an extreme yet
simple illustration of such an architecture. It has only one instruction, move memory to memory, yet it
is useful."

20. Catsoulis, John (2005), Designing embedded hardware (2 ed.), O'Reilly Media, pp. 327–333, ISBN 978-0-
596-00755-3

21. Mazonka, Oleg; Tsoutsos, Nektarios Georgios; Maniatakos, Michail (2016), "Cryptoleq: A
Heterogeneous Abstract Machine for Encrypted and Unencrypted Computation", IEEE Transactions on
Information Forensics and Security, 11 (9): 2123–2138, doi:10.1109/TIFS.2016.2569062 (https://doi.org/1
0.1109%2FTIFS.2016.2569062) , S2CID 261387 (https://api.semanticscholar.org/CorpusID:261387)

External links

Subleq on the esoteric programming languages wiki (http://esolangs.org/wiki/Subleq) –

interpreters, compilers, examples and derivative languages

Reductio ad absurdum (https://www.youtube.com/watch?v=NmWwRmvjAE8) on YouTube by

Christopher Domas

Laboratory subleq computer (https://web.archive.org/web/20151121172708/http://www.sccs.s

warthmore.edu/users/06/adem/engin/e25/finale/) – FPGA implementation using VHDL

The Retrocomputing Museum (http://catb.org/~esr/retro/#emulators) – SBN emulator and

sample programs

Laboratory SBN computer (http://bitstuff.blogspot.com/2007/02/subtract-and-branch-if-negat

ive.html) – implemented with 7400 series integrated circuits

RSSB on the esoteric programming languages wiki (http://esolangs.org/wiki/RSSB) –

interpreters and examples

Dr. Dobb's 32-bit OISC implementation (http://www.ddj.com/embedded/221800122?pgno=

1) – transport triggered architecture (TTA) on an FPGA using Verilog

Introduction to the MAXQ Architecture (http://www.maxim-ic.com/appnotes.cfm/appnote_nu

mber/3222) – includes transfer map diagram

OISC-Emulator (http://sourceforge.net/projects/oiscemulator) – graphical version

TrapCC (https://github.com/jbangert/trapcc) (recent Intel x86 MMUs are actually Turing-

complete OISCs.)

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Izhora (https://github.com/yoelmatveyev/Izhora) – Yoel Matveyev's Subleq computer built as

a cellular automation

SBN simulator (http://cs.drexel.edu/~bls96/oisc/) – simulator and design inspired by

CARDboard Illustrative Aid to Computation

One-bit Computing at 60 Hertz (http://laughtonelectronics.com/Arcana/One-bit%20computer/

One-bit%20computer.html) – intermediate between a computer and a state machine

The NOR Machine (https://demin.ws/blog/english/2010/04/06/modelling-a-cpu-with-only-one

-operation/) – info on building a CPU with only one Instruction

SUBLEQ eFORTH (https://github.com/howerj/subleq/) A complete Forth interpreter running

on the SUBLEQ OISC.

Cryptoleq (https://github.com/momalab/cryptoleq) – Cryptoleq resources repository

CAAMP (https://sites.google.com/site/comparchampsite/) – Computer Architecture A

Minimalist Perspective

SICO (https://alecdee.github.io/sico) – Single Instruction COmputer: a variant of SUBLEQ

using unsigned integers

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