Design Considerations for In-System Reprogrammable™

(ISR™) Programming of Cypress CPLDs

Introduction waveforms and provide the best solution to controlling trans-
™ ™
mission line effects.
The In-System Reprogrammable (ISR ) feature of Cypress
Complex Programmable Logic Devices (CPLDs) enables re- This note also discusses all issues related to programming
configurability of devices while soldered onto a system board. and reprogramming the devices in-system (i.e., while they are
A standard IEEE 1149.1 (JTAG) interface is available to facil- soldered onto a printed circuit board). These issues include:
itate device configuration as well as boundary scan opera- an explanation of the available ISR programming cables and
tions for straightforward prototyping, production program and ISR connections, using the ISR programming pins for both
test, field update, and general-purpose applications (note the functional logic and for programming, connecting ISR devices
FLASH370i™ family does not support boundary scan). The in a chain for programming as well as proper functional oper-
purpose of this application note is to detail applicable board ation.
design considerations and offer specific design guidance in For the purpose of this note, “ISR device” refers to any ISR-
order to simplify development of systems employing ISR ca- capable device family. Also, “Ultra37000(V)” refers to both 5V
pabilities. Ultra37000 and 3.3V Ultra37000V. This design consider-
The simplest method for integrating ISR functionality into a ations note complements other Cypress ISR application
system is to interface directly to a Cypress ISR PC cable. notes, which offer introductory or device-specific information.
Seamless PC control is provided by simply tying the ISR sig-
nals to an ISR header. While sections of this application note ISR Programming Pins
discuss specifics of the Cypress ISR PC cables, the design
considerations pertaining to CPLD family or board level is- The programming pins for the Delta39K, Quantum38K, and
sues are implementation-generic and are directly applicable PSI devices are standard JTAG signals: TDI, TDO, TMS, and
with any method of In-System Reprogrammable configura- TCK. Ultra37000(V) CPLDs include these pins, plus an addi-
tion, be it control via ISR PC cable, automated test equipment tional control pin called JTAGen in some device packages. For
(ATE), or embedded microprocessor. The guidelines dis- the FLASH370i family, the same pins are named SDI, SDO,
cussed herein are general and apply to any ISR interface SMODE, SCLK, and ISRen respectively. The reason for using
methodology. For example, proper ISR signal layout and ter- the standard JTAG naming convention for most ISR devices
mination practices should be followed to ensure good signal is that these families support Boundary Scan testing and are
integrity and reprogramming reliability. This involves aware- compliant with the IEEE 1149.1 (JTAG) standard. The pro-
ness of device drive capabilities and transmission line effects gramming interface for the FLASH370i devices also complies
pertaining to critical ISR signal distribution. with most of the standard; however, these devices do not sup-
port boundary scan so the names were changed from the
The In-System Reprogrammable feature is available in Cy- standard JTAG naming convention to prevent misleading the
press’s Delta39K™, Quantum38K™, Ultra37000(V)™, and user. For the purposes of this note the JTAG pin nomenclature
FLASH370i CPLD families, as well as Cypress’s Programma- is used.
ble Serial Interface™ (PSI™) programmable PHY family. Differ-
ences between product families yield certain device-specific All ISR devices can be cascaded into a single chain for pro-
design considerations. For example, Delta39K, Quantum38K gramming purposes so that one programming source (such
and PSI devices all offer 3.3V, 2.5V, and 1.8V I/O standard as an ISR PC cable) can program all of the ISR devices on a
configurations for the ISR interface, whereas Ultra37000 of- board. The pins on an ISR device used for programming are:
fers 5V and 3.3V capability. Additionally, certain compact JTAGen, TDI, TDO, TMS, and TCK. Their names and func-
package options with the Ultra37000(V) and FLASH370i tions are defined below.
CPLDs allow dual-function ISR pins to switch between pro- TDI (SDI) – Data Input
gramming and regular I/O modes. These device-specific dif-
ferences and their implications on ISR chain configuration are During programming, this pin provides the serial data input to
discussed herein. the device.
This application note discusses transmission line effects that TDO (SDO) – Data Output
can arise from the ISR chain, which can cause signal integrity
problems, and provides suggestions for trace layout to mini- During programming, this pin provides the serial data output
mize these effects. Transmission line effects are inherent in from the device.
the ISR programming set-up due to impedance mismatching TCK (SCLK) – Clock
between the ISR programming source (such as an ISR ca-
ble), traces and trace layout on the PCB, and ISR devices During programming, this pin is the clock input. TDI and TMS
themselves. Properly terminated discrete buffers on the PCB, are sampled on the rising edge of TCK, while TDO changes
while not required in most cases, produce the highest quality following the falling edge of TCK.

Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
November 9, 2001
 Design Considerations for ISR Programming of Cypress CPLDs

PC

TO PARALLEL PORT

ISR PROGRAMMING CABLE

TO 10–PIN CONNECTOR ON BOARD

Figure 1. ISR Programming Set-up using a PC

TMS (SMODE) – Mode Control useful for monitoring purposes or for user logic that controls
During programming, this is the mode control input that di- any dual-function ISR pins of specific Ultra37000(V) or
rects the Test Access Port (TAP) controller state machine con- FLASH370i devices, as discussed in Appendix A. If on-board
tained within the ISR interface on the device. logic uses this signal, ISR* should be pulled-up to VCC
through a pull-up resistor on the circuit board to handle the
JTAGen (ISRen) – Enables the 4-pin JTAG Interface case when no cable is attached.
This pin is present on packages of Ultra37000(V) or The ISR Programming Cables
FLASH370i devices where the JTAG pins share their function- The simplest method to program ISR devices is to use a PC
ality with I/O pins. Dual-mode device details are found in Ap- as shown in Figure 1. The ISR programming cable connects
pendix A. For the Ultra37000(V), when the JTAGen pin is at a the parallel port of the PC to a cable header on the user’s
TTL HIGH level the JTAG pin functionality is selected. When board where the ISR devices are soldered. The header on the
it is at a TTL LOW level the I/O pin functionality is selected. user’s board connects to traces that route to the JTAG pins on
For the FLASH370i devices the JTAG pin functionality is select- the ISR device itself. The ISR software runs on the PC and
ed when it is at a supervoltage of 12.0V and the I/O pin func- drives these pins on the board, through the cable and header,
tionality is selected when it is at a TTL LOW level. This func- to program the devices with the appropriate bitstream.
tional difference in the JTAGen pin for these two ISR device
families is important and is discussed later in this application Since each cable contains active components that buffer sig-
note. All other ISR device families do not use JTAGen. nals driven between the user’s board and the PC, the cable
must receive power from the user’s board. It is recommended
ISR* – Indicates Active ISR Operation Taking Place that the PC be powered-off prior to plugging in an ISR PC
This additional signal is not used by any CPLD device for cable.
programming. Rather, it is present on the ISR header to allow Table 1 shows the available Cypress ISR programming cables
the programming source (e.g., ISR PC cable) to signal to the and their appropriate usage.
user’s board when ISR operations are occurring. This can be
Table 1. Available ISR PC Programming Cables
Programming Cable Part Number Supported ISR Signal Voltages Supported Devices
C3ISR C3ISR.02 (rev. 0.02) 5V, 3.3V, 2.5V, 1.8V Delta39K, Quantum38K, PSI,
Ultra37000, Ultra37000V
UltraISR 37KISR.03 (rev. 0.03) 5V, 3.3V Delta39K, Quantum38K, PSI,
Ultra37000, Ultra37000V
ISRPCCABLE ISRPCCABLE.03A 5V FLASH370i, Ultra37000
(rev 0.03A) (with 12V supervoltage on ISRen) (Ultra37000V not supported)

2
 Design Considerations for ISR Programming of Cypress CPLDs

The C3ISR cable offers the most flexible choice of program- The ISRPCCABLE, on the other hand, is the only cable with
ming voltage and device support. Any selection of 5V, 3.3V, a built-in 5V-to-12V DC/DC converter to produce the 12V su-
2.5V, or 1.8V can power the cable (VCC of ISR connector pin), pervoltage to the ISRen pin required for FLASH370i program-
allowing TTL, LVTTL, LVCMOS, LVCMOS2, or LVCMOS18 ming, supplied by 5V from the user’s board. The schematic
ISR signal levels. The C3ISR cable is the recommended for the ISRPCCABLE, used for programming the FLASH370i
choice for ISR designs if the user does not need to program devices, is shown in Figure 4.
FLASH370i devices. A schematic of the C3ISR cable is shown The ISRPCCABLE allows programming of the FLASH370i and
in Figure 2. Ultra37000 device families (but not Ultra37000V). The ISR-
The UltraISR PC cable contains a simple buffer capable of 5V PCCABLE (revision 0.03A or greater) can be used to program
and 3.3V signaling. The UltraISR cable schematic is shown Ultra37000 devices because their JTAGen pin, if present on
in Figure 3. Both the C3ISR and UltraISRPCCABLE can be the selected package, is 12V tolerant. This means that the
used to program all ISR families at 3.3V or 5V levels, with the application of 12V on the Ultra37000’s JTAGen pin is equiva-
exception of FLASH370i devices (since these require a 12V lent to placing a TTL HIGH value on the pin.
supervoltage generated by the cable on the ISRen pin).

1 2 3 4

VCC_BOOST VCCIO

VCC

2
5.6k R6 R15 R25
10 20k
+ +

2
JP1 5.6k R7
L1 C6 C5
1 5.6k R8 DO3316P-103
D 14 D
5.6k R9 VCC_BOOST
2 U1 100uF 100uF VCC

1
15 1 16
I.C. I.C.
3 TDI_PAR 2 15
1

I.C. POUT C9 C10 C11

16 3 14
REF OUT 0.01uF 0.1uF 0.01uF
4 TMS_PAR 4 13
C4 CLK/SEL LX
17 5 12 D1
.22uF GND PGND VCC_BOOST
5 ISR*_PAR 6 11
I.C. FB
18 7 10 MBR0520L U4 VCC
/ONB I.C. 2 + +

2
6 8 9 C1 R26 1 8
ONA I.C. 9.1k C2 C7 IN OUT
19 C3 2 7
0.22uF

MAX1700 GND GND C17

7 3 6 +
GND GND 10uF
20 4 5
100uF 100uF .22uF /OFF SET
8 R16
1

21 1 MAX604CSA 1k
9 VCC VCCIO C8 0.1uF
R10
22 R32 0
4.7k GND VCCIO_clamped
10 U5 VCC
R31 0 (NP) R18
23 CONNECT GND PLANES U2A 1 24
GND GATE VCCIO
11 (ONE .020 TRACE) 1 2 23
G A1 B1 200k
C 24 18 TCK_3 R1 39 TCK_4 3 22 TCK_10PIN C
Y1 A2 B2
12 TCK_PAR 100 R19 TCK_2 2 16 4 21
A1 Y2 A3 B3 R13
25 4 14 TMS_3 R2 39 TMS_4 5 20 TMS_10PIN
A2 Y3 A4 B4 200
13 100 R20 TMS_2 6 12 TDI_3 R3 39 TDI_4 6 19 TDI_10PIN
A3 Y4 A5 B5
100 R21 TDI_2 8 ISR*_3 R4 39 ISR*_4 7 18 ISR*_10PIN
A4 A6 B6 VCCIO_clamped
PARALLEL PORT JTAGenable_3 R5 39 JTAGenable_4 8 17 JTAGen_10PIN
A7 B7 C14 C15
SN74HC244DW 9 16 C16 +
100 R22 ISR*_2 VCC A8 B8
R30 R29 10 15 D3 0.1uF 0.01uF
A9 B9
11 14 10uF
1k A10 B10
30 (NP) 12 13
A11 B11
3.9V ZENER (AZ23C3V9DICT-ND)
R14 SN74TVC3010
30 VCC

C12 C13 VCCIO

VCC
+VS

0.1uF 0.01uF
P2
1
8

U3
2
B U2B 3 B
2
19 4
7 G
9 5
3 Y1
11 7 6
A1 Y2
13 5 7
LT1719 A2 Y3
15 3 8
A3 Y4 R27
SHDN 6

5
4

17 9
A4
VCC 0 (NP) 10
GND
VEE

20 10 R28
VCC GND
VCCIO_clamped 0 10P HEADER
R12 R11 SN74LVC244A
C

20K
R23 1K
2.2k
Q1
B

2N2222A
R24
1.6k
E

A A

VCC D4
R17 D2

BAW56ZXCT-ND 51 OHM 1/8W LED

1 2 3 4

Figure 2. C3ISR Cable Schematic

3
 Design Considerations for ISR Programming of Cypress CPLDs

Dimension of the ISR Cables

The C3ISR programming cable consists of a six-foot IEEE-
1284 shielded cable attached to a blue transparent box con-
Parallel Port
Cable Head
User’s Board taining the drivers and voltage conversion circuitry. A short
one foot ribbon cable extending from this box attaches to the
5 volt HC244 CMOS Buffer ISR connector on the user’s board.
100 33 The UltraISR PC cable is a short one-foot ribbon cable with a
Data0(2) DA0 OA0

10k
TCK(4)
small PC board mounted inside the parallel port connector
10 pf
Data2(4)
100
DA1 OA1
33
TMS(2)
casing.
100
DA2 OA2
33 The ISRPCCABLE is a six-foot cable with one foot as a de-
Data1(3) TDI(6)
tachable, flexible 10-wire ribbon cable. The ribbon cable sec-
Ack(10)
100
OB3 DB3 TDO(9)
tion is connected to the 12V converter box at the end of a five-
foot cable.
1k
DB0 OB0
33
JTAGen(3)
The user may need a parallel port extension cable since there
1k
Data3(5) 2n3904-nd
may not be enough cable length from the parallel port on the
1k
PC to the circuit board. A high-performance IEEE-1284 cable
33
DB1 OB1 ISR*(5) extension is recommended for distances greater than six feet.
All ISR programming cables plug into the female parallel port
OB2 VCC(7)
PE(12) DB2
of the PC or the female end of an extension cable. However,
DA3 OA3 signal integrity problems may arise with long parallel cable
2.2uf tantalum
0.1uf
extensions.
/OEA /OEB
Connecting the ISR Cables to the Circuit Board
GND(23,24) GND(1,10)
To connect the cable to the system, a 10-pin, 2 x 5, boxed
Data4(6)
Port Sense
header male connector is mounted on the board. The ISR
Busy(11)
programming cable plugs into the boxed header. This boxed
header connector has a small opening in the box on one side
(the key) that allows the ISR programming cable to be
Figure 3. UltraISR Cable Schematic rev 0.03 plugged in one way only. The pins are on 0.100" centers. The
length of each pin is 0.230", and the pin cross-section is
0.025" x 0.025". This boxed header connector is available as
a straight-pin connector and as a right-angle connector. Ad-
Parallel Port Cable Head User Board
HCT244 CMOS buffer
ditionally, an open header can be used. Part numbers for two
compatible connectors are:
DA0 OA0
Data0(2) Sclk(4)
• DIGI-KEY part # S2012-05-ND
Data2(4)
DA1 OA1
Smode(2) (straight-pin connector)
DA2 OA2 • DIGI-KEY part # S2112-05-ND
Data1(3) SDI(6) (right-angle connector)
100 ohmsOB0 DB0
Ack(10) SDO(9) All ISR programming cables provided by Cypress have a fe-
male end which plugs into these ISR connectors installed on
ISR(5)
the user’s board. The position of the signal pins on the con-
DC/DC Converter nector is shown in Figure 5. The orientation of this figure is
+5.0V +12.0V such that the pin 1 location is the GND signal, which is located
+Vin +Vout ISRVPP(3) directly below the arrow on the female connector. The notch
D
DA3 OA3 G
S
PICO on the female connector is located near the ISR* signal, as
DATA3(5) 5GR12S
Si9433DY
-Vin -Vout
shown. If the right-angle connector is used, make sure the
raised key of the cable connector faces up so that it can be
0.01uf
20k
plugged into the boxed header without PCB interference.
OB1 DB1
PE(12) VCC(7)
OEA OEB 0.1 µf
PIN 1
GND(23) GND(1)
GND(24) GND(10)
TDO VCC ISR* JTAGen GND
Data7(9)
Port Sense
Error(15)
GND NC TDI TCK TMS

Figure 5. Layout of ISR Connector for PC Cable on Board

Figure 4. ISRPCCABLE Cable Schematic rev 0.03 Top View

4
 Design Considerations for ISR Programming of Cypress CPLDs

To program a single ISR device using any ISR programming With this configuration, it is recommended to place a 10-nF
cable described here, route the TDI, TDO, TCK, TMS, and capacitor located at the 10-pin header connector on the circuit
JTAGen pins from the cable connector to the TDI, TDO, TCK, board from the ISRen pin to ground. If the ISR cable is hot-
TMS, and JTAGen (if present on the package) pins of the ISR socket connected to the user’s board, which is not recom-
device, respectively. If no ISR devices use JTAGen, this pin mended, then this capacitor insures that a proper, slow ramp
can float. Multiple devices can be programmed in a single ISR up to 12V is applied to the devices to be programmed under
programming chain, explained later in this application note. all operating conditions, with no risk of damage to the ISRen
For multiple devices in the chain, the TDI and TDO pins are pin. Since the ISR cable could easily be hot-socket connected
connected in a serial chain such that the TDO of the first de- by accident, it is advisable and simple to incorporate this de-
vice in the chain connects to the TDI of the next device in the coupling capacitor. Again, this only applies if the
chain. The TDO of the last device in the chain then returns ISRPCCABLE is used.
back to the 10-pin header TDO pin.
In addition to these programming pins, there is an additional Simple ISR Device Cascading
signal available from the cable called ISR*. The purpose of You can cascade many ISR devices in a system. That is, you
this signal is to allow the user to monitor when ISR operations can daisy-chain the devices together and connect their pro-
are in progress. If ISR* is a logic LOW, it indicates that gramming pins in such a way that all devices can be pro-
JTAGen is asserted (at 12V supervoltage for FLASH370i de- grammed from a single connection to the ISR programming
vices) and ISR operations, such as programming, are in pro- source.
cess on the board. If ISR* is a logic HIGH, it indicates JTAGen
is 0V and no ISR operations are being performed. The ISR* To do this, simply tie all of the TCK and TMS pins (and
pin is needed when using the JTAG/IO pins in both ISR JTAGen if present) of each device to the corresponding pins
(JTAG) and functional (IO) modes, as supported by certain of the ISR connector. You then connect the TDI pin from the
packages of the Ultra37000 and FLASH370i families. It is used connector to the TDI pin of the first device in the chain, then
by on-board logic to determine when the JTAG signals should connect the TDO output of that device to the TDI input of the
be enabled and other driving signals to the ISR device should next device in the chain, and so forth, until you finally connect
be placed in the high-impedance state (three-stated). This is the TDO output of the last device in the chain to the TDO pin
discussed in detail in Appendix A. When the ISR cable is con- of the cable connector or other programming source (see Fig-
nected, this signal is driven appropriately to a HIGH or LOW ure 6).
level. When the cable is disconnected, the ISR* signal must
be pulled up on the circuit board, using a pull-up resistor to Cascading With Other IEEE 1149.1-Compliant Devices
the VCC pin of the ISR connector to indicate to the board that Other vendor IEEE 1149.1-compliant devices can be included
no ISR operation is in progress. in the chain. The ISR programming software will load the non-
There are three other connection points on the cable and ca- Cypress device’s instruction register with the proper BYPASS
ble header: VCC, GND, and NC. VCC connects to the VCC instruction.
plane on the board containing the ISR devices. It supplies
power to the active components within the ISR cable. This is
necessary for any ISR programming cable to be able to buffer Other JTAG
ISR Device ISR Device
JTAG signals or translate voltage levels. On the UltraISR PC Compliant
cable, VCC simply supplies power to the buffer in the cable for Device
the JTAG signals. On the C3ISR cable, VCC from the user’s TDI TDI TDO TDI TDO TDI TDO
board supplies power to the buffer and voltage translation log-
ic of the cable. GND provides a common ground reference TMS TCK TMS TCK TMS TCK
between the board and the ISR programming cable. NC is a
“no connect” pin and is not used. For boards containing both TCK
5V and 3.3V, it is recommended to connect 5V to the VCC TMS
header pin instead of 3.3V. This doesn’t apply for Delta39K,
Quantum38K, or PSI devices, which cannot tolerate 5V. TDO

Connecting the ISRPCCABLE to the Board Figure 6. Simple Cascading of ISR Devices
Since the ISRPCCABLE provides a high voltage (12V) to the
device, it is recommended that the ISR cable be plugged into Cascading Ultra37000 and FLASH370i ISR Devices
the PC and the customer’s board before power is applied to In addition to the optional external circuitry required to take
the board. (This is not as important for the C3ISR or UltraISR advantage of dual JTAG/IO functions per dual-mode ISR de-
PC cables since there are no 12V signals generated in the vice, the JTAGen pin has slightly different functionality be-
cables.) Once the cable is connected, the user can power up tween the FLASH370i and the Ultra37000 families. For details
the board. This assures a normal slew rate on the ISRen pin on Ultra37000 and FLASH370i cascading, see Appendix B.
for all possible conditions. It is also recommended that the
user run the ISR software after the cable is plugged into the
user’s board and PC parallel port. This allows the software to
correctly set the ISR pins to their appropriate initialized state
on the parallel port of the PC. All of the ISR signals are buff-
ered in the ISR cables and are permanently enabled.

5
 Design Considerations for ISR Programming of Cypress CPLDs

Board Layout Considerations

Transmission line effects are a critical design consideration to Ribbon Cable
Z=100 Ω
ensure suitable signal integrity and reliable In-System Repro- ISR
device
grammability performance.
Relevant design considerations discussed in this section in- PCB
clude: key transmission line effects to minimize, recommend- Large impedance
ed termination practices, signal layout, and on-board buffer- mismatch
Ringing with light capacitive load

ing guidance. BAD causing false-clocking

Condition for Terminating Transmission Line

Layout
1.5V
Lack of termination
Not all digital circuits require termination measures. For ISR Large impedance mismatch from cable to trace
programming applications, however, transmission line effects
are most often significant. Transmission line effects take the
form of unwanted voltage reflections and ringing under cer- Cable Buffer
tain conditions. These effects are caused by impedance mis- Ribbon Cable
Rs Z=100 Ω
match between source drivers, traces, receiver loads, and ISR
any discontinuity between them. For instance, low-imped- device

ance outputs driving high-impedance inputs will yield a cer- PCB

tain reflection coefficient. The size of the voltage reflection is ISR Header
directly proportional to the impedance mismatch at a particu- placed close to receiver
lar node. These inadvertent reflections can interfere at device
receivers, thereby degrading system operation. GOOD Source termination absorbs voltage reflections
Impedance discontinuity is minimized
The classical way of stating the condition for a voltage reflec-
tion to occur is when the signal rise time is less than or equal
Layout
to the round-trip (two-way) propagation delay of the line. In
equation form, transmission line effects are prominent when: Figure 7. Transmission Line Effect—Ringing
tr
L ≥ ------------------- Eq. 1 sition and notching of the signal during the edge transition
2 • t pdL itself.
where L is the length of PCB trace, tr is the rise time of the The first effect, overshooting and ringing, is worst-case with
signal at the source, and tpdL is the one-way propagation de- very light capacitive load. Severe signal bounce can cross the
lay of the line per unit length. receiver’s input threshold, thereby causing false-clocking.
While the ringing is not typically big enough to cause failure,
It is important to note that transmission line effects depend on it can be minimized by observing proper termination tech-
signal rise and fall times rather then on signaling rate. For the niques.
Cypress ISR programming cables, for example, even though
each clock cycle can span several hundred nanoseconds, the The recommended interconnect scheme for a single load
signal transition edge rates of the cable drivers are fast, in the connected to an ISR header is shown in Figure 7. In the “bad
order of 5 to 10 ns. Likewise, typical CPLD rise/fall times are layout” example, an external buffer drives a long transmission
on the order of a few nanoseconds. Transmission line effects line with no termination used. The impedance mismatch from
are therefore inevitable; however, certain layout practices can cable to PCB trace, combined with the lack of termination,
greatly reduce their harmful effects. creates voltage reflections and ringing. In the “good layout”
example, as implemented by any Cypress ISR programming
These effects can occur on any of the four ISR signals but are cable, source termination acts to absorb reflections. Placing
of special concern for the clock signal TCK. This is because the CPLD close to the ISR header will minimize the effect of
there is potentially plenty of time, many hundreds of nanosec- the impedance mismatch between the ribbon cable and the
onds, for the data signals to settle before the next rising clock device. Source termination is already employed in the cable,
edge. Further, the electrical characteristics of these other sig- so no other termination components are necessary.
nals are critical only at the active edge of TCK. Particular care
should be taken with the clock signal trace layout. Since all ISR programming cables use source termination to
absorb voltage reflections from the line, any additional type of
Thus, even for relatively short trace lengths, transmission line end termination is not recommended. The effect of a single
effects can be prominent at fast edge rates. A discussion of load pull-down resistor would degrade the VOH output high
transmission line effects is necessary to understand how to level due to the voltage divider effect of the termination resis-
best design the ISR chain. This discussion also applies to any tor and the buffer plus RS resistance. A parallel termination
method of ISR programming occurring at higher frequency, load, which employs a resistor connection to VCC and to
such as by an on-board microprocessor. Additional details ground, would degrade the VOL of the output buffer due to the
can be found in the references located at the end of this ap- voltage divider action of the resistor to VCC and the buffer plus
plication note. RS resistance to ground.
Transmission Line Effects The other transmission line effect that can cause false-clock-
There are two significant transmission line effects that can be ing is a notching, or glitching, of the clock transition while in
encountered. They are illustrated in Figure 7 and Figure 8. the middle of the transition itself. The notch is evident on both
These effects are overshoots with ringing after the edge tran- edges of the clock. The notch occurs because of a voltage

6
 Design Considerations for ISR Programming of Cypress CPLDs

Notching possible at
ISR device #1
ISR ISR
TCK Buffer #2 #3

1.5V

ISR
BAD #1 ISR
#5
Layout ISR
#4
Improper termination for daisy-chain
Long stubs promote ringing, notching

ISR
device
TCK Buffer ISR
ISR
device
VCC
device R1

R2
ISR
GOOD device

ISR
device
Layout
Parallel termination at end of daisy-chain
Short stubs minimize impedance discontinuities and reflections

Figure 8. Transmission Line Effect—Notching

divider effect between the source impedance of the buffer and the chain at device #5. Making the clock trace the same length
the characteristic impedance of the transmission line ZO. As to device #1 as device #5, as shown in Figure 9, can remove
illustrated in the “bad layout” above, the long stubs and asso- this notching effect. In general it is good to avoid stubs on the
ciated impedance mismatches cause reflections at each clock line to minimize this effect.
node. As the initial voltage wavefront propagates to the end
of the transmission line, reflections from adjacent nodes can
affect the voltage waveform at earlier receivers by creating PCB
notching. If the notch resides near the trip point of the ISR
#2 #4
device, (1.5V for both Delta39K LVTTL levels and Ultra37000
devices), then it could result in a false-clock scenario resulting Better clock #1 #3
trace layout
in ISR operation failure. This effect more typically occurs with with equal trace
multiple devices in the ISR chain because of differing clock lengths for each #6 #8
line trace lengths and improper trace layout. ISR device to
#5 #7
prevent notching
The daisy chain set-up shown in the “bad layout” example of
Figure 8 is not recommended. With source termination, as
used in all ISR programming cables, all load devices should Figure 9. Clock Trace Layout
be lumped at the end of the line. As this is not practical for
more than one ISR device, a buffering scheme must be adopt- While this scheme can be effective, its implementation on a
ed. A better layout practice is shown in the “good layout” ex- PCB may not be practical. This is due to the fact that the split
ample, yet this layout may still be susceptible to ringing or traces must be impedance matched to the feed wire in order
notching depending on the precise layout. Recall that since to prevent reflections and ringing between junctions.
all ISR programming cables employ series termination, an on-
board buffer is necessary. Other schemes for providing the An example implementation is shown in Figure 10. Here, the
best signal integrity are described in detail below. split trace widths are scaled smaller such that the parallel
combination of the split traces matches with the characteristic
TCK Clock Layout impedance of the feed trace. The example shows a clock tree
distributed to four ISR devices, each end terminated to a
The layout of the clock shown in Figure 9 can make a big proper Thevenin termination voltage. The characteristic im-
difference in reducing the transmission line effect of notching. pedance of the feed wire, ZO, matches with the four thin
If the clock trace is laid out exactly as shown in Figure 8, then scaled 4*ZO traces in parallel. While this configuration results
the first device can experience a notch of duration 2T, where in optimal signal integrity, it is little used on PCBs. This is due
T is the transmission line delay from device #1 to the end of

7
 Design Considerations for ISR Programming of Cypress CPLDs

uneven impedances when driving high and low for logic fam-
ilies such as TTL. This trade-off can still produce acceptable
signal integrity.
ISR
Extra buffering with termination is recommended wherever
device
VT the impedance of the trace changes greatly, such as at the
connection between a PCB and an add-on card. If large num-
bers of ISR devices are required in the ISR programming
4 ZO chain, the clock buffer outputs can feed a clock tree layout, or
VT
TCK Buffer can alternatively feed a daisy chain of cascaded ISR devices
(replacing source termination with end termination). This
4 ZO ISR combines the configuration shown in Figure 11 with one of
ZO Figure 9 or Figure 8.
VT device

ISR Cable Buffer

4 ZO
Ribbon Cable
device Rs Z = 1 0 0Ω
ISR
Impractical: 4 ZO device
VT
Difficulty to fabricate
traces with widely PCB
varying impedance
ISR Source Termination
device BEST
Layout ISR device
or group of devices
Figure 10. Clock Tree Trace Layout Implementation

to the manufacturing difficulty of fabricating traces with widely #1

varying impedance on the same board.
In lieu of this technique, it is recommended use the buffering HC244 #2
R = 3 3Ω
scheme described in the following section for best signal qual-
ity. R = 3 3Ω
TCK
R = 3 3Ω
Adding Extra Buffering on the PCB #3
R = 3 3Ω
The best signal integrity for the clock line is achieved by incor-
R = 3 3Ω
porating buffering on the board as shown in Figure 11. This #4
buffering, with proper termination, can guard more effectively R = 3 3Ω
against both of the transmission line effects previously de- R = 3 3Ω
scribed. The buffer should be placed close to the 10-pin head- R = 3 3Ω #5
er connector so that the termination resistor can match the
cable characteristic impedance and prevent reflection at the
buffer input. The on-board buffer can provide separate buffer-
ing for each ISR device clock line. The series resistor, placed #6
#8
close to the buffer output, can match the characteristic imped- #7
ance of the trace on the board and prevent reflections at the
buffer output. In Figure 11 it is not crucial that the clock traces PCB
have the same length for each device clock since there is no
danger of timing problems from one ISR device to the next. Figure 11. Buffering with Termination
This is because the data output from one ISR device does not
propagate to the next device until the falling edge of the clock Valid ISR Programming Voltages
as defined in the IEEE 1149.1 specification.
Only the Delta39K, Quantum38K, and PSI families of pro-
An HC buffer such as the HC244 for 5V VCC, or an LVT244 grammable devices support any choice of programming volt-
for 3.3V VCC, is recommended for on-board buffering. These age on the ISR signals (VCCJTAG) from 3.3V, 2.5V, and 1.8V.
are selected because they provide good drive capability and All are provided by the C3ISR programming cable. The rec-
input noise margin. An FC buffer should be avoided since the ommended voltage is 3.3V, device permitting.
faster edge rates will worsen transmission line effects. The
source termination resistor is selected to match the source Ultra37000 and FLASH370i devices permit 5V and 3.3V levels
impedance to the characteristic impedance of the trace. In (with appropriate VCCIO level). The FLASH370i device family is
this way, the output resistance of the buffer plus the source the only one that requires a 12V supervoltage on ISRen for
termination resistor RS equals ZO. A carefully matched programming. To maintain compatibility, Ultra37000 devices
source prevents voltage reflections towards the load. It is im- (except for Ultra37000V) are designed tolerant to 12V on the
portant to note that there is often no best value for RS due to equivalent JTAGen pin.

8
 Design Considerations for ISR Programming of Cypress CPLDs

Device-Specific ISR Design Considerations Ultra37000 CPLDs differ from Delta39K in that certain device
packages offer dual-function pins that operate as ISR signals
The In-System Reprogammability feature is available on a in programming mode or as regular input/output in I/O mode.
wide range of Cypress programmable devices. While the These are typically smaller packages with a restricted pin
board layout recommendations discussed herein apply to all count. For these dual-function devices, the pin called JTAGen
ISR devices, there are some notable ISR design consider- controls the multiplex between modes. When programming
ations that are distinct for each family. (JTAGen is HIGH), JTAGen enables the ISR interface for dual-
Board-level design issues addressed in this section include: mode devices. When the JTAGen signal disables the ISR in-
the state of ISR programming pins when floating, bus-hold pin terface (JTAGen is LOW), the ISR device will start driving
differences between the FLASH370i and the Ultra37000, and some of its output pins, based upon the functionality of the
supported I/O levels for JTAG signaling. design.
The Delta39K, Quantum38K, PSI, and Ultra37000 ISR device The user can configure a dual-function pin as an input, output,
families incorporate internal weak pull-ups on the JTAG pins or bidirectional input/output. This requires additional external
TDI and TMS as required by the IEEE 1149.1 specification. logic to mediate between JTAG signals and I/O signals. This
This is to ensure that, if a solder fault results in an open circuit external logic requirement is discussed in detail in Appendix
on a JTAG pin, the internal TAP controller in the device will A.
enter the predictable, safe Test-Logic-Reset state. The While specific FLASH370i devices also support dual-mode
FLASH370i family has a bus-hold structure on these pins. pins, there are small differences between ISRen for
While still JTAG compliant, this family alone does not support FLASH370i and JTAGen for Ultra37000 to take into consider-
boundary scan capability. ation. Simple cascading of single- and dual-function devices
It is important to consider that noise from a large number of of both families is discussed in Appendix B.
I/Os switching simultaneously during boundary scan opera-
tions can affect functionality. Therefore, it is highly recom- State of ISR Pins When the ISR Pins Float for Ultra37000
mended that these boundary scan tests be done in a relative- Devices
ly low noise environment. The ISR pins can be floating if, for example, a programming
cable is not attached to the on-board ISR header. The only
Delta39K/Quantum38K/PSI Families ISR programming difference between the Ultra37000 and
The Delta39K, Quantum38K and PSI families permit flexible FLASH370i family is the connection of the bus-hold latches on
signal levels on the ISR pins, including 3.3V, 2.5V, and 1.8V, the ISR interface pins. Specifically, for Ultra37000 CPLDs the
supporting LVTTL, LVCMOS, LVCMOS2, and LVCMOS18 I/O bus-hold latches are disconnected from the JTAG pins TCK,
standards. Each voltage can be selected by applying the de- TMS, TDI, and TDO when the JTAGen pin is HIGH, thereby
sired target voltage to the VCCJTAG pin. The recommended enabling the JTAG port. The bus-hold latches are connected
voltage for JTAG port signals is 3.3V. These devices have when the JTAGen pin is LOW, thereby disabling the JTAG
single-function dedicated JTAG pins. port. For the single-function devices there is no JTAGen pin
and the ISR interface is permanently enabled; therefore, the
Since these families lack 5V tolerance, they cannot directly be bus-hold latches for JTAG pins are permanently disabled.
driven by 5V levels without additional board components. These differences allow the Ultra37000 family to support
Consequently, Delta39K, Quantum38K, and PSI devices can- JTAG Boundary Scan testing. (Bus-hold latches could have
not directly follow an Ultra37000 or a FLASH370i device driving caused significant DC loading on the JTAG drivers of TCK and
5V within a scan chain cascade, since TDI will violate input TMS depending on the source impedance of the drivers and
voltage specs. Board-level solutions for interfacing Delta39K, the number of devices connected in the ISR chain. This could
Quantum38K or PSI I/Os to 5V is described in the Cypress occur because these signals, TCK and TMS, are connected
application note: “Interfacing Delta39K and Quantum38K in parallel to all the devices in the ISR chain.)
CPLDs to 5V Devices.”
An additional difference is that internal pull-up resistors are
These families, based on volatile SRAM technology, require enabled on the TDI and TMS JTAG pins when the ISR inter-
configuration at power-up prior to normal operation. I/Os are face is enabled. This change allows conformance to the IEEE
enabled only after configuration is complete. Up to this time, 1149.1 specification and is necessary to place the Test Ac-
I/Os are three-stated and can be subjected to live signals. For cess Port (TAP) controller of a JTAG device in a known benign
the case of a self-boot solution, the initial data stored on the state such as Test-Logic-Reset if solder open faults occur in
internal FLASH ensures I/Os three-state after device config- the ISR chain. The bus-hold latch is still permanently enabled
uration completes. For volatile devices requiring external con- on the JTAGen pin and powers up in the HIGH state. To de-
figuration, they will continually restart configuration cycles un- termine whether external resistors are needed we once again
til either a valid configuration bitstream is downloaded from must consider the single- and dual-function mode cases.
the boot EEPROM or JTAG instructions program the part.
More information on Delta39K configuration can be found in For single-function mode devices the only pin that needs an
the Cypress application note: “Configuring external resistor pull-down is the TCK pin since there are al-
Delta39K/Quantum38K.” ready internal pull-ups for TDI and TMS and the TDO pin is a
dedicated output pin.
Ultra37000 Family For dual-function mode devices operating in single-function
Ultra37000 devices support 5V or 3.3V I/Os (including the mode or dual-function mode no external pull-ups are neces-
ISR pins) since the I/O power supply, VCCIO, is split from the sary since the bus-hold latches are reconnected to the ISR
core power supply. Ultra37000V devices support only 3.3V, pins once the ISR interface is disabled.
yet have I/Os which are tolerant to 5V inputs.

9
 Design Considerations for ISR Programming of Cypress CPLDs

The value of this pull-down resistor for TCK is not crucial since ISR design considerations involved and adherence to the rec-
the external JTAG pin driver simply has to be strong enough ommended layout and termination practices, a printed circuit
to overpower the resistor. Typical values are 10 kΩ or 4.7kΩ. board designer can implement a reliable method for device
reconfiguration or in-system test using boundary scan.
FLASH370i Family
The Cypress ISR PC programming cables provide the sim-
Like the Ultra37000 family, FLASH370i CPLDs have a separate plest method to build In-System Reprogrammability of pro-
I/O power supply, VCCIO, which can support 5V or 3.3V levels. grammable devices into systems. In-System Reprogramma-
Only the ISRPCCABLE can program an ISR chain containing bility (ISR) of a programmable device has several benefits. It
FLASH370i devices. This is because this cable alone produces allows engineering development and debugging to occur
the required 12V supervoltage on the ISRen pin required for without having to socket the ISR devices and without having
device programming. This cable, however, does not support to remove them and reprogram them in a device programmer.
3.3V ISR signaling so it cannot be used with any 3.3V ISR This saves time regardless of the package type used. ISR is
device like the Delta39K. especially valuable when fine-pitch packages like TQFPs and
Smaller FLASH370i packages contain pins which offer dual- FBGAs are used. This not only saves time, it can also avoid
mode functionality between ISR programming mode and nor- the high likelihood of bending leads on very fine-leaded de-
mal I/O mode, similar to the Ultra37000 family. The necessary vices. Also, by allowing soldering of TQFP packages directly
external logic to support dual functionality is detailed in Ap- onto a board without sockets, it helps to avoid spending time
pendix A. Specific design considerations with cascading sin- simply checking device-to-socket-lead connections during
gle- and dual-function Ultra37000 and FLASH370i devices are debugging. ISR also allows for designs which can be recon-
found in Appendix B. figured in the field, either by a software update or by other
input from the system. The superior routability and flexible
Additional FLASH370i device and board-level design consider- architecture of the Cypress ISR CPLDs enhance the value of
ations are found in Appendix C. all of these benefits greatly by allowing design changes to be
State of General Cypress ISR Device I/Os at Power-Up made during prototyping, debugging, or field operation and
still successfully route to the already-defined pinout, even on
When ISR devices are shipped from Cypress, the devices designs that utilize most or all of the device’s resources.
have already been programmed, erased, and programmed
again as part of the testing process. They will not, therefore, This application note explains the available Cypress program-
be blank when they first come out of the tube. They will, how- ming cables and the signals they use, and also covers many
ever, be programmed such that all of the I/Os are three-stated design techniques and considerations that show how to easily
after power-up. Furthermore, all I/Os (except TDO) are three- use the capabilities of ISR devices. These include: descrip-
stated during device programming. This allows soldering of tion of the logic needed when using the dual-function pins on
ISR devices directly onto a user’s board without having to applicable ISR devices, connecting ISR devices in a program-
erase them first. It allows the user to power-up a board and ming chain, and ISR differences between the programmable
program the ISR devices on it without worrying whether their logic device families.
initial, non-blank state will cause any problems such as output Designing a daisy-chain of ISR devices is straightforward pro-
contention with other devices on the board. vided that the designer follows the layout guidelines set forth
The ISR programming procedure is to take ISR devices di- in this document. By following the recommended layout prac-
rectly from the tube, solder them onto the board, connect the tices, board-level problems will be eliminated and a highly
programming source (such as the ISR programming cable reliable programming method results.
attached to a PC), turn on the power to the board, and then
program the devices for the first time. Since many of the I/Os References
on the ISR device(s) are undoubtedly inputs, other devices on 1. Cypress Application Note. “System Design Considerations
the board could be driving those pins immediately upon pow- When Using Cypress CMOS Circuits,” 1993.
ering up the system. By having all of the ISR I/Os initially
programmed to be three-stated, and by guaranteeing the 2. IEEE Std 1149.1-1990 Test Access Port and Boundary
same three-state during ISR programming, you are assured Scan Architecture, IEEE Computer Society, May 1990.
that the ISR device will not also drive those pins. This pre- 3. Johnson, H. and Graham M. “High-Speed Digital Design,”
vents bus contention, and prevents the ISR devices or other Prentice-Hall, Inc., 1993.
devices on the board from being damaged. ISR devices can
be programmed for the first time in-system without fear that
other board components driving the CPLD will negatively ef-
fect operation.
As previously discussed, all ISR device I/Os will initially three-
state after first power-up regardless of whether the CPLD
contains volatile or non-volatile configuration bits.

Summary
The In-System Reprogrammable feature of Cypress ISR de-
vices provides the critical capability to manipulate program-
mable device configuration without the need to desolder com-
ponents from a user’s board. With a good understanding of

10
 Design Considerations for ISR Programming of Cypress CPLDs

Appendix A. Dual-Function Device Considerations for Ultra37000 and FLASH370i CPLDs

Only the Ultra37000 and FLASH370i CPLD families support pins as I/Os in your design. The other way to use them is as
dual-mode ISR programming pins, whereby compact packag- true dual-function pins, functioning both as JTAG pins in pro-
es offering these pins can function in JTAG mode or in normal gramming mode and as I/Os in normal operating mode. Most
I/O mode. It is suggested that the following three application customers will use the dual-function pins only in their JTAG
notes, “An Introduction to In-System Reprogramming with the function.
Ultra37000,” “An Introduction to In-System Reprogramming
with the FLASH370i,” and “Understanding Bus-Hold—A Fea- Devices With Dual-Function Programming Pins Used in Sin-
ture of Cypress CPLDs,” be read along with this application gle-Function Mode
note to become familiar with these product families. They give To use the ISR devices in this way, with the dual-function pins
a complete listing of all single- and dual-function mode devic- used as programming pins only, the total number of I/Os used
es for all members of the FLASH370i or Ultra37000 families in your design must be equal to or less than (n–4), where n is
Single-/Dual-Function Programming Pins the total number of input and I/O pins available on the device.
This way is the preferred method of design. It is much easier
The next portion of this note explains in detail how to use the and will save both time and components over implementing
IO function on the JTAG/IO pins. To address this issue, we the kind of logic described in the next section for dual-function
categorize designs into three types: designs using devices pins used in dual-function mode.
with single-function pins; designs using devices with dual-
function pins used in single-function mode; and designs using To design with the dual-function pins used in single-function
devices with dual-function pins in dual-function mode. The mode, simply do not allow an I/O function to be placed on
single-function/dual-function names refer to the four ISR pins these dual-function pins. Two ways to do this in software are
and whether they share their functionality with IO pins. Single- described below.
function mode refers to the ISR pins functioning as ISR pins First, if you are using the Cypress Warp® VHDL compiler, you
only. Dual-function mode refers to the ISR pins functioning in can use a simple synthesis directive called “pin_avoid” to
ISR mode during ISR operations as well as IO mode when make sure the compiler does not assign signals to whatever
the device is operating normally in the board. The three cases pins you specify. In this case, of course, you would specify the
are explained further below. pin number of the dual-function pins. An example of the exact
text to include in your VHDL code appears in Figure 12. This
Single-Function Pins/Single-Function Mode example assumes you are using the CY7C373i or CY7C374i
Some of the ISR devices have pinout/package combinations in the 84-pin PLCC package where pins 14, 35, 51, 72, and
such that the pins used for programming are single-function 83 are the ISR pins. For a complete listing of all the ISR pins
only; i.e., they are used as programming pins only. When the of all members of the FLASH370i or Ultra37000 families see
device is operating (i.e., not being programmed) they are not the application notes “An Introduction to In-System Repro-
in use and are extra pins. Designing with these devices simply gramming (ISR) with the FLASH370i” or “An Introduction to In-
requires a direct connection from the device ISR pins to the System Reprogramming (ISR) with the Ultra37000.”
pins on the ISR programming cable connector for full access If you prefer you can also ensure the dual-function pins do not
to in-system reprogramming. get used as I/Os in normal operating mode by explicitly as-
Dual-Function Pins/Dual-Function Mode signing all of the signals to pins in your design. You just need
to make sure you assign all of the signals to pins other than
The rest of the devices in the ISR family have pinout/package the dual-function pins. An example showing how to do this in
combinations such that the pins used for programming have Warp using the “pin_numbers” directive is shown in Figure 13.
dual functionality. They are used as programming pins when Again, this example assumes you are using the CY7C373i or
the device is being programmed, and they are used as I/Os CY7C374i in the 84-pin PLCC package, so pins 14, 35, 51,
when the device is in normal operating mode. To use both of 72, and 83 are not being used. Notice that none of the signals
these functions, you must design interface logic to isolate pro- used in the example in Figure 13 are assigned to these pins.
gramming signals from other devices on the board or incor- This approach can be more time-consuming than using the
porate some of this interface logic into the output enable de- “pin_avoid” directive, especially if your design has a large
sign of the devices driving the ISR devices to be programmed. number of I/Os. When you do this, you also need to take some
Dual-Function Pins/Single-Function Mode device-specific resource information into account. Since the
compiler can account for all of this for you automatically, it is
Alternatively, the designer can decide to use these dual-func- usually easier to just use the “pin_avoid” directive. Additional-
tion pins as programming pins only and not connect them as ly the “pin_avoid” attribute places fewer restrictions on the
I/Os for normal operation. In this case we refer to the use of fitter software making it easier to fit designs.
a dual-function device being used in single-function mode.
The design is simpler in this case as no special interface logic Devices With Dual-Function Programming Pins Used in Dual-
is required. Function Mode

Designs That Use Devices With Dual-Function Program- There are cases where you may need or want to take advan-
ming Pins tage of the dual functionality of the dual-function program-
ming pins. For example, you may not have enough I/O pins
There are two ways to design with devices that have dual- for your design if you do not use the dual-function ISR pro-
function programming pins. First, you could use the dual- gramming pins as I/Os when the device is in normal opera-
function pins as single-function pins. That is, you could decide tion. Other times, you may want to use the dual-function ISR
to use only the JTAG function of the pins and not use those

11
 Design Considerations for ISR Programming of Cypress CPLDs

-- example of using “pin_avoid” for single–function mode of

-- dual–function devices
entity cpuctl is port (
a : in bit_vector (31 downto 0);
rd, wr : out bit;
hold : buffer bit;
status : out bit_vector (7 downto 0));
attribute pin_avoid of cpuctl:entity is “14 35 51 72 83”;
end cpuctl;
-- architecture would follow

Figure 12. VHDL Code Fragment Showing pin_avoid Attribute

-- example of explicit pin assignments that avoid ISR pins

-- to facilitate single–function mode of dual–function devices
entity cpuctl is port (
a : in bit_vector (15 downto 0);
rd, wr : out bit;
hold : buffer bit;
status : out bit_vector (7 downto 0));
-- assign pins below and avoid pins 14, 35, 51, 72, and 83
attribute pin_numbers of cpuctl:entity is
“a(15):12 a(14):13 a(13):15 a(12):16 a(11):17 a(10):18 a(9):19 “ &
“a(8):24 a(7):25 a(6):26 a(5):27 a(4):28 a(3):29 a(2):30 “ &
“a(1):31 a(0):33 rd:36 wr:37 hold:38 status(7):54 status(6):55 “ &
“status(5):56 status(4):57 status(3):58 status(2):59 status(1):60 “ &
“status(0):61“;
end cpuctl;
-- architecture would follow

Figure 13. VHDL Code Fragment Showing pin_numbers Attribute

pins as I/Os in normal operation because their physical posi- the ISR device, and you do not want the normal operating
tion makes your board layout easier. If you want to do this in signal to drive, affect, or be affected by the programming logic
your design, you can do it fairly easily; it simply requires a little when the ISR device is operating normally in the system. The
bit of extra logic and some additional small components. This basic strategy in all of the cases listed above is to use three-
next section shows you how to do this. state buffers or multiplexers on these signals, and to have
The TDI, TCK, and TMS programming pins are all inputs to those buffers or multiplexers controlled by the ISR* signal
the device during programming, and they always share pins from the programming cable. The ISR* signal, recall, is a sig-
with bidirectional I/Os when they are dual-function pins. The nal from the programming cable that is a logic LOW when
TDO programming pin, on the other hand, is an output pin JTAGen is enabling the ISR interface.
from the device during programming. It, too, always shares a Dual-Function Mode Operation: I/O Pin Used as an Input
pin with a bidirectional I/O when it is a dual-function pin.
These I/O pins, in turn, can be used as input only, output only, First, consider the case of the ISR programming pins that are
or bidirectional I/Os in any design, based upon the function- inputs to the device during programming; TDI, TCK, and TMS.
ality that is described for these pins in the programmable logic When one of these device pins is being used as an input
chip’s design description. The result is that there are six dif- during normal operating mode, you simply have to select be-
ferent cases to consider: An ISR input programming pin (TDI, tween one of two inputs based on whether you are in pro-
TCK, TMS) can share a pin with a signal that is an input, an gramming mode or in operating mode. This is implemented
output, or an I/O; and you can have an ISR output program- very easily by using a 2:1 multiplexer where ISR* is the select
ming pin (TDO) sharing a pin with a signal that is an input, an line, as shown in Figure 14(a). Alternatively, you could imple-
output, or an I/O. We next look at each of these six cases ment this by having two three-state buffers whose inputs are
individually. TDI (or TMS or TCK) and signal, whose outputs are tied to-
gether and to the TDI/IO pin, and whose enable lines are
What you are trying to accomplish in all of these cases is controlled by opposite values of ISR*. This is shown in Figure
fundamentally the same. You are trying to isolate the pro- 14(b). One way you could implement this logic is with FCT-
gramming signals from the normal operating signals on the family devices. For example, you could use one of the four 2:1
board. You do not want the programming signal to drive or multiplexers in a 74FCT257T to implement the logic shown in
affect anything else on the board when you are programming Figure 14(a). Alternatively, you could use a pair of transceiv-

12
 Design Considerations for ISR Programming of Cypress CPLDs

ers or pass-transistors from a 74FCT244T or a Texas Instru- The inverter shown in Figure 14(e) can be eliminated by im-
ments SN74CBT3384A, for example, to implement the logic plementing an inversion within the SN74CBT3384A device.
shown in Figure 14(b). The connections for the FCT257T, This requires using only an external resistor and a few addi-
FCT244T, and SN74CBT3384A are shown in Figure 14(c), tional connections. An inversion of the connection to pin BE1*
(d), and (e), respectively. To reduce unnecessary noise it is a is accomplished by connecting +5V to pin A1 and connecting
good idea to tie the unused inputs on the FCT devices to one end of a resistor to GND and the other end to pin B1. B1
ground instead of letting them float. is then the inverse of the input connected to BE1*, which is

TDI 0
TDI TDI/IO
TDI/IO
y
Signal 1 S

Signal
ISR
ISR* ISR

ISR*

(a) Multiplexer Solution (b) Buffer Solution

ISR*
1
S
2
TDI I0a 4
3 TDI/IO
Ya
Signal I1a

FCT257T
DIP/SOIC/QSOP
ISR

(c) FCT257T Implementation

1
ISR*
OEA
19
OEB
TDI 2
DA0 18 TDI/IO
OA0
Signal 17
DB0 3
OB0

FCT244T
DIP/SOIC/QSOP
ISR

(d) FCT244T Implementation

1
ISR*
BE1
13
BE2
3
TDI 2
A0 TDI/I/O
14 B0 TDI/IO
Signal A5 15
B5
SN74CBT3384A
DIP/SOIC/QSOP

ISR

(e) SN74CBT3384A Implementation

Figure 14. Design for Dual-Function Pins: TDI/TCK/TMS used with Input

13
 Design Considerations for ISR Programming of Cypress CPLDs

ISR*. By implementing this inversion, the inverter in Figure

14(e) can be removed, and pin B1 can be connected to pin
BE2*. The BE1*, A0, A5, B0, and B5 pin connections remain
the same.
The FCT devices shown are just one possible way of imple-
menting this logic, of course. There are others, including us-
TDI TDI/IO
ing extra pins and gates from an ASIC, FPGA, CPLD, or PAL®
device already on the board. Regardless of whether the buffer
or multiplexer is in an FCT device, ASIC, FPGA, or other de-
vice, there will be some additional propagation delay for the
normal operating signal due to the presence of that logic. This ISR
must be accounted for in your design. Using the Signal
SN74CBT3384A provides the smallest extra delay, less than
one quarter of one nanosecond. The extra delay holds true
for the other cases presented next.
ISR*
Dual-Function Mode Operation: I/O Pin Used as an Output
In the case of the TDI, TCK, or TMS sharing a pin with an I/O Figure 15. Design for Dual-Function Pins: TDI/TCK/TMS
that is used only as an output during normal operating mode, Used as an Output
the logic is slightly different. Much like the case above, you
can just use a pair of three-state buffers or pass-transistors to You can also use a SN74CBT3384A as an alternative to the
separate the signals that are used for the two different func- buffers, as shown in the previous case. This would be the
tions. In this case, however, instead of tying the two outputs most flexible solution because it would work for all configura-
together, you tie the output of one buffer both to the dual- tions—the pin used as an I, O, or I/O—and allows you to de-
function pin of the ISR device and to the input of the other cide later exactly how to use that pin.
buffer. The input to the first buffer is the programming function
signal, and the output from the other buffer is the normal op- Dual-Function Mode Operation: I/O Pin Used as an Input and
eration output Signal. The first buffer is enabled when ISR* is an Output
asserted and is disabled otherwise, and the second buffer is In the case of the TDI, TCK, or TMS sharing a pin with an I/O
enabled when ISR* is deasserted and is disabled otherwise. that really is used as a bidirectional I/O, the logic needed is a
This is shown in Figure 15. Thus, when the device is being little more complicated. As seen in Figure 16, part of the logic
programmed, TDI (or TMS or TCK) is driving the TDI/IO pin is a combination of the two solutions for the two individual
and Signal is in three-state, and when the device is not being cases above in the way it uses ISR* to separate the program-
programmed, the TDI/IO pin is not driven as an input allowing ming function of TDI (or TMS or TCK) from the input and
the ISR output to drive Signal. Because Signal is in the three- output functions of Signal during normal operating mode.
state during programming, you may need to have a pull-up or There is more than just this logic required, however. It is also
pull-down resistor on Signal depending on how you use it on necessary to use an extra pair of buffers to separate the input
your board. and output functionality of Signal itself. This is required to
keep from unintentionally building a feedback loop and is im-
plemented using an extra signal that indicates the direction of
the I/O pin. In this example, we assume we have a signal
called dir, and that dir is HIGH when the I/O pin is being used
as an input and dir is LOW when the I/O pin is being used as
an output.

TDI W
b1

X
Signal b2 b4 TDI/I/O

Y ISR
b3 b5

ISR*
dir

Figure 16. Design for Dual-Function Pins: TDI/TCK/TMS Used With an I/O

14
 Design Considerations for ISR Programming of Cypress CPLDs

TDI TDI/I/O
b1

Signal b2

ISR
b3

ISR*

Figure 17. TDI/TCK/TMS Used With an I/O: Example of Incorrect Solution

To understand why this is necessary, consider just combining The only difference is that TDO is an output during program-
the logic from Figure 14(b) and Figure 15. The result would ming mode instead of an input. Therefore, the only difference
be the logic shown in Figure 17, which is different from Figure in the logic is the orientation of some of the buffers. The
16 in that buffers b4 and b5 were eliminated and intermediate solutions for the TDO case are presented without further ex-
signals w, x, and y are now all simply connected together and planation. The logic diagram for the case where TDO is con-
to the TDI/IO pin. In the logic of Figure 17, when the ISR nected to an I/O used only as an input is shown in Figure 18.
device is in normal operation mode and ISR* is HIGH, buffers The logic diagram for the case where TDO is connected to an
b2 and b3 would both be enabled. If Signal were an input at I/O used only as an output is shown in Figure 19. The logic
that time, it would drive the input to buffer b2, whose output diagram for the case where TDO is connected to an I/O really
would drive the input to buffer b3. The output of buffer b3 used as a bidirectional pin is shown in Figure 20. You can
would be driving the input of b2 again, resulting in a feedback alternatively use the SN74CBT3384A solution presented in
loop that could produce undesired affects. The same thing Figure 14(e) in each of these three cases.
would happen if Signal were an output at that time.
Buffers b4 and b5 in Figure 16 prevent this. In the logic of
Figure 16, when signal is an output from the ISR device, b5
is enabled and b4 is disabled; when Signal is an input to the
device, b4 is enabled and b5 is disabled. In both cases, both
the function and value at the pin of the device and the function TDO TDO/I/O
and value of Signal are the same, correct, and only driven by
one source. There is no dangerous self-driving feedback sys-
tem like there is in Figure 17.
The limitation of this solution is that it requires the extra signal ISR
Signal
dir. This signal may be already available; in fact, it may be an
input to the ISR device itself for use as the OE-control on the
pin in question. If it is not already available, you will need to
generate it using other logic on the board. If you cannot do it
using other logic on your board, you should certainly be able ISR*
to generate it using logic inside the ISR device itself, because,
as pointed out above, it should be the same signal as the OE Figure 18. Design for Dual-Function Pins:
used on that pin internally. To get the signal out of the ISR, TDO Used With an Input
however, requires an additional pin. If you are using the logic
in Figure 16 to save a pin, having to use a pin on the device
to generate dir will not gain you anything. If generating one dir TDO TDO/I/O
will help you save two or three pins by allowing you to use two
or three of TDI, TCK, and TMS as dual-function pins, then you
will still have a net savings of one or two pins and it may be
worth it.
As was mentioned in the case where the TDI (or TMS or TCK) Signal
dual-function pin was being used with an input-only pin or with
an output-only pin, you can also use the SN74CBT3384A so- ISR
lution of Figure 14(e) when trying to use the TDI (or TMS or
TCK) dual-function pin as a bidirectional I/O pin in normal ISR*
operating mode.
The logic for using the dual-functionality of the TDO/IO pin is Figure 19. Design for Dual-Function Pins:
essentially the same as is shown in the above three cases. TDO Used With an Output

15
 Design Considerations for ISR Programming of Cypress CPLDs

TDO TDO/I/O

Signal

ISR

ISR* dir

Figure 20. Design for Dual-Function Pins: TDO Used With an I/O
Dual-Function Summary
To summarize this section, there are many ways to accom-
plish programming when using devices with dual-function
pins. The easiest way to use the dual-function device is in
single-function mode. This uses the dual-function pins as pro-
gramming pins only, and is easily accomplished using the
pin_avoid and pin_numbers directives in the Warp design file.
There are also going to be cases where you will want to use
the dual-functionality, most likely because you need some or
all of the four ISR programming pins as inputs, outputs, or
I/Os during normal operation to get all the signals you need
into and out of the device for your design. The circuits needed
to share these pins are relatively straightforward and require
only buffers or pass-transistors. These are circuits you can
implement using FCT or other logic, or you may be able to
implement them using extra gates and pins of an ASIC,
FPGA, or another PLD you already have on the board.

16
 Design Considerations for ISR Programming of Cypress CPLDs

Appendix B. Simple Cascading Considerations for Ultra37000 and FLASH370i CPLDs

You can cascade many ISR devices in a system. That is, you ing in dual-function mode on the TMS signal of two of the
can daisy-chain the devices together and connect their pro- three devices in the chain.
gramming pins in such a way that the devices can be pro-
grammed from a single connection to the ISR programming Driving the JTAGen Pin on the Ultra37000 Dual-Function
cable. Mode Devices When Being Used in Single-Function Mode
Figure 21 shows that the user does not need to worry about
Cascading Single-Function ISR Devices or Dual-Function driving the JTAGen pin to a particular level if the JTAG pins
Devices in Single-Function Mode are only used for ISR operations. This example shows that it
To do this, you simply tie all of the JTAGen, TCK and TMS pins is possible for the dual-function pins to operate in the I/O
of each device to those same pins, respectively, on all of the mode for the Ultra37256 device when the ISR programming
other devices, and then connect them to the corresponding cable is removed since a TTL LOW level could exist on the
pins of the ISR cable connector. You then connect the TDI pin JTAGen pin. Observation of Figure 21 shows that I/O conten-
from the cable connector to the TDI pin of the first device in tion problems are possible through the ISR connections from
the chain, then connect the TDO output of that device to the one ISR device to another if multiple Ultra37000 devices were
TDI input of the next device in the chain, then connect the connected in the same chain and the JTAG pins are used in
TDO output of that device to the TDI input of the next device their I/O function. Output contention between devices is not a
in the chain, and so forth, until you finally connect the TDO problem if the output from all devices is the same polarity.
output of the last device in the chain to the TDO pin of the When and if further ISR operations need to be performed the
cable connector (see Figure 21). In Figure 21 many of the ISR cable drives the JTAGen pin HIGH which three-states the
Ultra37000 devices are single-function mode devices, there- I/O function and re-selects the JTAG function on the dual-
fore the JTAGen pin does not exist at all for these devices. function pins so there is no contention problem possible be-
tween the ISR device and the ISR cable.
Cascading Dual-Function ISR Devices in Dual-Function
Mode Driving the JTAGen Pin on the Ultra37000 Dual-Function
Mode Devices When Being Used in Dual-Function Mode
In addition to the extra circuitry needed for the dual-function
pins per ISR device, the JTAGen pin must also be connected In many designs the user will elect to either use a single-
differently on the Ultra37000 devices than the FLASH370i de- function mode Ultra37000 device or use a dual-function mode
vices. This is necessary because of its different functionality Ultra37000 device in single-function mode. For these cases
with a TTL HIGH input level as previously mentioned. This is the user can ignore the following discussion. Similar to the
explained further in the rest of this application note. Figure 24 FLASH370i family of devices, a TTL LOW level on the JTAGen
shows an example of two dual-function mode devices operat- pin enables the I/O functionality of the Ultra37000 dual-func-

ISR Programming
Cable Connector

JTAGen ISRen
TDI TDI CY7C374i
TDO TDO PLCC
TCK TCK
TMS TMS

TDI Ultra37512
TDO BGA
TCK
TMS

JTAGen
TDI Ultra37256
TDO TQFP

TCK
TMS

Figure 21. Simple Cascading Example - Single-Function Mode Operation

17
 Design Considerations for ISR Programming of Cypress CPLDs

tion devices. For the FLASH370i it is permissible to actually let JTAGen pin. Again the need for external biasing may not be
the JTAGen pin float to retain the I/O capability of dual-mode needed in many case because of the pull-down device incor-
pins. For the Ultra37000 devices this pin must be driven to a porated on the Ultra37128 devices and smaller and to be in-
LOW level to ensure the I/O functionality. For Ultra37128 and cluded on the Ultra37256 as well.
smaller devices a weak pull-down device replaces the bus-
hold latch on the JTAGen pin. This pull-down device (see the Using an External Component to Drive the JTAGen Pin
data sheet parameter IJTAG, which shows the strength of the LOW to Use the I/O Function of the Dual-Function Pins
pull-down device) keeps the pin in the LOW state after pro- The JTAGen pin can be driven LOW using any of the solutions
gramming and prevents the need for external biasing on the already presented in Figure 14 regarding using the dual-
JTAGen pin if a Ultra37000 device replaces a FLASH370i de- function pins in dual-function mode. The only difference is that
vice. Early Ultra37256P160 silicon did not have this pull down the JTAG input is JTAGen, which is tied to VCC instead of one
device on the JTAGen pin but more recent silicon has this of the four JTAG pins and the “signal” input is connected to
device. If the pull-down device is not employed then a bus- ground. You may be able to use unused resources in the ex-
hold latch is employed and this latch could hold a HIGH value ternal component solutions presented in Figure 14 to imple-
on the pin. With multiple devices in the chain, some devices ment this logic. Any of these solutions can be used for multiple
being Ultra37128 and smaller and some being Ultra37000 devices ganged together. Figure 22 shows two
Ultra37256P160 early silicon or FLASH370i devices, it is still examples for driving the JTAGen pin from the control of signal
possible for the JTAGen pin to be pulled into the HIGH state. ISR*. As mentioned before, a pull-up resistor is also needed
Two methods for driving the JTAGen pin LOW, using a exter- on the ISR* signal at the 10-pin header connector.
nal pull-down resistor and using an external component are
presented.

Using a Pull-down Resistor to Drive the JTAGen Pin LOW

to Use the I/O Function of the Dual-Function Pins JTAGen
ISR*
The JTAGen pin can be held at a TTL LOW by using a pull-
down resistor to ground. This works fine provided there are
not too many devices in the ISR chain. The problem with the
simple resistor is that the bus-hold latches on the JTAGen
pins may disturb the pull-down operation if there are many Ultra37000
other FLASH370i devices in the chain. This is because the bus-
hold latches that are connected in parallel produce a lower
source impedance. The bus-hold latch differences between
5 volts
the two ISR family members are discussed further in this note.
The resistor must be able to provide a low enough resistance
to overpower the combined bus-hold latches in parallel such 0
that the voltage on the JTAGen pin drops below the trip point y JTAGen
(Vtrip) of the bus-hold latches. Once the JTAGen pin voltage 1 S
drops below Vtrip all the bus-hold latches connected in parallel
will flip to the desired LOW state. The maximum resistance
that is guaranteed to overpower N FLASH370i bus-hold latch-
es in parallel is given by the formula: ISR*
Ultra37000

Rpulldown = Vtrip/(N*(IBHHO))
where Vtrip is 1.5V and IBHHO is –500 µA (maximum current Figure 22. JTAGen Driven for the Ultra37000
that is guaranteed to invert the state of a single bus-hold
latch). Rpulldown is 3 kΩ for 1 device, 600Ω for 5 devices, and Figure 23 shows the JTAGen pin driven by an extra I/O pin of
300Ω for 10 devices in the chain. It is recommended that the the Ultra37000 device by simply inverting the ISR* control
number of devices in the chain be limited to 5 devices if the signal. This would seem to be a simple alternative to adding
other devices in the chain are all FLASH370i devices. The extra components. This solution, however, won’t work. The
above limitation of 5 devices in the chain is suggested be- problem is that the I/O pins of the device enter three-state
cause the resistor value would need to be reduced which when the ISR mode is enabled (JTAGen driven HIGH). Be-
would place too high a DC current load on the JTAGen signal cause the I/O is three-stated there is no way to drive the
driven to 12V from the ISR cable. With a pull-down resistance JTAGen pin LOW. The dual-function pins are stuck in the
of 600Ω, the DC current load on the JTAGen pin is 12/600 or JTAG function because the bus-hold latch, which is always
20 mA, which is an acceptable load. Resistor values less than enabled, has latched a HIGH level on the pin. Figure 24
600Ω would require a higher wattage resistor than the stan- shows how to combine dual-function FLASH370i and
dard 1/4 watt rating, assuming 12V is needed for program- Ultra37000 devices in the same chain with the appropriate
ming FLASH370i devices in the same chain. If only JTAGen connections assuming the user wants to use one
Ultra37256P160 early silicon devices are in the chain and the dual-function pin in dual-function mode for each of the
UltraISRPCCABLE is used then the JTAGen pin only goes to Ultra37000 devices. The figure shows that one mux can be
a TTL HIGH so the number of devices in the chain can be used for two Ultra37000 devices but many more devices can
increased to 10. The above restriction of the pull-down resis- use the same mux output signal. In this example the TMS pin
tor can be avoided by using an external component to choose on both Ultra37000 devices is used in dual-function mode
between a TTL HIGH level and a TTL LOW level on the where the I/Os are used as JTAG pins and as input pins. The

18
 Design Considerations for ISR Programming of Cypress CPLDs

10-kΩ resistor on the ISR* signal is required to keep the mux

input HIGH when the ISR cable is removed from the board to
keep the JTAGen input LOW. Remember that, if it is not nec-
essary to use the dual-function pins in dual-function mode,
ISR*
the mux can be removed and the JTAGen pin can be tied to
VCC or left connected to the JTAGen pin from the 10-pin con-
nector.
At this point the user should understand how to connect
FLASH370i and or Ultra37000 devices in an ISR chain and JTAGen
how to bias the ISR interface for his programming and func-
tional needs. There are some remaining minor functional dif- Ultra37000
ferences between the two device families related to the place-
ment of the bus-hold latches on the five JTAG interface pins,
which was addressed in the Device-Specific ISR Design Con-
siderations section of this application note. Figure 23. JTAGen Incorrectly Driven by Ultra37000 I/O

ISR Programming
Cable Connector

JTAGen ISRen
TDI TDI
TDO TDO CY7C375i-125AC

TCK TCK
TMS TMS

ISR* vcc
0 y
JTAGen
1
vcc S TDI Ultra37128P160
10 kΩ
TDO
TCK
0 y TMS
input1
1
S
JTAGen
TDI
Ultra37256P160
TDO
TCK
S
0 y TMS
input2
1

Figure 24. Cascading Dual-Function Ultra37000 and FLASH370i Devices in the Same Chain

19
 Design Considerations for ISR Programming of Cypress CPLDs

Appendix C. Additional FLASH370i Family Design Considerations

This appendix describes additional FLASH370i device and external resistor is needed even on the TCK pin. This is be-
board-level design considerations not covered in the cause these pins are connected in parallel to all devices in the
FLASH370i device-specific section of this application note. chain and the bus-hold latches, which are always present on
the FLASH370i devices, hold the pin to a logic LOW or HIGH
State of ISR Programming Pins When the ISR Pins Float for level preventing it from floating.
FLASH370i Devices
The ISR pins can be floating if, for example, a programming Handling the 12V Signal on the Board for FLASH370i Devices
cable is not attached to the on-board ISR header. The ISR Unlike the Ultra37000 family, in which the JTAGen signal
programming cable is only plugged into the connector on your serves only to choose either JTAG or I/O function on the dual-
board during programming; however, it is acceptable to float function pins, FLASH370i devices uses this pin as the high-
the ISR pins for the FLASH370i devices when the board is voltage, low-impedance path required for programming the
powered up and operating. This is acceptable because the device. There are two requirements on the ISRen program-
ISR devices have been designed with bus-hold structures on ming voltage that necessitate special handling when pro-
every input, input/clock, and I/O pin, including the program- gramming FLASH370i devices. The first is that its voltage must
ming pins for both dual-function and single-function devices. be in the range 11.4V < ISRen < 12.6V during programming,
The exception to this is the TDO pin on single-function devic- and the second is that its maximum transient current is 40 mA
es, which is an output only and the JTAGen pin, which may per ISR device during programming. The 5V/12V DC/DC con-
incorporate a pull-down device instead of a bus-hold latch. verter and other components in the ISR programming cable
The bus-hold latch eliminates the need to use external pull- described in this application note have been chosen to ensure
up resistors or any other technique for handling the case that these specifications are met. Therefore it is suggested
where the ISR programming pins are left floating due to the that the 12V supplied by the ISR cable be used for program-
ISR programming cable being disconnected. ming rather than another 12V supply that may be available on
Bus-hold structures enable a pin to maintain its most recent the board.
logic value even when it is three-stated, whether that value Due to the higher than usual current and voltage require-
was being driven in as an input pin or driven out as an output ments on the ISRen signal, the trace on the printed-circuit
pin. This is done with a weak latch connected to the pin. Since board connecting the ISRen pin from the ISR programming
the ISR programming pins have bus-hold structures, when cable to the ISRen pin on the FLASH370i device(s) also de-
the ISR programming cable is disconnected and the board is serves special attention. First, to handle the current, the trace
powered on, the ISR programming pins all maintain a logic should be double the width of the standard traces. Second,
LOW or logic HIGH value even though they are no longer the trace should be kept as short as possible. In general, this
being driven. If the ISR programming cable is disconnected means the connector for the ISR programming cable should
when the board is powered-down, or if the board is powered- be placed as close as possible to the FLASH370i devices on
down and then back up after the cable has been disconnect- the board. Since the connector is small, it is much easier to
ed, there is still no problem. The ISR bus-hold structures have move the connector closer to the devices than change the
been designed to always power-up with a logic HIGH level whole board layout to place the devices close to the chosen
maintained on the pins to emulate an internal pull-up. spot for the connector.
The utility of the bus-hold structures applies both to the case Decoupling the ISRen Pin to Ground for FLASH370i Devices
of ISR programming pins used as single-function pins and as
dual-function pins. The bus-hold latch does not interfere with One further board layout recommendation is to place a 10-nF
the normal function of the pin because of the relative weak- capacitor located at the 10-pin header connector on the circuit
ness of the latch to the output driver. The latch is more than board on the JTAGen pin to ground if there are FLASH370i
50 times weaker than the ISR device’s output driver. devices to be programmed on the board. If proper ISR cable
connection procedures explained in this application note are
Note that the ISR* pin from the ISR programming cable con- followed this capacitor is not needed. If the ISR cable is hot-
nector does not connect to an ISR device pin. Since it does socket connected to the user’s board, which is not recom-
not, you must use a pull-up on the ISR* signal on your board mended, then this capacitor insures that a proper, slow ramp-
so that it is not left floating when the ISR programming cable ing 12V is applied to the devices to be programmed under all
is disconnected. This signal can be used to support dual- operating conditions with no risk of damage to the JTAGen
mode JTAG/IO pins or to simply monitor when programming pin. Since the ISR cable could easily be hot-socket connected
operations are taking place. by accident, it is advisable and simple to incorporate this de-
State of the ISR Programming Pins When the ISR coupling capacitor.
Programming Cable is Not Attached for Both Ultra37000
Devices and FLASH370i Devices in the Same ISR Chain
For the case where both single-function mode Ultra37000
and FLASH370i devices are in the ISR programming chain, no

In-System Reprogrammable, ISR, FLASH370i, Delta39K, Quantum38K, Ultra37000, Programmable Serial Interface, and PSI are
trademarks and Warp is a registered trademark of Cypress Semiconductor Corporation.
PAL is a registered trademark of Advanced Micro Devices.

© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.