MASTERGAN5

Datasheet

High power density 600 V half-bridge driver with two enhancement mode
GaNHEMT

Features
• 600 V system-in-package integrating half-bridge gate driver and high-voltage
GaN power transistors:
– QFN 9 x 9 x 1 mm package
– RDS(ON) = 450 mΩ
– IDS(MAX) = 4 A
• Reverse current capability
• Zero reverse recovery loss
• UVLO protection on low-side and high-side
• Internal bootstrap diode
• Interlocking function
• Dedicated pin for shut down functionality
• Accurate internal timing match
• 3.3 V to 15 V compatible inputs with hysteresis and pull-down
• Over temperature protection
• Bill of material reduction
• Very compact and simplified layout
• Flexible, easy and fast design.

Applications
Product status link
Switch-mode power supplies
Chargers and adapters
MASTERGAN5
High-voltage PFC, DC-DC and DC-AC Converters
Product label

Description
The MASTERGAN5 is an advanced power system-in-package integrating a
gate driver and two enhancement mode GaN power transistors in half bridge
configuration. The integrated power GaNs have 650 V drain-source blocking voltage
and RDS(ON) of 450 mΩ, while the high side of the embedded gate driver can be
easily supplied by the integrated bootstrap diode.
The MASTERGAN5 features UVLO protection on both the lower and upper
driving sections, preventing the power switches from operating in low efficiency
or dangerous conditions, and the interlocking function avoids cross-conduction
conditions.
The extended range of the input pins allows easy interfacing with microcontrollers,
DSP units or Hall effect sensors.
The MASTERGAN5 operates in the industrial temperature range, -40°C to 125°C.
The device is available in a compact 9x9 mm QFN package.

DS13775 - Rev 1 - July 2021 www.st.com

For further information contact your local STMicroelectronics sales office.
 MASTERGAN5
Block diagram

1 Block diagram

Figure 1. Block diagram

BOOT OUTb GH VS
VCC

VCC UVLO

Vbo
HON RGONH
UVLO
HIN Driver

Level Shifter HOFF

RGOFFH
LIN Logic, OUT
interlocking,
overtemp

SD/OD

RGONL
LON
Level Shifter Driver

LOFF RGOFFL
GND R BLEED

PVCC PGND GL SENSE

DS13775 - Rev 1 page 2/26

 MASTERGAN5
Pin descriptions and connection diagram

2 Pin descriptions and connection diagram

Figure 2. Pin connections (top view)

SD/OD
GND

VCC
N.C.

N.C.

N.C.
N.C.

HIN

LIN
31 30 29 28 27 26 25 24 23

GND
PVCC 1 EP1 22 BOOT

GL 2 21 OUTb

PGND 3 20 GH

SENSE 4 19 VS

SENSE 5 18 VS
SENSE 6 SENSE OUT 17 VS
EP2 EP3
SENSE 7 16 VS

SENSE 8 15 VS

9 10 11 12 13 14
SENSE

OUT
SENSE
SENSE

OUT
OUT

2.1 Pin list

Table 1. Pin descriptions

Pin Number Pin Name Type Function

15, 16, 17, 18, 19 VS Power Supply High voltage supply (high-side GaN Drain)
12, 13, 14, EP3 OUT Power Output Half-bridge output
4, 5, 6, 7, 8, 9, 10, 11, EP2 SENSE Power Supply Half-bridge sense (low-side GaN Source)
22 BOOT Power Supply Gate driver high-side supply voltage
Gate driver high-side supply voltage, used only for Bootstrap
21 OUTb Power Supply
capacitor connection. Internally connected to OUT.
27 VCC Power Supply Logic supply voltage
1 PVCC Power Supply Gate driver low-side supply voltage
28, EP1 GND Power Supply Gate driver ground
Gate driver low-side buffer ground. Internally connected to
3 PGND Power Supply
SENSE.
26 HIN Logic Input High-Side driver logic input
24 LIN Logic Input Low-Side driver logic input
25 SD/OD Logic Input-output Driver Shut-Down input and Fault Open-Drain
2 GL Output Low-Side GaN gate.
20 GH Output High-Side GaN gate.
23, 29, 30, 31 N.C. Not Connected Leave floating

DS13775 - Rev 1 page 3/26

 MASTERGAN5
Electrical Data

3 Electrical Data

3.1 Absolute maximum ratings

Table 2. Absolute maximum ratings

Each voltage referred to GND unless otherwise specified
Symbol Parameter Test Condition Value Unit

VDS GaN Drain-to-Source Voltage TJ = 25 °C 620 V

VCC Logic supply voltage - -0.3 to 11 V

PVCC-PGND Low-side driver supply voltage(1) - -0.3 to 7 V

VCC-PGND Logic supply vs Low-side driver ground - -0.3 to 18.3 V

PVCC Low-side driver supply vs logic ground - -0.3 to 18.3 V
PGND Low-side driver ground vs logic ground - -7.3 to 11.3 V
VBO BOOT to OUTb voltage(2) - -0.3 to 7 V

BOOT Bootstrap voltage - -0.3 to 620 V

Maximum external capacitance between GL and PGND and
CGL, CGH FSW = 500 kHz(3) 3.9 nF
between GH and OUTb
Minimum external pull down resistance between GL and
RGL, RGH - 6.8 kΩ
PGND and GH and OUTb

DC @ TCB = 25 °C(4) (5) 4 A

ID Drain current DC @ TCB = 100 °C(4) (5) 2.6 A

Peak @ TCB = 25 °C(4) (5) (6) 7 A

SRout Half-bridge outputs slew rate (10% - 90%) - 100 V/ns

Vi Logic inputs voltage range - -0.3 to 21 V

TJ Junction temperature - -40 to 150 °C

Ts Storage temperature - -40 to 150 °C

1. PGND internally connected to SENSE.

2. OUTb internally connected to OUT
3. CGx < 0.08/(Pvcc^2*Fsw)-(330*10-12)
4. TCB is temperature of case exposed pad
5. Range estimated by characterization, not tested in production
6. Value specified by design factor, pulse duration limited to 50 µs and junction temperature

3.2 Recommended operating conditions

Table 3. Recommended operating conditions

Each voltage referred to GND unless otherwise specified
Symbol Parameter Note Min Max Unit

VS High voltage bus - 0 520 V

VCC Supply voltage - 4.75 9.5 V

PVCC-PGND PVCC to PGND Low side supply(1) - 4.75 6.5 V

DS13775 - Rev 1 page 4/26

 MASTERGAN5
Thermal data

Symbol Parameter Note Min Max Unit

PVCC-PGND PVCC to PGND Low side supply(1) Best performance 5 6.5 V
PVCC Low-side driver supply - 3 8.5 V
VCC-PVCC VCC to PVCC pin voltage - -3 3 V

PGND Low-side driver ground(1) - -2 2 V

DT Suggested minimum dead time - 5 - ns

TIN_MIN Minimum duration of input pulse to obtain undistorted output pulse(2) - 120 - ns

- 4.4 6.5 V
VBO BOOT to OUTb pin voltage(3)
Best performance 5 6.5 V

BOOT BOOT to GND voltage - 0(4) 530 V

Vi Logic inputs voltage range - 0 20 V

TJ Junction temperature - -40 125 °C

1. PGND internally connected to SENSE

2. See Logic inputs for more detail
3. OUTb internally connected to OUT
4. 5 V is recommended during High Side turn-on

3.3 Thermal data

Table 4. Thermal data

Symbol Parameter Value Unit

Rth(J-CB)_HS Thermal resistance of each transistor’s junction to relevant exposed pad, typical 4.7 °C/W

Rth(J-A) Thermal resistance junction-to-ambient(1) 18.8 °C/W

The junction to ambient thermal resistance is obtained simulating the device mounted on a 2s2p (4 layer) FR4
board as per JESD51-5,7 with 6 thermal vias for each exposed pad. Power dissipation is uniformly distributed
over the two GaN transistors.

DS13775 - Rev 1 page 5/26

 MASTERGAN5
Electrical characteristics

4 Electrical characteristics

4.1 Driver

Table 5. Driver electrical characteristics

VCC = PVCC = 6 V, SENSE = GND, TJ = 25 °C, unless otherwise specified
Each voltage referred to GND unless otherwise specified
Symbol - Parameter Test condition Min Typ Max Unit

Logic section supply

VCC UV turn ON
VCCthON - 4.2 4.5 4.75 V
threshold(1)
VCC UV turn
VCCthOFF - 3.9 4.2 4.5 V
OFF threshold(1)
VCC UV
VCChys - 0.2 0.3 0.45 V
hysteresis(1)
VCC
undervoltage VCC = PVCC = 3.
IQVCCU - 320 410 μA
VCC vs. quiescent supply 8V
GND current
SD/OD = LIN = 5
VCC quiescent V;
IQVCC - 680 900 μA
supply current HIN = 0 V;
BOOT = 7 V
SD/OD = 5 V;
VCC switching VBO = 6.5 V;
ISVCC - 0.8 - mA
supply current VS = 0 V;
FSW = 500 kHz

Low-side driver section supply

PVCC quiescent
IQPVCC SD/OD = LIN = 5 V - 150 - μA
supply current
PVCC vs.
PGND PVCC switching VS = 0 V
ISPVCC - 1.0 - mA
supply current FSW = 500 kHz

GL vs. Low side gate

RBLEED PVCC = PGND 75 100 125 kΩ
PGND bleeder
Low side turn on I(GL) = 1 mA
RONL - - 77 - Ω
resistance(2) (source)

Low side turn off

ROFFL - I(GL) = 1 mA (sink) - 2 - Ω
resistance(2)
High-side floating section supply
VBO UV turn ON
VBOthON - 3.6 4.0 4.4 V
threshold(3)
VBO UV turn OFF
VBOthOFF - 3.4 3.7 4.0 V
threshold (3)
BOOT vs.
OUTb VBO UV
VBOhys - 0.1 0.3 0.5 V
hysteresis(3)
VBO undervoltage
IQBOU quiescent supply VBO = 3.4 V - 140 200 μA
current(3)

DS13775 - Rev 1 page 6/26

 MASTERGAN5
Driver

Symbol - Parameter Test condition Min Typ Max Unit

VBO = 6 V;
BOOT vs. VBO quiescent LIN = GND;
IQBO - 180 - μA
OUTb supply current(3) SD/OD = HIN = 5
V;
VBO =6 V;
BOOT switching SD/OD = 5 V;
ISBO BOOT - 1.1 - mA
supply current VS = 0 V;
FSW = 500 kHz

BOOT vs. High voltage BOOT = OUT = 60

ILK - - 11 μA
SGND leakage current 0V
SD/OD = LIN = 5
V;
VCC vs. Bootstrap diode HIN = GND = PGN
RDBoot - 140 175 Ω
BOOT on-resistance(4) D
VCC –
BOOT = 0.5 V
High side turn on I(GH) = 1 mA
RONH - - 77 - Ω
resistance(2) (source)

High side turn off I(GH) = 1 mA

ROFFH - - 2 - Ω
resistance(2) (sink)

Logic inputs
TJ = 25 °C 1.1 1.31 1.45
Low level logic
Vil V
threshold voltage Full Temperature
0.8 - -
range(5)
TJ = 25 °C 2 2.17 2.5
LIN, HIN,
High level logic
Vih SD/OD V
threshold voltage Full Temperature
- - 2.7
range(5)
Logic input
Vihys threshold 0.7 0.96 1.2 V
hysteresis
Logic ‘1’ input
IINh LIN, HIN = 5 V 23 33 55 μA
bias current
Logic ‘0’ input
IINl LIN, HIN LIN, HIN = GND - - 1 μA
bias current
Input pull-down
RPD_IN LIN, HIN = 5 V 90 150 220 kΩ
resistor
Logic “1” input
ISDh SD/OD SD/OD = 5 V 11 15 20 μA
bias current
Logic “0” input
ISDl SD/OD SD/OD = 0 V - - 1 μA
bias current

Pull-down SD/OD = 5 V
RPD_SD SD/OD 250 330 450 kΩ
resistor OpenDrain OFF
Thermal
VTSD SD/OD shutdown unlatch TJ = 25 °C(6) 0.5 0.75 1 V
threshold

Open drain ON TJ = 25 °C;

RON_OD SD/OD 8 10 18 Ω
resistance IOD = 400 mV(6)

Open Drain low TJ = 25 °C;

IOL_OD SD/OD 22 40 50 mA
level sink current VOD = 400 mV(6)

Prop. delay from

Td_GL LIN, GL (6) - 46 - ns
LIN to GL

DS13775 - Rev 1 page 7/26

 MASTERGAN5
GaN power transistor

Symbol - Parameter Test condition Min Typ Max Unit

Prop. delay from

Td_GH HIN, GH (6) - 46 - ns
HIN to GH
Over temperature protection
Shut down
TTSD - (5) - 175 - °C
temperature
Temperature
THYS - (5) - 20 - °C
hysteresis

1. VCC UVLO is referred to VCC - GND

2. Turn on and turn off total resistances include the values of the gate resistors and the driver Rdson
3. VBO = VBOOT - VOUT
4. RBD(on) is tested in the following way
RBD(on) = [(VCC - VBOOTa) - (VCC - VBOOTb)] / [Ia - Ib]
Where: Ia is BOOT pin current when VBOOT = VBOOTa; Ib is BOOT pin current when VBOOT = VBOOTb
5. Range estimated by characterization, not tested in production
6. Tested at wafer level

4.2 GaN power transistor

Table 6. GaN power transistor electrical characteristics

VGS = 6 V; TJ = 25 °C, unless otherwise specified.
Symbol Parameter Test condition Min Typ Max Unit

GaN on/off states

IDSS < 6.6 µA(1)

V(BR)DS Drain-source blocking voltage 650 - - V
VGS = 0 V

VDS = 600 V
IDSS Zero gate voltage drain current - 0.3 - µA
VGS = 0 V

VDS = VGS
VGS( th ) Gate threshold voltage - 1.7 - V
ID = 1.7 mA(1)

IGS Gate to source current VDS = 0 V(2) - 20 - µA

TJ = 25°C - 450 600

RDS( on) Static drain-source on-resistance ID = 1.2 A mΩ
TJ = 125°C (2) - 1012 -

1. Tested at wafer level

2. Range estimated by characterization, not tested in production

DS13775 - Rev 1 page 8/26

 MASTERGAN5
Device characterization values

5 Device characterization values

The information in Table 7 and Table 8 represent typical values based on characterization and simulation results
and are not tested in production.

Table 7. GaN power transistor characterization values (each transistor)

Symbol Parameter Test condition Min Typ Max Unit

VGS = 6 V, TJ = 25 °C
QG Total gate charge - 0.8 - nC
VDS = 0 to 400 V

QOSS Output charge - 7 - nC

EOSS Output Capacitance stored energy VGS = 0 V, VDS = 400 V - 0.9 - µJ

COSS Output capacitance - 7 - pF

CO(ER) Effective output capacitance energy related(1) - 11 - pF

VGS = 0 V, VDS = 0 to 400 V
CO(TR) Effective output capacitance time related(2) - 17 - pF

QRR Reverse recovery charge - - 0 - nC

IRRM Reverse recovery current - - 0 - A

1. CO(ER) is the fixed capacitance that would give the same stored energy as COSS while VDS is rising from 0 V to the stated
VDS
2. CO(TR) is the fixed capacitance that would give the same charging time as COSS while VDS is rising from 0 V to the stated
VDS

Table 8. Inductive load switching characteristics

Symbol Parameter Test condition Min Typ Max Unit

t(on)(1) Turn-on time - 70 - ns

tC(on)(2) Crossover time (on) - 25 - ns

VS = 400 V,
(2)
t(off) Turn-off time - 70 - ns
VGS = 6 V,
tC(off)(1) Crossover time (off) - 10 - ns
ID = 1.2 A
tSD Shutdown to high/low-side propagation delay - 70 - ns
See Figure 3
Eon Turn-on switching losses - 4.5 - µJ

Eoff Turn-off switching losses - 2.5 - µJ

1. t(on) and t(off) include the propagation delay time of the internal driver and GaN Turn on time
2. tC (on) and tC (off) are the switching times of GaN transistor itself under the internally given gate driving conditions

DS13775 - Rev 1 page 9/26

 MASTERGAN5
Device characterization values

Figure 3. Switching time definition

VDS ID ID VDS

10%ID 10%VDS 10%ID

10%VDS

t(ON) tC(OFF)
VIN
VIN t(OFF)
tC(ON)

(a) turn-on (b) turn-off

Figure 4. Typ ID vs VDS at TJ=25°C Figure 5. Typ ID vs VDS at TJ=125°C

10 5.0
TJ=25°C TJ=125°C
9 4.5
VGS=6V VGS=6V
8 4.0
VGS=5V VGS=5V
7 3.5

6 VGS=4V 3.0 VGS=4V

ID (A)

ID (A)

5 2.5

4 2.0

3 1.5

2 1.0

1 0.5

0 0
0 1 2 3 4 5 0 1 2 3 4 5
VDS (V) VDS (V)

DS13775 - Rev 1 page 10/26

 MASTERGAN5
Device characterization values

Figure 6. Typ RDS(ON) vs ID at TJ=25°C Figure 7. Typ RDS(ON) vs ID at TJ=125°C

0.8 1.6
TJ=25°C TJ=125°C
4V
1.5 4V
0.75

0.7 1.4

0.65 1.3
5V

RDS(on) (Ω)
RDS(on) (Ω)

5V
0.6 1.2

6V
6V
0.55 1.1

0.5 1

0.45 0.9

0.4 0.8
0 1 2 3 4 5 6 7 8 9 10 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
ID (A) ID (A)

Figure 8. Typ ID(ON) vs VDS Figure 9. Typ RDS(ON)_x vs TJ, normalized at 25°C

3.0

10
VGS=6V
Normalized RDS(on) (1 at 25°C)

9 TJ=25°C 2.5

8
TJ=50°C

7 2.0
TJ=75°C
6
ID (A)

TJ=100°C
5 1.5
TJ=125°C

3 1.0

1 0.5

0
0 1 2 3 4 5
0
VDS (V) -50 -10 30 70 110 150
Temperature (°C)

DS13775 - Rev 1 page 11/26

 MASTERGAN5
Device characterization values

Figure 10. Typ ISD vs VSD, at TJ=25°C Figure 11. Typ ISD vs VSD, at TJ=125°C

20 10
TJ=25°C TJ=125°C
18 9

16 8
VGS=6V
VGS=6V
14 7

12 6
IS (A)

IS (A)
VGS=0V VGS=0V
10 5

8 4

6 3
4 2
2 1
0 0
0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5 6 7 8 9 10
VSD (V) VSD (V)

Figure 12. Safe Operating Area at TJ=25°C Figure 13. Typ Gate Charge at TJ=25°C

7
400 V
10 0.2 μs 6 100 V

50 μs
1 4
VGS (V)
Id (A)

DC
0.1 2

0.01 0
1 10 100 1000 0 0.2 0.4 0.6 0.8 1
Vds (V) QG (nC)

DS13775 - Rev 1 page 12/26

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Logic inputs

Figure 14. Derating Curve

Figure 15. Typ RDboot vs TJ
35
300

30
250

25
200

RDBoot (ohm)
20
PDISS (W)

150
15

100
10

50
5

0
0 -50 -10 30 70 110 150
0 25 50 75 100 125 150
Temperature (°C)
TCB (°C)

5.1 Logic inputs

The MASTERGAN5 features a half-bridge gate driver with three logic inputs to control the internal high-side and
low-side GaN transistors.
The devices are controlled through following logic inputs:
• SD/OD: Shut-down input, active low;
• LIN: low-side driver inputs, active high;
• HIN: high-side driver inputs, active high.

Table 9. Inputs truth table (applicable when device is not in UVLO)

Input pins GaN transistors status

SD/OD LIN HIN LS HS

L X(1) X(1) OFF OFF

H L L OFF OFF
H L H OFF ON
H H L ON OFF

H H(2) H(2) OFF OFF

1. X: Don’t care
2. Interlocking

The logic inputs have internal pull-down resistors. The purpose of these resistors is to set a proper logic level in
case, for example, there is an interruption in the logic lines or the controller outputs are in tri-state conditions.
If logic inputs are left floating, the gate driver outputs are set to low level and the corresponding GaN transistors
are turned off.
The minimum duration of the on time of the pulses applied to LIN is TIN_MIN = 120ns; shorter pulses could be
either extended to TIN_MIN or blanked, if shorter than 30ns (typ). Minimum duration of the off time of the pulses
applied to LIN is 60ns or could be blanked if they are shorter.

DS13775 - Rev 1 page 13/26

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Bootstrap structure

The minimum duration of the off time of the pulses applied to HIN is TIN_MIN = 120ns; shorter pulses shall be
either extended to TIN_MIN or blanked, if shorter than 30ns (typ). Minimum duration of the on time of the pulses
applied to HIN is 60ns or could be blanked if they are shorter.
Interlocking feature interrupts running TIN_MIN to avoid unexpected cross-conduction.
Matched, short propagation delay between low side and high side are there.

5.2 Bootstrap structure

Bootstrap circuitry is typically used to supply the high-voltage section. MASTERGAN5 integrates this structure by
means of a patented integrated high-voltage DMOS to reduce the external components.
The Boostrap integrated circuit is connected to VCC pin and is driven synchronously with the low-side driver.
The use of an external bootstrap diode in parallel to the integrated structure is possible, especially when the
operating frequency is generally higher than 500 kHz.

5.3 VCC supply pins and UVLO function

The VCC pin supplies current to the logic circuit, level-shifters in the low-side section and the integrated bootstrap
diode.
The PVCC pin supplies low-side output buffer. During outputs commutations the average current used to provide
gate charge to the high-side and low-side GaN transistors flow through this pin.
The PVCC pin can be connected either to the same supply voltage of the VCC pin or to a separated voltage
source. In case the same voltage source is used, it is suggested to connect VCC and PVCC pins by means of
a small decoupling resistance. The use of dedicated bypass ceramic capacitors located as close as possible to
each supply pin is highly recommended.
The MASTERGAN5 VCC supply voltage is continuously monitored by under-voltage lockout (UVLO) circuitry that
turns the high-side and low-side GaN transistors off when the supply voltage goes below the VCC_thOFF threshold.
The UVLO circuitry turns on the GaN, accordingly to LIN and HIN status, approximately 20µs (typ) after the
supply voltage goes above the VCCthON voltage. A VCChys hysteresis is provided for noise rejection purposes.

Figure 16. VCC UVLO and Low Side

VCCthON
VCCthOFF

VCC = PVCC 0V
VCC rise
UVLO VCC

LIN 0V

PVCC

GL-PGND 0V

5.4 VBO UVLO protection

Dedicated under-voltage protection is available on the bootstrap section between BOOT and OUTb supply pins.
In order to avoid intermittent operation, a hysteresis set the turn-off threshold with respect to the turn-on threshold.
When the VBO voltage falls below the VBOthOFF threshold, the high-side GaN transistor is switched off.
Approximately 5µs (typ) after the VBO voltage reaches the VBOthON threshold, the device returns to normal
operation and the output remains off until the next input pin transition that requests the high-side to turn on.

DS13775 - Rev 1 page 14/26

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Thermal shutdown

Figure 17. VBO UVLO and High Side

VCCthON
VCCthOFF

VCC 0V

VBOthON
VBOthOFF
VBO
0V
UVLO VBO
VBO rise

HIN 0V

VBO
(GH-OUTB)
0V

5.5 Thermal shutdown

The integrated gate driver has a thermal shutdown protection.
When junction temperature reaches the TTSD temperature threshold, the device turns off both GaN transistors
leaving the half-bridge in 3-state and signaling the state forcing SD/OD pin low. SD/OD pin is released when
junction temperature is below TTSD-THYS and SD/OD is below VTSD.
GaN are driven again according to inputs when SD/OD rise above Vih.
The thermal smart shutdown system gives the possibility to increase the time constant of the external RC network
(that determines the disable time after the overtemperature event) up to very large values without delaying the
protection.

DS13775 - Rev 1 page 15/26

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Thermal shutdown

Figure 18. Thermal Shutdown timing waveform

T TSD
TJ

T TSD - T HYS

Fast shut down

GH/GL the driver outputs are switched off
immediately after overtemperature

SD/OD
VOD

Vih
VTSD
0V
1
OD gate 2
(internal)
t1 t2
disable time

THERMAL SHUTDOWN CIRCUIT

VPU

ROD_ext
FROM / TO SD/OD
CONTROLLER
THERMAL
COD RPD_SD RON_OD
SHUTDOWN
LOGIC

DS13775 - Rev 1 page 16/26

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Typical application diagrams

6 Typical application diagrams

Figure 19. Typical application diagram – Resonant LLC converter

H.V.
CBOOT

BOOT OUTb GH VS
VCC VCC
+ CbuS
VCC UVLO
CVCC
Vbo
HON RGONH
UVLO
FROM/TO CONTROLLER HIN
R Level Shifter
Driver
VOUT
C HOFF
RGOFFH
FROM/TO CONTROLLER LIN Logic, OUT
R interlocking,
C overtemp

SD/OD
VPU
LON RGON L
FROM/TO CONTROLLER
Level Shifter Driver
R
COD LOFF
RGOFFL
GND R BLEED

PVCC PGND GL SENSE

VCC

CPVCC

Figure 20. Typical application diagram – Active clamp flyback

H.V.

CBOOT CC
VOUT

BOOT OUTb GH VS
VCC VCC
+ CbuS
VCC UVLO
CVCC
Vbo
HON RGONH
UVLO

FROM/TO CONTROLLER HIN Driver

R Level Shifter
C HOFF
RGOFFH
FROM/TO CONTROLLER LIN Logic, OUT
R interlocking,
C overtemp

SD/OD
VPU
LON RGONL
FROM/TO CONTROLLER
Level Shifter Driver
R
COD LOFF
RGOFFL
GND R BLEED

PVCC PGND GL SENSE

VCC

CPVCC
TO CONTROLLER

DS13775 - Rev 1 page 17/26

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Package information

7 Package information

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages,
depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product
status are available at: www.st.com. ECOPACK is an ST trademark.

7.1 QFN 9 x 9 x 1 mm, 31 leads, pitch 0.6 mm package information

Table 10. QFN 9 x 9 x 1 mm package dimensions

Dimensions (mm)
Symbol
Min. Typ. Max.

A 0.90 0.95 1.00

A3 - 0.10 -
b 0.25 0.30 0.35
D 8.96 9.00 9.04
E 8.96 9.00 9.04
D1 3.30 3.40 3.50
E1 2.06 2.16 2.26
D2 1.76 1.86 1.96
E2 3.10 3.20 3.30
D3 1.70 1.80 1.90
E3 3.10 3.20 3.30
e - 0.60 -
K - 0.24 -
L 0.35 0.45 0.55
N 31
aaa 0.10
bbb 0.10
ccc 0.10
ddd 0.05
eee 0.08

Note: • Dimensioning and tolerances conform to ASME Y14.5-2009

• All dimensions are in millimeters
• N total number of terminals
• Dimensions do not include mold protrusion, not to exceed 0.15 mm
• Package outline exclusive of metal burr dimensions

DS13775 - Rev 1 page 18/26

 MASTERGAN5
QFN 9 x 9 x 1 mm, 31 leads, pitch 0.6 mm package information

Figure 21. QFN 9 x 9 x 1 mm package dimensions

BOTTOM VIEW

SIDE
VIEW

TOP VIEW

DS13775 - Rev 1 page 19/26

 MASTERGAN5
Suggested footprint

8 Suggested footprint

The MASTERGAN5 footprint for the PCB layout is usually defined based on several design factors as assembly
plant technology capabilities and board component density. For easy device usage and evaluation, ST provides
the following footprint design, which is suitable for the largest variety of PCBs.
The following footprint indicates the copper area which should be free from the solder mask,
while the copper area shall extend beyond the indicated areas especially for EP2 and EP3. To aid thermal
dissipation, it is recommended to add thermal vias under these EPADs to transfer and dissipate device heat to the
other PCB copper layers. A PCB layout example is available with the MASTERGAN5 evaluation board.

Figure 22. Suggested footprint (top view drawing)

TOP VIEW
Dimensions in mm

DS13775 - Rev 1 page 20/26

 MASTERGAN5
Ordering information

9 Ordering information

Table 11. Order codes

Order code Package Package Marking Packaging

MASTERGAN5 QFN 9 x 9 x 1 mm MASTERGAN5 Tray

MASTERGAN5TR QFN 9 x 9 x 1 mm MASTERGAN5 Tape and Reel

DS13775 - Rev 1 page 21/26

 MASTERGAN5

Revision history

Table 12. Document revision history

Date Version Changes

26-Jul-2021 1 Initial release.

DS13775 - Rev 1 page 22/26

 MASTERGAN5
Contents

Contents
1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
2 Pin descriptions and connection diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.1 Pin list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

3 Electrical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
3.1 Absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3.2 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3.3 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

4 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4.1 Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4.2 GaN power transistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

5 Device characterization values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

5.1 Logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.2 Bootstrap structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.3 VCC supply pins and UVLO function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.4 VBO UVLO protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5.5 Thermal shutdown. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

6 Typical application diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

7 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
7.1 [Package name] package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

8 Suggested footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

9 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
List of tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
List of figures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

DS13775 - Rev 1 page 23/26

 MASTERGAN5
List of tables

List of tables
Table 1. Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Table 2. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Table 3. Recommended operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Table 4. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 5. Driver electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 6. GaN power transistor electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 7. GaN power transistor characterization values (each transistor) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 8. Inductive load switching characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 9. Inputs truth table (applicable when device is not in UVLO). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 10. QFN 9 x 9 x 1 mm package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 11. Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 12. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

DS13775 - Rev 1 page 24/26

 MASTERGAN5
List of figures

List of figures
Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Figure 2. Pin connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Figure 3. Switching time definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 4. Typ ID vs VDS at TJ=25°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 5. Typ ID vs VDS at TJ=125°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 6. Typ RDS(ON) vs ID at TJ=25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 7. Typ RDS(ON) vs ID at TJ=125°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 8. Typ ID(ON) vs VDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 9. Typ RDS(ON)_x vs TJ, normalized at 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 10. Typ ISD vs VSD, at TJ=25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 11. Typ ISD vs VSD, at TJ=125°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 12. Safe Operating Area at TJ=25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 13. Typ Gate Charge at TJ=25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 14. Derating Curve . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 15. Typ RDboot vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 16. VCC UVLO and Low Side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 17. VBO UVLO and High Side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 18. Thermal Shutdown timing waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 19. Typical application diagram – Resonant LLC converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 20. Typical application diagram – Active clamp flyback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 21. QFN 9 x 9 x 1 mm package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 22. Suggested footprint (top view drawing) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

DS13775 - Rev 1 page 25/26

 MASTERGAN5

IMPORTANT NOTICE – PLEASE READ CAREFULLY

STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST
products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST
products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of
Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. For additional information about ST trademarks, please refer to www.st.com/trademarks. All other product or service
names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2021 STMicroelectronics – All rights reserved

DS13775 - Rev 1 page 26/26