Digital Electronics

EEE211
Lecture 9

Dr Atiqur Rahman
Dept. of Electrical and Computer Engineering
North South University
 Combinational Logic
• Logic circuits for digital systems may be
combinational
sequential
• A combinational circuit consists of input variables, logic
gates, and output variables.

2
 Analysis procedure
• To obtain the output Boolean functions from a logic
diagram, proceed as follows:
1. Label all gate outputs that are a function of input variables with
arbitrary symbols. Determine the Boolean functions for each
gate output.
2. Label the gates that are a function of input variables and
previously labeled gates with other arbitrary symbols. Find the
Boolean functions for these gates.
3. Repeat the process outlined in step 2 until the outputs of the
circuit are obtained.
4. By repeated substitution of previously defined functions, obtain
the output Boolean functions in terms of input variables.
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 Example
F2 = AB + AC + BC; T1 = A + B + C; T2 = ABC; T3 = F2’T1;
F1 = T3 + T2
F1 = T3 + T2 = F2’T1 + ABC = A’BC’ + A’B’C + AB’C’ + ABC

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 Combinational Logic Design

• A process with 5 steps

– Specification
– Formulation
– Optimization
– Technology mapping
– Verification
• 1st three steps and last best illustrated by
example

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 Specifications
• Write a specification for the circuits
• Specification includes
– What are the inputs: how many, how many bits in a given
output, how are they grouped,, are they control, are they
active high?
– What are the outputs: how many and how many bits in a
each, active high, active low, tristate output?
– The functional operation that takes place in the chip, i.e., for
given inputs what will appear on the outputs.

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 Formulation step
• Convert the specifications into a variety forms for
optimal implementation.
– Possible forms
• Truth Tables
• Expressions
• K-maps
• Binary Decision Diagrams
• IF THE SPECIFCATION IS ERRONOUS OR INCOMPLETE
(open for various interpretation) then the circuit will
perform as specified but will not perform as desired.
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 Last 3 steps

• Best illustrated by example

– A BCD to Excess-3 code converter
– BCD-to-7-segment decoder

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 BCD-to-Excess-3 Code converter
• BCD is a code for the decimal digits 0-9
• Excess-3 is also a code for the decimal digits

A B C D W X Y Z

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 Design Procedure for BCD-to-Excess3
• Specification:
– Inputs: a BCD input, A,B,C,D with A as the most significant bit
and D as the least significant bit.
– Outputs: an Excess-3 output W,X,Y,Z that corresponds to the
BCD input.
– Internal operation – circuit to do the conversion in
combinational logic.
• Formulation
– Excess-3 code is easily formed by adding a binary 3 to the
binary or BCD for the digit.
– There are 16 possible inputs for both BCD and Excess-3.
– It can be assumed that only valid BCD inputs will appear so
the six combinations not used can be treated as don’t cares. 10
 Optimization – BCD-to-Excess-3
Lay out K-maps for each output, W X Y Z
X
W

Y Z

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 Expressions for W X Y Z

• W(A,B,C,D) = Σm(5,6,7,8,9) + d(10,11,12,13,14,15)

• X(A,B,C,D) = Σm(1,2,3,4,9) + d(10,11,12,13,14,15)

• Y(A,B,C,D) = Σm(0,3,4,7,8) + d(10,11,12,13,14,15)

• Z(A,B,C,D) = Σm(0,2,4,6,8) + d(10,11,12,13,14,15)

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 Minimize K-Maps

• Y minimization • Z minimization
Y = CD + C’D’ Z = D’
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 Minimize K-Maps

• W minimization • X minimization
W = A + BC + BD X = BC’D’+B’C+B’D
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 Two level circuit implementation
• Have equations
W = A + BC + BD = A + B(C+D)
X = B’C + B’D + BC’D’ = B’(C+D) + BC’D’
Y = CD + C’D’
Z = D’

• Factoring out (C+D) and call it T

• Then T’ = (C+D)’ = C’D’
W = A + BT
X = B’T + BT’
Y = CD + T’
Z = D’

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 Create the digital circuit

• Implementing the second set of equations where

T=C+D results in a lower gate count.
• This gate has a fanout of 3 16
 BCD-to-Seven-Segment Decoder
• Specification
– Digital readouts on many digital products often use
LED seven-segment displays.
– Each digit is created by lighting the appropriate
segments. The segments are labeled a,b,c,d,e,f,g
– The decoder takes a BCD input and outputs the
correct code for the seven-segment display.

• Formulation
– Input: A 4-bit binary value that is a BCD coded input.
– Outputs: 7 bits, a through g for each of the
segments of the display.
– Operation: Decode the input to activate the correct
segments.
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 Formulation
• Construct a truth table

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 Optimization
• Create a K-map for each output and get
a = A’C+A’BD+B’C’D’+AB’C’
b = A’B’+A’C’D’+A’CD+AB’C’
c = A’B+A’D+B’C’D’+AB’C’
d = A’CD’+A’B’C+B’C’D’+AB’C’+A’BC’D
e = A’CD’+B’C’D’
f = A’BC’+A’C’D’+A’BD’+AB’C’
g = A’CD’+A’B’C+A’BC’+AB’C’

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 Note on implementation

• Direct implementation would require 27 AND gates

and 7 OR gates

• By sharing terms, can actualize and implementation

with 14 less gates.

• Normally decoder in a device name indicates that the

number of outputs is less than the number of inputs.

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 Binary Adder-Subtractor
• A combinational circuit that performs the addition of two bits is
called a half adder.
• The truth table for the half adder is listed below:
Truth Table – Half Adder
Sum, S = x’y + xy’

Carry C = xy

Sum, S = x  y

Carry C = xy
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 Full-Adder
• Performs the addition of three bits (two significant bits and a
previous carry) S

S=X’Y’Z+X’YZ’+XY’Z’+XYZ
= X  Y  Z
= (X  Y)  Z
C
C = XY +XY’Z +X’YZ
= XY +Z(XY’+X’Y)
= XY + Z(X  Y) 22
 Full adder Implementation
Using SOP

S C

Using two half adders and one OR gate (Carry Look-Ahead adder)

X S
Y

Z C 23