Functions SDRAM DDR DDR2 DDR3 DDR4

Prefetch 1 - Bit 2 - Bit 4 - Bit 8 - Bit 8-Bit per Bank

Data 100 - 166 266 - 400 533 - 800 1066 - 1600 2133-3200
Rate(MT/s)
Transfer 0.8 - 1.3 2.1 - 3.2 4.2 - 6.4 8.5 - 14.9 17 - 25.6
Rate(GB/s)
Voltage(V) 3.3V 2.5-2.6 1.8 1.35 - 1.5 1.2

logic [0:7] a, b; parameter [0:7] mask;

covergroup cg;
coverpoint a
{
bins high = {[128:255]};
bins low[] = {[0:127]};
}

coverpoint b
{
binsthree[]=bwith(item%3==0);
bins two[] = b with (item % 2 == 0);
}

X: cross a,b
{
bins apple = X with (a+b < 257) matches 127;
bins cherry = ( binsof(b) intersect {[0:50]} && binsof(a.low) intersect
{[0:50]}) with (a==b) );
bins plum = binsof(b.two) with (b > 12) || binsof(a.low) with (a & b &
mask);
}
endgroup

covergroup example

cp_var_1 : coverpoint var_1 {

bins value[] = {[1:4]};

bins value_5_7 = {[5:7]};

bins value_8 = {8};

bins value_9 = {9};

bins value_10 = {10};

bins value_11 = {11};

bins value_12_15 = {[12:15]};

bins value_16 = {16};

bins value_[] = {[17:32]};

cp_var_2 : coverpoint var_2 {

bins value[] = {[1:4]};

bins value_5_7 = {[5:7]};

bins value_8 = {8};

bins value_9 = {9};

bins value_10 = {10};

bins value_11 = {11};

bins value_12_15 = {[12:15]};

bins value_16 = {16};

bins value_[] = {[17:32]};

cp_var_3 : covepoint var_3 {

bins value[] = {0,2};

cp_var_4 : covepoint var_4 {

bins value[] = {0,2};

cx_cross_4_coverpoints : cp_var_1, cp_var_2, cp_var_3, cp_var_4 {

ignore_bins ig1_var_3_x_cp_var_4 = binsof(cp_var_3) intersect{0} && binsof(cp_var_4) intersect {0};

ignore_bins ig2_var_3_x_cp_var_4 = binsof(cp_var_3) intersect{2} && binsof(cp_var_4) intersect {2};
ignore_bins ig3_var_3_x_cp_var_4 = binsof(cp_var_3) intersect{0} && binsof(cp_var_4) intersect {2};

illegal_bins cp1_x_cp2_greater_than_256 = cx_cross_4_coverpoints with (((cp_var_1+1)/2*2) *

((cp_var_2+3)/4*4) > 256); }

endgroup

covergroup cg; a:

coverpoint v_a {

bins aa = {[1:10]

};

bins aaa = {[12:20]};

bins a1[] = {[2:27]};

bins a2[] = {[28:37]};

bins a3[] = {[38:47]}; ....

bins ax[] = {[1:20]};}

b: coverpoint v_a {

bins b1[] = {[2:27]};

bins b2[] = {[28:37]};

c1: cross a,b {ignore_bins ib = ! binsof(a.a1) || ! binsof(b) intersect {[3:6]};}

endgroup // cg

Variable a toggled in the range of 100 to 500 cycles . How do you come up with coverage for this?

[10:49 AM] Priya Ananthakrishnan

There are 2 clocks in your design.
Reference clock (CLKref) - 40 Mhz frequency. Frequency is constant over all voltage corners and it
is with 50% duty cycle.
Core clock (core_clk) : variable frequency depending on the Voltage corner.
Frequency = 800 Mhz. - OD corner (overdrive corner)
Frequency = 600 Mhz - NM corner (nominal corner)
Frequency = 400 Mhz - UD corner (underdrive corner)
Write a small Verilog code to determine the voltage corner in which your simulation is running.

 Write code for clock generation

1. Frequency - 1GHz
2. what is the duty cycle?
3. Rewrite clk generation for duty cycle 70%

 Write checker to verify Clock frequency, for every cycle

[10:36 AM] Priya Ananthakrishnan

class ABC;
int x;
task abc();
for(x=0;x<4;x++)
begin
$display("X Value %0d",x);
end
$display("X1 Value %0d",x);
endtask
endclass:ABC
What will be the output of the X ?

star 1

[10:40 AM] Gaurav Singh

X= 0,1,2,3 and X1 =4

.Assign a value to reg logic wire inside a module

[Yesterday 11:09 AM] Priya Ananthakrishnan

. Variable a toggled in the range of 100 to 500 cycles . How do you come up with coverage for this?
[Yesterday 11:09 AM] Priya Ananthakrishnan

write a coverage for the sequence 1110101

[Yesterday 11:15 AM] Zarna Patel

Priya Ananthakrishnan

. Variable a toggled in the range of 100 to 500 cycles . How do you come up with coverage for this?

covergroup cg;

b : covepoint b_1 {
bins value[] = {100:500};
}

c: cross a,b
{
binsof(a) intersect{b};
}
endgroup

covergroup example cp_var_1 : coverpoint var_1 { bins value[] = {[1:4]}; bins value_5_7 = {[5:7]}; bins
value_8 = {8}; bins value_9 = {9}; bins value_10 = {10}; bins value_11 = {11}; bins value_12_15 =
{[12:15]}; bins value_16 = {16}; bins value_[] = {[17:32]}; } cp_var_2 : coverpoint var_2 { bins value[] =
{[1:4]}; bins value_5_7 = {[5:7]}; bins value_8 = {8}; bins value_9 = {9}; bins value_10 = {10}; bins
value_11 = {11}; bins value_12_15 = {[12:15]}; bins value_16 = {16}; bins value_[] = {[17:32]}; }
cp_var_3 : covepoint var_3 { bins value[] = {0,2}; } cp_var_4 : covepoint var_4 { bins value[] = {0,2}; }
cx_cross_4_coverpoints : cp_var_1, cp_var_2, cp_var_3, cp_var_4 { ignore_bins ig1_var_3_x_cp_var_4 =
binsof(cp_var_3) intersect{0} && binsof(cp_var_4) intersect {0}; ignore_bins ig2_var_3_x_cp_var_4 =
binsof(cp_var_3) intersect{2} && binsof(cp_var_4) intersect {2}; ignore_bins ig3_var_3_x_cp_var_4 =
binsof(cp_var_3) intersect{0} && binsof(cp_var_4) intersect {2}; illegal_bins
cp1_x_cp2_greater_than_256 = cx_cross_4_coverpoints with (((cp_var_1+1)/2*2) * ((cp_var_2+3)/4*4)
> 256); } endgroup

To check coverage

while (c.get_inst_coverage!=100.00)

bit [3:0] data;

covergroup cg;

c1: coverpoint data {

bins d1[] = (9 => 3);

 bins d2[] = (4 => 8 => 12);

bins d3[] = (2,3 => 4,5);

bins d4[] = (2,3,4 => 5,6,7);

bins d5[] = (4'hd[*2] => 5,6,7);

bins d6[] = (7[*2:4]);

bins d7 = (9 => 5[->3] => 11);

bins d8 = (12 => 15[=3] => 10);

endgroup: cg

bit [3:0] data ; covergroup DATA ; wild: coverpoint ( data ) { wildcard

bins trans[] = ( [ 4'b000? : 4'b001? ] => [ 4'b110? : 4'b111? ] ) ; // Legal ?
wildcard bins val[] = { [ 4'b000? : 4'b001? ] } ; // Legal ? } endgroup

int var_a;
covergroup test_cg @(posedge clk);
cp_a: coverpoint var_a {
bins low = {0,1};
bins other[] = default; }
endgroup

What can be wrong with following coverage code?

bins a = (3[*3:5]); bins b[ ] = (3[*3:5]);

Assume a cache that has 32 sets and 4 ways and each line has a valid bit associated with it
▪Create Coverage for following conditions
▪Cache hits and miss based on a cacheHit signal == 0 0r 1
▪All ways in a set are getting cache hits
▪Cache miss happening when a set is full
▪At least 2 back to back cache hits and misses happening
▪Alternate cache hit and miss happening

bins b4[] = {[79:99],[110:130],140}

i have two signals address 16 bit and dat 32 bit write a cover group and sample them at the
posedge of clock

bit [2:0] a,b;

covergroup cg;

cross a,b;

endmgroup

cp_BxEvents: cross cp_B , cp_events

{
bins BxEvent3 = binsof( cp_events ) intersect { 3 } ;

bins BxEvent4 = binsof( cp_events ) intersect { 4 } ;

bins BxEvent5 = binsof( cp_events ) intersect { 5 } ;

}

int gen_mult_audio_hdrs;
int ado_hdr_size=1; //1hdr
int ado_cksum_size=1; //1hdr
rand int unsigned num_of_ado_hdrs;
rand int unsigned data_len_q[$];
rand bit[7:0] rec_type;

constraint c_mult_hdr
{
if(gen_mult_audio_hdrs)
{
foreach(data_len_q[i])
{
data_len_q[i] >0;
}
[b]//num_of_ado_hdrs == 2;[/b]
data_len_q.size() == num_of_ado_hdrs;
len-3 == (num_of_ado_hdrs * ado_hdr_size ) + data_len_q.sum()
+ ado_cksum_size;
len inside { [9:12] }; //6 is minimum =(3ucom hdr) -2 (aud
hdr+chksum) = 1 (data waord)
solve num_of_ado_hdrs before data_len_q.size;

}
}

class base;
rand bit [1:0]var1;
rand bit [3:0] var2;
rand bit var3;
constraint cnt1 {soft var1 inside {2,3};
(var1==2) -> (var2==0 && var3==0);
solve var1 before var2;}
endclass

module my_module;
 base obj;
initial begin
obj=new();
repeat(10) begin
obj.randomize();
$display("var1=%d,var2=%d,var3=%d",obj.var1,obj.var2,obj.var3);
end
end

class C; rand int q[]; rand int wsize; randc int index; //int
queue[$urandom_range(queue.size()-1)]; constraint select { wsize inside
{[0:10]}; q.size() == wsize; index inside{[0:q.size()-1]}; } endclass
module DA; initial begin C c; c = new(); if(c.randomize()) $info("randc
success"); else $error("fail"); foreach(c.q[i]) $display("Randc:%0d",
c.q[i]); end endmodule

Test paper:-
v

Rakesh kumar
9:33 PM
{ << 4 { 6'b11_0101 }}
{ << { 8'b0011_0101 }}
Rakesh kumar
9:35 PM
int j = { "A", "B", "C", "D" }; { >> {j}} // generates stream "A" "B" "C" "D" { << byte {j}} // generates stream "D" "C" "B"
"A" (little endian) { << 16 {j}} // generates stream "C" "D" "A" "B" { << { 8'b0011_0101 }} // generates stream
'b1010_1100 (bit reverse) { << 4 { 6'b11_0101 }} // generates stream 'b0101_11 { >> 4 { 6'b11_0101 }} // generates
stream 'b1101_01 (same) { << 2 { { << { 4'b1101 }} }} // generates stream 'b1110
Google
[10:04 AM] Priya Ananthakrishnan

. write a function to multiply two inputs a,b with out using any * or MUL function or operator

star 1

[10:05 AM] Priya Ananthakrishnan

. function to write read read/write, read only, write only and resevered bit and compare

star 1

Qualcomm

100 write and 100 read packets are sent to DUT.driver has given item_done indication but read
packets are dropped in

scoreboard. What you do for this scenario?

How to randomize a variable that is not declared as rand or randc?

Please explain with an example.

How to add 2 elements of two different arrays array with out using array functions

Rambus

Given the input that array1 ={1,2,3,4} and output that array2 = {7,9,1,2,3,4}.you want to get
the input is same as output.how will you compare the logic that {7 and 9} should not consider
and compare the logic?

Write a code for array = {7,9,1,3,5,6,2} in ascending order without using sort() method?

Can the UVM run_phase run in parallel to any other phase? Which phase?