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Apb Protocol

The document describes an APB protocol module that defines the state machine and logic for Address/Data Phase operations. It contains a design module that implements the protocol states (idle, setup, access) and logic to read/write data based on control signals. A test bench is provided to simulate writes to two addresses and a subsequent read back of the first address, verifying the correct operation of the protocol.

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30 views6 pages

Apb Protocol

The document describes an APB protocol module that defines the state machine and logic for Address/Data Phase operations. It contains a design module that implements the protocol states (idle, setup, access) and logic to read/write data based on control signals. A test bench is provided to simulate writes to two addresses and a subsequent read back of the first address, verifying the correct operation of the protocol.

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SUDHEER S
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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APB PROTOCOL

DESIGN:
module apb_protocol (PCLK,PRESETn,PADDR,PWRITE,PSEL,PENABLE,PWDATA,PRDATA,PREADY);

input PCLK;

input PRESETn;
input PSEL;
input [31:0]PADDR;

input PWRITE;

input PENABLE;
input [31:0]PWDATA;

input PREADY;

output reg [31:0]PRDATA;

reg [31:0]array[31:0];

parameter [1:0] idle_mode =2'b00;

parameter [1:0] setup_mode =2'b01;

parameter [1:0] acess_mode =2'b10;

reg [1:0] present_state,next_state;

always @(posedge PCLK or posedge PRESETn)

begin

if(PRESETn)

present_state <= idle_mode;


else
present_state <= next_state;

end
always@(*)
begin

case(present_state)

idle_mode:begin
if(PSEL && !PENABLE)

next_state <= setup_mode;


else

next_state <=idle_mode;

end

setup_mode:begin
if (PSEL && PENABLE)

next_state <=acess_mode;

else

next_state <=idle_mode;
end

acess_mode:begin

if (!PSEL && !PENABLE && PREADY)


next_state <=idle_mode;

else if (PSEL && !PENABLE && PREADY)

next_state <= setup_mode;


else if (PSEL && PENABLE && !PREADY)

next_state <= acess_mode;

else

next_state <= idle_mode;


end

default :
next_state <= idle_mode;

endcase

end
always @(posedge PCLK or PWRITE)
begin

if(next_state == idle_mode)

PRDATA <= 0;
else if (next_state == setup_mode)

PRDATA <= 0;
else begin

if (PWRITE ==1) begin

array[PADDR] <= PWDATA;end

else begin
PRDATA <= array[PADDR];end

end

end

endmodule

TEST BENCH:
module apb_tb;
// Inputs

reg PCLK;

reg PRESETn;
reg [31:0] PADDR;

reg PWRITE;

reg PSEL;

reg PENABLE;
reg [31:0] PWDATA;

reg PREADY;

// Outputs

wire [31:0] PRDATA;

// Instantiate the Unit Under Test (UUT)


apb_protocol uut (

.PCLK(PCLK),

.PRESETn(PRESETn),
.PADDR(PADDR),
.PWRITE(PWRITE),

.PSEL(PSEL),

.PENABLE(PENABLE),
.PWDATA(PWDATA),

.PRDATA(PRDATA),
.PREADY(PREADY)

);

initial begin

// Initialize Inputs
PCLK = 0;

PRESETn = 1;

PADDR = 0;

PWRITE = 0;
PSEL = 0;

PENABLE = 0;

PWDATA = 0;
PREADY = 0;

// Wait 10 ns for global reset to finish


//#10;

end

initial begin

PCLK = 1'b1;
forever #5 PCLK = ~PCLK;

end

initial begin

#3;

PRESETn = 0;
#8;

PWRITE = 1;
PADDR = 1;
PWDATA = 32'd8;

PREADY = 1;

PSEL = 1;
#10;

PENABLE = 1;
PREADY = 0;

#10;

PADDR = 2;

PWDATA = 32'd20;
#10;

PREADY = 1;

#10;

PSEL = 0;
PENABLE = 0;

PREADY = 0;

#10;
PREADY = 1;

#10;

PWRITE = 0;
PSEL = 1;

#10;

PENABLE = 1;

PREADY = 0;
#10;

PADDR = 1;
#10;

PREADY = 1;

#10;

PSEL = 0;
PENABLE = 0;

PREADY = 0;
end
endmodule

SIMULATION OUPUT:

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