19-3297; Rev 0; 5/04

155Mbps to 3.2Gbps, Low-Power SFP

Limiting Amplifiers
General Description Features

MAX3747/MAX3747A
The MAX3747/MAX3747A multirate limiting amplifiers ♦ Pin Compatible with Micrel SY88993V
function as data quantizers for OC-3 through OC-48 syn-
chronous optical network (SONET), Fibre-Channel, and ♦ 155Mbps to 3.2Gbps Operation
Gigabit Ethernet optical receivers. They are pin-for-pin
♦ >57dB of Gain for the MAX3747 and MAX3747A
compatible with the SY88993V from Micrel
Semiconductor, Inc. The amplifiers accept a wide range ♦ <10-12 BER with 2mVP-P Input Amplitude
of input voltages and provide constant-level, current-
♦ 18mA Supply Current
mode logic (CML) output voltages with controlled edge
speeds. The MAX3747 output voltage level is 500mVp-p ♦ Chatter-Free LOS with Programmable Threshold
and the MAX3747A output voltage is 800mVp-p.
♦ Output DISABLE Function
The MAX3747/MAX3747A limiting amplifiers feature a
programmable loss-of-signal detect (LOS) and an ♦ PECL-Compatible Inputs
optional disable function (DISABLE). Output disable can
be used to implement squelch.
Ordering Information
The MAX3747/MAX3747A are available in a 3mm, 10-pin
µMAX® package ideal for small form-factor receivers. PIN- PKG
PART TEMP RANGE
PACKAGE CODE
Applications
MAX3747EUB -40°C to +85°C 10 µMAX U10C-4
Gigabit Ethernet SFP/SFF Optical Transceiver
Modules MAX3747AEUB -40°C to +85°C 10 µMAX U10C-4
1G/2G Fibre-Channel SFP/SFF Optical µMAX is a registered trademark of Maxim Integrated Products, Inc.
Transceiver Modules
Multirate OC-3 to OC-48 FEC SFP/SFF Optical Pin Configuration appears at end of data sheet.
Transceiver Modules
10G LX4 Transceiver Modules
Typical Application Circuit
SFP OPTICAL RECEIVER HOST BOARD

3-INPUT SUPPLY FILTER HOST FILTER

DIAGNOSTIC VCC
MONITOR VCC_RX

MAX4004
DS1859
VCC
0.1µF MAX3747 0.1µF
IN+ MAX3747A OUT+
50Ω

MAX3745 SERDES
0.1µF 0.1µF
IN- OUT-
50Ω

5-PIN TO-HEADER
50Ω 50Ω VREF TH GND LOS DISABLE

4.7kΩ TO 10kΩ
VCC_HOST

LOS
R1

0.1µF

R2 0.1µF

R1 + R2 ≥ 5kΩ
VCC

________________________________________________________________ Maxim Integrated Products 1

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
 155Mbps to 3.2Gbps, Low-Power SFP
Limiting Amplifiers
ABSOLUTE MAXIMUM RATINGS
MAX3747/MAX3747A

Power-Supply Voltage (VCC) .................................-0.5V to +4.5V Continuous Current at CML Outputs

Voltage at IN+, IN- ..........................(VCC - 2.4V) to (VCC + 0.5V) (OUT+, OUT-) ..............................................-25mA to +25mA
Voltage at DISABLE, LOS, TH, VREF ..........-0.5V to (VCC + 0.5V) Continuous Power Dissipation (TA = +70°C)
Current into LOS ...................................................-1mA to +9mA 10-Pin µMAX (derate 6.9mW/°C above +70°C) ...........552mW
Current into VREF ..................................................................2mA Operating Junction Temperature Range (TJ) .......-55°C to +150°C
Differential Input Voltage (IN+ - IN-) .....................................2.5V Storage Ambient Temperature Range (TS)...........-55°C to +150°C

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS
(VCC = +2.97V to +3.63V, CML output load is 50Ω to VCC, TA = -40°C to +85°C. Typical values are at VCC = +3.3V and TA = +25°C,
unless otherwise specified.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
POWER SUPPLY
MAX3747 includes the CML output current 30 35
MAX3747A includes the CML output current 36 41
Supply Current (Note 2) ICC mA
MAX3747/MAX3747A exclude the CML
18 24
output current
Power-Supply Noise Rejection PSNR f < 2MHz 30 dB
INPUT SPECIFICATION
Input Sensitivity VIN-MIN (Note 3) 4 mVP-P
Input Overload VIN-MAX (Note 3) 1200 mVP-P
OUTPUT SPECIFICATION
Output Resistance ROUT 42 50 58 Ω
Differential Output Return Loss DUT is powered on, f < 3GHz 15 dB
MAX3747A 4mVP-P ≤ VIN ≤ 1200mVP-P 600 800 1000
CML Differential Output Voltage mVP-P
MAX3747 4mVP-P ≤ VIN ≤ 1200mVP-P 400 500 600
Differential Output Signal When AC-coupled outputs, VIN-MAX applied to the
15 mVP-P
Disabled input (Note 4)
Data-Output Transition Time 20% to 80% (Note 4) 70 120 ps
TRANSFER CHARACTERISTIC
K28.5 pattern at 3.2Gbps 13.2 19
PRBS 223 - 1 equivalent pattern at 2.7Gbps
14 25
(Note 6)
Deterministic Jitter (Notes 4, 5) DJ psP-P
K28.5 pattern at 2.1Gbps 12 17
PRBS 223 - 1 equivalent pattern at 155Mbps
85 150
(Note 6)
Random Jitter VIN = 4mVP-P (Notes 4, 7) 3.5 5 psRMS
Input-Referred Noise VIN = 4mVP-P (Note 4) 120 150 µVRMS
Low-Frequency Cutoff 6.4 kHz

2 _______________________________________________________________________________________
 155Mbps to 3.2Gbps, Low-Power SFP
Limiting Amplifiers
ELECTRICAL CHARACTERISTICS (continued)

MAX3747/MAX3747A
(VCC = +2.97V to +3.63V, CML output load is 50Ω to VCC, TA = -40°C to +85°C. Typical values are at VCC = +3.3V and TA = +25°C,
unless otherwise specified.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
LOSS OF SIGNAL
LOS Hysteresis 10log(VDEASSERT / VASSERT) (Note 4) 1.25 dB
LOS-Assert/Deassert Time (Notes 4, 8) 2.3 40.0 µs
Low LOS Assert Level VTH = -1.3V (Notes 4, 9) 2.5 4.1 5.9 mVP-P
Low LOS Deassert Level VTH = -1.3V (Notes 4, 9) 6.2 9.3 mVP-P
Medium LOS Assert Level VTH = -0.68V (Notes 4, 9) 22 29 31 mVP-P
Medium LOS Deassert Level VTH = -0.68V (Notes 4, 9) 44.8 57 mVP-P
High LOS Assert Level VTH = -0.114V (Notes 4, 9) 36.0 53.7 63.6 mVP-P
High LOS Deassert Level VTH = -0.114V (Notes 4, 9) 86 115 mVP-P
TTL/CMOS I/O
VCC - VCC - VCC -
VREF Voltage VREF V
1.35 1.3V 1.19
LOS Output High Voltage VOH RLOS = 4.7kΩ to 10kΩ to VCC_HOST (3V) 2.4 V
LOS Output Low Voltage VOL RLOS = 4.7kΩ to 10kΩ to VCC_HOST (3.6V) 0.4 V
DISABLE Input High VIH 2.0 V
DISABLE Input Low VIL 0.8 V
DISABLE Input Current RLOS = 4.7kΩ to 10kΩ to VCC_HOST 10 µA
Note 1: The data-input transition time is controlled by a 4th-order Bessel filter with f-3dB = 0.75 x 2.667GHz for all data rates of
2.667Gbps and below. The f-3db = 0.75 x 3.2GHz for a data rate of 3.2Gbps.
Note 2: Supply current is measured with unterminated outputs or with AC-coupled output termination (see Figure 1).
Note 3: Between sensitivity and overload, all AC specifications are met and the output is 0.95 x limited output amplitude.
Note 4: Guaranteed by design and characterization.
Note 5: The deterministic jitter (DJ) caused by the input filter is not included in the DJ generation specification.
Note 6: The PRBS 223 - 1 equivalent pattern consists of a K28.5 pattern plus 240 ones plus K28.5 pattern plus 240 zeros.
Note 7: Random jitter was measured without using a filter at the input.
Note 8: The signal at the input is switched between two amplitudes, Signal_ON and Signal_OFF, as shown in Figure 2.
Note 9: VTH is the voltage at pin 5 referenced to VCC (see Figure 5).

_______________________________________________________________________________________ 3
 155Mbps to 3.2Gbps, Low-Power SFP
Limiting Amplifiers
MAX3747/MAX3747A

VCC
ICC
(SUPPLY IOUT
CURRENT) (CML OUTPUT
VIN
CURRENT)
SIGNAL ON

1dB MAXIMUM DEASSERT LEVEL

50Ω 50Ω

6dB MAXIMUM POWER-DETECT WINDOW

MINIMUM ASSERT LEVEL

SIGNAL OFF
0V TIME
MAX3747
MAX3747A

Figure 1. Power-Supply Current Measurement Figure 2. LOS Deassert Threshold—Set 1dB Below the
Minimum by Receiver Sensitivity

Typical Operating Characteristics

(VCC = +3.3V, TA = +25°C, unless otherwise noted.)

OUTPUT EYE DIAGRAM OUTPUT EYE DIAGRAM

(MINIMUM INPUT) (MAXIMUM INPUT)
MAX3747/MAX3747A toc01 MAX3747/MAX3747A toc02

3.2Gbps, 223 - 1 PRBS, 4mVP-P 3.2Gbps, 223 - 1 PRBS, 1200mVP-P

60mV/div 60mV/div

50ps/div 50ps/div

4 _______________________________________________________________________________________
 155Mbps to 3.2Gbps, Low-Power SFP
Limiting Amplifiers
Typical Operating Characteristics (continued)

MAX3747/MAX3747A
(VCC = +3.3V, TA = +25°C, unless otherwise noted.)

OUTPUT EYE DIAGRAM OUTPUT EYE DIAGRAM

(MINIMUM INPUT) (MAXIMUM INPUT) OUTPUT EYE DIAGRAM AT +100°C
MAX3747/MAX3747A toc03 MAX3747/MAX3747A toc04 MAX3747/MAX3747A toc05

2.7Gbps, 223 - 1 PRBS, 4mVP-P 2.7Gbps, 223 - 1 PRBS, 1200mVP-P 2.125Gbps, CJTPAT, 50mVP-P

60mV/div 60mV/div 60mV/div

70ps/div 70ps/div 80ps/div

SUPPLY CURRENT vs. TEMPERATURE TRANSFER FUNCTION

(EXCLUDES OUTPUT CURRENT) (OUTPUT VOLTAGE vs. INPUT VOLTAGE) RANDOM JITTER vs. TEMPERATURE
50 1000 3.0
MAX3747/MAX3747A toc06

MAX3747/MAX3747A toc07

MAX3747/MAX3747A toc08
VIN = 50mVP-P, FREQ = 2.7Gbps
45 900 2.7
DIFFERENTIAL OUTPUT (mVP-P)

800 2.4
40 MAX3747A
RANDOM JITTER (psRMS)
SUPPLY CURRENT (mA)

700 2.1
35 600 1.8
30 500 1.5
MAX3747
25 400 1.2
300 0.9
20
200 0.6
15 100 0.3
10 0 0
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 0 1 2 3 4 5 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80
TEMPERATURE (°C) DIFFERENTIAL INPUT (mVP-P) TEMPERATURE (°C)

RANDOM JITTER vs. INPUT AMPLITUDE BIT-ERROR RATIO vs. INPUT VOLTAGE
5
MAX3747/MAX3747A toc10
MAX3747/MAX3747A toc09

3.2Gbps 13,000
12,000 MAXIM
4 11,000 MAX3747
BIT-ERROR RATIO (10-12)
RANDOM JITTER (psRMS)

10,000
9000
3 8000
7000
6000
2
5000
4000 MICREL
1 3000 SY88993V
2000
1000
0 1
1 10 100 1000 10,000 0 1 2 3 4 5 6 7 8 9 10
DIFFERENTIAL INPUT AMPLITUDE (mVP-P) DIFFERENTIAL INPUT AMPLITUDE (mVP-P)

_______________________________________________________________________________________ 5
 155Mbps to 3.2Gbps, Low-Power SFP
Limiting Amplifiers
MAX3747/MAX3747A

Typical Operating Characteristics (continued)

(VCC = +3.3V, TA = +25°C, unless otherwise noted.)

DETERMINISTIC JITTER DETERMINISTIC JITTER

vs. INPUT AMPLITUDE vs. TEMPERATURE
25 40

MAX3747/MAX3747A toc11

MAX3747/MAX3747A toc12
3.2Gbps, K28.5 PATTERN FREQ = 3.2Gbps
35 PATTERN = K28.5
DETERMINISTIC JITTER (psP-P)

20
30

DETERMINISTIC JITTER (ps)

25
15
20
10 15
VIN = 5mVP-P
10
5
5
VIN = 500mVP-P
0 0
1 10 100 1000 10,000 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80
DIFFERENTIAL INPUT AMPLITUDE (mVP-P) TEMPERATURE (°C)

ASSERT/DEASSERT vs. VTH ASSERT/DEASSERT vs. TEMPERATURE

120 40
MAX3747/MAX3747A toc13

MAX3747/MAX3747A toc14
VTH (V) = VOLTAGE AT PIN 5 (V) VTH = -1.1V, FREQ = 2.7Gbps
110
WITH RESPECT TO VCC
35 PATTERN = PRBS 223 - 1
100
ASSERT/DEASSERT (mVP-P)

90
ASSERT/DEASSERT (mV)

30
80
70 DEASSERT 25
60 DEASSERT
50 20
40
ASSERT 15
30
20 10 ASSERT
10
0 5
-1.4 -1.2 -1.0 -0.8 -0.6 -0.4 -0.2 0 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80
VTH (V) TEMPERATURE (°C)

OUTPUT RETURN vs. FREQUENCY (SDD22) INPUT RETURN vs. FREQUENCY (SDD11)
(INPUT SIGNAL LEVEL = -60dBm) (INPUT SIGNAL LEVEL = -60dBm)
30 30
MAX3747/MAX3747A toc16
MAX3747/MAX3747A toc15

20 20

10 10
SDD11 (dB)
SDD22 (dB)

0 0

-10 -10

-20 -20

-30 -30
100 1000 10,000 100 1000 10,000
FREQUENCY (MHz) FREQUENCY (MHz)

6 _______________________________________________________________________________________
 155Mbps to 3.2Gbps, Low-Power SFP
Limiting Amplifiers
Pin Description

MAX3747/MAX3747A
MAX3747/ MICREL
PIN MAX3747A SY8893V FUNCTION
NAME NAME
Disable Function Pin. The data outputs are held static when this pin is asserted high,
1 DISABLE EN
transistor-to-transistor logic (TTL).
2 IN+ DIN Noninverted Input Signal, CML
3 IN- DIN Inverted Input Signal, CML
4 VREF VREF Reference Voltage for LOS Threshold Setting
Loss-of-Signal Level Set. A voltage on this pin created by a two-resistor divider sets
5 TH LOSLVL the threshold level. Connect one resistor from this pin to VCC and another from this pin
to VREF (see Figure 5).
6 GND GND Ground
Loss-of-Signal, Open Collector. LOS is high when the level of the input signal drops
7 LOS LOS below the preset threshold set by the TH input. LOS is deasserted low when the signal
level is above the threshold.
8 OUT- DOUT Inverted Data Output, CML
9 OUT+ DOUT Noninverted Data Output, CML
10 VCC VCC Positive Power Supply

Detailed Description
The limiting amplifiers consist of a multistage amplifier,
offset-correction circuitry, an output buffer, and loss-of-
signal detect circuitry (see the Functional Diagram).
Input Stage MAX3747 VCC
The input stage is shown in Figure 3. It provides 50Ω MAX3747A
termination to VREF for each input signal, IN+ and IN-.
The MAX3747/MAX3747A should be AC-coupled.
Multistage Amplifier
The high-bandwidth multistage amplifier provides
approximately 57dB of gain for the MAX3747 and 61dB ESD
of gain for the MAX3747A. STRUCTURES

Offset Correction Loop

The MAX3747/MAX3747A are susceptible to DC offsets
in the signal path because they have high gain. In com-
munication systems using NRZ data with a 50% duty
cycle, pulse-width distortion present in the signal or gen-
50Ω 50Ω
erated in the transimpedance amplifier appears as an
input offset and is reduced by the offset correction loop.
VREF
The offset correction loop sets a low-frequency cutoff of
3.2kHz.

Figure 3. CML Input Stage

_______________________________________________________________________________________ 7
 155Mbps to 3.2Gbps, Low-Power SFP
Limiting Amplifiers
Functional Diagram
MAX3747/MAX3747A

VCC

MAX3747
MAX3747A 50Ω 50Ω
DIGITAL
OFFSET OUT+
CORRECTION OUT-

IN+

IN-

50Ω 50Ω DISABLE

VREF
VREF SIGNAL DETECT

VREF TH LOS

R1

R2 R1 + R2 ≥ 5kΩ

VCC

CML Output Buffer

The CML outputs of the MAX3747/MAX3747A limiting VCC
amplifiers provide high tolerance to impedance mis-
matches and inductive connectors. The output current
is approximately 10mA for the MAX3747 and 16mA for 50Ω 50Ω
the MAX3747A. Connecting the DISABLE pin to VCC
disables the output. If the LOS pin is connected to the OUT+
DISABLE pin, the outputs OUT+ and OUT- are at a stat- OUT-
ic voltage (squelch) whenever the input signal level
drops below the LOS threshold. The output buffer can DISABLE Q3 Q4 Q1 Q2
be AC- or DC-coupled to the load (Figure 4). ESD
The MAX3747 output is 500mVP-P and the MAX3747A STRUCTURES

output is 800mVP-P. DATA

DISABLE DISABLE

Figure 4. CML Output Buffer

8 _______________________________________________________________________________________
 155Mbps to 3.2Gbps, Low-Power SFP
Limiting Amplifiers
Loss-of-Signal Indicator Applications Information

MAX3747/MAX3747A
The MAX3747/MAX3747A are equipped with LOS cir-
cuitry that indicates when the input signal is below a pro- Program the LOS Assert Threshold
grammable threshold, set by a voltage on the TH pin Program the LOS assert threshold according to Figure
(see the Typical Operating Characteristics). The voltage 5. The combination of R1 and R2 should be greater
on the TH pin is set by two resistors, one connecting than or equal to 5kΩ, see the Assert/Deassert vs. VTH
from the TH pin to VCC and the other connecting from TH graph in the Typical Operating Characteristics.
to VREF (Figure 5). An RMS power detector compares Select the Coupling Capacitor
the input signal amplitude with this threshold and feeds When AC-coupling is desired, coupling capacitors CIN
the signal-detect information to the LOS output, which and COUT should be selected to minimize the receiv-
is open collector. To prevent LOS chatter in the region of er’s deterministic jitter. Jitter is decreased as the input
the programmed threshold, approximately 2dB of hys- low-frequency cutoff (fIN) is decreased:
teresis is built into the LOS assert/deassert function.
Once asserted, LOS is not deasserted until the input fIN = 1 / [2π(50)(CIN)]
amplitude rises to the required level. Figure 6 shows the For all applications, the recommended value for CIN and
LOS output circuit. COUT is 0.1µF, which provides fIN equal to 32kHz. Refer
to Application Note HFAN-1.1: Choosing AC-Coupling
Capacitors on the Maxim website (www.maxim-ic.com).
VCC
EMI Performance
R1 The MAX3747/MAX3747A have been designed for bet-
ter EMI performance. To help reduce EMI, special care
TH
has been taken to produce symmetrical signal outputs.

R2 Pin Configuration
VREF

TOP VIEW

VTH = (R1 x (VREF - VCC)) / (R2 + R1) DISABLE 1 10 VCC

VTH IS VCC REFERENCED
R1 + R2 ≥ 5kΩ IN+ 2 9 OUT+
MAX3747
IN- 3 MAX3747A 8 OUT-
Figure 5. MAX3747/MAX3747A LOS Threshold Circuit
VREF 4 7 LOS
VCC
TH 5 6 GND

µMAX

Chip Information
LOS
TRANSISTOR COUNT: 443
PROCESS: SiGe Bipolar
ESD
STRUCTURE

Figure 6. MAX3747/MAX3747A LOS Output Circuit

_______________________________________________________________________________________ 9
 155Mbps to 3.2Gbps, Low-Power SFP
Limiting Amplifiers
Package Information
MAX3747/MAX3747A

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)

10LUMAX.EPS
e 4X S

10 10 INCHES MILLIMETERS
DIM MIN MAX MIN MAX
A - 0.043 - 1.10
A1 0.002 0.006 0.05 0.15
A2 0.030 0.037 0.75 0.95
D1 0.116 0.120 2.95 3.05
H
D2 0.114 0.118 2.89 3.00
E1 0.116 0.120 2.95 3.05
0 0.50±0.1 E2 0.114 0.118 2.89 3.00
H 0.187 0.199 4.75 5.05
0.6±0.1
L 0.0157 0.0275 0.40 0.70
L1 0.037 REF 0.940 REF
b 0.007 0.0106 0.177 0.270
1 1 e 0.0197 BSC 0.500 BSC
0.6±0.1
c 0.0035 0.0078 0.090 0.200
BOTTOM VIEW 0.498 REF
TOP VIEW S 0.0196 REF
α 0° 6° 0° 6°

D2 E2
GAGE PLANE
A2 A c

b E1
A1
α L
D1 L1

FRONT VIEW SIDE VIEW

PROPRIETARY INFORMATION
TITLE:

PACKAGE OUTLINE, 10L uMAX/uSOP

APPROVAL DOCUMENT CONTROL NO. REV.
1
21-0061 I 1

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

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