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Optimised space vector switching sequences for

mutilevel inverters

Conference Paper · February 2001

DOI: 10.1109/APEC.2001.912507 · Source: IEEE Xplore

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 Optimised Space Vector Switching Sequences for Multilevel Inverters
* * **
B. P. McGrath , D.G. Holmes and T. A. Lipo
*
Department of Electrical and Computer Systems Engineering,
Monash University
Wellington Road, Clayton, 3168, AUSTRALIA
**
Department of Electrical and Computer Engineering
University of Wisconsin - Madison
1415 Engineering Drive Madison, WI 53706, USA

Abstract – Previous work has shown that Space Vector have been proposed, the two most common topologies are
modulation and Carrier modulation for 2 level inverters achieve the Cascaded Inverter and its derivatives [1][2], and the
the same phase leg switching sequences when appropriate zero Diode Clamped inverter [3]. Figure 1 shows topologies for
sequence offsets are added to the reference waveforms for five level configurations of a Cascaded Inverter and a Diode
Carrier modulation. This paper presents a similar equivalence
Clamped Inverter. The two most popular control strategies
between the PD Carrier and Space Vector Modulation
for these multilevel inverter topologies are Carrier [4] and
Strategies applied to Diode Clamped, Cascaded N-level or
Hybrid multilevel inverters. By analysis of the time integral
Space Vector (SVM) [5] modulation.
trajectory of the converter voltage, the paper shows that the Carrier based modulation techniques control each phase
optimal harmonic profile for a Space Vector Modulator occurs leg of the inverter separately and allow the line to line
when the two middle Space Vectors are centred in each voltage to be developed implicitly. For multilevel inverters,
switching cycle. The required zero sequence offset to achieve it is generally accepted that the Phase Disposition (PD)
this centring for an equivalent carrier based modulator is then method [4] gives rise to the lowest harmonic distortion. This
determined. The results can be applied to any multilevel method was first applied to an N-level Diode Clamped
converter topology without differentiation. Discontinuous converter, and arranges N-1 phase matched triangular carrier
behaviour is also examined, with the Space Vector and Carrier waveforms to fully occupy contiguous bands between +VDC
based modulation methods shown to similarly produce identical and –VDC. A single reference waveform for each phase is then
performance. Both simulation and experimental results are
compared against these carriers to determine how the phase
presented.
leg should switch. Recent work has also shown how PD
I. INTRODUCTION modulation can be applied to Cascaded Inverter structures to
achieve the same harmonic performance [6].
Multilevel converters offer many benefits for higher power
In contrast SVM identifies each switching state of a
applications. In particular, these include an ability to
multilevel inverter as a point in complex (α,β) space. Then a
synthesise voltage waveforms with lower harmonic content
than two level converters and operation at higher DC reference phasor rotating in the (α,β) plane at the
voltages using series connected semiconductor switches. fundamental frequency is sampled within each switching
While many different multilevel converter topologies period, and the nearest three inverter switched states are
selected with duty cycles calculated to achieve the same volt-
VA VB VC
+VDC
C1 SA1 SB1 SC1

DA1 DB1 DC1

SA1 SA2 SB1 SB2 SC1 SC2 SA2 SB2 SC2
+ + +
VDC VDC VDC
DA2 DB2 DC2
SA3 SB3 SC3

C2
S'A1 S'A2 S'B1 S'B2 S'C1 S'C2
DA3 DB3 DC3
SA4 SB4 SC4 VC

VB
VA

C3 S'A1 S'B1 S'C1

SA3 SA4 SB3 SB4 SC3 SC4
+ + + DB3
DA3 DC3
VDC VDC VDC
S'A2 S'B2 S'C2
DA2 DB2 DC2

DA1 S'A3 DB1 S'B3 DC1 S'C3

S'A3 S'A4 S'B3 S'B4 S'C3 S'C4
C4
S'A4 S'B4 S'C4
VN -VDC

Figure 1: Five Level configurations of a (a) Cascaded Inverter, (b) Diode Clamped Inverter.
second average as the sampled reference phasor. This cycles through 4 switched states in each switching period. At
directly controls the inverter line to line voltages, and only least the first and last of these must be a redundant space
implicitly develops the phase leg voltages. Recent work has vector state if only the three nearest space vectors are to be
shown how to do this calculation for a general N-level Diode used (eg. 101 – 201 – 211 – 212).
Clamped inverter [5], but gives no insight into the optimal Depending where in the αβ space the reference phasor is
sequence of space vector states or the method’s applicability located, there are two alternatives for this sequence, viz:
to other multilevel inverter topologies. (i) Select two vectors of even redundancy and one vector
Previous work has shown that Space Vector and Carrier of odd redundancy (eg. 211/100, 221/110 and 210), or:
modulation of two level converters produce identical space (ii) Select one vector of even redundancy and two vectors
vector sequences despite their apparent differences [7]. This of odd redundancy (eg. 211/100, 200 and 210).
paper presents a similar equivalence for multilevel inverters (For two level inverters, only case (ii) is possible since the
by showing that the optimised SVM switching sequences for zero state vector is the only redundant switch combination.)
a multilevel inverter are the same as those created by Carrier Figure 3 illustrates a subset of a 5 level Space Vector plot,
PD modulation when an appropriate zero sequence and Table 1 summarises all possible sequences for this subset
component is injected into the carrier system references. that achieve the required minimum of three switching
transitions per phase leg in a switching period. Note that
II. OPTIMISED SPACE VECTOR SEQUENCES. from two level SVM theory it is well known that these
Figure 2 shows the space vector diagrams for 3 and 5 level sequences should be reversed in the next switching cycle for
Diode Clamped systems, where each digit of the space vector minimum harmonic impact [7] and so the reverse sequences
identifier represents the voltage level to which the A, B and need not be explicitly considered.
C phase legs are respectively switched. Note that some For triangles (b) and (d) there is only one possible
switched states are redundant and create the same space sequence. For triangles (a) and (c) the “correct” sequence can
vectors. The difficult task of selecting the optimum set of be identified from the possible alternatives by ensuring that
these space vectors for a given reference phasor was recently no extra switching transitions occur when moving between
solved by Celanovic et al. [5] using a linear coordinate triangles. For example, sequence c(i) should be used when
transformation, and identified that the harmonic profile of the moving from triangle (b) to (c) since it begins with the same
overall switched waveform is minimised when the nearest state as the sequence in (b), or sequence c(ii) should be used
three space vectors are used. However, this solution does not when moving from triangle (c) to (d) since it begins with the
identify how to sequence or place these three nearest space same state as the sequence in (d). Within triangle (c)
vectors in the (half carrier equivalent) switching period so as sequences c(i) and c(ii) must be swapped at some point, and
to minimise the total number of switching transitions and this is most conveniently done when the duty cycle for the
fully optimise the harmonic profile of the output voltage. space vector {431/320} exceeds that of {421/310}.
For a three phase inverter the minimum number of switch Applying this principle to triangle (a) means that
transitions in one switching cycle under continuous sequences a(i) and a(ii) cannot be used because they will
modulation is 3 (ie. one per phase leg), so that the converter introduce extra switching transitions when moving into
β
β 140 240
040 340 440
020 120 220
241 341
041 141 130 230 441 430

030 330
042 142 431 420
021 121 221
010 210 031 320
110
043 143 421 410
032 310
144 α
α
411
122 211
022 044 033 300 400
011 100 200 134 412

034 023 301 401

124 413
101
112 013 302 402
012 201 024
001 212
114 414

014 003 214 314 303 403

103 203

002 102 202 004 104 204 304 404

Figure 2(a): Space Vector States for 3 Level NPC converter. Figure 2(b): Space Vector States for 5 Level NPC converter.
 III. OPTIMAL SPACE VECTOR POSITION WITHIN A SWITCHING PERIOD
430 Once the optimum switching space vector sequence for
continuous modulation has been identified, it must be placed
in each switching period to optimise the harmonic profile of
(d)
the waveform. This means splitting the duty cycle of the first
vector in the sequence (which is redundant with the last
431, (c) 420
320 vector) across the first and last switching state, but just what
fraction of time should be spent in each state? Fukuda et al.
(a)
[10]proposed a technique for two level converters which
421, (b) when refined for multilevel systems answers this question.
432, 321, 310
210 410 Figure 4(a) shows the trajectory of the time integral of the
converter output voltage (ie. flux) in αβ space. The ideal
Reference Phasor
Figure 3 : Subset of 5 Level Space Vector Diagram. In triangles (a) and (c)
trajectory is circular for a sinusoidal output voltage, but the
2 vectors of even redundancy and 1 of odd redundancy exist. In triangles switched nature of the converter operation restricts the real
(b) and (d) 1 vector of even redundancy and 2 of odd redundancy exist. trajectory to a quasi-circular path as shown.
Figure (4b) shows the flux trajectories for one switching
triangle (c). This is very important if the reference phasor cycle. The switching sequence uses space vectors V1, V2 and
lies near the boundary of triangles (a) and (c) because it will V3 with respective duty cycles d1, d2, and d3. Vector V1 is
cross the linear boundary between triangles (a) and (c) twice split so as to occupy the first and last state of the switching
in a fundamental cycle, and there are many type (c) triangles sequence with durations given by:
in the space vector plot. So only sequences a(iii) and a(iv) t1 = kd1 ∆T t 2 = (1 − k )d 1 ∆T (1)
can be used, and these are identical to sequences c(i) and c(ii)
except that state {420} has been replaced by state {321}. where ∆T denotes the switching period.
Hence only state {321} of the triply redundant vector The deviation between the switched quasi-circular
{432/321/210} is useable. trajectory and the ideal circular path at each switching cycle
Similar analysis for vectors with even redundancies greater gives a measure of the harmonic distortion of the modulating
than three reveals that only two states can ever be used to process. This distortion can be evaluated by integrating the
achieve minimal switching, and for vectors with odd area between the two trajectories over each switching period
redundancies greater than two, only one state is useable. Note as shown in Figure 4(c). (Note that for large pulse ratios the
also that all useful sequences begin and end with an even ideal trajectory can be approximated to a chord between end
redundant space vector state. points p and p’, to simplify the evaluation.) The issue then
While the above analysis is from the perspective of a becomes to determine the value for k that minimises this area
Diode Clamped topology the only significant difference with to achieve the optimum modulation strategy.
the Cascaded topologies is that there is a greater variety of Figure 5 shows the optimum values for k for successive
redundancies. A similar analysis for Cascaded type inverter switching periods over a complete fundamental cycle, for a 3,
systems leads to an identical restriction on states and 5 and 7 level inverter. These values were found from
sequences which can be used to achieve the minimum simulation by varying k within each switching period to
number of switching transitions in a fundamental cycle. minimise the flux error area. Clearly the optimal value of k
varies insignificantly about the value 0.5, and so for the
optimal harmonic performance the start and end redundant
TABLE 1 : POSSIBLE SEQUENCES IN FIVE LEVEL SPACE vector periods should be made equal.
VECTOR SUBSET (SEE FIGURE 3). REVERSE SEQUENCES
ARE NOT SHOWN. β
Quasi-Circular
Current Trajectory
Triangle Sequence
(a) (i) {432 to 431 to 421 to 321}
(ii) {210 to 310 to 320 to 321}
(iii) {421 to 321 to 320 to 310}
(iv) {431 to 421 to 321 to 320}
(b) {421 to 420 to 410 to 310}
(c) (i) {421 to 420 to 320 to 310} α
(a) (b) (c)
(ii) {431 to 421 to 420 to 320} Figure 4: (a) Quasi-Circular Loci of the Flux Trajectories; (b) Flux
(d) {431 to 430 to 420 to 320} Trajectories in one switching cycle; (c) Area between the nearest three space
vectors and the approximated Ideal Flux trajectories.
 1
centring the two middle vectors of the switching sequence.
0.75
The limitation with (2) is that it assumes that the first and
0.5 7 Level last switching transition in the each switching period is
0.25 determined by the comparison of the absolute maximum and
0 minimum reference values against the carrier. This is not
1
necessarily the case for a multilevel inverter. For example,
0.75
Figure 6 shows that the last switching transition in the first
0.5 5 Level half carrier period is caused by the comparison of Vb
0.25 reference against the carrier, and this is the middle reference
0 value. Hence to proceed it is necessary to identify which of
1
references Va, Vb or Vc will be responsible for the first and
0.75
last switching transitions in each half carrier period.
0.5 3 Level
This can be done using a modulus function to vertically
0.25
shift the (2 level optimised) reference voltages so their carrier
0
0 π/3 2π/3 π 4π/3 5π/3 2π
intersections lie within a common carrier band, ie.
ω0t
Figure 5: Value of k which gives Minimum Vector Area for a pulse ( )  2V 
Vk ' = Vk + Voff + VDC mod DC , k = a, b, c (3)
ratio of 120, Modulation Depth of 0.8.  N −1
IV. SVM COMPARED TO CARRIER BASED PWM. Note that a DC offset must be added to the reference
waveforms to avoid the modulus function operating on a
For 2 level inverters, it is known [7] that the addition of a
negative number. An additional common mode voltage
common offset voltage to the three phase references, of
max (Va,Vb,Vc ) + min (Va,Vb,Vc )
which correctly positions the first and last switching
Voff = − (2) transitions in each switching period can then be determined
2 using a similar max/min expression as before, viz
will centre the active space vectors in the switching period,
and hence match carrier modulation to optimised SVM.
V
V 'off = DC −
(max (Va ' ,Vb ' ,Vc ') + min (Va ' ,Vb ' ,Vc ')) (4)
Figure 6 shows the converter switching states which result N −1 2
when this offset is used for a 5 level system operating under The final reference waveforms are then generated by
PD modulation. For the expanded switching condition adding the offset voltages described by (2) and (4) to the
shown, the sequence consists of two vectors of even original sinusoidal phase voltages. Figure 7 shows the offset
redundancy (V1 and V3) and one vector of odd redundancy and phase voltages for 3, 5 and 7 level systems, which
(V2). Examination of this sequence shows that the durations closely match results obtained by other authors [8], [9].
of the two states of V1 are not equal, but rather centre the
V. DISCONTINUOUS MODULATION
vector of odd redundancy in the middle of the half carrier
period. Hence this offset will not achieve the optimum of A further possibility with space vector positioning is to
move to discontinuous SVM by eliminating either the first or
last state in each switching sequence. While this approach
does not achieve a minimum flux error, the increase in
VDC

+VDC
0 7 Level
Phase A Phase A

-VDC
VDC

0
0 5 Level
Phase B Phase B
Phase C Phase C -VDC
-VDC VDC
V1 V2 V3 V1 V1 V3 V2 V1
411 410 310 300 300 310 410 411
(d 1 + d 3 )∆T (d 1 − d 3 )∆T (d 1 − d 3 )∆T (d 1 + d 3 )∆T 0 3 Level
2 d2∆T d3∆T 2 2 d3∆T d2∆T 2

∆T ∆T
-VDC
Figure 6: Space Vector Positions resulting from 2 level SVM common
0 π/3 2π/3 π 4π/3 5π/3 2π
mode offset. The effect is to centre the Vector with odd redundancy (V3), ω0t
rather than making equal dwell times in the states of V1. Figure 7: Centred SVM Reference and Offset Waveforms.
switching frequency of 3/2 that is possible because of the [6],[12] and this will not be discussed further here. But in
reduced number of switching transitions that are required, passing it should be noted that the modulus function can be
can give harmonic benefits for certain modulation ranges. efficiently implemented experimentally by scaling the
The simplest approach for discontinuous modulation is to calculation in (3) to make the divisor a power of 2, and then
lock particular phase legs to the upper or lower voltage rails simply masking the dividend with the divisor minus one.
for fractions of the fundamental cycle. For multilevel Figure 9 shows the simulated spectrum of a 3 level inverter
inverters, this may require additional switching transitions operating under centred SVM. Figures 10 and 11 show
which reduce the possible increase in switching frequency experimental results for PD modulation of a 3 level Cascaded
from the theoretical maximum, but there are still useful inverter, with the appropriate zero sequence offsets added to
harmonic gains to be achieved. (Note that for multilevel the phase references to make the start and end redundant
inverters, the increased number of voltage levels does create space vector periods equal. The extremely close match of the
a greater variety of possible modes of discontinuity, but it has simulation and experimental results confirms the equivalence
been found that all have similar harmonic profiles and so of SVM and PD Carrier modulation when an appropriate
only the simplest alternative will be considered here.) zero sequence offset is added to the reference waveforms.
Figure 8 shows the zero sequence offset waveforms which Similar results have been obtained for a 5 level inverter
should be added to the phase reference voltages to achieve system, but are not presented here because of space
discontinuous switching for a carrier based modulation limitations.
system. These reference waveforms are immediately familiar Figures 12, 13 and 14 show similar results for a 7 level PD
as the DPWM1 and DPWM3 waveforms described in earlier modulated hybrid converter compared to 7 level centred
work [11], and can be described mathematically as: SVM. Again, the extremely close match of the simulated and
Voff = max[abs(Va ), abs(Vb ), abs (Vc )], VZS _ DPWM 1 = − sgn (Voff ) + Voff (5) experimental spectra confirm the equivalence between SVM
and PD carrier modulation for any multilevel converter
Voff = mid [abs (Va ), abs(Vb ), abs(Vc )], VZS _ DPWM 3 = − sgn (Voff ) + Voff (6)
topology, when appropriate zero sequence offsets are added
Alternatively, as was done for this paper, these offset to the carrier system phase reference waveforms.
waveforms can be developed by demodulating the phase Figures 15, 16 and 17 compare 3 level SVM simulation
voltages implicitly developed by a discontinuous results against 3 level Cascaded inverter PD modulation
implementation of a multilevel SVM system. o
under 30 discontinuous operation (once more with the
appropriate zero sequence offsets added for the PD
VI. SIMULATION AND EXPERIMENTAL RESULTS. modulation). Once again, the extremely close match of the
The modulation principles presented above have been simulation and experimental spectra confirm the equivalence
verified both in simulation, and experimentally with a 3 and between the two modulation strategies. Note also the
5 level Cascaded inverter and a 7 level Hybrid inverter (with characteristic low order extended spectral “tail” in Figures 15
only two phase legs in each case). Each phase leg for the and 16, and the low order distortion in the experimental
experimental system comprised 2 series connected full bridge system because of sector commutation, which is a typical
single phase inverter modules, with DC buses supplied from signature of discontinuous modulation strategies.
tapped transformers to allow different bus voltages to be
created for the Cascaded and the Hybrid inverter systems. VII. CONCLUSION.
Previous work has reported how PD modulation can be It is already well established for 2 level inverters that
implemented for the Cascaded and Hybrid inverter systems Carrier and Space Vector modulation methods create exactly

Demodulated
Phase Voltage Demodulated
MVDC MVDC Phase Voltage
Zero Sequence

Zero Sequence

0 0

Fundamental
-MVDC -MVDC
Fundamental
0 60 120 180 240 300 360 0 60 120 180 240 300 360
Fundamental Angle (deg) Fundamental Angle (deg)
0 0
(a) Three Level 60 Discontinuous SVM (b) Three Level 30 Discontinuous SVM.
Figure 8: SVM Demodulated Phase Voltages for discontinuous modulation. Pulse Ratio = 200.
 100
the same phase leg switching sequences when appropriate
zero sequence offsets are added to the reference waveforms
for Carrier modulation. This paper identifies a similar
10-1
equivalence for PD Carrier modulation and Space Vector
Modulation for Diode Clamped, N-level Cascaded and
Hybrid multilevel inverters. Using flux trajectory concepts, it
has been shown that the optimum switching arrangement 10-2
maintains the middle space vectors of a switching sequence
centred within each switching period. The required zero
sequence component to achieve this result for a carrier based 10-3
modulator is then determined, with the results being Mod Depth = 0.9
applicable to any multilevel inverter topology. FC = 2100Hz, F0 = 50Hz
THD(120th Harmonic) = 32.0%
The paper also shows how discontinuous modulation can WTHD(120th Harmonic) = 0.41%
10-4
be applied to multilevel inverters using zero sequence offset 0 1000 2000 3000 4000 5000 6000
Frequency (Hz)
voltages derived from 2 level inverter Space Vector concepts. Figure 9: 3 Level Centred SVM – Simulated Line to Line Voltage
Both simulation and experimental results are presented to Spectrum.
support the conclusions of the paper.
100
VIII. REFERENCES.
[1] F. Z. Peng, J.S. Lai, J. W. McKeever, J. VanCoevering, “A Multilevel
Voltage-Source Inverter with Separate DC Sources for Static Var
10-1
Generation”, IEEE Transactions on Industry Applications, Vol 32, No.
5, September/October 1996, pp.1130-1138.
[2] M. D. Manjrekar, P. Steimer, T. A. Lipo, “Hybrid Multilevel Power
Conversion System: a competitive solution for high power
10-2
applications”, in Conf. Rec. 1999 IEEE/IAS Annual Meeting,
pp.1520-1527.
[3] J. Lai, F. Peng, “Multilevel Converters – A New Breed of Power
Converters”, IEEE Transactions on Industry Applications, Vol. 32, 10-3
No. 3, May/June 1996, pp. 509-517.
[4] G. Carrara, S. Gardella, M. Marchesoni, R. Salutari and G. Sciutto, “A Mod Depth = 0.9
FC = 2100Hz, F0 = 50Hz
New Multilevel PWM Method: A Theoretical Analysis”, IEEE
THD(120th Harmonic) = 30.8%
Transactions on Power Electronics, Vol. 7, No. 3, July 1992, pp.497- 10-4
0 1000 2000 3000 4000 5000 6000
505. Frequency (Hz)
[5] N. Celanovic, D. Boroyevich, “A Fast Space Vector Modulation
Algorithm for Multilevel Three-Phase Converters”, in Conf. Rec. Figure 10: 3 Level Cascaded Inverter – Centred PD Modulation,
IEEE IAS Annual Meeting 1999, pp.1173-1177. Experimental Line to Line Voltage Spectrum.
[6] B. P. McGrath, D. G. Holmes, “A Comparison of Multicarrier PWM
Strategies for Cascaded and Neutral Point Clamped Multilevel Asymmetrical Regular Sampled 3 Level Cascaded Inverter
Waveforms – Centered SVPWM
Inverters.”, in Conf. Rec. 2000 IEEE PESC Meeting, pp. 674-679.
[7] D. G. Holmes, “The General Relationship Between Regular-Sampled 150V
Pulse-Width-Modulation and Space Vector Modulation for Hard
Phase
Switched Converters”, in Conf. Rec. IEEE-IAS Annual Meeting, Voltage
1992, pp. 1002-1010.
-150V
[8] F. Wang, “Sine-Triangle vs. Space Vector Modulation for Three-
300V
Level PWM Voltage Source Inverters”, in Conf. Rec. IEEE IAS
Annual Meeting 2000, pp.2482-2488.
Line
[9] Y. Lee, D. Kim, D. Hyun, “Carrier Based SVPWM Method for Multi- Voltage
Level System with Reduced HDF”, in Conf. Rec. IEEE IAS Annual
Meeting 2000, pp.1996-2003. -300V
[10] S. Fukuda, Y. Iwaji, “A Single-Chip Microprocessor-Based PWM
5A
Technique for Sinusoidal Inverters”, in Conf. Rec. IEEE IAS Annual
Meeting 1988, pp. 921-926. Line
[11] A. M. Hava, R. J. Kerkman, T. A. Lipo, “Simple Analytical and Current

Graphical Methods for Carrier-Based PWM-VSI Drives”, IEEE

-5A Mod Depth = 0.9
Transactions on Power Electronics, Vol. 14, No. 1, January 1999, pp. FC = 2.1 kHz
49-61. F0 = 50Hz
[12] B. P. McGrath, D. G. Holmes, M. Manjrekar, T. A. Lipo, “An 0 10 20 30 40 50
Improved Modulation Strategy for a Hybrid Multilevel Inverter”, in Time (mSec)

Conf. Rec. IEEE IAS Annual Meeting 2000, pp.2086-2093 Figure 11: 3 Level Cascaded Inverter – Centred PD Modulation.
Experimental Switched Inverter Waveforms.
 100 100

10-1 10-1

10-2 10-2

10-3 10-3
Mod Depth = 0.9
Mod Depth = 0.9
FC = 3000Hz, F0 = 50Hz
FC = 2100Hz, F0 = 50Hz
THD(120th Harmonic) = 31.6%
THD(120th Harmonic) = 10.03%
WTHD(120th Harmonic) = 0.52%
10-4
WTHD(120th Harmonic) = 0.14% 10-4
0 1000 2000 3000 4000 5000 6000 0 1000 2000 3000 4000 5000 6000
Frequency (Hz) Frequency (Hz)
0
Figure 12: 7 Level Centred SVM – Simulated Line to Line Voltage Figure 15: 3 Level 30 Discontinuous SVM – Simulated Line to Line
Spectrum. Voltage Spectrum.

100 100

10-1 10-1

10-2 10-2

10-3 10-3

Mod Depth = 0.9 Mod Depth = 0.9

FC = 2100Hz, F0 = 50Hz FC = 3000Hz, F0 = 50Hz
THD(120th Harmonic) = 10.5% THD(120th Harmonic) = 32.2%
10-4 10-4
0 1000 2000 3000 4000 5000 6000 0 1000 2000 3000 4000 5000 6000
Frequency (Hz) Frequency (Hz)
Figure 13: 7 Level Hybrid Inverter – Centred PD Modulation, Experimental Figure 16: 3 Level Cascaded Inverter - 300 Discontinuous PWM .
Line to Line Voltage Spectrum. Experimental Line to Line Voltage Spectrum.

225V 150V

Phase Phase
Voltage Voltage

-225V -150V

375V 300V
Line
Voltage
Line
Voltage
-300V

-375V 5A
Line
8A Current

Line -5A
Current

-8A Mod Depth = 0.9 Mod Depth = 0.9

FC = 2.1 kHz FC = 3.0 kHz
F0 = 50Hz F0 = 50Hz
0 10 20 30 40 50 0 10 20 30 40 50
Time (mSec) Time (mSec)
Figure 14: 7 Level Hybrid Inverter – Centred PD Modulation. Figure 17: 3 Level Cascaded Inverter – 300 Discontinuous PD Modulation.
Experimental Switched Inverter Waveforms. Experimental Switched Inverter Waveforms.

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