Sequential Logic – Sequential circuits

1
 Sequential logic has state

state

i
CL o
s
n m
CL
in out
Combinational Logic n m

Sequential Logic

2
 D Flip-Flop

• Input: D
• Output: Q d q
D Q
• Clock
^
• Q outputs a steady value clk
• Edge on Clock changes Q to be D
• Flip-flop stores state
• Allows sequential circuits to iterate d s s q
D Q

^
clk

3
Synchronous Sequential Logic
state B
A

next_state
A
B s
D Q
s
CL B
C
in out
n m
clk

clk

in A B C

next SB=f(A,SA) SC=f(B,SB) SD=f(C,SC)

state SA SB SC SD
Example: State table and State diagram

Next state Out

state in = 0 in = 1 in = 0 in = 1
00 00 01 0 0
01 00 11 0 0
10 01 10 0 0
11 11 00 0 1

5
 Summary
• Sequential logic
– State feedback around combinational logic
• Synchronous sequential logic
– State register synchronizes state transitions with a clock.
– All bits of state are updated at the same time on the rising edge of the clock.
– Reduces synchronous machine design to combinational design of next-state
function.
• State diagram and table describe next-state and output functions
carew Current State Next State Output
!carew carew
carew
gns yns gew gew gns gns yns 100001 lgns
100 001 010 001 001 100 001 010 yns gew gew 010001 lyns
gew yew yew 001100 lgew
yew gns gns 001010 lyew

• State assignment
– Assign binary codes to states – one hot or binary
• Implementation
– Design combinational logic for next-state and output functions
• Verilog
– Explicitly instantiate flip-flops
– Case (or casex) statement for next-state function
– Use defines for state assignment
Sequential Logic – State assignment

7
A Traffic-Light Controller

Car Det

Car Det

carew
carew
rst lights
FSM
clk 6

8
 Traffic Light FSM Behavior

• Reset to a state where the light is green (red) in the north-south (east-
west) direction.
• When a car is detected, go through a sequence that makes the light
green in the east-west direction and then return to green in the north-
south direction.
• A direction with green light must first transition to a state where the light is
yellow before going to a state with red light.
• A direction can have a green light only if the light in the other direction is
red.

9
 Traffic Light FSM

• Finite state machine is specified by

– States, Inputs, Outputs
• Four states
– Green north-south (red east-west)
– Yellow north-south (red east-west)
– Green east-west (red north-south)
– Yellow east-west (red north-south)
• Input
– Carew : is there a car waiting on the east-west road?
– Reset : return to initial state (need not go through yellow)
• Output: two 3-bit traffic light signals (1-hot) (gyr gyr)
– 100 001: NS green, EW red; 001 010 NS red, EW yellow

10
Complete Traffic Light State machine

11
State Table (ignoring reset for now)

¬carew
carew

carew
carew
gns yns gew yew

100 001 010 001 001 100 001 010

Current State Next State Output

!carew
¬carew carew
carew
gns gns yns 100001 lgns
yns gew gew 010001 lyns
gew yew yew 001100 lgew
yew gns gns 001010 lyew

12
 State Assignment

• Assign values to encode each state (gns, yns, gew, yew) on state and
next_state signals

state

next_state
D Q
s s
CL
in out
n m
clk

13
One-Hot State Assignment

State Encoding
gns 1000
yns 0100
gew 0010
yew 0001

state

next_state
D Q
s s
CL
in out
n m
clk

14
Translating No-Reset FSM To One-Hot Controller
¬carew
carew * *

gns yns gew yew

100 001 010 001 001 100 001 010

15
Binary State Assignment (Gray Code)

State Encoding
gns 00
yns 01
gew 11
yew 10
state

next_state
D Q
s s
CL
in out
n m
clk

16
 Summary
• Sequential logic
– State feedback around combinational logic
• Synchronous sequential logic
– State register synchronizes state transitions with a clock.
– All bits of state are updated at the same time on the rising edge of the clock.
– Reduces synchronous machine design to combinational design of next-state
function.
• State diagram and table describe next-state and output functions
carew Current State Next State Output
!carew carew
carew
gns yns gew gew gns gns yns 100001 lgns
100 001 010 001 001 100 001 010 yns gew gew 010001 lyns
gew yew yew 001100 lgew
yew gns gns 001010 lyew

• State assignment
– Assign binary codes to states – one hot or binary
• Implementation
– Design combinational logic for next-state and output functions
• Verilog
– Explicitly instantiate flip-flops
– Case (or casex) statement for next-state function
– Use defines for state assignment
Sequential Logic - Implementation

18
Translating No-Reset FSM To One-Hot Controller
¬carew
carew * *

gns yns gew yew

100 001 010 001 001 100 001 010
Binary State Assignment (Gray Code)

State Encoding
gns 00
yns 01
gew 11
yew 10
state

next_state
D Q
s s
CL
in out
n m
clk

20
Encoded state table and next-state K-maps
State Next State Output
!carew
¬carew carew
carew
00 00 01 100001
01 11 11 010001
11 10 10 001100
10 00 00 001010
 Logic Equations

ns1 = s0
State Next State Output ns0 = (s0 | carew) & ¬s1
¬carew
!carew carew
carew lgns = ¬s0 & ¬s1
00 00 01 100001 lyns = s0 & ¬s1
01 11 11 010001 lrns = s1
11 10 10 001100 lgew = s0 & s1
10 00 00 001010 lyew = ¬s0 & s1
lrew = ¬s1

22
Implementation of traffic-light controller with binary
state assignment

lgns

s1 lyns
D Q

lrns

lgew

s0
D Q
lyew
carew

clk lrew

23
 FSMs in Verilog (Style guide)

• All feedback through explicitly instantiated DFF module!

• Next state and output functions are combinational – case or assign
– No “inferred latches”
• Make sure you can reset your FSM
• Use defines for state encoding (and width)

24
¬carew
carew //------------------------------------------------------
// Traffic_Light
carew
carew
// Inputs:
gns yns gew gew // clk - system clock
// rst - reset - high true
100 001 010 001 001 100 001 010
// carew - car east/west - true when car is waiting in east-west direction
// Outputs:
// lights - (6 bits) {gns, yns, rns, gew, yew, rew}
//--------------------------------------------- // Waits in state GNS until carew is true, then sequences YNS, GEW, YEW
// FSM Example // and back to GNS.
// Bill Dally 1/30/03 //------------------------------------------------------
//--------------------------------------------- module Traffic_Light(clk, rst, carew, lights) ;
// define state assignment - one hot input clk ;
//--------------------------------------------- input rst ; // reset
`define SWIDTH 4 input carew ; // car present on east-west road
`define GNS 4'b1000 output [5:0] lights ; // {gns, yns, rns, gew, yew, rew}
`define YNS 4'b0100 wire [`SWIDTH-1:0] state, next ; // current and next state
`define GEW 4'b0010 reg [`SWIDTH-1:0] next1 ; // next state w/o reset
`define YEW 4'b0001 reg [5:0] lights ; // output - six lights 1=on
//---------------------------------------------
// define output codes // instantiate state register
//--------------------------------------------- DFF #(`SWIDTH) state_reg(clk, next, state) ;
`define GNSL 6'b100001
`define YNSL 6'b010001 // next state and output equations - this is combinational logic
`define GEWL 6'b001100 always @(state or carew) begin
`define YEWL 6'b001010 case(state)
//--------------------------------------------- `GNS: {next1, lights} = {(carew ? `YNS : `GNS), `GNSL} ;
// define flip-flop `YNS: {next1, lights} = {`GEW, `YNSL} ;
//--------------------------------------------- `GEW: {next1, lights} = {`YEW, `GEWL} ;
module DFF(clk, in, out) ; `YEW: {next1, lights} = {`GNS, `YEWL} ;
parameter n = 1; // width endcase
input clk ; end
input [n-1:0] in ; // add reset
output [n-1:0] out ; assign next = rst ? `GNS : next1 ;
reg [n-1:0] out ; endmodule
always @(posedge clk)
out = in ;
endmodule
 Feedback (state) in explicitly declared DFF module
//--------------------------------------------- //------------------------------------------------------
// FSM Example // Traffic_Light
// Bill Dally 1/30/03 // Inputs:
//--------------------------------------------- // clk - system clock
// define state assignment - one hot // rst - reset - high true
//--------------------------------------------- // carew - car east/west - true when car is waiting in east-west direction
`define SWIDTH 4 // Outputs:
`define GNS 4'b1000 // lights - (6 bits) {gns, yns, rns, gew, yew, rew}
`define YNS 4'b0100 // Waits in state GNS until carew is true, then sequences YNS, GEW, YEW
`define GEW 4'b0010 // and back to GNS.
`define YEW 4'b0001 //------------------------------------------------------
//--------------------------------------------- module Traffic_Light(clk, rst, carew, lights) ;
// define output codes input clk ;
//--------------------------------------------- input rst ; // reset
`define GNSL 6'b100001 input carew ; // car present on east-west road
`define YNSL 6'b010001 output [5:0] lights ; // {gns, yns, rns, gew, yew, rew}
`define GEWL 6'b001100 wire [`SWIDTH-1:0] state, next ; // current and next state
`define YEWL 6'b001010 reg [`SWIDTH-1:0] next1 ; // next state w/o reset
//--------------------------------------------- reg [5:0] lights ; // output - six lights 1=on
// define flip-flop
//--------------------------------------------- // instantiate state register
module DFF(clk, in, out) ; DFF #(`SWIDTH) state_reg(clk, next, state) ;
parameter n = 1; // width
input clk ; // next state and output equations - this is combinational logic
input [n-1:0] in ; always @(state or carew) begin
output [n-1:0] out ; case(state)
reg [n-1:0] out ; `GNS: {next1, lights} = {(carew ? `YNS : `GNS), `GNSL} ;
`YNS: {next1, lights} = {`GEW, `YNSL} ;
always @(posedge clk) `GEW: {next1, lights} = {`YEW, `GEWL} ;
out = in ; `YEW: {next1, lights} = {`GNS, `YEWL} ;
endmodule endcase
end
// add reset
carew
assign next = rst ? `GNS : next1 ;
endmodule
carew
gns yns gew gew

100 001 010 001 001 100 001 010

 Next-state and output functions are combinational
//--------------------------------------------- //------------------------------------------------------
// FSM Example for Lecture 7 // Traffic_Light
// Bill Dally 1/30/03 // Inputs:
//--------------------------------------------- // clk - system clock
// define state assignment - one hot // rst - reset - high true
//--------------------------------------------- // carew - car east/west - true when car is waiting in east-west direction
`define SWIDTH 4 // Outputs:
`define GNS 4'b1000 // lights - (6 bits) {gns, yns, rns, gew, yew, rew}
`define YNS 4'b0100 // Waits in state GNS until carew is true, then sequences YNS, GEW, YEW
`define GEW 4'b0010 // and back to GNS.
`define YEW 4'b0001 //------------------------------------------------------
//--------------------------------------------- module Traffic_Light(clk, rst, carew, lights) ;
// define output codes input clk ;
Case statement
//---------------------------------------------
`define GNSL 6'b100001
input rst ;
input carew ;
// reset
// car present on east-west road
`define YNSL 6'b010001 output [5:0] lights ; // {gns, yns, rns, gew, yew, rew}
concatenation
`define GEWL 6'b001100 wire [`SWIDTH-1:0] state, next ; // current and next state
`define YEWL 6'b001010 reg [`SWIDTH-1:0] next1 ; // next state w/o reset
to assign next state
//---------------------------------------------
// define flip-flop
reg [5:0] lights ; // output - six lights 1=on

//--------------------------------------------- // instantiate state register

and outputs
module DFF(clk, in, out) ; DFF #(`SWIDTH) state_reg(clk, next, state) ;
parameter n = 1; // width
input clk ; // next state and output equations - this is combinational logic
input [n-1:0] in ; always @(state or carew) begin
output [n-1:0] out ; case(state)
reg [n-1:0] out ; `GNS: {next1, lights} = {(carew ? `YNS : `GNS), `GNSL} ;
`YNS: {next1, lights} = {`GEW, `YNSL} ;
always @(posedge clk) `GEW: {next1, lights} = {`YEW, `GEWL} ;
out = in ; `YEW: {next1, lights} = {`GNS, `YEWL} ;
endmodule endcase
end
// add reset
carew
assign next = rst ? `GNS : next1 ;
endmodule
carew
gns yns gew gew

100 001 010 001 001 100 001 010

 Explicit reset
//--------------------------------------------- //------------------------------------------------------
// FSM Example for Lecture 7 // Traffic_Light
// Bill Dally 1/30/03 // Inputs:
//--------------------------------------------- // clk - system clock
// define state assignment - one hot // rst - reset - high true
//--------------------------------------------- // carew - car east/west - true when car is waiting in east-west direction
`define SWIDTH 4 // Outputs:
`define GNS 4'b1000 // lights - (6 bits) {gns, yns, rns, gew, yew, rew}
`define YNS 4'b0100 // Waits in state GNS until carew is true, then sequences YNS, GEW, YEW
`define GEW 4'b0010 // and back to GNS.
`define YEW 4'b0001 //------------------------------------------------------
//--------------------------------------------- module Traffic_Light(clk, rst, carew, lights) ;
// define output codes input clk ;
//--------------------------------------------- input rst ; // reset
`define GNSL 6'b100001 input carew ; // car present on east-west road
`define YNSL 6'b010001 output [5:0] lights ; // {gns, yns, rns, gew, yew, rew}
`define GEWL 6'b001100 wire [`SWIDTH-1:0] state, next ; // current and next state
`define YEWL 6'b001010 reg [`SWIDTH-1:0] next1 ; // next state w/o reset
//--------------------------------------------- reg [5:0] lights ; // output - six lights 1=on
// define flip-flop
//--------------------------------------------- // instantiate state register
module DFF(clk, in, out) ; DFF #(`SWIDTH) state_reg(clk, next, state) ;
parameter n = 1; // width
input clk ; // next state and output equations - this is combinational logic
input [n-1:0] in ; always @(state or carew) begin
output [n-1:0] out ; case(state)
reg [n-1:0] out ; `GNS: {next1, lights} = {(carew ? `YNS : `GNS), `GNSL} ;
`YNS: {next1, lights} = {`GEW, `YNSL} ;
always @(posedge clk) `GEW: {next1, lights} = {`YEW, `GEWL} ;
out = in ; `YEW: {next1, lights} = {`GNS, `YEWL} ;
endmodule endcase
end
// add reset
carew
assign next = rst ? `GNS : next1 ;
endmodule
carew
gns yns gew gew

100 001 010 001 001 100 001 010

Separate assign
for reset
 Use defines for state assignment and width.
Defines for output codes are a good idea too.
//--------------------------------------------- //------------------------------------------------------
// FSM Example for Lecture 7 // Traffic_Light
// Bill Dally 1/30/03 // Inputs:
//--------------------------------------------- // clk - system clock
// define state assignment - one hot // rst - reset - high true
//--------------------------------------------- // carew - car east/west - true when car is waiting in east-west direction
`define SWIDTH 4 // Outputs:
`define GNS 4'b1000 // lights - (6 bits) {gns, yns, rns, gew, yew, rew}
`define YNS 4'b0100 // Waits in state GNS until carew is true, then sequences YNS, GEW, YEW
`define GEW 4'b0010 // and back to GNS.
`define YEW 4'b0001 //------------------------------------------------------
//--------------------------------------------- module Traffic_Light(clk, rst, carew, lights) ;
// define output codes input clk ;
//--------------------------------------------- input rst ; // reset
`define GNSL 6'b100001 input carew ; // car present on east-west road
`define YNSL 6'b010001 output [5:0] lights ; // {gns, yns, rns, gew, yew, rew}
`define GEWL 6'b001100 wire [`SWIDTH-1:0] state, next ; // current and next state
`define YEWL 6'b001010 reg [`SWIDTH-1:0] next1 ; // next state w/o reset
//--------------------------------------------- reg [5:0] lights ; // output - six lights 1=on
// define flip-flop
//--------------------------------------------- // instantiate state register
module DFF(clk, in, out) ; DFF #(`SWIDTH) state_reg(clk, next, state) ;
parameter n = 1; // width
input clk ; // next state and output equations - this is combinational logic
input [n-1:0] in ; always @* begin
output [n-1:0] out ; case(state)
reg [n-1:0] out ; `GNS: {next1, lights} = {(carew ? `YNS : `GNS), `GNSL} ;
`YNS: {next1, lights} = {`GEW, `YNSL} ;
always @(posedge clk) `GEW: {next1, lights} = {`YEW, `GEWL} ;
out = in ; `YEW: {next1, lights} = {`GNS, `YEWL} ;
endmodule endcase
end
// add reset
carew
assign next = rst ? `GNS : next1 ;
endmodule
carew
gns yns gew gew

100 001 010 001 001 100 001 010

# 0 x xxxx xxxxxx
//-----------------------------------------------
# 1 0 xxxx xxxxxx // test bench
//-----------------------------------------------
# 0 0 1000 100001 module test_fsm1 ;
reg clk, rst, carew ;
# 0 0 1000 100001 wire [5:0] lights ;

# 0 0 1000 100001 traffic_light tl(clk, rst, carew, lights) ;

# 0 1 1000 100001 // clock with period of 10 units

initial
# 0 0 0100 010001 forever
begin
# 0 0 0010 001100 #5 clk = 1 ; #5 clk = 0 ;
$display("%b %b %b %b",
# 0 0 0001 001010 rst, carew, tl.state, lights ) ;
end
# 0 0 1000 100001
// input stimuli
# 0 0 1000 100001 initial begin
#10 rst = 0 ; // start w/o reset to show x state
# 0 0 1000 100001 #20 rst = 1 ; carew = 0 ; // reset
#10 rst = 0 ; // remove reset
# 0 1 1000 100001 #30 carew = 1 ; // wait 3 cycles, then car arrives
#10 carew = 0 ; // car leaves
# 0 1 0100 010001 #60 carew = 1 ; // wait 6 cycles then car comes and stays
#80 // 8 more cycles
# 0 1 0010 001100 $stop ;
end
# 0 1 0001 001010 endmodule

# 0 1 1000 100001
# 0 1 0100 010001
# 0 1 0010 001100
# 0 1 0001 001010
# 0 x xxxx xxxxxx
# 1 0 xxxx xxxxxx State starts at X
//-----------------------------------------------
// test bench
//-----------------------------------------------
# 0 0 1000 100001 need to reset
module test_fsm1 ;
reg clk, rst, carew ;
# 0 0 1000 100001 wire [5:0] lights ;

# 0 0 1000 100001 traffic_light tl(clk, rst, carew, lights) ;

# 0 1 1000 100001 // clock with period of 10 units

initial
# 0 0 0100 010001 forever
begin
# 0 0 0010 001100 #5 clk = 1 ; #5 clk = 0 ;
$display("%b %b %b %b",
# 0 0 0001 001010 rst, carew, tl.state, lights ) ;
end
# 0 0 1000 100001
// input stimuli
# 0 0 1000 100001 initial begin
#10 rst = 0 ; // start w/o reset to show x state
# 0 0 1000 100001 #20 rst = 1 ; carew = 0 ; // reset
#10 rst = 0 ; // remove reset
# 0 1 1000 100001 #30 carew = 1 ; // wait 3 cycles, then car arrives
#10 carew = 0 ; // car leaves
# 0 1 0100 010001 #60 carew = 1 ; // wait 6 cycles then car comes and stays
#80 // 8 more cycles
# 0 1 0010 001100 $stop ;
end
# 0 1 0001 001010 endmodule

# 0 1 1000 100001
# 0 1 0100 010001
# 0 1 0010 001100
# 0 1 0001 001010
# 0 x xxxx xxxxxx
//-----------------------------------------------
# 1 0 xxxx xxxxxx // test bench
//-----------------------------------------------
# 0 0 1000 100001 module test_fsm1 ;
reg clk, rst, carew ;
# 0 0 1000 100001 wire [5:0] lights ;

# 0 0 1000 100001 traffic_light tl(clk, rst, carew, lights) ;

# 0 1 1000 100001 Car arrives on

// clock with period of 10 units

# 0 0 0100 010001 initialeast-west road

forever
begin
# 0 0 0010 001100 #5 clk = 1 ; #5 clk = 0 ;
$display("%b %b %b %b",
# 0 0 0001 001010 rst, carew, tl.state, lights ) ;
end
# 0 0 1000 100001
// input stimuli
# 0 0 1000 100001 initial begin
#10 rst = 0 ; // start w/o reset to show x state
# 0 0 1000 100001 #20 rst = 1 ; carew = 0 ; // reset
#10 rst = 0 ; // remove reset
# 0 1 1000 100001 #30 carew = 1 ; // wait 3 cycles, then car arrives
#10 carew = 0 ; // car leaves
# 0 1 0100 010001 #60 carew = 1 ; // wait 6 cycles then car comes and stays
#80 // 8 more cycles
# 0 1 0010 001100 $stop ;
end
# 0 1 0001 001010 endmodule

# 0 1 1000 100001
# 0 1 0100 010001
# 0 1 0010 001100
# 0 1 0001 001010
Change the state assignment with defines

//----------------------------------
// define state assignment - Gray code
//----------------------------------
`define SWIDTH 2
`define GNS 2'b00
`define YNS 2'b01
`define GEW 2'b11
`define YEW 2'b10

33
# 0 x xx xxxxxx
# 1 0 xx xxxxxx
# 0 0 00 100001
# 0 0 00 100001
# 0 0 00 100001
# 0 1 00 100001
# 0 0 01 010001
# 0 0 11 001100
# 0 0 10 001010
# 0 0 00 100001
# 0 0 00 100001
# 0 0 00 100001
# 0 1 00 100001
# 0 1 01 010001
# 0 1 11 001100
# 0 1 10 001010
# 0 1 00 100001
# 0 1 01 010001
# 0 1 11 001100
# 0 1 10 001010
 Summary
• Sequential logic
– State feedback around combinational logic
• Synchronous sequential logic
– State register synchronizes state transitions with a clock.
– All bits of state are updated at the same time on the rising edge of the clock.
– Reduces synchronous machine design to combinational design of next-state
function.
• State diagram and table describe next-state and output functions
carew Current State Next State Output
!carew carew
carew
gns yns gew gew gns gns yns 100001 lgns
100 001 010 001 001 100 001 010 yns gew gew 010001 lyns
gew yew yew 001100 lgew
yew gns gns 001010 lyew

• State assignment
– Assign binary codes to states – one hot or binary
• Implementation
– Design combinational logic for next-state and output functions
• Verilog
– Explicitly instantiate flip-flops
– Case (or casex) statement for next-state function
– Use defines for state assignment