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Week 3 - CMOS Logic Circuits

- Switch logic uses binary variables and switches controlled by those variables to process information. MOS transistors act as switches in logic circuits. - Static CMOS gates implement logic functions using a pull-up PMOS network and a pull-down NMOS network. The gates have a restoring output. - Tri-state circuits allow outputs to be in a high impedance state. They are not true CMOS gates as their outputs are not always fully driven to VDD or GND.

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8 views

Week 3 - CMOS Logic Circuits

- Switch logic uses binary variables and switches controlled by those variables to process information. MOS transistors act as switches in logic circuits. - Static CMOS gates implement logic functions using a pull-up PMOS network and a pull-down NMOS network. The gates have a restoring output. - Tri-state circuits allow outputs to be in a high impedance state. They are not true CMOS gates as their outputs are not always fully driven to VDD or GND.

Uploaded by

서종현
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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CMOS Logic Circuits – Switch model

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Switch Logic

Digital systems use binary variables to represent information and switches


to be controlled by the variables to process information.

Variable a controls a switch that connects a voltage source to a light bulb.

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AND, OR, OR-AND Switch Networks

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Two switch networks of 3-input majority function

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Switch networks of XOR

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Example: Series-parallel networks
Draw and simplify a series-parallel circuit that realizes the function
f(d,c,b,a) = 1 if dcba is a legal thermometer encoding (0000, 0001, 0011,
0111, or 1111).
MOS Transistor 구조

7
Operation of n-channel MOSFET

8
Operation of p-channel MOSFET

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Electrical Model of PFET and NFET

10
Output voltage of an inverter as a function of input
voltage

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Logic circuit → Switches

Switches → MOS transistors

Logic circuit → MOS transistors

Gate with restoring output → static CMOS gate

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Summary

• Switch logic to drive gate circuits


• NMOS ad PMOS transistors act as switches with restrictions
• NMOS ad PMOS transistors have the parasitic resistance and
capacitance, which affect the switching delay.
CMOS Logic Circuits - Gates

14
Static CMOS Gate Circuits

restoring output

Duality?

15
CMOS gate: Monotonic decreasing function

If the transitions on the outputs are in the opposite direction to the


transitions on the inputs, it is a monotonic decreasing or inverting
logic function.

If the transitions are in the same direction, it is called a monotonic


increasing function.

To realize a non-inverting or monotonic increasing logic function


requires multiple stages of CMOS gates.

16
A CMOS Inverter

Bubble rule Where possible, signals that are output from a gate with
an inversion bubble on its output shall be input to a gate with an
inversion bubble on its input.

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Switch networks used to realize NAND and NOR gates

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A CMOS NAND

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A CMOS NOR

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Example: Four-input static CMOS NAND

Draw the transistor-level implementation of a four-input NAND gate


f = 𝑎𝑏𝑐𝑑

21
Complex Gates

AND-OR-inverter (AOI) gate

Gates built from arbitrary series-parallel (i.e., not a simple series and
parallel) networks or networks that are not series-parallel.

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XOR gates

Boolean equation for 2-input XOR gate?

Can we build a single-stage 2-input XOR gate ?

Boolean equation for 3-input XOR gate?

Can we build a single-stage 3-input XOR gate ?

23
Example: CMOS gate synthesis

Draw a complex gate for f = (𝑐 ത


ҧ 𝑏)(𝑏𝑎)

24
Summary

• CMOS gate circuit to implement a logic function f.


– Pull-down NFET network to implement for f = 0.
– Pull-up PNET network to implement for f = 1.
– Dual network of NFET network
• Inverters, NANDs, NORs, and Complex gates
• All CMOS gates are monotonically decreasing.
• Multiple stages of CMOS gates are requited to build increasing or
non-inverting functions.

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CMOS Logic Circuits – Tri-state

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Tri-state circuit

Tri-state-inverter Multiplexer using tri-state-inverters


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Circuits to avoid

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(a) Would-be-buffer

It attempts to pass 1 through NFET and a 0 through PFET.

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(b) No-restoring circuit

It does not restore its output. If b = 0, a noise in input a is passed


directly to the output.

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(c) Tri-state circuit

When a = 1 and b = 0, its output is disconnected. Due to parasitic


capacitance, the previous output value will be stored for a short period of
time on the output node. However, after a period, the stored charge will
________ and the output node becomes _________ value.
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(d) Short circuit

Both of the pull-up and pull-down network conduct when a and b are not
equal. This static current from power to ground outputs __________
value, wasting __________, and potentially __________ the chip.

32
Summary

• Tri-state circuits: Not a CMOS gate, can be in unconnected state

33

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