Verilog Description of Combinational Logic

- Introduction

1
Verilog

• A hardware description language (HDL)

• Used as an input to:
– Synthesis – implement hardware with gates, cells, or FPGAs
– Simulation – see what your hardware will do before you build it
• Basic unit is a module
• Modules have
– Module declaration
– Input and output declarations
– Internal signal declarations
– Logic definition
• Assign statements
• Case statements
• Module instantiations

2
 Example: Verilog for Thermostat

module Thermostat(presetTemp, currentTemp, fanOn) ;

input [2:0] presetTemp, currentTemp ; // temperature inputs, 3
bits each
output fanOn ; // true when current >
preset

wire fanOn ;
assign fanOn = (currentTemp > presetTemp) ;
endmodule

3
 Module declaration I/O list

module Thermostat(presetTemp, currentTemp, fanOn) ;

input [2:0] presetTemp, currentTemp ; // temperature inputs, 3 bits each
output fanOn ; // true when current > preset

Declare I/Os 3-bit wide signals

wire fanOn ;
assign fanOn = (currentTemp > presetTemp) ;
endmodule

An assign statement defines a signal

with an equation

A wire is a signal set with an assign

statement or connected to a module

4
 Example: Days in Month Function

module DaysInMonth(month, days) ;

input [3:0] month ; // month of the year 1 = Jan, 12 = Dec
output [4:0] days ; // number of days in month

reg [4:0] days ;

always @(month) begin // evaluate whenever month changes

case(month)
2: days = 5’d28 ; // February has 28
4,6,9,11: days = 5’d30 ; // 30 days have September ...
default: days = 5’d31 ; // all the rest have 31...
endcase
end
endmodule
5
module DaysInMonth(month, days) ;
Reg defines
input [3:0] month a signalof
; // month set the
in an year 1 = Jan, 12 = Dec
always
output [4:0] days ; block. It does of
// number NOTdays in month
define a register.
reg [4:0] days ; Always block evaluates each time
activity list changes. In this case
always @(month) begin each
// evaluate whenever month changes
time month changes
case(month) Case statement selects statement
2: days = 5’d28 ; // February
depending has 28
on value of argument.
4,6,9,11: days = 5’d30 ; // 30a truth
Like daystable.
have September ...
default: days = 5’d31 ; // all the rest have 31...
endcase
end Can have multiple values
endmodule per statement
Default covers values not
listed.
6
Verilog design style – for synthesizable modules

1. Combinational modules use only

1. Assign statements
2. Case or Casex statements (with default)
3. If statements – only if all signals have a default assignment
4. Instantiations of other combinational modules
2. Sequential modules use only
1. Combinational logic
2. Explicitly declared registers (flip-flops)
3. Do not use
1. Loops
2. Always blocks except for case, casex, or if
4. Do use
1. Signal concatenation, e.g., {a, b} = {c, d}
2. Signal subranges, e.g., a[7:1] = b[6:0] ;
5. Logic is organized into small modules
1. Leaf modules not more than 40 lines
2. If it could be made two modules, it should be

7
Verilog design style – for synthesizable modules

6. Use lots of comments

1. Comments themselves
2. Meaningful signal names – tempHigh, not th
3. Meaningful module names – DaysInMonth, not Mod3
7. Activation lists for case statements include ALL inputs (or use *)
8. Constants
1. All constants are `defined if used more than once
2. Width of all constants is specified 5’d31, not 31
9. Signals
1. Buses (multi-bit signals) are numbered high to low
• e.g., wire [31:0] bus
2. All signals should be high-true (except primary inputs and outputs)
10. Visualize the logic your Verilog will generate.
• If you can’t visualize it, the result will not be pretty
8
Verilog Description of Combinational Logic
- Coding examples

9
 Reminder: 4-bit Prime Number Function
0XX1
ba a a
dc 00 01 11 10 001X d 0XX1

b
00

0 1 1 1
001X
c
f
01

0 1 1 0
c

X011
X011
0 1 0 0
11

X101
d

0 0 1 0
10

X101

a
b
d

dcba b
c
0xx1 f
001x
x101
x011
10
 Using case

module prime(in, isprime) ;

input [3:0] in ; // 4-bit input
output isprime ; // true if input is prime
reg isprime ;
always @(in) begin
case(in)
1,2,3,5,7,11,13: isprime = 1'b1 ;
default: isprime = 1'b0 ;
endcase
end
endmodule

11
 Using casex

module prime1(in, isprime) ;

input [3:0] in ; // 4-bit input
output isprime ; // true if input is prime
reg isprime ;

always @(in) begin

casex(in)
4'b0xx1: isprime = 1 ;
4'b001x: isprime = 1 ;
4'bx011: isprime = 1 ;
4'bx101: isprime = 1 ;
default: isprime = 0 ;
endcase
end
endmodule
12
 Using assign

module prime2(in, isprime) ;

input [3:0] in ; // 4-bit input
output isprime ; // true if input is prime

assign isprime = (in[0] & ~in[3]) |

(in[1] & ~in[2] & ~in[3]) |
(in[0] & ~in[1] & in[2]) |
(in[0] & in[1] & ~in[2]) ;
endmodule

13
 Using structural description

module prime3(in, isprime) ;

input [3:0] in ; // 4-bit input
output isprime ; // true if input is prime
wire a1, a2, a3, a4 ;

and and1 (a1, in[0], ~in[3]) ;

and and2 (s2, in[1], ~in[2], ~in[3]) ;
and and3 (a3, in[0], ~in[1], in[2]) ;
and and4 (s4, in[0], in[1], ~in[2]) ;
or or1 (isprime, a1, a2, a3, a4) ;
endmodule

14
Which is a better description?

• Using case
• Using casex
• Using assign
• Using structural description

15
 Result of synthesizing description using case

module prime ( in, isprime );

input [3:0] in;
output isprime;
wire n1, n2, n3, n4;
OAI13 U1 ( .A1(n2), .B1(n1), .B2(in[2]), .B3(in[3]), .Y(isprime) );
INV U2 ( .A(in[1]), .Y(n1) );
INV U3 ( .A(in[3]), .Y(n3) );
XOR2 U4 ( .A(in[2]), .B(in[1]), .Y(n4) );
OAI12 U5 ( .A1(in[0]), .B1(n3), .B2(n4), .Y(n2) );
endmodule
in[0]

in[3] n3 U5
U3

in[2] 0XX1
n4
U4 X101
X01X X011
X10X n2
isprime
U1
in[1] n1
U2
001X
16
Synthesis Reports
**************************************** ****************************************
Report : area Report : timing
Design : prime -path full
Version: 2003.06 -delay max
Date : Sat Oct 4 11:38:08 2003 -max_paths 1
**************************************** Design : prime
Version: 2003.06
Library(s) Used: Date : Sat Oct 4 11:38:08 2003
****************************************
XXXXX
Operating Conditions:
Number of ports: 5 Wire Load Model Mode: enclosed
Number of nets: 9
Number of cells: 5 Startpoint: in[2] (input port)
Number of references: 4 Endpoint: isprime (output port)
Path Group: (none)
Combinational area: 7.000000 Path Type: max
Noncombinational area: 0.000000
Net Interconnect area: undefined (Wire load has zero Des/Clust/Port Wire Load Model Library
net area) ------------------------------------------------
prime 2K_5LM XXXXX
Total cell area: 7.000000
Total area: undefined Point Incr Path
--------------------------------------------------------
---
input external delay 0.000 0.000
r
in[2] (in) 0.000 0.000
r
U4/Y (EX210) 0.191 0.191
f
U5/Y (BF051) 0.116 0.307
r
U1/Y (BF052) 0.168 0.475
f
isprime (out) 0.000 0.475
f
data arrival time 0.475
--------------------------------------------------------
---
(Path is unconstrained)
 Summary

• Truth table can be directly converted to a Verilog case statement.

• The Verilog casex statement is like the case statement, but it allows
our cases to allow x's (don't cares) in some of the bits.

• The Verilog assign statement allows to write a logic equation

directly.
• Synthesizer keeps the optimized logic in ____________ description.

• We verify a Verilog module by writing a ____________ for that

module. It is not _____________ and just used for ______________.

18
Verilog Description of Combinational Logic
- Testbench

19
 Using case for 4-bit Prime Number Function

module prime(in, isprime) ;

input [3:0] in ; // 4-bit input
output isprime ; // true if input is prime
reg isprime ;
always @(in) begin
case(in)
1,2,3,5,7,11,13: isprime = 1'b1 ;
default: isprime = 1'b0 ;
endcase
end
endmodule

20
 Test bench

module test_prime ;
reg [3:0] in ;
wire isprime ;
// instantiate module to test
prime p0(in, isprime) ;
initial begin
in = 0 ;
repeat (16) begin
#100
$display("in = %2d isprime = %1b",in,isprime) ;
in = in+1 ;
end
end
endmodule

21
Test benches use a very different style of Verilog

• Initial statements
• $display
• Repeat and other looping constructs
• #delay

• Don’t use these constructs in synthesizable modules

22
Testing Result

# in = 0 isprime = 0
# in = 1 isprime = 1
# in = 2 isprime = 1
# in = 3 isprime = 1
# in = 4 isprime = 0
# in = 5 isprime = 1
# in = 6 isprime = 0
# in = 7 isprime = 1
# in = 8 isprime = 0
# in = 9 isprime = 0
# in = 10 isprime = 0
# in = 11 isprime = 1
# in = 12 isprime = 0
# in = 13 isprime = 1
# in = 14 isprime = 0
# in = 15 isprime = 0
23
Wave output

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

24
 Using casex

module prime1(in, isprime) ;

input [3:0] in ; // 4-bit input
output isprime ; // true if input is prime
reg isprime ;

always @(in) begin

casex(in)
4'b0xx1: isprime = 1 ;
4'b001x: isprime = 1 ;
4'bx011: isprime = 1 ;
4'bx101: isprime = 1 ;
default: isprime = 0 ;
endcase
end
endmodule
25
module test_prime1 ;
reg [3:0] in ;
reg check ;
wire isprime0, isprime1 ;

prime p0 (in, isprime0) ;

prime1 p1 (in, isprime1) ;

initial begin
in = 0 ;
check = 0 ;
repeat (16) begin
#100
if (isprime0 !== isprime1) check = 1 ;
in = in+1 ;
end
if (check != 1) $display(“PASS”) ; else $display(“FAIL”) ;
end

endmodule
 Summary

• Truth table can be directly converted to a Verilog case statement.

• The Verilog casex statement is like the case statement, but it allows
our cases to allow x's (don't cares) in some of the bits.

• The Verilog assign statement allows to write a logic equation

directly.
• Synthesizer keeps the optimized logic in ____________ description.

• We verify a Verilog module by writing a ____________ for that

module. It is not _____________ and just used for ______________.

27