Chapter4: Combinational Logic

Lecture6- Study Decoders, Function Implementation using

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 Decoders
• A decoder is a combinational circuit that converts binary information from
n input lines to a maximum of 2n unique output lines. Only one output can
be active (high) at any time.
• Decoders are a class of combinational logic circuits that convert a set of
input variables representing a code into a set of output variables
representing a different code. The relationship between the input and
output codes can be expressed in a truth table i.e 4-to-10-lines decoder
circuit.
• If the n-bit coded information has unused combinations, the decoder has
fewer than 2n outputs

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 Decoder Applications
• Generate minterms/complement of minterms and are used for functions
implementation.
• Memory addressing- Decoders are widely used in the memory system of a
computer where they respond to the address code generated by the central
processor to activate a particular memory location.
• Code Conversion. Example is BCD-to-7-segment decoder.
• DeMUX function.
• Used in conjunction with counters to decode (detect) counter states and
provide timing or sequencing signals.
• Provide enabling inputs when used in the design of MUXs with tri-state gates.
• Computers communicate with peripheral devices (printers, modems, scanners,
keyboards, video monitors, external disk drives and other computers) by
sending and/or receiving data through I/O ports. Decoders are used to select
I/O as determined by the computer to receive or send data.

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Implementation of Full Adder with a
Decoder
• There are three inputs and eight outputs so we need 3-to-8-line
decoder
• Two OR gates are required for logical sum of the desired minterms

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 Decoder Example (Code Converter)
• BCD-to-seven-segment display converter is one common example of
code converters, which converts one BCD digit into information
suitable for driving a digit-oriented display.

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 Demultiplexer
• A decoder with an enable input (Figure 4-19) can function as
demultiplexer (1-to-4-line demultiplexer)
➢E is taken as data input line and A and B are takes as selection
inputs

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 Timing Signals Generation using
Counters
• Counters may be used to generate timing signals to control the
sequence of operations in a digital system. 2n timing signals can
be generated using an n-bit binary counter together with an n-to-
2n-line decoder

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MUX Design using Tri-State gates
and Decoders

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 3-to-8-Line Decoder
• A 3-to-8-Line Decoder is a decoder in which three inputs are
decoded into eight outputs, each representing one of the minterms
of the three input variables.
• Each one of the eight AND gates generates one of the minterms.
• A particular application of this decoder is binary-to-octal conversion,
however 3-to-8-line decoder can be used for decoding any 3-bit
code to provide eight outputs, one for each element of the code

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3-to-8-Line Decoder Truth Table
Inputs Outputs
X Y Z D0 D1 D2 D3 D4 D5 D6 D7
0 0 0 1 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 0 0 0
0 1 0 0 0 1 0 0 0 0 0
0 1 1 0 0 0 1 0 0 0 0
1 0 0 0 0 0 0 1 0 0 0
1 0 1 0 0 0 0 0 1 0 0
1 1 0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 0 0 0 1

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 Decoders with NAND gates
• Some decoders are constructed with NAND gates. Since a NAND gate
produces the AND operation with inverted output, it becomes more
economical to generate the decoder minterms in their complemented
form. Decoder include one or more enable inputs to control the circuit
operation
• A 2-to4-line decoder with an enable input is shown next. (see Fig on
next slide).
➢The circuit operates with complement outputs and a complement
enable input.
➢The decoder is enabled when E is equal to 0 and disabled when E =
1
➢The output whose value is equal to 0 represents the minterm
selected by inputs A and B.
➢Only one output can be zero at any given time, all other outputs
are 1
• Some decoders have two or more enable inputs that must satisfy a
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Decoders with NAND gates

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 Demultiplexer
• A demultiplexer is a circuit that receives information from a single line
and directs it to one of 2n possible output lines.
• The selection of a specific output is controlled by the bit combination
of n selection lines.

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 Constructing large Decoders
• Decoders with enable inputs can be connected together to form a
larger decoder circuit.
➢ two 3-to-8 decoder can be connected to form a 4-to-16 decoder
➢ The top decoder outputs generates minterms 0000 to 0111 and the
bottom decoder outputs generate minterms 1000 to 1111.
Generates from
0000 to 0111

Generates from
1000 to 1111

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Combinational Logic Implementation
• A decoder provides the 2n minterms of n input variables.
• Any function is can be expressed in sum of minterms.
• Use a decoder to make the minterms and an external OR gate to make
the logical sum.
• In this way any combinational circuit with n inputs and m outputs can
be implemented with an n-to-2n line decoder and m OR gates. Such
implementation needs that the Boolean function is expressed in sum
of minterms
• For example: consider a full adder. x y z c s
➢S(x,y,z) = Σ(1,2,4,7) 0 0 0 0 0
➢C(x,y,z) = Σ (3,5,6,7) 0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
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Implementation of Full Adder with a
Decoder
• There are three inputs and eight outputs so we need 3-to-8-line decoder
• Two OR gates are required for logical sum of the desired minterms

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Implementation of Full Adder with a
Decoder
• A function with long list of minterms requires an OR gate with large
number of inputs
• A function having a list of K minterms can be expressed in its
complemented form F′ with 2n-K minterms
• If the number of minterms in a function is greater than 2n/2 then Fˊ
can be expressed with fewer minterms
• In such case it is advantageous to use a NOR gate to sum the minterms
of Fˊ. The output of the NOR gate complements this sum and
generates the normal output F

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Problem Solving
Session

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Problem: 4-25
Construct a 5-to-32 line Decoder with four 3-to-8 line Decoders with an
enable input and a 2-to-4 line Decoder. Use block diagrams for the
components.

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Problem: 4-27
CA combinational circuit is specified by the following three Boolean
equations:-
F1 (A,B,C)=∑(2,4,7)
F2 (A,B,C)=∑(0,3)
F3 (A,B,C)=∑(0,2,3,4,7)
Implement the circuit with a Decoder constructed with NAND gates and
external NAND or AND gates connected to the Decoder outputs. Use a
block diagram for the Decoder. Minimize the number of inputs in the
external gates.

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The End

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