JOURNAL OF COMPUTING, VOLUME 2, ISSUE 6, JUNE 2010, ISSN 2151-9617 HTTPS://SITES.GOOGLE.COM/SITE/JOURNALOFCOMPUTING/ WWW.JOURNALOFCOMPUTING.

ORG 208

Optimization of reversible sequential circuits

Abu Sadat Md. Sayem, Masashi Ueda
AbstractIn recent years reversible logic has been considered as an important issue for designing low power digital circuits. It has voluminous applications in the present rising nanotechnology such as DNA computing, Quantum Computing, low power VLSI and quantum dot automata. In this paper we have proposed optimized design of reversible sequential circuits in terms of number of gates, delay and hardware complexity. We have designed the latches with a new reversible gate and reduced the required number of gates, garbage outputs, and delay and hardware complexity. As the number of gates and garbage outputs increase the complexity of reversible circuits, this design will significantly enhance the performance. We have proposed reversible D-latch and JK latch which are better than the existing designs available in literature. Index TermsReversible logic, garbage output, Latch, quantum computation

to be in demand in high speed power aware circuits, low 1 INTRODUCTION powerCMOSdesign. The main challenges of designing reversible circuits are to reduce number of gates, garbage outputs, delay and quantum cost. Another important matter is hardware odels of computation which are not logically complexity.Intheexistingdesignsinliteratureofsequential reversibletypicallyloseinformationintheprocess circuitsseveraldesignsareproposed.Inthispaperwehave of execution. As the laws of physics appear to be proposedmostoptimizeddesignsofreversibleDLatchand reversible, that information cannot really be being lost, it JK Latch. While designing the reversible latches; few must be being translated into another form. That form is researchers concentrated on reducing the number of gates usually heat. So, loss of information results power and garbage output, while other tried to reduced the dissipation.Toreducethispowerdissipationreversiblelogic quantum cost. . In this paper we optimized the number of wasintroduced.Themainideaofreversiblelogicistoallow gates, garbage output, delay and hardware complexity for the construction of reversible computers by using the total circuit and shown the results with illustrative components which preserve information content, and can calculation. Reversible RS and T latch is designed in the thuspotentiallyberunbackwards.Hence,byimplementing mostoptimizedformin[4].SowehaveworkedwiththeD reversibledesignsofcomputerhardwaresignificantamount Latch and JK Latch. A new reversible gate Sayem Gate of heat can be reduced. It has been shown that, for (SG)isproposedheretodesignthelatches. irreversible logic computations, each bitof information lost generates kTln2 joules of heat energy, where k is 2 REVERSIBLE LOGIC AND DIFFERENT REVERSIBLE Boltzmanns constant and T the absolute temperature at GATES: which computation is performed [1],[2]. Benet showed the Inthissection,wehavepresentedthebasicdefinitionsand reversethat,kTln2energydissipationwouldnotoccurifthe ideas related to reversible logic and few reversible gates computationwerecarriedoutinareversiblemanner[3]. whichareusedandrelevantwiththisresearchwork. Reversible circuits do not lose information and reversible computation in a system can be performed only when the Definition2.1.a. A Reversible Gate is a kinput, koutput systemconsistsofreversiblegates.Reversiblelogicislikely (denoted by k * k) circuit that produces a unique output

pattern[5],[6]foreachpossibleinputpattern. Definition 2.1.b. ReversibleGatesarecircuitsinwhichthe number of outputs is equal to the number of inputs and there is a one to one correspondence between the vector of

A. S. M. Sayem is with the National Institute of informatics, Tokyo, Japan. M. Ueda is with the National Institute of informatics, Tokyo, Japan.

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inputsandoutputs,i.e.,itcangenerateuniqueoutputvector fromeachinputvectorandviceversa. A reversible circuit must incorporate reversible gates in it andthenumberofgatesusedinadesignisalwaysagood complexitymeasureforthecircuit.Itisalwaysdesirableto realizeacircuitwithminimumnumberofgates. Example2.1.LettheinputvectorbeIv,outputvectorOvand theyaredefinedasfollows,Iv=(Ii,Ii+1,Ii+2Ik1,Ik,)andOv= (Oi,Oi+1,Oi+2Ok1,Ok).Foreachparticulari,thereexiststhe relationshipIvOv Definition2.2. Unwanted or unused output of a reversible gate(orcircuit)isknownasGarbageOutput.Moreformally, theoutputs,whichareneededonlytomaintainreversibility, arecalledgarbageoutputs. Example2.2. If we wish to perform ExclusiveOR between two inputs, we can use the Feynman gate [7], but in that case,oneextraoutputwillbegeneratedaswell,whichisthe garbage output in this regard. The garbage output of FeynmanisshowninFig.2.1with*.
Fig 2.2 Block diagram of Toffoli Gate

Toffoli gate plays an important role in the reversible logic synthesis. It is also used in the design of any Boolean function and hence it can be considered as a universal reversiblegate. Definition2.5. Theinputvector,Ivandoutputvector,Ovfor 3*3Fredkingate(FRG)[9]isdefinedasfollows:Iv ( A, B, C)

_ _ =andOv=(P= A ,Q= A B AC ,R= A C AB ).

Example2.5. The block diagram for 3 * 3 Fredkin gate is showninFig2.3.

Fig 2.1 Garbage Output Fig 2.3 Block diagram of a 3 * 3 Fredkin gate.

Definition2.3. Theinputvector,Ivandoutputvector,Ovfor 2 * 2 FeynmanGate(FG) [7] is defined as follows: Iv=(A,B) andOv=(P=A,Q=A B). Example 2.3: The block diagram for 2 * 2 Feynman gate is showninFig2.1. FeynmangateisalsoknownasCNOT(ControlledNot)gate. Thetwokeyreasonstousethisgateinreversiblecircuitare: makethecopyofaninput(puttinganyof theinputaconstant0) ii) to invert an input bit ( putting any of the inputaconstant1) Definition2.4. Theinputvector,Ivandoutputvector,Ovfor 3 * 3 Toffoligate(TG) [8] is defined as follows: Iv=(A,B,C) andOv=(P=A,Q=B,R=AB C). i)

Fredkin gate also has its importance in reversible literature as it is a 1through gate (one input is directly generated as output) and two other outputs can generate two different Boolean functions. Fredkin gate is the mostly used reversiblegatetodesignreversiblelatches. Definition2.6. The input vector, Ivand output vector, Ovfor 3 * 3 Peres gate (PG)[10] is defined as follows: Iv = (A,B, C) andOv=(P=A,Q=A B,R=AB C). Example2.6.Theblockdiagramfor3*3Peresgateisshown inFig2.4

Example2.4. The block diagram for 3 * 3 Toffoli gate is showninFig2.2.

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Fig 2.4 Block diagram of a 3 * 3 Peres gate.

to be taken under consideration. According to [12] delay is definedasfollows Thedelayofalogiccircuitisthemaximumnumberofgates in a path from any input line to any output line. This definitionisbasedonthefollowingassumptions: Eachgateperformscomputationinoneunittime. All inputs to the circuit are available before the computationbegins. ThedelayofthecircuitofFig2.1isobviously1asitisthe onlygateinanypathfrominputtooutput. In this paper in every calculation we use the definition of delayof[12].

ActuallythePeresGateisthecombinationofFeynmanGate (FG) and Toffoli Gate (TG), and so it can simultaneously generate two output functions (from Q and R). Peres gate has the least quantum cost among the all 3X3 reversible gates, so it is mostly used in the various reversible logic circuits.

2.2 OPTIMIZATION PARAMETERS:

The main challenge of designing reversible circuits is to optimize the different parameters which result the design costly. The most important parameters which have dominantcontributionindesigningreversiblecircuitsare Garbage Output: Garbage outputs are the unwanted outputs of a reversible circuit which is described in the section 2.1.c. The less number of garbage outputs are produced the higher the performance and lesser the complexityofacircuitis. Numberofgates:Thetotalnumberofgatesusedinacircuit. Minimumpossiblenumberofgatesmustbeusedinacircuit. QuantumCost:Thisreferstothecostofthecircuitinterms of the cost of a primitive gate. It is calculated knowing the number of primitive reversible logic gates (1*1 or 2*2) requiredtorealizethecircuit. Flexibility: This refers to the universality of a reversible logicgateinrealizingmorefunctions GateLevel:Thisreferstothenumberoflevelsinthecircuit whicharerequiredtorealizethegivenlogicfunctions. HardwareComplexity:itreferstothetotalnumberoflogic operationinacircuit.MeansthetotalnumberofAND,OR andEXORoperationinacircuit.[11] Delay:Delayisoneofthemostimportantparameterwhile designing reversible circuits. Many researchers suggested different definition of Delay for reversible circuits. In [4] Delayhasbeencalculatedbythequantumcost.Inquantum computation each gate is realized using 1x1 or 2x2 reversible gates such Controlled V gate,, ControlledV+ gate,CNOTgate.In[4]ifthequantumofcostofareversible gateisxthenthedelayisconsideredasx,whereisunit delay .But as the delay is directly related to the number of gatessotheconceptofdelaywithquantumcostshouldyet

3 PROPOSED REVERSIBLE GATE

WehaveproposedanewreversiblegatenamedSayemGate (SG).SGisa1trough4x4reversiblegate.Theinputand outputvectorofthisgateare, Iv=(A,B,C,D)and Ov=(A,AB AC,AB AC D,AB AC D).the blockdiagramofthisgateisshowninFig3.1

Fig3.1. Block diagram of new reversible SG

WecanverifyfromthecorrespondingtruthtableofSGthat the output and input vectors have one to one mapping between them which satisfies the condition of reversibility ofagate.ThecorrespondingtruthtableisshowninTableI. We can see from Table I that the 16 different input and output vectors are unique means they have one to one mapping between them. So SG satisfies the condition of reversibility.

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TABLE I: TRUTH TABLE OF NEW REVERSIBLE SG

A 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

of SG. Fig 4.1(a) shows the design of DLatch with only Q outputandFig3.1(b)showsthedesignofreversibleDLatch with both the output Q and Q+ .One FG is needed tocopy andproducethecomplementofQfromSGforthedesignof Fig 4.1(b). In the existing design of literature except the design of [4], [13], [14] all the latches were designed with only output Q. But the complement output Q+ is also needed in various logic implementation of nanotechnology based system. So we also proposed a novel design of reversibleDLatchwithQandQ+.OurdesignneedsoneSG andoneFGwhilethedesignof[4]needsoneFRGandtwo FGs. So numbers of gates are reduced. In [14] the same design is proposed using two FRG but in that case the hardware complexity is much than our design which is illustratively shown in the discussion section. The delay of thisdesignisalsolessthanthedesignof[4]. ThegaterequiredforthedesignwithQandQ+is2while3 gatesarerequiredinthedesignof

B 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

C 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

D A AB AC 0 0 0 1 0 0 0 0 0 1 0 0 0 0 1 1 0 1 0 0 1 1 0 1 0 1 0 1 1 0 0 1 1 1 1 1 0 1 0 1 1 0 0 1 1 1 1 1

ABAC D 0 1 0 1 1 0 1 0 0 1 1 0 0 1 1 0

ABAC D 0 1 1 0 0 1 1 0 0 1 0 1 1 0 1 0

Fig 3.2 SG as a two input universal gate

Fig 4.1(a): Proposed design of D-Latch with only output Q

Thisgatecanbeusedasatwoinputuniversalgatemeansit canperformanytwoinputBooleanfunction.Ifwegivethe 3rdinput0and4thinput1wegetNANDoffirsttwoinputs atthe4thoutputwhichsatisfiestheuniversalityofagatein Booleanlogic.ThisoperationisshowninFig3.2.Withthis new reversible SG reversible Latches can be design efficiently.
Fig 4.1(b): Proposed design of D-Latch with output Q and Q
+

DESIGN OF REVERSIBLE LATCHES:

[4].Delayiscalculatedforthisdesignwiththecalculationof [12].Delayofourdesignis2whilethedelayof[4]is3.This isthemostoptimizeddesignofreversibleDLatchinterms of number of gates and garbage output. We observed that no further improvement is possible for number of gates requiredforthedesignofreversibleDLatch.

In this section we described the proposed novel design of reversible DLatch and JK Latch which are optimized in terms of the optimization parameters described in section 2.2.

4.1 D-LATCH:
ThecharacteristicequationofDLatchisQ+=DE+EQ.Itcan be realized with one SG. It can be mapped with SG by givingE,Q,Dand0respectivelyin1st,2nd,3rdand4thinput

4.2 J-K LATCH:

The characteristics equation of JK latch is Q+= (JQ+KQ) E+EQ.ItcanbemappedwithoneFRGand1SG.Equation

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JQ+KQisrealizedby1FRGwithcomplementofKgiving inthe3rdinput.Nowthe2ndoutputofFRGisJQ+KQwhich canbeusedasinputDofDlatchshowninprevioussection. One SG is needed to get the desired output of (JQ+KQ) E+EQ.For generating both the Q and Q+ we need another FG.BothdesignsareshowninFig4.2(a)andFig4.2(b).

TABLE II: COMPARISON OF DIFFERENT D-LATCH WITH OUTPUT Q

D-Latch with Q This work Existing work[4] Components and cost
No of gates Garbage Output Delay

1 2

2 2

1 2

TABLE III: COMPARISON OF DIFFERENT D-LATCH WITH OUTPUT Q AND Q+

D-Latch with Q and Q+ This work Components and cost
No of gates Garbage Output Delay

2 3 7

2 2 6

2 3 7

Fig 4.2(a) Proposed design of reversible JK Latch with output Q

Existing work[4] Existing work [13]

From table II we can see that the design is better than the designof[4].hereweneedonlyonegateforgeneratingthe Qoutputwhilethedesignof[4]needstwogates.Thedelay ofourdesignis1andthedelayof[4]is2.Sothisdesignis optimizedthanthedesignof[4]intermsofnoofgates. Table III shows the comparison of different Dlatches with
Fig 4.2(a) Proposed design of reversible JK Latch with output Q and Q
+

output Q and Q+. This work needs only 2 gates while [4] need 3 gates.The delay ofour design is 2 and the delay of [4]is3.Sothisdesignisbetterthan[4]intermsofnumber of gates and delay. The same design is proposed with two gatesin[14]butthatdesignhasmorehardwarecomplexity. If

To design the JK Latch with Only Q our design needs only 2 reversiblegateswith3garbageoutputsandwithbothoutputQ andQ+itneeds3reversiblegateswith3garbageoutputs.

RESULTS AND DISCUSSION

= A two input EX-OR gate calculation = A two input AND gate calculation = A NOT calculation Then the hardware complexity of our design is 5+6+3 where the hardware complexity of [14] is 4+8+4 so this design is better than the design of [14] also. Evaluation of proposed design of Reversible JK Latch: Our proposed design of reversible JK latch is better than the design of existing designs in literature. Table IV and V shows the comparative results of different JK latch designs.

5.1 Evaluation of Proposed Reversible SG: The proposed reversible gate is a 1 through 4X4 gate.Itcanbeusedasatwoinputuniversalgate.Usingthis gate the design ofdifferentLatches has been improved. As latches are most important memory elements and used in severalcircuitslikeRAM,LogicBlocksofFPGA[15]sothis gate can contribute significantly in the reversible Logic community. 5.2EvaluationofproposeddesignofDLatch: The two different design of reversible DLatch are optimized than the existing design of literature. In table II andIIIthecomparisonofdifferentdesignsareshown.

TABLE IV: COMPARISON OF DIFFERENT REVERSIBLE JK LATCH WITH

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OUTPUT Q
JK Latch with Q This work Existing work[4] Components and cost
No of gates Garbage Output Delay

ACKNOWLEDGEMENT
Authors would like to thank National Institute of Informatics, Tokyo, Japan for supporting the research program. We are grateful to member of informatics lab of National Institute of Informatics for their co operation to complete the research work.

2 3

3 3

2 3

REFERENCES
TABLE V: COMPARISON OF DIFFERENT REVERSIBLE JK LATCH WITH OUTPUT Q AND Q+
D-Latch with Q and Q+ This work Existing design[4] Existing design [13] Components and cost
No of gates Garbage Output Delay

3 4 10

3 3 12

3 4 10

[1] R. Keyes, R. Landauer Minimal Energy Dissipation In IBMJournalofResearchandDevelopment1970;14:1537. [2] R. Landauer Irreversibility and heat generation in the computational processs IBM Journal of Research Development1961;5:18391. [3] C.H Bennett Logical reversibility of computation; IBM JournalofResearchandDevelopment1973;17:52532. [4] R. Thapliyal, N. Ranganathan. Design of Reversible Latches Optimized for Quantum Cost, Delay and Garbage Outputs, vlsid, pp.235240, 2010 23rd International ConferenceonVLSIDesign,2010 [5] .M.H. Babu, M.R. Islam, A.R. Chowdhury, S.M.A. Chowdhury, Reversible logic synthesis for minimization of fulladder circuit, IEEE Conference on Digital System Design2003;504. [6] H.M.H. Babu, M.R. Islam, A.R. Chowdhury, .SM.A. Chowdhury, Synthesis of fulladder circuit using reversible logic, 17th International Conference on VLSI Design2004;75760. [7] R. Feynman, Quantum Mechanical Computers, Optical News1985;1120. [8] T.Toffoli Reversible Computing, Tech memo MIT/LCS/TM151,MITLabforComputerScience1980. [9] E. Fredkin and E. Toffoli Conservative Logic, InternationalJournalofTheoreticalPhysics,1983;21:21953. [10]A. Peres. Reversible Logic and Quantum Computers, PhysicalReview,1985;326676. [11]M. Haghparast,K. Navi, A Novel Reversible BCD Adder For Nanotechnology Based Systems; American Journal of AppliedSciences5(3):282288,2008,ISSN15469239. [12]A.K.Biswas,M.M.Hasan,A.R.ChowdhuryandH.M.H. Babu, Efficient Algorithms for Implementing Reversible BinaryCodedDecimalAdders,Microelectron.J,39(12):1693 1703,2008. [13] H. Thapliyal, M. B. Srinivas, and M. Zwolinski, A beginning in the reversible logic synthesis of sequential circuits,In Proc. the Military and Aerospace Programmable LogicDevicesIntl.Conf.,Washington,Sept.2005.

From table IV we can see that the design of reversible JK latchwithonlyoutputQwasrealizedby3gatesanddelay was3in[4]whileourdesignisrealizedwithtworeversible gatesanddelayis2.Sothisdesignisbetterthanthedesign of[4]intermsofnumberofgateanddelay. ThedesignofreversibleJKlatchwithoutputQandQ+was realized with 4 gates in [4] and 10 gates in [13] where our design needs only 3 gates. The delay for our proposed design is 3, where in [4] its 4 and in [13] its 10. So our proposeddesignisoptimizedthan[4]and[13]. ThesamedesignofreversibleJKLatchwasproposedwith3 gatesin[14]butthatdesignhasmuchhardwarecomplexity than ours. The hardware complexity of our design is

7+10+7 and the hardware complexity of [14] is 6+12+8. Though is greater but the other two parameter are less than
[14]thuswecansaythatourproposeddesignisbetterthan [14] in terms of hardware complexity. We have observed that no further improvement is possible for designing a reversibleJKlatchintermsofnumberofgates.

CONCLUSION:
In this paper we have proposed the reversible design of DLatch and JK Latch. Latches are important memory element. Thus this optimization will result in great contribution in designing logic circuits with memory and sequential elements. We have given the lower bounds for both the design in terms of number of gates and delay. We have proposed a new reversible gate which can contribute significantly in reversible logic community.

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[14]H. Thapliyal and A. P. Vinod, Design of reversible sequential elements with feasibility of transistor implementation In Proc. the 2007 IEEE Intl. Symp. On Cir. andSys.,pages625628,NewOrleans,USA,May2007. [15]A.S.M. Sayem,M.M.A. Polash,H.M.H. Babu,Design of a reversible logic block of FPGA, proceedings of silver Jubilee Conference on Communication Technologies and VLSI design (CommV09), VIT University, Vellore, India.Oct.810,2009,pp:501502.

A.S.M. Sayem received his B.Sc. degree in Computer Science & Engineering from University of Dhaka, Bangladesh in 2009.He is perusing his M.Sc.in Computer Science & Engineering from University of Dhaka and currently on a research program in National Institute of Informatics, Tokyo, Japan. He is a member of IEEE. He was awarded IEEE Computer Society best student paper award in the Silver Jubilee Conference on Communication Technologies and VLSI design (CommV09), VIT University, Vellore, India.Oct. 8-10, 2009. His research interest includes reversible logic design, Low power VLSI, DNA computing and finite languages.

M.Ueda is an Assistant Professor in National Institute of Informatics, Japan from 2006. He received his B.Ec. in Faculty of Economics, Kyoto University in 1998, and M.I. in Graduate School of Informatics, Kyoto University in 2000. He was a visiting fellow in Crawford School of Economics and Government, Australian National University in 2006, and was post doctorial fellow in Institute of Economics and Political Studies, Kansai University, Japan from 2003 to 2005. His concern is social effect of network structure and its competitive modeling. His analysis is focused upon public utility services, like high-speed Internet infrastructure, grid networks, and open source software, based upon economics and management approach.