Unit-4

Combinational Logic
Combinational circuit is a circuit which consist of logic gates whose outputs at any instant of
time are determined directly from the present combination of inputs without regard to
previous input. The combinational circuit do not use any memory.
- There will be 2𝑛 combination of input variable for 𝑛 inputs.
- A combinational circuit can have 𝑛 number of inputs and 𝑚 number of outputs.
- For e.g. adders, subtractors, decoders, encoders etc.

Fig: Block diagram of combinational circuit

Combinational logic circuit design procedure:
1. The problem is stated.
2. The number of available input variables and required output variables is determined.
3. The input and output variables are assigned letter symbols.
4. The truth table that defines the required relationships between inputs and outputs is
derived.
5. The simplified Boolean function for each output is obtained.
6. The logic diagram is drawn.

Adders
Adders are the combinational circuits which is used to add two or more than two bits at a
time.
Types of adders:
- Half Adder
- Full Adder

1. Half Adder:
A combinational circuit that performs the addition of bits is called half adder. This circuit
needs two binary inputs and two binary outputs. The input variables designate the
augend(𝐴) and addend(𝐵) bits; the output variables produce the sum(𝑆) and carry(𝐶).

Fig: Block diagram

Truth table to identify the function of half adder:

K-map:

From k-map the logical expression for sum and carry is:
𝐶 = 𝐴𝐵
𝑆 = 𝐴̅𝐵 + 𝐴𝐵̅= 𝐴⨁𝐵
Logic diagram:

Q. Design a half adder using only NAND gates.

Soln:
Input variables: A & B, Output variables: sum(𝑆) and carry(𝐶)
𝑆 = 𝐴̅𝐵 + 𝐴𝐵̅
𝐶 = 𝐴𝐵
Logic diagram of half adder using NAND gates only:
Q. Design a half adder logic circuit using NOR gates only.
Soln:
Input variables: A & B, Output variables: sum(𝑆) and carry(𝐶)
̅
𝑆 = 𝐴𝐵 + 𝐴𝐵 ̅
𝐶 = 𝐴𝐵
Logic diagram of half adder using NOR gates only:

2. Full Adder:
A combinational circuit that performs the addition of three bits at a time is called full
adder. It consists of three inputs and two outputs, two inputs are the bits to be added, the
third input represents the carry from the previous position.

Fig: Block diagram

Truth table for full adder:

- The sum(S) output is equal to 1 when

only one input is equal to 1 or when all
three inputs are equal to 1.
- The carry output (𝐶𝑜𝑢𝑡) has a carry 1 if
two or three inputs are equal to 1.
Simplified expression using k-map in SOP can be obtained as;

𝑆𝑢𝑚(𝑆) = 𝐴̅𝐵̅𝐶𝑖𝑛 + 𝐴̅𝐵𝐶𝑖̅ 𝑛 + 𝐴𝐵̅𝐶𝑖̅ 𝑛 + 𝐴𝐵𝐶𝑖𝑛

𝐶𝑜𝑢𝑡 = 𝐴𝐵 + 𝐴𝐶𝑖𝑛 + 𝐵𝐶𝑖𝑛
Logic Diagram:

For carry For sum

Fig: SOP implementation of full-adder
Note: It can also be implemented in POS form. (Try yourself)

Implementation of a full-adder with two half-adders and an OR gate:

(See the derivation part in your class note)

Subtractors
Subtractor is a combinational logic circuit which is used to subtract two or more than two bits
at a time, and provides difference and borrow as an output.
Types of Subtractors:
- Half subtractor
- Full subtractor

1. Half Subtractor:
A half-subtractor is a combinational logic circuit that subtract two bits at a time and
produces their difference.
It has two inputs minuend (A) & subtrahend (B) and two outputs difference and borrow.
The difference is a result of subtraction and borrow is used to indicate borrow from next
most significant bit. The borrow bit is present only when 𝐴 < 𝐵.

Truth table:

K-map:

Logic Diagram:

Fig: Implementation of half-subtractor

2. Full Subtractor:
A combinational logic circuit used to subtract three binary digits at a time is called full
subtractor.
This circuit has three input and two outputs. The three inputs are 𝐴, 𝐵 𝑎𝑛𝑑 𝐵𝑖𝑛, denote the
minuend, subtrahend and previous borrow respectively. The two outputs, 𝐷 𝑎𝑛𝑑 𝐵𝑜𝑢𝑡
represent the difference and output borrow, respectively.
Truth table for full subtractor:

Simplified expression of D and Bout using k-map in SOP can be obtained as;

Logic circuit for full subtractor:

For D For Bout

Fig: SOP implementation of full-subtractor

Note: It can also be implemented in POS form. (Try yourself)

Implementation of full subtractor using two half subtractor and one OR gate:

(Similar to that of full adder)

Parity Generator and Checker

Parity Generator:
A parity generator is a combinational logic circuit that generates the parity bit in the
transmitter.
- A parity bit is used for the purpose of detecting errors during transmission of binary
information. It is an extra bit included with a binary message to make the number of 1’s
either odd or even.
- Types of parity: Even parity & Odd parity.
- In Even parity, added parity bit will make the total number of 1’s an even amount.
- In Odd parity, added parity bit will make the total number of 1’s an odd amount.
3-bit even parity generator truth table:

Solving the truth table for all the

cases where 𝑃 is 1 using SOP
method:
3-bit even parity generator circuit:

Parity checker:
A circuit that checks the parity in the receiver is called parity checker. The parity checker
circuit checks for possible errors in the transmission.
- Since the information transmitted with even parity, the received must have an even
number of 1’s. If it has odd number of 1’s, it indicates that there is an error occurred
during transmission.

3-bit even parity checker truth table;

The output of the parity checker is denoted by 𝑃𝐸𝐶 (Parity Error Checker). If there is error,
that is, if it has odd number of 1’s, it will indicate 1. If no then 𝑃𝐸𝐶 will indicate 0.
3-bit even parity checker circuit:

# Implementation of half subtractor using universal gate:

Using NAND gate only:

Using NOR gate only:

Binary Adder
This circuit sums up two binary numbers 𝐴 𝑎𝑛𝑑 𝐵 of n-bits using full-adders to add each bit
pair and carry from previous bit position.

Binary Parallel Adder:

A binary parallel adder is a digital circuit that produces the arithmetic sum of two binary
numbers in parallel. It consists of full adders connected in cascade, with the output carry from
one full adder connected to the input carry of the next full adder. An 𝑛 bit parallel adder
requires 𝑛 full adders.

4-bit binary parallel adder:

Fig: 4-bit binary parallel adder

A 4-bit binary parallel adder consists of 4-full adder. The augend bits are 𝐴4, 𝐴3, 𝐴2, 𝐴1 and
addend bits are 𝐵1, 𝐵2, 𝐵3, 𝐵4. This parallel adder produces their sum as 𝐶4𝑆3𝑆2𝑆1𝑆0 where
𝐶4 is the final carry. The carries are connected in chain through the full-adders. The input
carry to the first full adder is 𝐶1 and the output carry from MSB position of full adder is 𝐶4.

Magnitude Comparator
A magnitude comparator is a combinational circuit that compares two numbers 𝐴 & 𝐵 and
determines their relative magnitudes. The outcome of the comparison is specified by three
binary variables that indicate whether 𝐴 > 𝐵, 𝐴 = 𝐵, 𝑜𝑟 𝐴 < 𝐵.

Note: Out of these three outputs only one

output will be 1 and other two outputs will
be 0 at a time.
1-bit magnitude comparator: (Refer to class note)

2-bit magnitude comparator: (Refer to class note)

Decoders
A decoder is a combinational circuit that converts binary information from 𝑛 input lines to a
maximum of 2𝑛 unique output lines.
- If 𝑛-bit decoded information has unused or don’t care combinations, the decoder output
will have less than 2𝑛 outputs.
- The decoders presented here are called 𝑛 − 𝑡𝑜 − 𝑚 line decoders where 𝑚 ≤ 2𝑛. Their
purpose is to generate the 2𝑛 (or less) minterms of 𝑛 input variables.

3-to-8 line decoder:

The three inputs are decoded into eight outputs, each output representing one of the minterms
of the 3-input variables.
A particular application of this decoder would be a binary-to-octal conversion. The input
variable may represent a binary number and the outputs will then represent the eight digits in
the octal number system
Three inputs: 𝑋, 𝑌 & 𝑍
Eight outputs: 𝐷0 − 𝐷7

Fig: 3-to-8 line decoder

Truth table:

From the truth table it is observed that the output variables are mutually exclusive because
only one output can be equal to 1 at any one time. The output line whose value is equal to 1
represents the minterm equivalent of the binary number presently available in the input lines.

Encoder
An encoder is a combinational circuit that performs the inverse operation from that of
decoder. It has 2𝑛 input lines and 𝑛 output lines.
The output lines generate the binary code corresponding to the input value.

Fig: Block diagram of encoder

E.g. Octal to binary encoder which has 8 inputs and 3 outputs.
Truth table for octal to binary encoder:

Boolean function of output variables:

𝑋 = 𝐷4 + 𝐷5 + 𝐷6 + 𝐷7
𝑋 = 𝐷2 + 𝐷3 + 𝐷6 + 𝐷7
𝑋 = 𝐷1 + 𝐷3 + 𝐷5 + 𝐷7

Logic circuit:

Limitation: Only one input can be enabled at a time. If two inputs are enabled at the same
time, then output is undefined.
Q. Design a 2-to-4 line decoder using NAND gates.
Soln:

Truth table:
Inputs Outputs
A B 𝐷0 𝐷1 𝐷2 𝐷3 For the NAND decoder only one output can be
0 0 0 1 1 1 LOW and equal to logic ‘0’ at any given time
0 1 1 0 1 1 with all other outputs being HIGH at logic ‘1’.
1 0 1 1 0 1
1 1 1 1 1 0

Note: Similar method for 3-to-8 line decoder in which 3-lines of input are present and 8
output lines.
Q. Using a decoder and external gates, design the combinational circuit defined by the
following three Boolean functions:
𝑭𝟏 = 𝒙′𝒚′𝒛 + 𝒙𝒛′
𝑭𝟐 = 𝒙′𝒚𝒛′ + 𝒙𝒚′
𝑭𝟑 = 𝒙𝒚𝒛′ + 𝒙𝒚
Soln:
Truth table:

Logic Diagram

Multiplexer (MUX)
- A multiplexer is a combinational circuit that selects binary information from one of many
input lines and directs it to a single output line.
- Multiplexing is the process of transmitting a large number of information over a single
line.
- The selection of a particular input lines is controlled by a set of selection lines. Normally
there are 2𝑛 input lines and 𝑛 selection lines whose bit combinations determine which
input is selected.
- A multiplexer is also called a data selector, since it selects one of many inputs and steers
the binary information to the output line.
4-to-1 line Multiplexer:
Demultiplexer (DEMUX)
- A decoder with an enable input can function as a de-multiplexer.
- A de-multiplexer is a circuit that receives information on a single line and transmit this
information on one of 2𝑛 possible output lines. The selection for particular output line is
controlled by the bit values of 𝑛 selection lines.

Fig: A 2-to-4 line decoder with enable (E) input

The decoder of fig can function as a de-multiplexer if the 𝐸 line is taken as a data input line
and lines A and B are taken as the selection lines.

1 to 4 DEMUX:
The 1:4 Demux consists of 1 data input bit, 2 control bits and 4 output bits. I is the input bit,
Y0, Y1, Y2, Y3 are the four output bits and S0 and S1 are the control bits.
1 to 8 De-Multiplexer using 1x4 De-Multiplexers and 1x2 De-Multiplexer:

The common selection lines, s1 & s0 are applied to both 1x4 De-Multiplexers. The outputs of
upper 1x4 De-Multiplexer are Y7 to Y4 and the outputs of lower 1x4 De-Multiplexer are Y3 to
Y0.
The other selection line, s2 is applied to 1x2 De-Multiplexer. If s2 is zero, then one of the four
outputs of lower 1x4 De-Multiplexer will be equal to input, I based on the values of selection
lines s1 & s0. Similarly, if s2 is one, then one of the four outputs of upper 1x4 De-Multiplexer
will be equal to input, I based on the values of selection lines s1 & s0.
MUX-DEMUX Application Example

- This enables sharing a single communication line among a number of devices.

- At any time, only one source and one destination can use the communication line.