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MAX32520 ChipDNA Secure Arm Cortex

M4 Microcontroller

General Description Benefits and Features

DeepCover® embedded security solutions cloak sensitive ● High-Efficiency Microcontroller for Secure Element IoT
data under multiple layers of advanced physical security • Arm Cortex-M4F with FPU Up to 120MHz
to provide the most secure key storage possible. • 16KB Unified Code Cache
The DeepCover secure microcontroller MAX32520 pro- • 2MB PUF Encrypted Flash Memory with Cache
vides an interoperable, secure, and cost-effective solution Provides Ultimate Firmware IP Protection
to build new generations of trusted embedded systems • Low Latency On-the-Fly Decryption of Flash
and communication devices such as IoT, IoT gateways, Execution
and wireless access points. • 136KB SRAM + 34KB ECC
• 8KB User-Programmable OTP
The MAX32520 incorporates Maxim's patented
ChipDNA™ PUF technology. ChipDNA technology in- ● Secure Element
volves a physically unclonable function (PUF) that enables • PUF-Based Keys
cost-effective protection against invasive physical attacks. • For Internal Flash Encryption
Using the random variation of semiconductor device char- • For Strong Device Authentication
acteristics that naturally occur during wafer fabrication, the • Secure Boot Loader with Public Key Authentication
ChipDNA circuit generates a unique output value that is and Serial Flash Emulation
repeatable over time, temperature, and operating voltage. • AES, SHA, and ECDSA Accelerators
Attempts to probe or observe ChipDNA operation modifies • Hardware True Random Number Generator
the underlying circuit characteristics, preventing discovery • SP800-90B Compliant Entropy Source
of the unique value used by the chip cryptographic func- • SP800-90A Compliant DRBG
tions. The MAX32520 utilizes the ChipDNA output as key • Die Shield
content to cryptographically secure all device stored da- • Temperature and Voltage Tamper Monitor
ta including user firmware. User firmware encryption pro- • External Tamper Sensor with Random Dynamic
vides ultimate software IP protection. The ChipDNA can Pattern
also generate a private key for the ECDSA signing opera- ● Power Management Maximizes Operating Time for
tion. Battery Applications
The MAX32520 integrates an Arm® Cortex® -M4 proces- • Single 3.3V/2.5V/1.8V Supply
sor, 2MB of Flash, 136KB of system RAM + 34KB ECC, • Down to 3.2µA Backup Mode
8KB of one-time-programmable (OTP) memory and • 15µs Wake-Up Time from Standby Mode
128KB of boot ROM. • Clock Gating, Power Gating, Registers, and
Memory Retention Modes
The MAX32520 provides a FIPS/NIST compliant TRNG,
environmental and tamper detection circuitry to facilitate ● Multiple Peripherals for System Control
system-level security. • One UART
• One I2C Interface
Multiple high-speed interfaces are supported including • QSPI
SPI, UART, and an I2C. The four on-chip timers also sup- • Four Timers with PWM Capability
port PWM output generation for direct control of external • Up to 27 General-Purpose I/O Pins with Selectable
devices. One of the SPI ports has a serial flash emulation Output Driver Strength
mode allowing direct code fetching enabling secure boot • 4-Channel DMA Controller
for a host microcontroller. • 4-Pin JTAG

Applications Ordering Information appears at end of data sheet.

● Embedded Connected Systems
● Secure Industrial Appliances, Sensors, and Arm and Cortex are registered trademarks of Arm Limited
Controllers (or its subsidiaries) in the US and/or elsewhere.
● IoT Nodes and Gateways
DeepCover is a registered trademark and ChipDNA is a
● Embedded Communication Equipment (Routers, trademark of Maxim Integrated Products, Inc.
Gateways, etc.)
● Set-Top Boxes

19-100583; Rev 0; 6/19

MAX32520 ChipDNA Secure Arm Cortex
M4 Microcontroller

Simplified Block Diagram

MAX32520

120MHz
ARM® CORTEX® -M4

Tx/Rx
FIFO
1 × I2C MASTER/SLAVE
WITH FPU
7.3728MHz 120MHz SHARED PAD
FUNCTIONS
8kHz NVIC
TIMERS/PWM

Tx/Rx
FIFO
1 × 2-WIRE UART
CAPTURE/
MEMORY COMPARE
POWER-ON RESET,
BROWNOUT MONITOR, SPI GPIO/
RSTN FLASH 1 x SPI MASTER/SLAVE ALTERNATE

Tx/Rx
FIFO
SUPPLY VOLTAGE I 2C
2MB (4 CS) FUNCTION
MONITORS UART
DUAL BANK UP TO 27
MULTI-LAYER BUS MATRIX – AHB/APB JTAG
CACHE
VDD 1 x SPI/QSPI MASTER/
MEMORY Tx/Rx SLAVE (2 CS) EXTERNAL
DECRYPTION UNIT FIFO INTERRUPTS
REG SINGLE OUTPUT SERIAL FLASH
VOLTAGE EMULATION
CACHE 16KB EXTERNAL
REGULATION
VSSA TAMPER
&
POWER CONTROL 4 × 32-BIT TIMERS
SRAM
VDDA
170KB (SEC-DED)

ROM 128KB SECURITY

ENVIRONMENTAL, AES 128, 192, 256
EXTERNAL SENSORS &
OTP 8KB SHA-1/256/384/512
DIE MESH
CORE I/O ANALOG
CHIP DNA PHYSICALLY DES, 3DES
UNCLONABLE
4-CH DUAL DMA FAULT DETECTORS
FUNCTION(PUF)
FLASH ENCRYPTION KEY ECDSA
2 × WATCHDOG ECDSA SIGNING KEY (UP TO P-521)
TIMER TRNG RSA (SOFT)
SP-800-90B, SP-800-90A (UP TO 4096)

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MAX32520 ChipDNA Secure Arm Cortex
M4 Microcontroller

TABLE OF CONTENTS
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Benefits and Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Simplified Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
32 TQFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
30 WLP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Electrical Characteristics—SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Electrical Characteristics—I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
32 TQFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
30 WLP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Arm Cortex-M4 with FPU Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Internal Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Internal SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Internal ROM and Boot Loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Clocking Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
ChipDNA Physically Unclonable Function (PUF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
True Random Number Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Serial Flash Emulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Cryptographic Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
AES Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
ECDSA Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
SHA Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
RSA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Debug and Development Interface (SWD/JTAG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Standard DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

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MAX32520 ChipDNA Secure Arm Cortex
M4 Microcontroller

TABLE OF CONTENTS (CONTINUED)

Programmable Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Active Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
DeepSleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Backup Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Wake-Up Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Security Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Internal Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
External Tamper Sensors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Typical Application Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Secure Serial Boot/External Code Flash with JEDEC Flash Command Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Extended Secure Serial Boot/External Code Flash with Secure System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

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MAX32520 ChipDNA Secure Arm Cortex
M4 Microcontroller

LIST OF FIGURES
Figure 1. SPI Master Mode Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 2. SPI Slave Mode Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 3. I2C Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 4. Timer Block Diagram, 32-Bit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

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MAX32520 ChipDNA Secure Arm Cortex
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LIST OF TABLES
Table 1. Wake-Up Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

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MAX32520 ChipDNA Secure Arm Cortex
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Absolute Maximum Ratings

Continuous Power Dissipation (TA = +70°C) (Single-layer board, VDDA ........................................................................ -0.3V to 3.6V
derate 21.3mW/°C above +70°C) ................................ 1702.1mW RSTN, GPIO ................................................. -0.3V to VDD + 0.5V
Continuous Power Dissipation TQFN (Multilayer Board) (TA = VSSA ......................................................................................1mA
+70°C, derate 34.5mW/°C above +70°C.).................. 2758.6 mW VSS ....................................................................................100mA
Operating Temperature Range .......................... -40°C to +105°C Output Current (sink) by Any GPIO Pin ...............................25mA
Storage Temperature Range .............................. -65°C to +150°C Output Current (source) by Any GPIO Pin ......................... -25mA
VDD.......................................................................... -0.3V to 3.6V

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the
device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.

Package Information
32 TQFN
Package Code T3255+8C
Outline Number 21-0140
Land Pattern Number 90-0013
Thermal Resistance, Single-Layer Board:
Junction to Ambient (θJA) 47°C/W
Junction to Case (θJC) 1.70°C/W
Thermal Resistance, Four-Layer Board:
Junction to Ambient (θJA) 29°C/W
Junction to Case (θJC) 1.70°C/W

30 WLP
Package Code W302N2+1
Outline Number 21-100380
Land Pattern Number Refer to Application Note 1891
Thermal Resistance, Four-Layer Board:
Junction to Ambient (θJA) 49.38°C/W
Junction to Case (θJC) N/A
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”, “#”, or “-” in the package code indicates
RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status.
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board. For detailed information on package thermal
considerations, refer to www.maximintegrated.com/thermal-tutorial.

Electrical Characteristics
(Limits are 100% tested at TA = +25°C and TA = +105°C. Limits over the operating temperature range and relevant supply voltage
range are guaranteed by design and characterization. Specifications marked GBD are guaranteed by design and not production tested.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
POWER SUPPLIES
Input Supply Voltage,
VDD 1.71 1.8 3.6 V
Digital
Input Supply Voltage,
VDDA 1.71 1.8 3.6 V
Analog

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MAX32520 ChipDNA Secure Arm Cortex
M4 Microcontroller

Electrical Characteristics (continued)

(Limits are 100% tested at TA = +25°C and TA = +105°C. Limits over the operating temperature range and relevant supply voltage
range are guaranteed by design and characterization. Specifications marked GBD are guaranteed by design and not production tested.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Total current into VDD = 1.8V 10.6
VDD pins,
fSYS_CLK =
120MHz, CPU in
VDD Current, Active
IDD_ACT Active mode, mA
Mode VDD = 3.3V 10.7
executing While(1)
from cache, inputs
tied to VSS, outputs
source/sink 0mA
Total current into VDD = 1.8V 2.16
VDD pins,
fSYS_CLK =
VDD Current, Sleep
IDD_SLP 120MHz, CPU in mA
Mode VDD = 3.3V 2.35
Sleep mode, inputs
tied to VSS, outputs
source/sink 0mA
VDD Fixed Current, Standby state with VDD = 1.8V 65
IDD_FDSL μA
DeepSleep Mode full retention VDD = 3.3V 69
72KB ECC memory
retention, VDD = 4.72
1.8V
72KB ECC memory
retention, VDD = 6.74
3.3V
No memory
retention, VDD = 3.22
1.8V
Total current into No memory
VDD pins, inputs retention, VDD = 5.25
VDD Current, Backup tied to VSS, AES 3.3V
IDD_BK μA
Mode keys retained, 32KB ECC memory
outputs source/sink retention, VDD = 3.84
0mA 1.8V
32KB ECC memory
retention, VDD = 5.87
3.3V
64KB ECC memory
retention, VDD = 4.4
1.8V
64KB ECC memory
retention, VDD = 6.5
3.3V
CLOCKS
System Clock
fSYS_CLK 0.0625 120,000 kHz
Frequency

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MAX32520 ChipDNA Secure Arm Cortex
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Electrical Characteristics (continued)

(Limits are 100% tested at TA = +25°C and TA = +105°C. Limits over the operating temperature range and relevant supply voltage
range are guaranteed by design and characterization. Specifications marked GBD are guaranteed by design and not production tested.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
1/
System Clock Period tSYS_CLK fSYS_CL ns
K
Nano-ring Oscillator
fNANO 8 kHz
Frequency
High-Speed Oscillator
fHSCLK 115.5 120 124.5 MHz
Frequency
7MHz Oscillator
f7MCLK 7.3728 MHz
Frequency
GENERAL-PURPOSE I/O
Input Low Voltage for All 0.3 x
VIL V
GPIO VDD
Input Low Voltage for 0.3 x
VIL_RSTN V
RSTN VDD
Input High Voltage for 0.7 x
VIH V
All GPIO VDD
Input High Voltage for 0.7 x
VIH_RSTN V
RSTN VDD
GPIOn_DS_SEL[1:0]
0.2 0.4
= 00, IOL = 1mA
GPIOn_DS_SEL[1:0]
0.2 0.4
Output Low Voltage for = 01, IOL = 2mA
VOL VDD = 1.71V V
All GPIO GPIOn_DS_SEL[1:0]
0.2 0.4
= 10, IOL = 4mA
GPIOn_DS_SEL[1:0]
0.2 0.4
= 11, IOL = 8mA
Combined IOL, All GPIO IOL_TOTAL GBD 48 mA
GPIOn_DS_SEL[1:0] VDD -
= 00, IOL = -1mA 0.4
GPIOn_DS_SEL[1:0] VDD -
Output High Voltage for = 01, IOL = -2mA 0.4
VOH VDD = 1.71V V
All GPIO GPIOn_DS_SEL[1:0] VDD -
= 10, IOL = -4mA 0.4
GPIOn_DS_SEL[1:0] VDD -
= 11, IOL = -8mA 0.4
Combined IOH, All GPIO IOH_TOTAL GBD -48 mA
Input Hysteresis
VIHYS 300 mV
(Schmitt)
Input Leakage Current VDD = 3.6V, VIN = 0V, internal pullup
IIL -1 +1 μA
Low disabled
Input Leakage Current VDD = 3.6V, VIN = 3.6V, internal pulldown
IIH -1 +1 μA
High disabled

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MAX32520 ChipDNA Secure Arm Cortex
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Electrical Characteristics (continued)

(Limits are 100% tested at TA = +25°C and TA = +105°C. Limits over the operating temperature range and relevant supply voltage
range are guaranteed by design and characterization. Specifications marked GBD are guaranteed by design and not production tested.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Input Pullup Resistor
RPU_R 25 kΩ
RSTN
Input Pullup/Pulldown RPU1 Normal resistance 25 kΩ
Resistor for All GPIO RPU2 Highest resistance 1 MΩ
ENVIRONMENTAL SENSORS
VDD Overvoltage
VDD_OV 3.6 3.8 V
Threshold
VTM_LOTHSEL = [00] 1.56 1.66 1.76
VDD Undervoltage
VDD_UV VTM_LOTHSEL = [01] 2.1 2.2 2.3 V
Threshold
VTM_LOTHSEL = [1x] 2.7 2.8 2.9
High-Temperature
THTR GBD 115 125 135 °C
Threshold
Low-Temperature TLTR1 GBD -70 -60 -50
°C
Threshold TLTR2 GBD -50 -40 -30

Electrical Characteristics—SPI
(Timing specifications are guaranteed by design and not production tested.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
MASTER MODE
SPI Master Operating fSYS_CLK = 120MHz, fMCK(MAX) =
fMCK 60 MHz
Frequency fSYS_CLK/2
SPI Master SCK Period tMCK 1/fMCK ns
SCK Output Pulse-
tMCH, tMCL tMCK/2 ns
Width High/Low
MOSI Output Hold Time
tMOH tMCK/2 ns
After SCK Sample Edge
MOSI Output Valid to
tMOV tMCK/2 ns
Sample Edge
MOSI Output Hold Time
tMLH tMCK/2 ns
After SCK Low Idle
MISO Input Valid to
SCK Sample Edge tMIS 5 ns
Setup
MISO Input to SCK
tMIH tMCK/2 ns
Sample Edge Hold
SLAVE MODE
SPI Slave Operating
fSCK 50 MHz
Frequency
SPI Slave SCK Period tSCK 1/fSCK ns
SCK Input Pulse-Width
tSCH, tSCL tSCK/2
High/Low

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MAX32520 ChipDNA Secure Arm Cortex
M4 Microcontroller

Electrical Characteristics—SPI (continued)

(Timing specifications are guaranteed by design and not production tested.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
SSx Active to First Shift
tSSE 10 ns
Edge
MOSI Input to SCK
Sample Edge Rise/Fall tSIS 5 ns
Setup
MOSI Input from SCK
Sample Edge Transition tSIH 1 ns
Hold
MISO Output Valid After
SCLK Shift Edge tSOV 5 ns
Transition
SCK Inactive to SSx
tSSD 10 ns
Inactive
SSx Inactive Time tSSH 1/fSCK μs
MISO Hold Time After
tSLH 10 ns
SSx Deassertion

Electrical Characteristics—I2C
(TIming specifications are guaranteed by design and not production tested.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
STANDARD MODE
Standard mode, from VIH(MIN) to
Output Fall Time tOF 150 ns
VIL(MAX)
SCL Clock Frequency fSCL 0 100 kHz
Low Period SCL Clock tLOW 4.7 μs
High Time SCL Clock tHIGH 4.0 μs
Setup Time for
Repeated Start tSU;STA 4.7 μs
Condition
Hold Time for Repeated
tHD;STA 4.0 μs
Start Condition
Data Setup Time tSU;DAT 300 ns
Data Hold Time tHD;DAT 10 ns
Rise Time for SDA and
tR 800 ns
SCL
Fall Time for SDA and
tF 200 ns
SCL
Setup Time for a Stop
tSU;STO 4.0 μs
Condition
Bus Free Time Between
a Stop and Start tBUS 4.7 μs
Condition
Data Valid Time tVD;DAT 3.45 μs

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MAX32520 ChipDNA Secure Arm Cortex
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Electrical Characteristics—I2C (continued)

(TIming specifications are guaranteed by design and not production tested.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Data Valid Acknowledge
tVD;ACK 3.45 μs
Time
FAST MODE
Output Fall Time tOF From VIH(MIN) to VIL(MAX) 150 ns
Pulse Width Suppressed
tSP 75 ns
by Input Filter
SCL Clock Frequency fSCL 0 400 kHz
Low Period SCL Clock tLOW 1.3 μs
High Time SCL Clock tHIGH 0.6 μs
Setup Time for
Repeated Start tSU;STA 0.6 μs
Condition
Hold Time for Repeated
tHD;STA 0.6 μs
Start Condition
Data Setup Time tSU;DAT 125 ns
Data Hold Time tHD;DAT 10 ns
Rise Time for SDA and
tR 30 ns
SCL
Fall Time for SDA and
tF 30 ns
SCL
Setup Time for a Stop
tSU;STO 0.6 μs
Condition
Bus Free Time Between
a Stop and Start tBUS 1.3 μs
Condition
Data Valid Time tVD;DAT 0.9 μs
Data Valid Acknowledge
tVD;ACK 0.9 μs
Time
FAST MODE PLUS
Output Fall Time tOF From VIH(MIN) to VIL(MAX) 80 ns
Pulse Width Suppressed
tSP 75 ns
by Input Filter
SCL Clock Frequency fSCL 0 1000 kHz
Low Period SCL Clock tLOW 0.5 μs
High Time SCL clock tHIGH 0.26 μs
Setup Time for
Repeated Start tSU;STA 0.26 μs
Condition
Hold Time for Repeated
tHD;STA 0.26 μs
Start Condition
Data Setup Time tSU;DAT 50 ns
Data Hold Time tHD;DAT 10 ns

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MAX32520 ChipDNA Secure Arm Cortex
M4 Microcontroller

Electrical Characteristics—I2C (continued)

(TIming specifications are guaranteed by design and not production tested.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Rise Time for SDA and
tR 50 ns
SCL
Fall Time for SDA and
tF 30 ns
SCL
Setup Time for a Stop
tSU;STO 0.26 μs
Condition
Bus Free Time Between
0.5
a Stop and Start tBUS μs
Condition
Data Valid Time tVD;DAT 0.45 μs
Data Valid Acknowledge
tVD;ACK 0.45 μs
Time

SHIFT SAMPLE SHIFT SAMPLE

SSx
(SHOWN ACTIVE LOW)
tMCK
SCK
CKPOL/CKPHA
0/1 OR 1/0
SCK tMCH tMCL
CKPOL/CKPHA
0/0 OR 1/1
tMOH
tMOV tMLH
MOSI/SDIOx
(OUTPUT) MSB MSB-1 LSB

tMIS tMIH
MISO/SDIOx
(INPUT) MSB MSB-1 LSB

Figure 1. SPI Master Mode Timing Diagram

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MAX32520 ChipDNA Secure Arm Cortex
M4 Microcontroller

SHIFT SAMPLE SHIFT SAMPLE

SSx tSSE
tSSH
(SHOWN ACTIVE LOW)
tSSD
SCK tSCK
CKPOL/CKPHA
0/1 OR 1/0
tSCH tSCL
SCK
CKPOL/CKPHA
0/0 OR 1/1

tSIS tSIH
MOSI/SDIOx
(INPUT) MSB MSB-1 LSB

tSOV tSLH
MISO/SDIOx MSB MSB-1 LSB
(OUTPUT)

Figure 2. SPI Slave Mode Timing Diagram

START STOP START

START
REPEAT tBUS

SDA
tOF tR
tSU;STO
tSP
tSU;DAT tSU;STA tHIGH

SCL
tHD;STA
tHD;DAT
tLOW
tVD;ACK
tVD;DAT

Figure 3. I2C Timing Diagram

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MAX32520 ChipDNA Secure Arm Cortex
M4 Microcontroller

Pin Configuration
32 TQFN
TOP VIEW

P1.7

P1.6

P1.5
P1.4

P1.3

P1.2

P1.1

P1.0
24 23 22 21 20 19 18 17

RSTN 25 16 P0.15
P1.8 26 15 P0.14

VDD 27 14 P0.13
REG 28 13 P0.12
MAX32520
VSSA 29 12 P0.11

VDDA 30 11 P0.10

P1.9 31 EP* 10 P0.9

+
P1.10 32 9 P0.8

1 2 3 4 5 6 7 8
*EP =
P0.0

P0.1

P0.2

P0.3

P0.4

P0.5

P0.6

P0.7
EXPOSED
PAD
5mm x 5mm

Pin Description
FUNCTION MODE
PIN NAME Primary Signal Alternate Alternate FUNCTION
(Default) Function 1 Function 2
UART
P0.0: GPIO0 Port 0
1 P0.0 P0.0 UART_RXD —
UART_RXD: UART Data Input
P0.1: GPIO1 Port 0
2 P0.1 P0.1 UART_TXD —
UART_TXD: UART Data Output
SPI
P0.2: GPIO2 Port 0
SPI0_DIO0: Quad SPI I/O 0 (SPI0 Master Out
SPI0_DIO0 SFSPIS_DIO0
3 P0.2 P0.2 Slave In)
(MOSI0) (SFSI)
SFSPIS_DIO0: Serial Flash SPI Slave I/O 0
(SFSPI Slave In)
P0.3: GPIO3 Port 0
SPI0_DIO1: Quad SPI I/O 1 (SPI0 Master In
SPI0_DIO1 SFSPIS_DIO1
4 P0.3 P0.3 Slave Out)
(MISO0) (SFSO)
SFSPIS_DIO1: Serial Flash SPI I/O 1 (SFSPI
Slave Out)
P0.4: GPIO4 Port 0
5 P0.4 P0.4 SCK0 SFSPIS_SCK SCK0: SPI0 Clock
SFSPIS_SCK: Serial Flash SPI Clock
P0.5: GPIO5 Port 0
6 P0.5 P0.5 SSEL0_0 SFSPIS_SS0 SSEL0_0: SPI0 Slave Select 0
SFSPIS_SS0: Serial Flash SPI Slave Select 0

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MAX32520 ChipDNA Secure Arm Cortex
M4 Microcontroller

32 TQFN
FUNCTION MODE
PIN NAME Primary Signal Alternate Alternate FUNCTION
(Default) Function 1 Function 2
P0.6: GPIO6 Port 0
7 P0.6 P0.6 SSEL0_1 SFSPIS_SS1 SSEL0_1: SPI0 Slave Select 1
SFSPIS_SS1: Serial Flash SPI Slave Select 1
P0.7: GPIO7 Port 0
8 P0.7 P0.7 SPI0_DIO2 SFSPIS_DIO2 SPI0_DIO2: Quad SPI I/O 2
SFSPIS_DIO2: Serial Flash SPI I/O 2
P0.8: GPIO8 Port 0
9 P0.8 P0.8 SPI0_DIO3 SFSPIS_DIO3 SPI0_DIO3: Quad SPI I/O3
SFSPIS_DIO3: Serial Flash SPI I/O 3
P0.11: GPIO11 Port 0
12 P0.11 P0.11 MISO1 —
MISO1: SPI1 Master In Slave Out
P0.12: GPIO12 Port 0
13 P0.12 P0.12 MOSI1 —
MOSI1: SPI1 Master Out Slave In
P0.13: GPIO13 Port 0
14 P0.13 P0.13 SCK1 —
SCK1: SPI1 Clock
P0.14: GPIO14 Port 0
15 P0.14 P0.14 SSEL1_0 —
SSEL1_0: SPI1 Slave Select 0
P0.15: GPIO15 Port 0
16 P0.15 P0.15 SSEL1_1 —
SSEL1_1: SPI1 Slave Select 1
I²C
P0.9: GPIO9 Port 0
10 P0.9 P0.9 SDA —
SDA: I2C Data
P0.10: GPIO10 Port 0
11 P0.10 P0.10 SCL —
SCL: I2C Clock
TIMER
P1.0: GPIO0 Port 1
17 P1.0 P1.0 TCLK0 —
TCLK0: Timer 0 Clock I/O
P1.1: GPIO1 Port 1
18 P1.1 P1.1 TCLK1 —
TCLK1: Timer 1 Clock I/O
P1.6: GPIO6 Port 1
23 P1.6 P1.6 TCLK2 SSEL1_2 TCLK2: Timer 2 Clock I/O
SSEL1_2: SPI1 Slave Select 2
P1.7: GPIO7 Port 1
24 P1.7 P1.7 TCLK3 SSEL1_3 TCLK3: Timer 3 Clock I/O
SSEL1_3: SPI1 Slave Select 3
JTAG
P1.2: GPIO2 Port 1
19 P1.2 P1.2 TDI —
TDI: JTAG Test Data Input
P1.3: GPIO3 Port 1
20 P1.3 P1.3 TDO —
TDO: JTAG Test Data Output
P1.4: GPIO4 Port 1
21 P1.4 P1.4 TMS/SWDIO — TMS/SWDIO: JTAG Mode Select / Single Wire
Debug I/O

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MAX32520 ChipDNA Secure Arm Cortex
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32 TQFN
FUNCTION MODE
PIN NAME Primary Signal Alternate Alternate FUNCTION
(Default) Function 1 Function 2
P1.5: GPIO5 Port 1
22 P1.5 P1.5 TCK/SWCLK — TCK/SWCLK: JTAG Test Clock / Single Wire
Debug Clock
EXTERNAL TAMPER
EXT_SENS_OU P1.8: GPIO8 Port 1
26 P1.8 P1.8 —
T EXT_SENS_OUT: External Sensor Output
P1.9: GPIO9 Port 1
31 P1.9 P1.9 EXT_SENS_IN —
EXT_SENS_IN: External Sensor Input
P1.10: GPIO10 Port 1
TAMPER_OUT: External Tamper Detection
32 P1.10 P1.10 TAMPER_OUT —
Output. This pin is active when external tamper
is detected.
POWER AND SYSTEM
VDD: Core and I/O supply voltage. Bypass VDD
27 VDD VDD — — with 1μf and 100nF capacitors with ESR
<100mΩ
REG: Regulator Capacitor. Bypass REG with
28 REG REG — —
1μf and 100nF capacitors with ESR < 100mΩ
29 VSSA VSSA — — VSSA: 1.8V Analog Ground
VDDA: 1.8V Analog Power Supply. Bypass
30 VDDA VDDA — — VDDA with 1μf and 100nF capacitors with ESR <
100mΩ
— EP VSS — — Exposed Pad. Ground.
RSTN: Hardware Reset (Active-Low) Input. The
device remains in reset while this pin is in its
active state. When the pin transitions to its
inactive state, the device performs a warm reset
25 RSTN RSTN — — (resetting all logic) and begins execution. This
pin has an internal pullup to the VDD supply.
This pin should be left unconnected if the
system design does not provide a reset signal to
the device.

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MAX32520 ChipDNA Secure Arm Cortex
M4 Microcontroller

Pin Configuration
30 WLP
TOP VIEW
(BUMP SIDE DOWN)

1 2 3 4 5 6

+
VSS P0.9 P0.11 P0.12 P0.15 P1.0
A

P0.6 P0.8 P0.10 P0.14 P1.1 P1.2

B

P0.4 P0.5 P0.7 P0.13 P1.4 P1.3

C

P0.1 P1.10 P0.2 P0.3 P1.5 VDD

D

P0.0 VDDA VSSA VSS REG RSTN

E

2.6mm x 2.6mm

Pin Description
FUNCTION MODE
PIN NAME Primary Signal Alternate Alternate FUNCTION
(Default) Function 1 Function 2
UART
P0.0: GPIO0 Port 0
E1 P0.0 P0.0 UART_RXD —
UART_RXD: UART Data Input
P0.1: GPIO1 Port 0
D1 P0.1 P0.1 UART_TXD —
UART_TXD: UART Data Output
SPI
P0.2: GPIO2 Port 0
SPI0_DIO0: Quad SPI I/O 0 (SPI0 Master Out
SPI0_DIO0 SFSPIS_DIO0
D3 P0.2 P0.2 Slave In)
(MOSI0) (SFSI)
SFSPIS_DIO0: Serial Flash SPI Slave I/O 0
(SFSPI Slave In)
P0.3: GPIO3 Port 0
SPI0_DIO1: Quad SPI I/O 1 (SPI0 Master In
SPI0_DIO1 SFSPIS_DIO1
D4 P0.3 P0.3 Slave Out)
(MISO0) (SFSO)
SFSPIS_DIO1: Serial Flash SPI I/O 1 (SFSPI
Slave Out)
P0.4: GPIO4 Port 0
C1 P0.4 P0.4 SCK0 SFSPIS_SCK SCK0: SPI0 Clock
SFSPIS_SCK: Serial SPI Clock

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MAX32520 ChipDNA Secure Arm Cortex
M4 Microcontroller

30 WLP
FUNCTION MODE
PIN NAME Primary Signal Alternate Alternate FUNCTION
(Default) Function 1 Function 2
P0.5: GPIO5 Port 0
C2 P0.5 P0.5 SSEL0_0 SFSPIS_SS0 SSEL0_0: SPI0 Slave Select 0
SFSPIS_SS0: Serial Flash SPI Slave Select 0
P0.6: GPIO6 Port 0
B1 P0.6 P0.6 SSEL0_1 SFSPIS_SS1 SSEL0_1: SPI0 Slave Select 1
SFSPIS_SS1: Serial Flash SPI Slave Select 1
P0.7: GPIO7 Port 0
C3 P0.7 P0.7 SPI0_DIO2 SFSPIS_DIO2 SPI0_DIO2: Quad SPI I/O 2
SFSPIS_DIO2: Serial Flash SPI I/O 2
P0.8: GPIO8 Port 0
B2 P0.8 P0.8 SPI0_DIO3 SFSPIS_DIO3 SPI0_DIO3: Quad SPI I/O3
SFSPIS_DIO3: Serial Flash SPI I/O 3
P0.11: GPIO11 Port 0
A3 P0.11 P0.11 MISO1 —
MISO1: SPI1 Master In Slave Out
P0.12: GPIO12 Port 0
A4 P0.12 P0.12 MOSI1 —
MOSI1: SPI1 Master Out Slave In
P0.13: GPIO13 Port 0
C4 P0.13 P0.13 SCK1 —
SCK1: SPI1 Clock
P0.14: GPIO14 Port 0
B4 P0.14 P0.14 SSEL1_0 —
SSEL1_0: SPI1 Slave Select 0
P0.15: GPIO15 Port 0
A5 P0.15 P0.15 SSEL1_1 —
SSEL1_1: SPI1 Slave Select 1
I²C
P0.9: GPIO9 Port 0
A2 P0.9 P0.9 SDA —
SDA: I2C Data
P0.10: GPIO10 Port 0
B3 P0.10 P0.10 SCL —
SCL: I2C Clock
TIMER
P1.0: GPIO0 Port1
A6 P1.0 P1.0 TCLK0 —
TCLK0: Timer 0 Clock I/O
P1.1: GPIO1 Port1
B5 P1.1 P1.1 TCLK1 —
TCLK1: Timer 1 Clock I/O
JTAG
P1.2: GPIO2 Port 1
B6 P1.2 P1.2 TDI —
TDI: JTAG Test Data Input
P1.3: GPIO3 Port 1
C6 P1.3 P1.3 TDO —
TDO: JTAG Test Data Output
P1.4: GPIO4 Port 1
C5 P1.4 P1.4 TMS/SWDIO — TMS/SWDIO: JTAG Mode Select / Single Wire
Debug I/O
P1.5: GPIO5 Port 1
D5 P1.5 P1.5 TCK/SWCLK — TCK/SWCLK: JTAG Test Clock / Single Wire
Debug Clock

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MAX32520 ChipDNA Secure Arm Cortex
M4 Microcontroller

30 WLP
FUNCTION MODE
PIN NAME Primary Signal Alternate Alternate FUNCTION
(Default) Function 1 Function 2
POWER AND SYSTEM
VDD: Core and I/O Supply Voltage. Bypass VDD
D6 VDD VDD — — with 1μf and 100nF capacitors with ESR <
100mΩ.
REG: Regulator Capacitor. Bypass REG with
E5 REG REG — —
1μf and 100nF capacitors with ESR < 100mΩ.
E3 VSSA VSSA — — VSSA: 1.8V Analog Ground
VDDA: 1.8V Analog Power Supply. Bypass
E2 VDDA VDDA — — VDDA with 1μf and 100nF capacitors with ESR <
100mΩ.
E4, A1 VSS VSS — — Ground
RSTN: Hardware Reset (Active-Low) Input. The
device remains in reset while this pin is in its
active state. When the pin transitions to its
inactive state, the device performs a warm reset
E6 RSTN RSTN — — (resetting all logic) and begins execution. This
pin has an internal pullup to the VDD supply.
This pin should be left unconnected if the
system design does not provide a reset signal to
the device.
P1.10: GPIO10 Port 1
TAMPER_OUT: External Tamper Detection
D2 P1.10 P1.10 TAMPER_OUT —
Output. This pin is active when external tamper
is detected.

www.maximintegrated.com Maxim Integrated | 20

MAX32520 ChipDNA Secure Arm Cortex
M4 Microcontroller

Detailed Description
DeepCover embedded security solutions cloak sensitive data under multiple layers of advanced physical security
to provide the most secure key storage possible. The DeepCover secure microcontroller MAX32520 provides an
interoperable, secure, and cost-effective solution to build new generations of trusted embedded systems and
communication devices such as wireless access points. The MAX32520 incorporates Maxim's patented ChipDNA™ PUF
technology. ChipDNA technology involves a physically unclonable function (PUF) that enables cost-effective protection
against invasive physical attacks. Using the random variation of semiconductor device characteristics that naturally occur
during wafer fabrication, the ChipDNA circuit generates a unique output value that is repeatable over time, temperature,
and operating voltage. Attempts to probe or observe ChipDNA operation modifies the underlying circuit characteristics to
prevent the discovery of the unique value used by the chip cryptographic functions. The MAX32520 utilizes the ChipDNA
output as key content to cryptographically secure all device stored data and optionally, under user control, as the private
key for the ECDSA signing operation. The MAX32520 integrates an Arm Cortex-M4 processor, 2MB of flash, 136KB of
system RAM + 34KB ECC, 8KB of one-time-programmable (OTP) memory and 128KB of boot ROM.
In addition to hardware crypto functions, the MAX32520 provides a FIPS/NIST-compliant true random number generator,
as well as environmental and tamper detection circuitry to facilitate system-level security for the application.
The MAX32520 microcontroller includes multiple communication interfaces: two SPI ports, one UART, and an I2C bus.
The four on-chip timers also support PWM output generation for direct control of external devices. One of the SPI ports
has a serial flash emulation mode to allow direct code fetching and thus enable a secure boot for a host microcontroller.

Arm Cortex-M4 with FPU Processor

The Arm Cortex-M4 with FPU processor combines high-efficiency signal processing functionality with flexible low-power
operating modes. The features of this implementation of the familiar Arm Cortex-M4 architecture include:
● Floating point unit (FPU)
● Memory protection unit
● Full debug support level
• Debug access port (DAP)
• Breakpoints
• Flash patch
• Halting debug
• Development and debug interface
● NVIC support
• Programmable IRQ generation for each interrupt source
• Unique vectors for each interrupt channel
• 8 programmable priority levels support nesting and preemption
• External GPIO interrupts grouped by GPIO port
● DSP supports single instruction multiple data (SIMD) path DSP extensions, providing:
• 4 parallel 8-bit add/sub
• 2 parallel 16-bit add/sub
• 2 parallel MACs
• 32- or 64-bit accumulate
• Signed, unsigned, data with or without saturation

Memory

Internal Flash Memory

2MB of internal flash memory provides nonvolatile storage of program and data memory. The flash memory can be
fully AES encrypted using a 256-bit, PUF-generated key. In this case, the memory content is decrypted on the fly for
execution. Firmware encryption through AES- and PUF-generated encryption key provides unmatched level of software

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MAX32520 ChipDNA Secure Arm Cortex
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IP protection.
A dedicated state machine enables direct access to the flash block. Thanks to this state machine the MAX32520 can
emulate a serial flash and the content of the flash is directly accessible from a host CPU. The typical application is the
support of the secure boot function for a host processor.

Internal SRAM
The internal 170KB SRAM provides low-power retention of application information in all power modes except shutdown.
The SRAM can be configured as 136KB + 34KB ECC SEC-DED.
The internal SRAM can be divided into granular banks that create a flexible SRAM retention architecture. This data
retention feature is optional and configurable. This granularity allows the application to minimize its power consumption
by only retaining the most essential data.

Internal ROM and Boot Loader

Upon assertion and deassertion of system reset, the Arm Cortex-M4 is reset and begins program execution of internal
ROM code. A secure bootloader is implemented to provide trusted boot, secure flash upload, and flash integrity
verification upon reboot.
A built-in public key authentication scheme allows secure firmware updates from both UART and SPI interfaces.

Clocking Scheme
The high-frequency internal oscillator operates at a nominal frequency of 120MHz. It is the primary clock source for the
digital logic and peripherals. Select a 7.3728MHz internal oscillator to optimize active power consumption. A nanopower
8kHz ring oscillator is also available. Wakeup is possible from either the 7.3728MHz internal oscillator or the 120MHz
internal oscillator.

ChipDNA Physically Unclonable Function (PUF)

Physically unclonable functions exploits the natural silicon manufacturing variations to generate unpredictable values that
are statistically unique per chip. The MAX32520 uses PUF to generate unique keys while providing ultimate resistance
against reverse-engineered based attacks.
The PUF instance present in the MAX32520 generates the flash encryption key. It can also provide a unique ECDSA
private key for device strong authentication. The associated public key can be further exported and signed by a
certification authority.

True Random Number Generator

Random numbers are a vital part of a secure application, providing random numbers that can be used for cryptographic
seeds or strong encryption keys to ensure data privacy.
Software can use random numbers to trigger asynchronous events that result in nondeterministic behavior. This is helpful
in thwarting replay attacks or key search approaches. An effective true random number generator (TRNG) must be
continuously updated by a high-entropy source.
The provided TRNG is continuously driven by a physically-unpredictable entropy source. It generates a 128-bit true
random number in 128 system clock cycles.
The TRNG can support the system-level validation of many security standards such as FIPS 140-2, SP800-90, PCI-PED,
and Common Criteria. Contact Maxim for details of compliance with specific standards.

Serial Flash Emulation

One of the SPI ports provides the ability for a host microcontroller to use the device as an external serial flash for secure
boot. The full capacity of flash memory is accessible and the amount of flash accessible can also be restricted. This
feature provides a highly secure boot function for non-secure host microcontrollers. The device recognizes serial flash
JEDEC commands.

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MAX32520 ChipDNA Secure Arm Cortex
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Cryptographic Functions

AES Engine
The dedicated hardware-based AES engine supports the following algorithms:
● AES-128
● AES-192
● AES-256

ECDSA Engine
The ECDSA engine enables ECDSA signature and verification for following key lengths:
● 256 bits
● 384 bits
● 521 bits
Brainpool and NIST curves are supported.

SHA Engine
The SHA engine supports following SHA algorithms:
● SHA-1
● SHA-256
● SHA-384
● SHA-512

RSA
A crypto API enables RSA computation with key lengths up to 4096 bits.

UART
The universal asynchronous receiver-transmitter (UART) interface supports full-duplex asynchronous communication,
including:
● 16-byte send/receive FIFO
● Full-duplex operation for asynchronous data transfers
● Interrupts available for frame error, parity error, Rx FIFO overrun, and FIFO full/partially full conditions
● Automatic parity and frame error detection
● Independent baud-rate generator
● Programmable 9th bit parity support
● Multidrop support
● Start/stop bit support
● Baud Rate Generation with ±2%
● Maximum baud rate 1843.2kB
● Two DMA channels can be connected (read and write FIFOs)
● Programmable word size (5 bits to 8 bits)
Note: No hardware flow control using RTS/CTS.

I2C Interface
The I2C interface is a bidirectional, two-wire serial bus that provides a medium-speed communications network. It can
operate as a one-to-one, one-to-many or many-to-many communications medium. The I2C master/slave interface to a
wide variety of I2C-compatible peripherals. This engine support both standard mode and fast mode I2C standards. It
provides the following features:
● Master or slave mode operation
● Supports standard (7-bit) addressing or 10-bit addressing

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● Support for clock stretching to allow slower slave devices to operate on higher speed busses
● Multiple transfer rates
• Standard mode: 100kbps
• Fast mode: 400kbps
• Fast mode plus: 1000kbps
● Internal filter to reject noise spikes
● Receiver FIFO depth of 16 bytes
● Transmitter FIFO depth of 16 bytes

SPI
The serial peripheral interface (SPI) is a synchronous interface allowing multiple SPI-compatible devices to be
interconnected.
The provided SPI supports the following features:
● Full-duplex, synchronous communication of 8-/16-bit characters
● 4-wire interface plus
• 1 additional slave select (SPI0)
• 3 additional slave selects (SPI1)
● Master and slave mode of operation
● Master mode data transfer rate of up to one-fourth of the APB clock frequency
● Slave mode data transfer rate of up to one-eighth of the APB clock frequency
● Dedicated baud rate generator
● 8 x 16 transmit and receive FIFOs
● Transmit and receive DMA support
The MAX32520 has two SPI ports SPI0 and SPI1.

Debug and Development Interface (SWD/JTAG)

Development versions of the device are available with a serial wire debug or JTAG interface that is used only during
application development and debugging. The interface is used for code loading, ICE debug activities and for control of
boundary scan activities. Devices in mass production must have the debugging/development interface disabled.
The Ordering Information section contains unique part numbers for devices with the debugging/development interface
enabled or disabled.

Interrupt Sources
The Arm nested vector interrupt controller (NVIC) provides a high-speed, deterministic interrupt response, interrupt
masking, and multiple interrupt sources. Each peripheral is connected to the NVIC and can have multiple interrupt flags
to indicate the specific source of the interrupt within the peripheral.

Standard DMA Controller

The standard DMA (direct memory access) controller provides a means to off-load the CPU for memory/peripheral data
transfer leading to a more power-efficient system. It allows automatic one-way data transfer between two entities. These
entities can be either memories or peripherals. The transfers are done without using CPU resources. The following
transfer modes are supported:
● 4 channel
● Peripheral to data memory
● Data memory to peripheral
● Data memory to data memory
All DMA transactions consist of an AHB burst read into the DMA FIFO followed immediately by an AHB burst write from
the FIFO.

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Programmable Timers
Four 32-bit timers provide timing, capture/compare, or generation of pulse-width modulated (PWM) signals.
● 32-bit up/down autoreload
● Programmable 16-bit prescaler
● PWM output generation
● Capture, compare, and capture/compare capability
● GPIOs can be assigned as external timer inputs, clock gating or capture, limited to an input frequency of 1/4 of the
peripheral clock frequency
● Timer output pin
● Timer interrupt

32-BIT TIMER BLOCK

APB
TIMER CONTROL TIME INTERRUPT
BUS
REGISTER REGISTER

32-BIT COMPARE
REGISTER
TIMER
COMPARE
APB INTERRUPT
CLOCK INTERRUPT
32-BIT TIMER PWM AND TIMER
(WITH PRESCALER) OUTPUT
CONTROL
COMPARE TIMER
32-BIT OUTPUT
PWM/COMPARE

TIMER
INPUT

Figure 4. Timer Block Diagram, 32-Bit Mode

Watchdog Timer
A watchdog timer (WDT) is provided. The watchdog uses a 32-bit timer with prescaler to generate the watchdog reset.
When enabled, the watchdog timer must be written prior to timeout. Failure to write the watchdog timer prior to the pre-
programmed interval time results in a watchdog timeout. The WDT1 is set on reset if a watchdog expiration caused the
system reset. The clock source for the watchdog timer is the system clock.

Power Management

Active Mode
In this mode, the CPU is executing application code and all digital and analog peripherals are available on-demand.
Dynamic clocking disables peripherals not in use, providing the optimal mix of high-performance and low-power
consumption.

Sleep Mode
This mode consumes less power, but wakes faster because the clocks can optionally be enabled.
The device status is as follows:
● The CPU is asleep
● Peripherals are on
● Standard DMA blocks are available for optional use.

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DeepSleep Mode
This mode corresponds to the Arm Cortex-M4 DeepSleep mode. In this mode, CPU and critical peripheral configuration
settings and all volatile memory is preserved.
The device status is as follows:
● The CPU is off.
● The GPIO pins retain their state.
● The transition from DeepSleep to Active mode is faster than the transition from Backup mode because system
initialization is not required.
● The system oscillators are all disabled to provide additional power savings over Sleep mode.
• 120MHz high-speed oscillator
• 7.3728MHz oscillator

Backup Mode
This mode places the CPU in a static, low-power state that supports a fast wake-up to Active mode feature.
The device status is as follows:
● CPU is off.
● Only 72KB, 64KB, 32KB, or 8KB of the SRAM can be retained.

Wake-Up Sources
The sources of wake-up from the Sleep, DeepSleep, and Backup operating modes can be summarized in Table 1.

Table 1. Wake-Up Sources

OPERATING MODE WAKE-UP SOURCE
Sleep Interrupts (GPIO, all peripherals), RSTN assertion
DeepSleep Interrupts (GPIO), RSTN assertion
Backup Interrupts (GPIO), RSTN assertion

Security Monitor

Internal Sensor
The behavior of the system is constantly monitored by a range of internal sensors. The internal sensors include
environmental sensors such as die shield sensor, fault detection sensors and temperature sensor. Furthermore, there
are core sensors monitoring internal core voltage on all rails.

External Tamper Sensors

The device provides an external dynamic tamper sensor. The external tamper sensor uses two pins (EXT_SENSOR_IN,
EXT_SENSOR_OUT) that provide a random, changing pattern generated by an internal, true random entropy source.
The two pins can be connected to a mesh or user-defined, normally-closed tamper switch. External tamper detection
triggers both predefined and user-customizable reactions. Tamper detection also toggles the TAMPER_OUT pin so that
MAX32520 can signal tamper detection to external devices.

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Typical Application Circuits

Secure Serial Boot/External Code Flash with JEDEC Flash Command Support
1.8V 1.8V

1µF 100nF 1µF 100nF 1µF 100nF

MAX32520: SECURE SERIAL BOOT/EXTERNAL CODE

FLASH WITH JEDEC FLASH COMMAND SUPPORT
REG VDD VDDA

MAX32520
NONSECURE HOST MCU

SPI_D0 SFSPIS_DIO0
SPI_D1 SFSPIS_DIO1 UP TO
SPI_D2 SFSPIS_DIO2 MAXIMUM
SPI_D3 SFSPIS_DIO3 FLASH SIZE
SERIAL FLASH
SPI_SCK SFSPIS_SCK SPI EMULATION
SPI_CS SFSPIS_SS0

GPIO RSTN

VSS VSSA

Extended Secure Serial Boot/External Code Flash with Secure System

1.8V 1.8V

1µF 100nF 1µF 100nF 1µF 100nF

MAX32520: EXTENDED SECURE SERIAL

BOOT/EXTERNAL CODE FLASH WITH SECURE REG VDD VDDA
SYSTEM

MAX32520 P0.0 WP#

NONSECURE HOST MCU P0.1 HOLD#

SPI_D0 SPI0_DIO0 MISO1 SO

SPI_D1 SPI0_DIO1 SPI MOSI1 SI
SERIAL SPI FLASH
SPI_D2 SPI0_DIO2 MASTER SCK1 SCK
SPI SLAVE
SPI_D3 SPI0_DIO3 SSEL1_0 CE#
SPI_SCK SCK0 SSEL1_1
SPI_CS SSEL0_0

GPIO RSTN 1.8V

SI
VSS VSSA SO BLUETOOTH
SCK LOW ENERGY
CS

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Ordering Information
PART DEBUG INTERFACE PIN-PACKAGE
MAX32520-BNJ+ Yes 32 TQFN
MAX32520-BNS+ No 32 TQFN
MAX32520-BNS+T No 32 TQFN
MAX32520/W+JU* Yes 30 WLP
MAX32520/W+U* No 30 WLP
MAX32520/W+T* No 30 WLP
+Denotes a lead(Pb)-free/RoHS-compliant package.
T = Tape and reel. Full reel.
*Future product—contact factory for availability.

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Revision History
REVISION REVISION PAGES
DESCRIPTION
NUMBER DATE CHANGED
0 6/19 Initial release —

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Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent
licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max
limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.

Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc. © 2019 Maxim Integrated Products, Inc.