Signal Integrity Interview Questions

Vikas Shukla:
Tom � I was reading this rise time and knee frequency stuff. It says that the rise
time is a significant thing and determines the highest frequency content. Does it
mean that if I have a 1 KHz square wave that has a rise time of 100 ps, it should be
treated as a high frequency signal with spectral frequency of or 3.5 GHz?

Bob � Ideally, yes, this 1 KHz signal should be treated as a 3.5 GHz signal at least
from some of the SI angle, e.g., EMI. But Tom tell me why will anyone design a circuit
with 1 KHz frequency with such a fast rise edge? Does it make sense? A very fast
rising edge makes sense only when you want to achieve high data rate. A fast rising
edge for high data rate reduces Inter Symbol Interference (ISI). But there is no use of
100 ps rise time on a 1 KHz clock signal. It will be source of unnecessary EMI. Fast rise
time and high clock rate usually go hand in hand. A 100 ps rising edge will usually be
observed in clock rates between 500 MHz to 1 GHz signals. And if you do see 100 ps
rise time signal for a 1 KHz clock signal, use a capacitor to slow it down.

Tom � You mentioned ISI in answer to my previous question. What is Inter Symbol
Interference (ISI).

Bob - Tom, I think that the best way to understand a concept is by picture. So, I am
presenting you two pictures and I will let you find the difference between them.
 Figure 2.5
Data transition without any significant Inter Symbol Interference

Figure 2.6
Data transition with Inter Symbol Interference

Both the pictures belong to a random data transition. Which of these two pictures
you like more as a signal integrity engineer? I know you know the answer. The first
picture obviously looks good. The second picture looks screwed up.

If the transitions are in quick successions, the amplitudes are smaller. When the
transition pattern is like 1010101, the signal in not able to rise to its full value. The
signal may also not rise to its full amplitude, if the signal passes though capacitive
loads. The signal starts to rise slowly and before it could rise to full amplitude, the
signal starts to fall. This keeps happening if the signal switches fast in 101010 like
pattern.

Now consider the case when we have the data pattern like 0111110, i.e., a 0
followed by a long sequence of 1s. As the signal rises from 0 to 1, it keeps rising and
reaches to full voltage amplitude and stays at that value. We see that the signal
amplitude in this case is higher than that in the case where the pattern was 010101.
RF Engineers paraphrase this fact as � there is a signal loss and phase change which
is a function of frequency. A pattern like 10101010 is equivalent to higher frequency.
A 111100001111 like pattern is equivalent to a low frequency. At higher frequency
there is higher loss.

Tom � How did the two diagrams originate? What makes data transitions to
become screwed like the one in figure 2-4.

Bob � Both the diagrams were generated with hspice. Both had rise time of 250 ps
and same transitions. In the second case, however, there is a 10 pf capacitor at the
load which kind of screws the figure. The hspice code used to generate these
diagrams can be accessed at

http://referencedesigner.com/books/si/hspice/isi_with_cap.sp

http://referencedesigner.com/books/si/hspice/isi_no_cap.sp

The Intersymbol Interference originates if the rise time is comparable to the time
period of the signal. The Intersymbol Interference gets worse if there are capacitive
loads or discontinuities.

Q1. Which one is a more accurate method of analyzing clock and data signal
relations.

A. Time of propagation of clock and data signal

B. Distance on PCB of clock and data signal

Q2. In a design, timing between the clock and data signal is required to be
matched. Clock signal is routed in stripline and data signal is routed in microstrip.
Then

A. The clock signal will have smaller length

B. The data signal will have smaller length
C. Both clock and data signals will be equal

Answer and Explanations

1. A, the receiver IC seed the timing difference. Although as a PCB designer we will
work primarily on distance
2. A, Signal travels slower in stripline and requires smaller length.

Answer and Explanations

1. C
2. A

3. A, With wider traces, relatively more and more electric lines of forces are between
the trace and the returning plane. This increases the effective dielectric constant.

Q1. Consider the two structures shown below. Both these structures have identical
perimeter( 24 cm). Which of these two structure will have smaller loop inductance.

A. Structure 1
B. Structure 2
C. Both structures will have equal loop inductance

Q2. Consider the inductance of straight wire. Which of the following has a greater
effect on the inductance of wire.

A. Length of the wire.

B. Diameter of the wire.
C. Both of these have same effect.
Q3. A 0603 SMD resistor mounted in normal condition has
A. Mainly Capacitive parasitic
B. Mainly Inductive parasitic

Answer and Explanations

1. A => By keeping the traces close, the magnetic lines of loop cancel and give rise to
lower loop inductance. The structure B is the kind of structure you will follow for
power and ground routing (keep power and ground traces close).

2. A, The inductance of the wire depends more upon the length of wire. Doubling will
not double the inductance; it will only marginally increase it.

3. B In its normal mounting condition, the metallic layer on a resistor resides on the
top surface. This being a bit far from the ground layer makes it somewhat inductive.

Tom � Hey Bob, I just got started with the design for a 4 Layer stack up. I designed
with Layer2 with ground and Layer3 with VCC. The top and bottom layers are for
routing, including high speed signaling. Now this PCB is standard 0.063�. I was told
that the separation between the power and ground planes should be as small as
possible. But I need to keep my top and bottom layer controlled impedance 5 mils to
get the required impedance. With that, the separation between power and ground
layers will be too high � about 50 mils. Is it not too high. What do I do ?

Bob � An excellent question Tom. You have advanced information about controlled
impedance and let me congratulate you about this. The power plane capacitance is
almost non existence which, as you will see later, is required for very high frequency
filtering. You have following options.

1. If your mechanics allows, reduce the total thickness of the board to, say, 0.033�
in place of 0.063�. This will make the board thinner and you will have to see if this
thickness is acceptable. Electrically, this will reduce the power and ground
separation, and provide more power and ground plane capacitance.

2. Fill up the unused areas of the top and bottom layers with ground and power
copper. If layer 2 is a ground layer, fill up top l layer with power. If layer 3 is a power
layer, fill up layer 4 with ground layer. This will provide some additional power to
ground plane capacitance.

3. If it is not too expensive consider upgrading to a 6 layer stackup. You should

consider this option if your board is sensitive to the high frequency noise in the
power plane.

Tom � I designed a six layer stack up with

Signal 1
Ground
Signal 2
Signal 3
Power
Signal 4

In the stuck up I do not get significant power and ground plane coupling. How can
minimize the effect of the lower power plane decoupling

Bob - You should fill up unused areas on the Signal 1, Signal 2, Signal 3 and Signal 4
layers. That should provide some additional power ground capacitance. In this
stackup you should also be careful about providing stitching capacitors in the
different power islands in the Power plane.

Tom � I am designing a new board that is based upon a reference design that I
received from the chip designers. The original design has 14 layers. Since we want to
take the design to production, we want to reduce the number of layers. What are
the things that I should be concerned when reducing the number of layers

Bob � Most of the basic signal integrity requirements are fulfilled with 8 Layer stack
up. There is really no big advantage of the increasing the number of layers beyond 8
layers. An 8 layer stack up, can provide good power ground coupling, tight signal to
power ground coupling. Increasing the layers exceeding 8 is meaningful only if you
are out of space in routing signals. This will depend upon the density of the BGA IC
that you are using.

I will let you reduce the stack up to 8 layers. Don�t reduce it below 8 layers.
Reducing below 8 layers will mean that you are sacrificing one or more signal
integrity concerns.
Practically you should do it step by step. If your original design has 6 power and
ground layers and 8 signal layers, then first remove a pair of ground and layer. Move
the power islands of the removed power plane into the existing power planes. That
reduces the number of layers to 12. Now find which two layers have least density of
signals. Removes these two layers and make sure you can still route the un routed
signals in the existing layers. This reduces the number of layers to 10. Probably you
would like to stop here. But you can keep moving and remove two more signal
layers. Do not reduce the total number of power planes (ground + power) below 4.

Tom � Hey Bob, my circuit has lot of noise in power supply. I can feel it. When I put
my oscilloscope probe, I can see a lot of power supply noise the power and the
ground planes even when I placed the active pin of the probe very close to the
ground wire of the probe. How can I design such that there is no noise between the
power and ground rails.

Bob � You have taken one good step. You have put up a scope and observed the
noise. This is the beginning. You have an analytical and sensitive mind. If there is a
noise it can be suppressed by the use of capacitors. A capacitor provides a low
impedance path between the power and ground rail. Because of the low impedance
path, the ac noise on the power rail gets shorted with the ground.

Tom � I see. I do understand that a capacitor is helpful in ensuring a smooth power

supply. But what is this low impedance path? How does a capacitor provide a low
impedance path?

Bob - I am glad to know you understand the importance of capacitor in suppressing

the noise. You understand its need. The only other thing you need is the ability to
quantitatively specify the value and number of the capacitors required. As far as the
low impedance path provided by a capacitor is concerned, consider the circuit below.
The impedance of a capacitor is given by

Xc= 1/ 2*pi*fc Where,

XC = Impedance in Ohms,
f = frequency,
C = Capacitance in Farad

Now XC is very low if the frequency f is high and/or C is high. As an example, if C =

0.1�F and f = 100 MHz, then
Xc= 1/(2*pi*100*10e6*0.1*10e-6) XC = 0.016 Ohms

This is indeed very low impedance. It will essentially mean that if 100 MHz noise is
present at power rail it should get shorted to ground by the low impedance path.

Tom � OK. OK. So you said that you can provide a low impedance path by using a
capacitor. I use a big capacitor, say 1000 �F. My uncle has a factory that makes 1000
�F capacitors. I will use one of those in my design. With this capacitor I have

Xc= 1/ 2*pi*fc
Now at f = 10 KHz
or,
XC = 0.016 Ohms

Also at f = 100 GHz Xc= 1/(2*pi*100*10e9*1000*10e-6)

or,
XC = 0.0016 micro Ohms

So I keep improving my performance at higher frequencies. I have very low

impedance at all frequencies from 10 KHz to 100 GHz. If frequency is higher than 100
GHz, its performance will be even better at it will have even lower impedance.

Bob � Oh Tom, you are an excellent observer. Your going to extremes to ask
questions make me happy. That is the way to learn. You can not learn by just
monotonically reading. You have to take the assumptions to extremes to
understand.

Now, you have designed a power supply decoupling system that works till 100 GHz.
Let me congratulate you on your observation that the impedance decreases with the
increase in frequency. At 100 GHz it is even better. In fact, with your observation,
your power supply decoupling system gets better at higher frequency. As per your
observation we should not worry about higher frequency noise at all. XC gets lower
and lower at higher and higher frequency. All we need to worry about is the lower
frequency where XC will be somewhat higher as frequency f will be lower.

The reasoning is totally justified, but O Tom, there are evil things in the world and we
need to fight them out. This time the enemy is parasitic inductance of the capacitor.
A 1000 �F capacitor that your uncle makes has a parasitic inductance close to 10
nH. This inductance becomes our enemy at higher frequencies. A 1000 �F capacitor,
such as the one that your uncle makes can be modeled as an inductor in series with a
Capacitor.

Figure 7 6 A real capacitor with parasitic inductance L and series resistance R

Now, the impedance of this structure is given by

Where,
Z = Impedance in Ohms,
f = frequency in Hz,
C = Capacitance in Farad
L = Parasitic inductance of the Capacitance in Henry, also called ESL
R= Effective Series Resistance (ESR) of the capacitor

Now calculate your impedance again at 100 GHz. At 100 GHz, the impedance term
due to the capacitance is simply dwarfed. Let us calculate the impedance at 100 GHz.
Let us ignore the ESR for now.

or,

Z= 6.28 Kilo Ohms

At 100 GHz, you capacitor has an impedance of 6.28 Kilo Ohms. This is as good as
open for the purpose of power supply decoupling. All noise coming into the power
supply rail will not be shorted to ground � it will go directly to IC.

Forget 100 GHz, even at 100 M Hz, there will be 6.28 Ohm impedance. Many
microprocessor supplies can not tolerate that much of impedance. You need much
lower impedance.

Tom � Bob that was helpful. I can now see my enemy � the inductance. If I ask my
uncle to make a 1000 �F capacitor with zero inductance, it will solve my problem.
Correct ?
Bob � Yes it will, if your uncle could design a capacitor with 1000 �F capacity and
no parasitic inductance. However, as the capacitor start growing in size, its leads and
mechanical structure gets bigger and bigger. And therefore, you will usually see
larger parasitic inductance rather than lower parasitic inductance at higher capacitor
value. But I admire your vision of 1000 �F capacity and no parasitic inductance.

Many companies are trying to research to make capacitors with as low parasitic
inductance as possible. Even if it is possible to get capacitances with zero inductance,
there will be trace inductance connecting the capacitor to the power and ground
rails. These trace inductance prevent low impedance at higher frequency.

Tom - Bob, pardon me for my excesses on 1000 �F capacity and 100 GHz frequency
extremes. And thanks for pointing out un practicality of producing an inductor less
1000 �F capacitor. Now tell me

- If 100 GHz is an extreme, what is the reasonable frequency range for which, I
should target to achieve low impedance.

- What is a reasonable low impedance value.

Bob � Tom, now we are in a real and practical discussion. Most of the modern
processor based systems need clean supply free from noise till 1 GHz. For many of
them adequate low impedance till 300 MHz will work.

As for the low impedance value is concerned, I will say the lower the better. A value
of 0.005 Ohm is a reasonably good number. The requirements of processors are
becoming more and more demanding and some of them need as low as 0.001 Ohm
impedance between power and ground rails. Now you know the ball park number. It
is between 0.01 to 0.001, the lower, the better.

Tom � Bob, that seems easy. I see the problem with high value capacitor. They have
high inductance. So now I am choosing 0.1 �F capacitors. I checked that their
parasitic inductance is 0.6 nH.
Now I am calculating their impedance at 1 KHz.

Now neglecting the ESR,

Z = 1592 Ohms

Such a capacitor is useless Bob if we have a noise at 1 KHz at power supply rail.
Isn�t it Bob.

Bob - Your observation is exactly correct. The 0.1 �F capacitor is useless to filter 1
KHz noise on the power rail. That is why you need a high 1000 �F capacitor. It has
low impedance at 1 KHz. This way your uncle will not get out of business. The 0.1 �F
capacitor will have its use at higher frequency.

Tom � Oh, I am very happy to know my Uncle will not get out of business with his
capacitor factory. He has promised me a job after I complete my understanding of
this high speed design stuff.

Now that this 0.1 �F capacitor is useless for filtering low frequency noise of at 1
KHz, I am going to use it for high frequency filtering. Let me see how it performs at 1
GHz.

Neglecting the ESR,

Z = 3.77 Ohms

You had said that we need 0.001 Ohms for most of today�s system designs. This
3.77 Ohms at 1 GHz means this capacitor is useless at high frequency.

You had earlier said that this capacitor is useless at lower frequency and I have to use
my uncle�s 1000 �F capacitor at lower frequency. Now I see that it is useless at
higher frequency of 1 GHz too. If this capacitor is not useful at low frequency, if this
capacitor is not useful at high frequency, then O Bob, what the heck this whole world
keeps using this 0.1 �F capacitor in hundreds of numbers in each of their designs.

Bob � O Tom, going to extremes is good for beginners. It is good to start, but as you
become more and more accomplished, you have to see in between.

Look at the impedance of capacitor

For this case of the 0.1 �F Capacitor, we have

L = 0.1 nH
C = 0.1 �F
Let us also assume some realistic value of the ESR for this capacitor. A 0.1 �F
capacitor has a typical ESR value of 0.05 Ohms.
Now impedance Z is a function of frequency f . So what we need to do is to plot a
curve which shows variation of Z with respect to the frequency f. Here is the curve. I
have generated this curve using Microsoft XL sheet. First I created a column which
had frequency in column
1. The second column has the value of Z. Finally, a plot was generated which is
presented here.
Figure 7 7 Impedance of a Capacitor with Parasitic Inductance

As it can be seen, the impedance is very high at low frequency. The capacitor is
useless there. You will need to use your uncle�s 1000 �F capacitor in this region.
This will keep him in business. At very high frequency also the impedance is high. We
can not use this frequency for very high frequency.

But, in between these two frequencies, this capacitor is useful. It has a relatively low
impedance in some range of frequency around the minima of the above curve. There
is one frequency at which the impedance is lowest. This frequency is given by

Tom � Ah, I am delighted to see this curve. Ok, so the left part of the curve says that
my uncle�s 1000 �F capacitor manufacturing factory will not go out of business. I
will now, no more ask questions about the low frequency range, otherwise you may
change your mind during the discussion and my uncle will go out of business. That
leaves the middle part of the curve and the right part of the curve. I will come to the
right part of the curve later (there is obviously a concern as the impedance is high
there). But first tell me � the impedance is still high in the middle range. The lowest
I see is still about 0.2 Ohm. You were telling that we need to achieve substantially
lower impedance.

Bob � Oh yes the impedance in the middle part of the curve is still high. But we can
lower them. Do you know what is the inductance of two inductors is parallel ?

If L1 and L2 are two inductors connected in parallel, then their equivalent inductance
L is given by

If there are n Inductors each of inductance L are connected in parallel, their

equivalent inductance is given by

And you also know the if there are n Capacitors connected in parallel, their
equivalent capacitance is given by

Now consider that instead of just one of these 0.1 �F capacitors we put n number of
them. They are in parallel. Their equivalent capacitance becomes to , and their
equivalent inductance becomes . So the equivalent inductance is given by

If there are 10 such 0.1 �F capacitors then the equivalent impedance will be one
tenth of the impedance of one capacitor at ALL frequencies. If there are 100 such 0.1
�F capacitors then the equivalent impedance will be one hundredth of the
impedance of one capacitor at ALL frequencies. What it means that the lowest
impedance that you observed to be 0.2 Ohms will become 0.002 Ohms if we use 100
such capacitors.

The curve below shows the impedance of one capacitor versus impedance of 100
capacitors.
 Figur
e 7 8 Impedance of a Capacitor with Parasitic Inductance � comparison of 1
capacitor ( blue) impedance Vs. 100 capacitor impedance.

Tom � Oh, now I understand why people use millions of 0.1 �F capacitors in
designs. Now coming to the higher frequency part of the curve, I see that at
frequencies in 500 MHz to 1 GHz range, the impedance is still high. How do we
overcome that.

Bob � At very high frequency, it is very difficult to get filtering using capacitors. You
can get low impedance using low inductance capacitors and by increasing the
number of capacitors. But even then there is a limitation. The traces and vias that
connect the capacitors to the ground and power rail will have some inductance. This
trace inductance will prevent achieving low impedance for high frequency near 1
GHz.

There is one way we can achieve low impedance near 1 GHz � Using the
capacitance between the power and ground plane. If the power and ground planes
are adjacent to each other by a very thin dielectric, say 3 mils, then this acts as a
capacitor with one good property � it has very low inductance. With power and
ground planes, it is possible to achieve low impedance at frequencies close to 1 GHz.

Tom � OK, OK. Now I understand additional importance of ground and power plane.
I had thought that the power and ground planes were only for ease of routing and
for achieving desired characteristic impedances of the high speed traces on
microstrip and stripline.

Now you had talked about low inductance capacitors. It looks like an interesting area
for my uncle�s business. Can I ask my uncle to start business on low inductance
capacitor. Can you tell me what kind of technology is there in it.

Bob � Many companies are producing these low inductance capacitors. The trick is
to place many capacitors in parallel. The resulting capacitor is called an array
capacitor. By keeping the capacitors in parallel, their equivalent inductances reduce.
These capacitors are more expensive than the normal capacitors. I do not have
business sense, but you can ask your uncle to look into it. They do come expensive,
so there should be some good margin in this product. You must however, note that
the inductance of the mounting trace and mounting vias will not be reduced by the
use of these magic capacitors. The sum total of the inductance of these capacitor and
the mounting trace inductance must be compared against the sum total of the
inductance of low cost capacitor and their mounting trace inductance. It turns out
that the difference may not be that great. My thinking is the cost of these magic
capacitors will be a deciding factor. If the cost of these magic capacitor is only
marginally higher than the regular capacitor, then I will definitely use these magic
capacitors.

Tom � You talked about mounting trace inductance. But you did not take into
account the mounting trace inductance when plotting the impedance for the
capacitor.

Bob � Yes I did not take into account the mounting trace inductance. Ideally, it
should be taken into account. The mounting trace inductance is layout dependent.
We should have traces that are as wide as possible and as small in length as possible
to reduce the trace inductance.

You can take a typical value of the mounting trace inductance of the order of 0.2 nH.
You should derate the capacitors� inductance value to take into account the
mounting inductance.

Tom � You earlier told that the required impedance of a power supply system
should be of the order of 0.01 Ohms. Where did you get this figure ? � out of the air
? This is unscientific. How do we know the value of impedance required by a power
supply voltage rail.

Bob- This 0.01 is a reasonable figure for typical embedded processor core supplies. It
is slightly at higher end for IO supplies for the modern processor based designs. But,
yes, there is a way to calculate the lowest ac impedance between power and ground
planes required by a power supply system.

You must have known AC ripple, as you told in your first question that you observed
some noise between the power and ground rails. Let us say ?V is the maximum
allowed ripple in the power supply rail. If ?I is the maximum change in current, then
the required impedance by the power supply system is given by
Z = dV/dI
As an example, consider a processor system that works on an IO voltage of 1.8V. The
1.8V is often used in mobile DDR IO. Most of the embedded processor to flash IC also
use 1.8V. A typical requirement on this power supply is to have a maximum voltage
ripple of 40 mV. A typical value of maximum change of current is 2 Amps.

The required impedance is given by

Z = dV/dV
or
Z = 40mV /2 Amps

or Z = 0.020 Ohms

Processor cores usually have more switching current requirement and tighter ripple
voltage requirements, leading to required impedance of 0.01 ohms or lower.
8.15 Questions and Answers

Q1. If the separation between the positive and negative traces of a differential
microstrip transmission line is increased, without changing the width of the traces of
the dielectric material, its differential impedance

A. Increases
B. Decreases
C. Stays constant

Q2. Which of the following is not an example of differential bus

A. SATA Bus
B. PCI-X
C. HyperTransport
D. USB

Answers

1. A
2. B

Q1. Which of the following cases needs transmission line instead of an ordinary PCB
trace on most urgent basis

A. Low frequency small interconnect length

B. Low frequency large interconnect length
C. High frequency small interconnect length
D. High frequency large interconnect length

Q2. Which of the following is true about a microstrip transmission line

A. A wider trace has lower capacitance per unit length

B. The capacitance per unit length does not change with the increase in trace width
C. A wider trace has higher capacitance per unit length

Q3. The dielectric loss

A. Increases with frequency

B. Decreases with frequency
C. Does not change with frequency

Q4. Which of the following methods have best accuracy for calculating the
impedance of a microstrip structure.

A. 2D Field Solver
B. IPC Formula
C. Wadell Formula

Q5. The output voltage in open circuit condition of a driver is 3.3v. The driver has an
output impedance of 10 ohms. The driver is driving a 50 Ohm transmission line. The
initial voltage launched into the transmission line is
A. 3.3V
B. 2.75V
C. Depends upon the termination at the end of line.
D. 1.65 V

Q6. The skin depth

A. Increases with increase in frequency

B. Decreases with increase in frequency
C. Does not depend upon frequency.

Answer and Explanations

1.D
2.C
3.A
4. A , Wadell formula is very close to the accurate result under certain conditions. IPC
formula is accurate only for a very small set of values.
5. B. The initial launched voltage will be

6. B

Questions and Answers

Q1. Which of the following does not reduce cross talk

A. Increasing the separation between the traces.

B. Increasing the width of trace
C. Reducing the separation between trace and ground plane.

Q2. Which of the following is not true about Near End Cross talk (NEXT)

A. Near end cross talk amplitude saturates when the parallel length of the
transmission line exceeds half the rise time of the signal.
B. Near end cross talk increases in proportional to the length of the parallelism if the
length of parallel traces is less than one half of the signal rise time.
C. Increasing the length of parallelism beyond half the rise time increases the
duration of the NEXT and not its amplitude.
D. The Near End Cross Talk can not be reduced by separating the traces farther away.

Q3. Which of the following will NOT lead to reduction in cross talk level

A. Reducing separation between traces

B. Using stripline in place of microstrip.
C. Reducing separation between the traces and the ground/power plane.
D. Reducing the dielectric constant of the medium.

Q4. Assume a ramp signal of 0 to 100 % rise time of Tr is incident on a transmission

line of length equivalent to propagation delay of Tp. Tp is much greater than tr.
Which one best describes the duration of the backward cross talk signal.

A. Tp
B. 2Tp
C. 2Tp+2Tr
D. Tp+Tr

Q5. The shape of the forward cross talk is

A. Same as the shape of the incident signal

B. Same as the first derivative of the incident signal
C. Same as the shape of the incident signal, except that it is inverted in sign.
D. None of the above.

Q6. Consider a pair of microstrip traces spaced at distance D apart. The separation
from the ground plane is H. Which of these cases generates greatest amount of cross
talk.

A. D = 4 mils , H = 8 mils
B. D = 6 mils, H = 8 mils
C. D = 8 mils, H = 4 mils
D. D = 8 mils, H = 6 mils

Q7. Consider guard traces inserted in between two traces between a pair of
microstrip. Which one of the following cases is not true.

A. The effectiveness of guard traces increase if they are grounded.

B. The guard traces do not reduce the cross talk at all.
C. Guard traces show more promising improvement in case of microstrip than in case
of stripline.

Answer and Explanations

1.B
2.D
3. D
4. C
5. B
6. A Lower the D/H ratio, more is the crosstalk.
7. B

Question and Answers

Q1 � Which of the following is not likely to cause increase in EMI radiation

A. Increase the length of the trace carrying high speed current
B. Reduce the separation between the trace carrying high speed current and return
path.
C. Increase the rise time

Q2 � If the separation between the trace and the ground layer is increased, the
radiation

A. Increases
B. Decreases
C. Remains unchanged
Answer and Explanations

Q1. C
Q2. A

Test your understanding of Signal Integrity with the questions.

Q1. A high speed digital signal has a 10% to 90% rise time of about 175 psec. What is
the approximate bandwidth of the signal?

A. 10 MHz
B. 500 MHz
C. 2 GHz
D. 5 GHz

Q2. An Oscilloscope has rated bandwidth of 10 GHz. Using this oscilloscope the
10%to 90% rise time of this signal is observed to be 60 ps. What is the approximate
actual rise time of the signal.

A. 30ps
B. 48ps
C. 56ps
D. 74ps

Q3. Consider the following two capacitors

C = 10uF, Effective Series Inductance = 2 nH

C = 4.7uF, Effective Series Inductance = 0.5 nH

Which of the following two capacitors is more effective for power supply filtering at
10 MHz
A. The Capacitor with 10uF capacitance and 2nH inductance
B. The Capacitor with 4.7uF capacitance and 0.5nH inductance

Q4. An SMD test pad is added on a signal path of a microstrip PCB trace for probing.
The width of the test pad is wider than the trace. What is the effect of the test pad
on the trace impedance.

A. Trace impedance decreases at the test pad.

B. Trace impedance increases at the test pad.
C. There is no effect on the trace impedance due to the test pad.

Q5. Which of the following is best for very high frequency ( 1 GHz or more) power
supply noise filtering

A. Electrolytic Capacitors
B. Ceramic Capacitors
C. Ceramic capacitors with low ESR.
D. Capacitance formed by power planes

Q6. Consider the approach where source series termination as well as the end
parallel termination is used. Which of the following is not true about this termination
scheme.

A. This reduces the signal amplitude at the receiver.

B. This scheme has better chance of reducing the reflection as compared to source
series termination alone or the end parallel termination.
C. This termination scheme increase the signal reflections.

Q7. Consider a transmission line with characteristic impedance Zo. A driver of source
resistance x drives the transmission line. What should be the value of the series
resistance to in the series termination scheme to minimize reflection:

A. Zo-x
B. Zo/2 �x
C. (Zo-x)/2
D. Zo+x

Q8. The electric signal travels fastest in

A. Stripline
B. Microstrip with soldermask
C. Microstrip without soldermask

Q9. Which of the following is not a reason for using adjacent ground and power
plane scheme.

A. It provides power supply filtering at very high frequency.

B. They provide decoupling for low frequency noise.
C. Adjacent power and ground planes have high inductance between them required
for high speed signals.
D. It reduces EMI.

Q10. Which of the following is NOT a preferred reason for choosing a BGA package
over a QFN package.

A. A BGA package has lower lead inductance

B. BGA package are easier for assembly house and are better for board level
testability.
C. A BGA package will have lower SSN noise.
Q11. Consider the 6 Layer stack ups with following two possible arrangements

Stackup A

Layer1
GND
Layer2
Layer3
VCC
Layer4

Stackup B

Layer1
Layer2
GND
VCC
Layer3
Layer4

Which of the following statements is NOT true.

A. In stackup B, the separation between GND and VCC is kept minimum for more
power plane capacitance.
B. In stackup B, high speed signals are routed mostly on Layer2 and Layer3.
C. In stackup A, high speed signals can be routed on all four signal layers.
D. Stackup A is better from the power plane capacitance perspective, as it has more
capacitance per unit area than that of stackup B.

Q12. Which of the following packages have highest pin inductance

A. DIP
B. QFP
C. PLCC
D. BGA

Q13. Which of the following is NOT true about SSN ( Simultaneous Switching Noise)

A. Faster IO edge rates generate more SSN.

B. Greater the number of data I/O pins, more is the SSN.
C. Smaller load capacitance increases SSN.
D. Higher package pin inductance increases SSN.

Q14. Consider the PCB traces for connecting the traces of a 1210 capacitor. Which of
the following is the best way to connect the traces to power and ground pins for
minimal trace inductance.
Q15. A transmission line has a small capacitive discontinuity along its length. It can
be partially overcome by

A. Making traces slightly wider of at the two sides of the capacitive discontinuity.
B. Making traces thinner at the two sides of the capacitive discontinuity.

Q16. Consider a 50 ohm source driver driving a transmission line. The impedance of
the transmission line is varied from 40 ohms to 60 Ohms in steps of 5 ohms and the
following simulation curve is obtained. Which of these belong to 55 ohm

A. Curve marked A
B. Curve marked B
C. Curve marked C
D. Curve marked D

Q17. When a signal propagates down a transmission line, it is reflected by a lumped

capacitor encountered in its path. Which of the following is not true

A. The magnitude of the reflected wave is higher if the rise time is shorter.
B. The reflected wave has polarity opposite to that of the incident signal.
C. The magnitude of the reflected wave is smaller if the impedance of the
transmission line is high.
D. The rise time of the transmitted signal slows down.

Q18. Which of the following is not the reason for speed improvement of DDR2 over
DDR
A. DDR2 has on die series termination, while DDR has motherboard series
termination.
B. DDR2 has differential Data Strobe Signals (DQS) while DDR has single ended Data
Strobe Signals (DQS).
C. DDR2 has smaller clock latency (CL) than the DDR

Q19. Assume a differential clock signal and a single ended data signal. If the length of
differential clock signal is same as that of the data signal, then

A. The clock signal arrives earlier than the data signal

B. The data signal arrives earlier than the clock signal
C. The two signals arrive simultaneously.

Q20. Consider two signals A and B both having equal length on the PCB. The signal A
is the DDR command and address signal and has more capacitive loading than that of
signal B, a clock signal. A signal is launched simultaneously on trace A as well as trace
B. Ignoring the fact that clock B is a differential signal,

A. Signal A arrives at its destination earlier that the signal B at its destination.
B. Signal B arrives at its destination earlier that the signal A at its destination.
C. Both the signals arrive simultaneously at their destination.

Q21. It is required to achieve 50 ohm impedance on a 2 Layer board which has

bottom layer as the ground layer. Which of the following will achieve this with least
thickness of the top layer trace.

A. Board thickness 0.063 � , Er = 4.7

B. Board thickness 0.033 � , Er = 4.7
C. Board thickness 0.063 � , Er = 3.8
D. Board thickness 0.033 � , Er = 3.8
Q22. Which of the following are not the advantages of the reduced voltage signaling

A. Reduced Power consumption

B. Reduced EMI
C. Less susceptible to noise

Q23. Which of the following is not the advantage of using a higher impedance (say
70 Ohm) over a lower impedance (say 40 Ohm)

A. Lower power consumption

B. Simplified design for connector and cables.
C. Reduced Cross talk
D. Better attenuation

Q24. Which of the following is not true about ISI

A. The ISI is higher if there is capacitive or other discontinuity in the signal path.
B. The ISI can be partially removed using pre-emphasis
C. ISI can not be observed using eye diagram

1. C
2. B
3. B
4. A
5. D
6. C
7. A
8. C
9. B
10. B
11. D
12. A
13. C
14. D
15. B
16. C
17. C
18. C
19. A
20. B
21. B
22. C
23. C
24. C

Explanations

Q1. The general rule for the calculating the Bandwidth of signal is with rise time Tr is

Band Width = 0.35/Tr

Q2. If an oscilloscope has a rise time ( = 0.35/ band_width) of Tr1 and the signal has a
actual rise time of Tr2, the observed bandwidth is given by

Tr = v(Tr12+Tr22)
Or,
Tr2 = v(Tr2-Tr12)
Here Tr = 60 ps

Tr1 = 0.35 / (10 GHz) = 35 ps

Substituting these values, we get

Tr2 = 48.73 ps
Q3. The impedance of the capacitor will given by the absolute value of

Z = 1/(2pfC) - 2pfL

For the first capacitor,

f = 10 MHz
C=10uF
L=2nH

Substituting these values,

Z = 0.124 Ohms

For the second capacitor

f = 10 MHz
C=4.7uF
L=0.5nH
Substituting these values,

Z = 0.028 Ohms or 28 milli Ohms

Obviously the second capacitor is a better choice for 10 MHz frequency .

Q4. The test pad acts as an additional capacitance. This decreases the trace
impedance.

Q5. Even the capacitors with low ESR loose their effectiveness at frequency as high
as 1 GHz because of the finite inductance of its leads and because of the finite
inductance of the trace connecting the capacitor to power and ground plane. The
parallel plate capacitance formed by a power and ground plane works at highest
frequencies.

Q6. If a series termination as well as the end parallel termination is used the chances
of reflections are greatly reduced. First the signal will get terminated at the receiver.
If because of some mismatch, there is a signal reflection, it will travel back and will
get absorbed at the matched series source termination. The scheme will however,
reduce the signal amplitude at the receiver.

Q7. The sum of the driver source resistance and the external source resistance
should match the characteristic impedance of the transmission line.

Q8. The speed of the electrical signal flowing is copper is reduced by the dielectric
media around it. A stripline is slowest. The solder mask on one side of the microstrip
acts as a partial dielectric and reduces the signal propagation speed. Microstrip
without the soldermask is fastest as it has least effective dielectric around it.

Q9. Because of the low inductance the power planes are effective for filtering very
high frequency power supply noise. Unfortunately, low values of the capacitance
does not make them effective at low frequencies .

Q10. Even though BGA assembly has matured, they can not be directly inspected.
XRays of the BGA parts can only reveal shorts, they can not find open.

Q17. The magnitude of the reflected signal will depend upon the difference in the
impedance of the transmission line and the capacitor. The capacitor provides a low
impedance. A higher transmission line impedance will lead to higher reflection

Q11. DDR2 has in fact, higher clock latency than DDR. This somewhat reduces gain
achieved by way of increased frequency. A DDR2 at 400 MT/s will be slower that the
corresponding DDR at 400 MT/s.

Q19. As a result of the coupling the differential signals travel faster than the single
ended signal. Because of this, whenever, it is required to maintain a timing
relationship between a differential signal and a data signal, the differential signal is
routed for a length greater than the length of the data signal.

Q21. A two layer PCB is sometimes used by RF designers to get a low cost prototype.
Some RF ICs have very small number of pins unlike the digital designs with large
number of address and data pins. A 0.063� thick PCB will require a larger trace
width. To achieve a smaller trace width use a 0.033� thick PCB and high Er.

Q22. Although, the reduced voltage signaling does reduce the power consumption
and the EMI, it becomes more susceptible to the external noise. If we do want to use
a low voltage signaling, especially, single ended low voltage signaling, we should be
careful about the crosstalk and keep the signal away from nearby high speed signals.

Q23. Higher impedance design takes less power. It simplifies the connector and cable
system design because we can spread the signal and return current at reasonable
distance. However, higher impedance means that the signal trace and return ground
plane separation is increased, leading to more cross talk.

1. What is signal integrity?

Signal integrity is a measure of the quality of an electrical signal. It is a

measure of how well the signal can be reproduced at the receiving end, and
how well it can be distinguished from noise.

2. What are some of the challenges that designers face when dealing with signal
integrity?

One of the main challenges that designers face when dealing with signal
integrity is crosstalk. Crosstalk is when the signal from one wire interferes with
the signal on another wire, and can cause all sorts of problems. Another
challenge is impedance mismatches, which can cause reflections and signal
distortion.
3. Can you explain what cross-talk and ground bounce are in context with SI issues?

Cross-talk is when the signal from one trace interferes with the signal on
another trace. Ground bounce is when the ground voltage fluctuates, causing
the signal to be distorted. Both of these can cause SI issues.

4. How does crosstalk impact digital circuits?

Crosstalk is a phenomenon that occurs when a signal from one circuit element
interferes with another signal in an adjacent circuit element. This can cause all
sorts of problems in digital circuits, as it can lead to false signals being
generated, or even cause the circuit to malfunction entirely.

5. What is the difference between noise and jitter?

Noise is any random, unpredictable signal that can interfere with the normal
operation of a system. Jitter, on the other hand, is a type of distortion that
occurs when a signal is not transmitted at a constant rate. Jitter can cause
problems with data transmission and can make digital signals appear analog.

6. Can you explain how to perform an SI analysis without simulation software?

There are a few different ways to analyze signal integrity without simulation
software. One way is to use a mathematical approach, which involves solving
equations that describe the behavior of the signal. Another way is to use a
physical approach, which involves measuring the signal directly and then
analyzing the results.

7. Is it possible to use a multimeter to measure signal integrity? If yes, then how?

Yes, it is possible to use a multimeter to measure signal integrity. This can be

done by measuring the voltage and current of the signal, as well as the rise
time and fall time. By measuring these values, you can get an idea of how well
the signal is being transmitted and whether or not there is any degradation.

8. Why do you think it’s important to have complete information about your design
before starting SI analysis?

There are a few reasons why it is important to have complete information

about your design before starting SI analysis. First, if you don’t have complete
information, you may not be able to accurately model your design, which
could lead to incorrect results. Second, if you don’t have complete information,
you may not be able to identify all potential sources of interference, which
could lead to your design not meeting SI requirements. Finally, if you don’t
have complete information, you may not be able to optimize your design for
SI, which could lead to poorer performance.

9. Are there any advantages or disadvantages to using high speed signals over low
speed ones?

There are a few potential advantages to using high speed signals over low
speed ones. First, high speed signals can carry more data than low speed
signals, so they can be more efficient. Second, high speed signals can be less
susceptible to interference than low speed signals. Finally, high speed signals
can be less likely to experience crosstalk than low speed signals.

There are also a few potential disadvantages to using high speed signals.
First, high speed signals can be more difficult to route than low speed signals.
Second, high speed signals can be more difficult to debug than low speed
signals. Finally, high speed signals can require more power than low speed
signals.

10. What are some ways to mitigate the effects of SI problems on PCBs?

Some ways to mitigate the effects of SI problems on PCBs include:

-Using proper grounding techniques

-Using shielded cables
-Using proper power supply filtering
-Using proper decoupling techniques
-Using proper layout techniques

11. What’s the difference between edge rates and rise times?

Edge rates refer to the speed at which a signal changes from one logic state
to another, while rise times refer to the speed at which a signal transitions
from its low state to its high state.

12. Do you know what EMC testing is? How does it relate to Signal Integrity?

EMC testing is a process of testing electronic devices and systems to ensure

that they are resistant to electromagnetic interference. This is important for
signal integrity, because if a device is not resistant to interference, then the
signal that it is sending or receiving can be corrupted.
13. What do you understand about impedance mismatching?

Impedance mismatching occurs when there is a difference in impedance

between two components that are connected together. This can cause signal
reflections and distortion, which can reduce the quality of the signal.

14. What is skin effect and how does it affect signal propagation on a trace?

The skin effect is the tendency of an electrical current to flow more on the
surface of a conductor than through the conductor’s interior. This effect
becomes more pronounced as frequency increases. On a trace, the skin
effect can cause signal attenuation and distortion.

15. What are the different types of coupling?

The three main types of coupling are capacitive, inductive, and conductive.
Capacitive coupling is when two conductors are close together, but not
touching, and inductive coupling is when two conductors are wrapped around
each other. Conductive coupling is when two conductors are touching.

16. What do you understand about power planes? Can you give me some examples?

Power planes are layers in a printed circuit board (PCB) that are used to
distribute power to the different components in the circuit. The most common
type of power plane is a ground plane, which is used to provide a common
reference point for all of the components in the circuit. Power planes can also
be used to distribute power to specific components or groups of components,
such as when you have a power-hungry component that needs its own
dedicated power supply.

17. What questions should you ask yourself before beginning an SI analysis?

1. What is the purpose of the analysis?

2. What are the objectives of the analysis?
3. What is the system under analysis?
4. What are the sources of signal integrity issues?
5. What are the potential consequences of signal integrity issues?
6. What are the risks associated with signal integrity issues?
7. What are the costs of signal integrity issues?
18. What’s the best way to achieve maximum signal integrity while designing a PCB?

The best way to achieve maximum signal integrity while designing a PCB is to
use a ground plane. A ground plane helps to reduce crosstalk and
interference between different signal traces on the PCB. It also helps to
provide a low-impedance return path for signals, which helps to reduce signal
losses.

19. What are the main differences between high speed and low speed devices?

The main difference between high speed and low speed devices is that high
speed devices are designed to operate at much higher frequencies than low
speed devices. This means that high speed devices are generally much more
expensive and require more careful design and manufacturing.

20. What are the different types of transmission line topologies?

The three most common types of transmission line topologies are microstrip,
stripline, and twin-wire. Each has its own advantages and disadvantages, so it
is important to choose the right one for your application. Microstrip is the
simplest and most common type of transmission line, and it is easy to
fabricate and integrate into circuits. However, it is also the least efficient type
of transmission line, and it is susceptible to crosstalk. Stripline is more efficient
than microstrip and is less susceptible to crosstalk, but it is more difficult to
fabricate and integrate into circuits. Twin-wire is the most efficient type of
transmission line, but it is also the most difficult to fabricate and integrate into
circuits.

6. What are some of the parasitic issues in high-speed PCBs?

High-speed PCBs are very critical to the design, as they completely

depend on the placement and the routing of components. Until now,
some of the parasitic issues I have come across in high-speed PCB are
high-frequency circuits, inductive coupling, series inductance, shunt
capacitance and capacitive coupling.

To overcome these issues, we can consider increasing the distance

between conductors to provide a larger clearance, which eventually
reduces parasitic capacitance. Other than that, we can be more
mindful of the use of vias in our design, as an excessive amount can
introduce a larger amount of parasitic capacitance.
What steps do you take to ensure design compliance for EMI?
I use cable connectors for all common mode chokes and
ensure that we place the common mode chokes in
proximity to the connector. It is also important that the
ground and power planes are as close to each other as
possible. When testing, the high-speed signal ideally
refers to a power or ground plane and never crosses a
split plane. If we use a split plane, I ensure that we also
add a stitching capacitor

https://dridhon.com/pcb-design-interview-questions-
answers/

1. What PCB (Printed Circuit Board) material should I use?

The PCB material must be chosen entirely on the basis of a balance of design
requirement, volume production, and cost. Electrical elements that need be taken
into account during high-speed PCB design are called design demand. In
addition, the frequency should be taken into account when determining the
dielectric constant and dielectric loss.

2: How can high-frequency interference be avoided?

The most important approach for overcoming high-frequency interference is to

minimise crosstalk, which can be accomplished by increasing the distance
between high-speed signals and analogue signals or by using ground guard or
shunt traces alongside analogue channels. Furthermore, the noise interference
induced by digital ground on analogue ground must be taken into account.

3. What is the best way to arrange traces that convey differential signals?

When designing traces carrying differential signals, two points should be kept in
mind. On the one hand, two lines should be the same length; on the other, the
spacing between two lines should remain parallel.
4. How can you organise traces conveying differential signals when the
output terminal only has one clock signal line?

In order for traces carrying differential signals to work, both the signal sources
and the receiving end must be differential signals. As a result, differential routing
cannot be used with clock signals with only one output end.

5 .Is it possible to apply matching resistance between differential pairs at

the receiving end?

At the receiving end, matched resistance is frequently applied between differential

pairs. matching resistance is usually used.

6. Why should differential pair traces be parallel and close to each other?

Differential pair traces should be close and parallel to one other. Differential
impedance, a critical reference parameter in differential pair design, determines
the distance between differential pair traces.

7. How can conflicts between manual and automatic routing on high-speed

signals be resolved?

Most automatic routers may now specify constraint constraints to regulate wire
running manner and number of through holes. In terms of wire running
methodologies and constraint condition setup, all EDA vendors differ significantly.
The ability to run wires is closely connected to the difficulty of autonomous
routing. As a result, this issue can be rectified by purchasing a router with a high
throughput.

8. The blank space of signal layers can be plated with copper in high-speed
PCB design. On grounding and powering, how should copper be divided
across many signal layers?

In most blank areas, copper covering is largely attached to the ground. Because
coated copper reduces characteristic impedance a little, the distance between
copper coating and signal lines should be carefully calculated. Other layers'
characteristic impedance should not be altered in the meantime.
9. Can a micro strip line model be used to calculate characteristic
impedance on the power plane? Is it possible to utilise the micro strip line
model on communications between the power plane and the ground plane?

Of course. Both the power plane and the ground plane can be used as reference
planes in the calculation of characteristic impedance.

10. Can test points created by automation on high-density PCBs match the
testing demands of large-scale manufacturing?

It depends on the situation whether test point regulations are consistent with test
machine requirements. Furthermore, if routing is done too intensively and test
point restrictions are too rigorous, there may be no way to put test points on each
line segment. Manual procedures can, of course, be employed to supplement test
points.

11. Can the addition of test points affect the quality of high-speed signals?

It all relies on the situation, such as the test point adding method and the signal
running speed. Adding test points is accomplished by attaching them to lines or
removing a segment.

12. How should the ground lines of each PCB be connected when a few of
PCBs are integrated into a system?

According to Kirchoff's current law, when power or signals are delivered from
Board A to Board B, an equal amount of current is returned from the ground plane
to Board A, and the current on the ground plane flows back at the path with the
lowest impedance. As a result, the number of pins contributing to the ground
plane at each interface of power or signal connectivity should never be too small,
in order to limit ground impedance and noise. In addition, the entire current loop
should be examined, particularly the area where current is the greatest and the
ground plane connection.

13: Can ground lines be added to differential signal lines in the middle?

Ground lines cannot be added to differential signal lines because the benefit of
mutual coupling between differential signal lines, such as flux cancellation and
noise immunity, is the most important aspect of the differential signal line
principle. If ground lines are put between them, the coupling effect will be lost.

14. What is the principle behind selecting an appropriate PCB and covering
the grounding point?

The idea is to use chassis ground to provide a low-impedance conduit for

returning current and to control the path of that returning current. Screws, for
example, are commonly used to connect the ground plane to a high-frequency
component or clock generator. to limit the total current loop area as much as
feasible, i.e. to reduce electromagnetic interference.

15. When it comes to PCB debugging, where should you start?

When it comes to digital circuits, the following steps should be followed in order.
To begin, all power levels should be double-checked to ensure that the design
requirement is met on average. Second, make sure that all of the clock signal
frequencies are working properly and that there are no non-monotonic issues on
the edge. Third, in order to meet the standard requirement, reset signals must be
confirmed. If all of the above is true, the chip should send signals in the first
cycle. Then, using the system operating protocol and the bus protocol, debugging
will be carried out.

16. What is the ideal method for designing a high-speed, high-density PCB
with a set board area?

Crosstalk interference should be given special attention during the design of high-
speed and high-density PCBs since it has a significant impact on timing and
signal integrity. There are a few design options presented. First, the routing
characteristic impedance should be regulated for continuity and matching.
Second, observe the spacing, which is usually twice the line width. Third, the
appropriate termination mechanisms should be chosen. Fourth, routing should be
done in diverse directions in adjacent levels. Fifth, to expand route space,
blind/buried vias might be used. Furthermore, differential and common-mode
termination should be preserved to minimise the impact on timing and signal
integrity.
17 .At analogue power, the LC circuit is commonly used to filter the wave.
Why is it that LC sometimes outperforms RC?

When comparing LC with RC, it's important to consider if the frequency band and
inductance are properly chosen. Because inductance reactance is connected with
inductance and frequency, LC performs worse than RC if the noise frequency of
power is too low and inductance isn't high enough. However, one of the
disadvantages of RC is that the resistor consumes a lot of energy and is
inefficient.

18. What is the best strategy to meet EMC requirements without breaking the
bank?

The cost of a PCB board increases due to EMC, mainly because the layer count
is increased to increase shielding stress and some components, such as ferrite
beads or chokes, are prepared to halt high-frequency harmonic wave
components. Other shielding structures on other systems should also be
employed to meet EMC requirements. To begin, as many components with a low
slew rate as possible should be used to reduce high-frequency sections created
by signals. Second, high-frequency components should never be installed too
close to connectors on the outside. Third, high-speed signals' impedance
matching, routing layer, and return current channel should be carefully planned to
minimise high-frequency reflection and radiation.

19. When there are many digital/analog modules on a PCB board, the
standard solution is to divide them. Why?

The reason for separating digital and analogue modules is that noise is generated
at power and ground when high and low potentials are switched, and the amount
of noise is proportional to signal speed and current. Even though analogue and
digital signals do not come across, analogue signals will be influenced by noise if
analogue and digital modules are not split and the noise generated by the digital
module is bigger and the circuit at the analogue region is similar.

20. How should impedance matching be implemented when designing high-

speed PCBs?
When it comes to high-speed PCB design, impedance matching is crucial. one of
the most important considerations The absolute relationship between impedance
and routing can be found in impedance. Characteristic impedance, for example, is
determined by a number of factors such as the distance between the microstrip or
stripline/double stripline layer and the reference layer, routing width, PCB
material, and so on. To put it another way, characteristic impedance cannot be
determined until the circuit is routed. The most important answer to this problem
is to prevent impedance discontinuity as much as feasible.

21. Which EMC/EMI mitigation measures should be taken throughout the

high-speed PCB design process?

In general, both radiated and conducted components of EMI/EMC design should

be considered. The former belongs to the segment with a higher frequency
(greater than 30MHz), while the latter belongs to the portion with a lower
frequency (less than 30MHz) (less than 30MHz). As a result, both the high-
frequency and low-frequency portions of the signal should be noted. Component
placement, PCB stack up, routing, component selection, and other aspects of a
good EMI/EMC design should all be considered. Costs are likely to rise if such
factors are ignored. The clock generator, for example, should be kept as far away
from the external connector as practicable. Additionally, connecting points
between the PCB and the chassis should be carefully chosen.

22. What is the topology of a routing network?

In a network with numerous terminators, routing topology, also known as routing

order, refers to the order of routing.

23. What changes should be made to the routing topology to improve signal
integrity?

Because this form of network signal is so complicated, the topology varies

depending on the direction, level, and type of signal. As a result, determining
which types of signals are favourable to signal quality is tough.

24 What is the significance of copper coating?

Copper plating is frequently done for a couple of reasons. To begin with, a huge
ground or power copper covering will have a shielding effect, and some special
grounds, such as PGND, can serve as a protective ground. Second, to assure
superior electroplating or stop lamination performance. Copper should be coated
on PCB boards with less routing to prevent deformation. Third, signal integrity
necessitates the use of copper covering. High-frequency digital signals should
have a complete return path, and DC network routing should be minimised.
Thermal dissipation should also be taken into account.

25. What is the definition of return current?

High-speed digital signals move from drivers to carriers along a PCB transmission
line, then back to the driver terminal via the quickest path along ground or power.
Return current refers to the signals that return to ground or power.

A differential pair is routed as a microstrip and the weave of the FR4 causes the er
on one of the signals in the pair to vary a lot from the other member of the pair
(think egregious, 3.4 on one, 4.5 on the other). What effects can you expect and
what can you do to mitigate
Time of flight different, impedance different, common mode noise. Try routing the pair at an
angle to the weave if possible. Typically, you wouldn't see a spread of er that wide. Probably
closer to 4.5 and 4.2 or something

Details on a PLL - loop bandwidth filter selection choice and detailed technical
explanation

What is the most important figure of merit with signal integrity?

Slew rate (data rate is also a good answer, but thats a frequency domain figure. Digital analyses
are typically more focused on time domain, so slew rate is a better answer)

What are the most important characteristics of a transmission line?

Impedance, loss, crosstalk/coupling, delay
Define the target impedance of a power distribution network
Z = delta(V)/delta(I). Ratio of the max voltage ripple required by load component to the largest
dynamic change in current

What is the shape of a capacitor model in frequency domain?

V-shape or U-shape

Why does the PCIe spec limit the time skew of a common clock architecture to less
than 12 ns skew between the clock routed to the transmitter side and the sum of
the clock routed to the receiver side PLUS the routing length of the TX lane to the
receiver.

A differential pair is routed as a microstrip and the weave of the FR4 causes the er
on one of the signals in the pair to vary a lot from the other member of the pair
(think egregious, 3.4 on one, 4.5 on the other). What effects can you expect and
what can you do to mitigate.

Details on a PLL - loop bandwidth filter selection choice and detailed technical
explanation

Lots of questions about stackups, and how you would advise designers early in the
design process to avoid SI and PI issues

What is the most important figure of merit with signal integrity?

All sorts of questions. One interviewer has a full list of 20+ questions to blast thur.
Didn't seem to care how and what I've done from my past job experience.

What are the most important characteristics of a transmission line?

What is the shape of a capacitor model in frequency domain?

Define the target impedance of a power distribution network

Explain TDR response Explain trace return loss

What is a byte lane?

what is the phase relationship between clock and data?

Far end crosstalk and Near end crosstalk - explain. Importance of Preemphasis.
How is the value of an AC capacitor determined in the signal topology Details
about lab experience on TDA, VNA

Characteristics impedance in detail -Differential VIA design -Some high speed

timing related questions -Many more related to signal integrity i.e. tool
knowledge, electromagnetic theory etc.

Primarily looks at your knowledge on transmission lines and ways to mitigate

coupling losses. Knowledge of 3D EM Simulation software comes in handy.

High frequency resistor, capacitor, inductor model, effect of capacitor & inductor
in series resonance circuit, differential signal, skew finding method of differential
trace, termination method of differential trace, TDR response of LPF, eye diagram,
bounce diagram, Probing method, voltmeter & ammeter, VNA calibration
procedure, skin effect, bit rate & band width, current distribution on CPW &
microstrip and some behavioral questions

Signal Integrity basics, Transmission line theory, crosstalk, few questions based on
impedance
They are friendly and they will ask you to explain the basic concepts in the white
board, The basic concepts includes KCL, KVL, x y z parameters, eye diagram, digital
basics, txn line theory etc

A few questions about RLC circuits, and high-pass/low-pass filtering circuits.

Talk about electrostatic interference and cross talk in High Speed PCB

Why put a resistor in series with signal line?

Yes, signal integrity is the reason. Using a cap will slow the edge down a lot and ins't as clean. The
standard book on the subject is High Speed Digital Design: A Handbook of Black Magic. As a rule
of thumb, 22.1 ohms is typically used as a starting point. You can use a signal integrity simulation
tool such as Mentor Graphics' HyperLynx to get a better analysis before the board is built.
On the VDD line that isn't the reason. Some people might put a milliohm resistor there to measure
power, then replace it with a 0 ohm for production. Others, especially analog may put an RC filter on
there to get rid of noise.

Why are PCIE's coupling capacitors so large

The larger AC coupling value passes the low-speed 'ping' pulses used for sensing the
presence of a link partner. The TX PHY sends the pulses, then watches the signal using the
known R-C time constant to detect an open or terminated line.

Here's an excerpt from an article describing this:

"Receiver detection: PCIe uses an ingenious means to recognize both the presence of a
physical link and channel width. The specification exploits the fact that an un-terminated,
ac-coupled transmission line will have a very different charge time when the line is
terminated versus open. Each PCIe transmitter, at the commencement of linkup, produces a
low-frequency “ping” on each of the differential TX outputs. The transmitter includes a
simple detection circuit to monitor the line response to this ping. With no receiver attached,
the edge rate (and amplitude) of the line change is much higher than when a receiver is
present. Because the specification has a defined range of coupling capacitance and the
receiver termination, a distinct, detectable time constant range defines when a receiver is
present or not."

: https://www.electronicdesign.com/technologies/communications/article/21762833/pci-
express-and-the-physical-journey-to-gen-3
How to transmit high current (2.6A) with low voltage (1.2V)
for a long distance?
19

In general, trying to push final regulated power any distance is not a good idea. In your case it clearly
won't work. Yes, the return path adds to the total resistance since it is in series with the load. It is
strange that you have connectors in the positive supply but not in the ground. If this is a fixed
installation, then why not solder wires from one end to the other?

A better way to deal with the need for distributed regulated power, especially at low voltage and high
currents as you have, is to distribute a higher roughly regulated voltage and make the final tightly
regulated voltage locally. This does two useful things:

1. The drop in distributing the higher voltage won't matter since is will be regulated anyway to the
final voltage. You do have to make sure the voltage at the other is at least the minimum required
for that regulator to work correctly, but that headroom is usually easy to build in.
2. In the case of local regulators being switchers, the higher voltage will have less current, which
means it will also have less voltage drop accross the distance, with less power wasted and heat
that must be dealt with.
So where does your 1.2V supply come from? You probably have some higher voltage with a buck
converter somewhere. Send that higher voltage over the distance and put a buck regulator right at the
DSP. Note that this relaxes the requirements on the 1.2V supply on the main board. Two smaller
buck regulators will still be more expensive than one larger one, but allowing both to be smaller will
help somewhat. It also distributes the heat from any losses, which usually makes that easier to deal
with.

Added in response to your comment:

If you really really can't put a local regulator by the load, then the next best thing is to have a sense
line coming back. This line reports that actual voltage at the far end back to the regulator on the main
board. This voltage is used as feedback so that the voltage at the far end is what is regulated. The
voltage at the regulator then will automatically be higher as needed to overcome the voltage drop on
the way to the load. The sense line doesn't experience these voltage drops since it has very little
current flowing thru it. It is just a voltage feedback signal.

If the ground connection also can have significant voltage drop, then it gets more tricky. Sometimes
you use two sense lines and treat them differentially at the power supply. Sometimes you assume the
forward and backward voltage drops will be about equal and add a little bit of gain in the sense
circuit. Sometimes you just set the output of the supply a little higher to compensate for the nominal
total voltage drop and not try to actively regulate around it at all.

Reflection

What is the typical PCB trace impedance?

The most common impedance for signals lines is 50 ohms. This
matches cable impedance and provides a good tradeoff between conduction losses
and reflections.

When do reflections need mitigation?

Reflections must be addressed whenever fast edge rates under 1-2ns rise time are
present on unmatched transmission lines longer than 1/10th wavelength.

How can reflections be observed?

An oscilloscope plots signal waveform ringing and noise caused by impedance

discontinuities. Time domain reflectometry (TDR) tools also measure reflections.

Where should source termination resistors be placed?

Series resistors should be located as close as possible to the driver output pin or
package to prevent resonances on the line prior to damping reflections.

What values are used for termination resistors?

Terminator resistance should match the trace characteristic impedance (typically

50Ω). Lower values attenuate while higher values reflect more energy.

1. What is the most critical board design you have worked on?
2. when is DRC check done on the PCB?
3. What are all the DRC checks you perform on the PCB?
4. What are all the PCB design tools you have worked on?
5. what are all the inputs required for a PCB design engineer to start his work?
6. Explain a 8-layer stack up
7. Who decides the stack up in your organization?
8. How do you come up with layer stack up for a given PCB design?
9. How do you determine the PCB material to be used for the fabrication?
10. What is the process to create a footprint?
11. What is the IPC standard followed in the footprint creation?
12. what is the minimum pitch BGA routing you have worked with?
13. what is blind via?
14. what is buried via?
15. What is Ratsnest in PCB Layout terminology?
16. Have you performed thermal analysis on your PCB?
17. what are the different PCB file extensions you are familiar with?
18. How do you ensure that your PCB exactly fit into the mechanicals?
19. Is silkscreen outline a must in PCB Layout? How does this help?
20. what is the need for fiducials on the PCB?
21. what are the instructions a PCB Design engineer provide to manufacturing/fabrication
house?
22. What are the different types of fiducials on the PCB?
23. How do your determine via size in a PCB?
24. what does the term fanout mean in PCB terminology?
25. what are the guidelines you follow for routing a clock signal on a PCB?
26. what are the guidelines you follow while placing the power section of the PCB?
27. Can you place a right angled connector inside the PCB rather than at the edge?
28. How do you place the decoupling capacitor which is connected to a power line for a IC?
29. what are the routing guidelines you follow on a board which has analog and digital signals?
30. what are .stp files?
31. What is the sequence followed while starting a PCB Layout activity?
32. Define Skin depth
33. How do you calculate the characteristic impedance for a signal?
34. Define characteristic impedance?
35. what is the difference between impedance and resistance?
36. what are the routing guidelines to be followed for current sense resistor?
37. How is track length and impedance related?
38. How is track width and impedance related?
39. Give few guidleines for placing the crystal oscillator used for prociding clock to
microcontroller.
40. what are the various package types for which you have created footprints?
41. what is the biggest mistake you have done in the PCB routing?
42. What is the purpose of Valor tool?
43. How do you calculate the Trace impedance?
44. How do you calculate the trace impedance of a already farbicated board?
45. what is the use of common mode choke in the PCB?
46. what are the routing guidelines for routing ethernet signals?
47. If a series termiantion is used in the design, where do you place the termination?
48. what is the best termination technique to be used for clock signal?
49. Hardware design engineer has given a PCB to you for routing. You have started the activity.
what would be the value addition to the hardware design engineer from your side?
50. What is the use of stitching capacitor?
51. What is the process followed during the PCB fabrication?
52. A LED is present in the design and how as a PCB design engineer you ensure good
palcement such that design engineer and aseembly house benefit?
53. what are press fit connectors?
54. There is a 20-pin connector on the board. 4 pins are 5V and 6 pins are GND. The total power
input to the board is 150W. what are all the routing guidelines you follow to ensure proper
board functionality?
55. What specification of the given IC from the datasheet helps thermal analysis of that part?
56. what is the difference between operating and storage temeprature?
57. why characteristic impedance reduces with increses in trace width?
58. Why does signal reflection occur in a PCB?
59. what do you mean by termination on the board?
60. Can you define cross talk?
61. Does analog effect digital signals or digital signals effect analog signals?
62. what are the generic criteria to be followed during high speed board designs?
63. How can say that a signal is high speed signal?
64. What is the definition of characteristic impedance?
65. What is the dielectric constant of a FR4 material?
66. For suppose, you are working on a high speed design board which has PCIe lines, Ether net
lines and DDR, what is the PCB material you would propose?
67. Provide any 3 inputs to arrest the EMI that can arise out of the board?
68. What is PDN in a PCB layout terminology?
69. What is the difference between loosely coupled and tightly coupled differential lines? Where
do you use them?
70. What is the difference between DFT and DFM?
71. Why is lenght matching essential in a PCB?
72. Give any few tips to maintain integrity of a signal on a PCB?
73. What is the length matching requirement for PCIe 2.0 signals?
74. How do you determine the spacing between the signal and reference plane in a PCB stack
up?
75. If you have to route a signal of curernt capaibility of 12A, what are the steps you follow for
routing this signal?
76. What is propogation delay?
77. Whcih topology has more propogation delay? Stri-pline or microstrip?
78. Draw the structure of stripline.
79. which topology do you use for clock routing, stripline or microstripline?
80. What are the difefrrent types of cross talks on PCB?
81. whay does cross talk happen on a PCB?
82. why does ringing occur on the signals?
83. Why differential signalling is preffred for high speed signals?
84. What is common mode noise nd differential mode noise?
85. Why does conducted EMI occur in a PCB?
86. Hardware design engineer has come back to you saying that the board has failed in
EMI/EMC test? How do you start debugging the board to find potential issues with layout?
87. Let us assume there are several ICs placed on the board. What is the best method to have a
minimal PCB ground impedance?
88. What are current/ground loops in a PCB layout?

EDACafe: In your view, what are the major signal integrity and power integrity challenges posed – in
high-speed PCB design – by next generation applications such as 5G and by new semiconductor
devices such as DDR5 memories? Can you provide practical examples of critical issues in next-
generation PCB layout?

Wade Smith: There are quite a few signal integrity problems that dampen high-speed PCB designs
for applications such as 5G. Material and fabrication fluctuations, increased sensitivity to noise on
power planes, cables and connectors, EMI, and multi-physics are but a few issues that contribute to a
degradation in high-speed signals. For example, 5G is, without a doubt, pushing datacenters to ramp
up their signal processing capabilities to the levels that will support applications such as smart cities,
IIoT, autonomous vehicles, next-gen healthcare, next-gen military, AR/VR applications, and more. We
hear all about the need for 32 Gbps, 56 Gbps, or 112 Gbps signals being pushed around in new server
applications. Signals at these speeds can be extremely sensitive to changes in materials, such as
dielectric property deltas and conductor surface roughness. Fabrication tolerances that give rise to
changing signal line metal dimensions or differences in electrical dielectric properties can cause the
impedance a signal sees to differ sometimes up to 10% (or more depending on the material quality).
Multi-physics issues, such as thermal, once thought to be a higher order problem, is now showing to
cause a larger degradation on high speed signals due to its ability to alter the electrical properties of
PCB materials (such as raising the metal resistivity or slightly modifying the loss tangent of
dielectrics). Power plane noise from switching regulators or SSN issues can lead to issues on very
sensitive low core voltages used by modern chips that handle these huge amounts of data. Also, since
higher speed signals have such shorter bit times, effects such as mismatches when a signal flows
through a connector are becoming an even larger hurdle. Chip packaging is another issue that is
starting to plague signal integrity. New package systems are incorporating very complex interposers
which need to reliably handle high-speed signals without offering too much degradation. Companies
exploring the use of chiplets, HBM applications and more tend to want to cram more chips onto these
complex interposers thereby leading to many signal lines that may not have a very clean reference.
The combinations of these effects, in addition to other issues, are making it more and more difficult to
maintain clean signal integrity.

EDACafe: If not properly addressed, what impact could these challenges have on system
performance, cost and time to market? Is “overdesign” a common problem today?

Wade Smith: Not paying attention to fabrication tolerances and operation conditions, such as
temperature, for example, can be detrimental to designs employing high-speed signals such as
16Gbps, 28Gbps, 32Gbps, 56Gbps, etc. These signals have ps bit periods, so they are easily affected
by impedance discontinuities caused by changes in how the signal flows. Issues such as those
discussed above can be handled by advanced simulation tools, so users can quantify the effects of
these discontinuities to figure out how much their signals will be affected by them. Not doing so
opens the door for design failures and re-spins that can cause hundreds of thousands to millions of
dollars in fabrication costs, engineering time for lab testing/debug/redesign, increased time to market,
and more. Also, depending on the application, for example health care or autonomous vehicles, poor
designs that ship with potential signal/power/thermal integrity or EMI issues can lead to somebody
getting seriously hurt.

Overdesign typically comes into play with people are using back-of-the-napkin estimations to try to
make designs work or there is a bit of inexperience in designing for projects pushing high data rate
applications. However, on the other hand, I have seen some applications where underdesign was a
problem due to pressure by management to cut costs, forcing engineers to use subpar materials, or a
tight timeline caused engineers to rush the design. In these cases, simulation can be used in
incremental stages of the design, or automation can be crafted so the simulations are automatically
setup and ran thereby allowing the engineer to tackle multiple tasks in shorter time periods.

EDACafe: The EDA industry as a whole is developing new approaches to tackle the new signal
integrity and power integrity challenges, such as SI/PI co-simulation and the adoption of IBIS-AMI
models for DDR5 memories. In your view, what are the most promising approaches? How mature are
they?

Wade Smith: When discussing DDR5, it is interesting to ponder the obstacles that designers will face
in order to make this work correctly. First of all, DDR5 will have a faster data rate in comparison to
previous DDR applications. JEDEC specs show DDR5 being capable of handling speeds up to 6400
MT/s per signal lane at 1.1V. The clock for this speed will be 3.2GHz. This means signal channel
design on the PCB needs to be more sensitive and accurate than needed by slower designs in the past
and bandwidths of close to 20GHz will be needed. This will push many board analysis applications into
the realm of full-wave electromagnetic simulation tools. Also, it may be a good idea to model more of
the channel than in past designs, so the DIMM and the DIMM connector should be included with the
PCB to get a more accurate view of how the channel will affect the signal. The inclusion of multiple
boards and connector models in a single simulation should help better characterize issues such as
impedance mismatch, signal reflections, crosstalk, ISI, channel dispersion, and power/ground bounce
are a few of the more common issues designers should expect. DDR5 applications are planned to
include Decision Feedback Equalization (DFE) to help mitigate some of these effects and open the eye
at the receiver chip. In this case, an SI engineer needs to have some idea of what Bit Error Rate is
needed to guarantee a solid signal at the receiver in addition to voltage and timing margins. DDR5
will need a BER of 10-16. Simulating enough bits to get to a 10-16 resolution using standard transient
engines with SPICE or IBIS models can take a ridiculous amount of time; hence the interest in using
IBIS-AMI models. The methodology used by IBIS-AMI can greatly speed up simulation times because
millions of bits are not required. These models also provide a more accurate algorithm from the
vendor that characterizes their equalization methodologies. The use of IBIS-AMI models to
characterize the operation of DDR5 in simulations is a great addition, however there are some issues it
brings with it. One being the inability to characterize how power fluctuations will affect bit reliability.
SPICE models, and more recent IBIS models, allow for the power rails to be included in the device
simulation, so reference plane bounce can be added to the simulation. IBIS-AMI models do not
handle this information, and DDR5 devices have a very small allowance for power plane fluctuations,
so this could lead to some potential miscalculations. There are other signal characteristics required by
DDR that are not currently handled by IBIS-AMI models, such as DC offset and rise/fall time
differences, that may lie on the EDA simulation software to figure out how to handle. However, IBIS-
AMI models being used in DDR5 applications seem to be a step in the right direction.

Another area, many times not discussed, I see as a growing concern for engineers is EMI. Many
engineers are trying to simulate EMI to get a better idea of how their systems will operate within more
sensitive margins. One of the major areas of interest tends to be around switching voltage regulators
because their switching speeds are becoming faster, thereby leading to more harmonic content in the
100’s of MHz. This not only leads to more noise in the supply rails, but also more potential for
radiated emissions. This is another application for more tools that can help point out issues before
engineers find them by accident in the lab. Tools such as EMI Scanners for boards can be employed
at the initial phases of layout analysis to help find SI/PI/EMI issues before one advances into heavier
electromagnetic simulations. Also, if needed, the power of High-Performance Computing allows for
huge simulations to be completed, so users can actually place full boards in virtual anechoic chambers
to run virtual EMI tests.

EDACafe: Several major EDA vendors, such as your company, are already offering solutions
addressing the new signal integrity and power integrity challenges. How can users choose the best
solution? What features should they be looking for, when choosing a new EDA platform for this kind of
application?

Wade Smith: The whole idea of signal/power/thermal integrity analysis is to create a virtual
prototype of a physical geometry one can use to modify and optimize in order to gain design insight
while reducing the probabilities of redesigns. Weather the problem is the analysis of a 3D integrated
circuit chip and packaging application, the quantization of power planes on a PCB to verify the planar
impedance is at a level where it will not cause problems while supplying power to the devices in need,
or the characterization of the effect a certain connector has on a 56Gbps signal, the simulation
software has to be accurate. Therefore, one wants to make sure the tool of choice is reliable and well
established. Tools such as ANSYS HFSS, for example, have been solving 3D electromagnetic problems
for decades. This tool has been compared to a wealth of experimental data, so there is a high
confidence level associated with it. There’s no arguing that sensitive electronic devices are being
placed into more complex environments, so the characterization of those environments will certainly
help better predict the end goal operation of the device in question. These environments could be a
high-speed signal application in an autonomous vehicle which may have changing ambient
temperatures depending on its location (in Phoenix in summer or Ottawa in winter). The environment
may be a mini-server for a picocell 5G edge network application that sits inside a radome mounted to
the side of a building in direct sunlight in Dallas. In these cases, it is a good idea to have an accurate
thermal solver, such as ANSYS Icepak, that can analyze how temperatures will affect the hardware in
question and feed that information back into HFSS so those effects can be taken into account in the
electrical analysis. Also, I’ve noticed the physical simulations engineers are running are getting larger
and larger. I wouldn’t have thought of running a full server motherboard with a press-fit connector
and an IO card, all together in one EM simulation being even possible a few years ago. These types of
simulations are possible with new algorithms that mix different electromagnetic solvers and make use
of large compute cluster environments. If an engineer is looking to create realistic virtual prototypes
that are large and complex, High Performance Computing is a must have option. Lastly, the ability to
construct solutions in both the frequency and time domains is a must. In signal integrity applications,
the end results usually are viewed in the time domain because the end goal is to make sure bits will
travel from point A to point B. Therefore, the ability to combine the physical electromagnetic solutions
with the proper stimulus such as SPICE, IBIS, or IBIS-AMI models is something that should be highly
considered.

EDACafe: Can you briefly describe your company’s offering in this space, including the suggested
design flow? Can you highlight the features and benefits that set your solution apart from the others?

Wade Smith: In our case, we offer a full Multi-physics Chips to Cities approach. We have
applications that can analyze the dynamic EM fields at the die level all the way to a full city while, at
the same time, taking into effect thermal and mechanical reliability. This is a huge advantage for
applications such as autonomous vehicles, electrification, modern medical designs, aerospace and
defense, IoT, and 5G. We are able to offer methods of analyzing chip package system that can
include a full EM simulation of a die, a package, and a board together to give the best characterization
of how the channel really affects a signal. This can be extremely important for applications such as
power integrity, because now you can characterize what magnitude of SSN that die actually sees (as
opposed to only what is seen only on the board). Also, for signal integrity, having a unified die,
package and board models can provide a better channel model than a piecemealed model, and this
can be especially important for millimeter wave RF signals used in 5G applications, where impedance
discontinuities can really damage a sensitive signal. We also are able to mix CAD environments, so
users can pull in connectors, for example, from an MCAD model and mount them directly on a board in
an ECAD environment. This allows a user to easily modify board parameters, while remaining in an
ECAD environment, around a connector landing to adjust for better signal flow. Multiple boards can be
linked together through connectors, and to top it off, IBIS, IBIS-AMI, SPICE, transient sources,
statistical sources, and others TX/RX components can be added directly to the chip/package/board
model thereby eliminating the need to create a circuit schematic. We also mix solvers in this
environment, so a user can simulate entire sections using a full wave 3D solver, or the user can
choose smaller sections that are more sensitive to 3D signal flow changes, and solve those with a 3D
solver while solving other parts with a 2.5D EM solver. This can dramatically speed up the simulation
time with a minimal degradation in accuracy. To top it all off, we can also mix physics into the
solutions too, so a user can analyze the device with thermal solvers and take into account how
materials will change as devices heat up, for this will affect the signal channel during high speed
operation. As we leave the board, we can get into applications where antenna systems can be
designed and placed into realistic environments, such as cars or cities to figure out how they will
properly communicate in large environments. This helps answer questions plaguing 5G systems such
as “where do I place this picocell to get the best coverage in this urban environment?” or “how is my
link budget affected when my antenna heats up” or “how do I control the beam steering of my MIMO
base station array so it can target track multiple autonomous vehicles simultaneously?”. In addition
to this, we offer electronics multi-physics reliability applications that can assist users in assessing
mean-time-to-failure of their designs in various environments with various thermal and mechanical
stress conditions. In addition, solvers can be linked to large optimization engines that can help study
the effects of fabrication tolerances, materials changes, or geometry manipulations. Lastly, if
applicable, the use of High-Performance Computing can be employed to allow for immense simulation
time speed up. Our goal is to provide the user with the most physically complete and most accurate
signal channel simulation possible, no matter if the channel is just signal lines in a die, or a full 5G
channel that includes an entire city. Ansys can analyze from chips to cities.