Digital Logic and Computer Architecture

Unit-III
 Memory
Memory is required to store:
1. data
2. application programs
3. operating system
 Memory Organization

Registers are used for temporary storage of few bits of data.

For storing bulk of data a memory or storage unit is used.

A memory unit consists of large number of binary storage cells and data is
stored there during data processing.

A memory cell is the smallest amount of information storage, holding
either a 1 or 0. Memory cells are often grouped together to form words.

Besides the large number of memory cells, a memory has a small number
of registers to facilitate storage and retrieval of data from memory and set
of control signals.
 Memory Organization
Desirable Characteristics of Memory cell:
a) It must have stable states.
b) While it is in one of the stable states it should not consume any power. If it does consume
power it must be small so that the total energy dissipated by the memory is small.
c) It should be possible to switch between the two stable states an infinite number of times.
d) The data stored in a cell must not decay with the passage of time.
e) Each binary cell must occupy very little space.
f) The cost of each cell must be low.
g) Time taken to read data from a group of cells or for storing data in them must be small.
h) When power is turned off, the cell should not lose data stored in it.
 Memory Organization

Functions performed on memory are read or write.

In earlier days, magnetic cores were used as the memory elements of main
memory. Principle of magnetization was used for storage.

Now, the computer memory elements are semiconductor devices.

A semiconductor substance lies between the conductor and insulator e,g.
silicon. It controls and manages the flow of electric current in electronic
equipment and devices.

In semiconductor memory flow of current or no flow of current is
responsible for storage.

As its packing density is very high it is suitable for making bulk of memory.
 Memory Organization
Memory Parameters:
A string of bits is called a word. A word is always treated as an
entity and it moves in and out of memory as one unit.
The movement of words in and out of memory is controlled by
signals called write and read signals.
Read and write operations are performed with the help of two
registers -
1)Memory buffer register (MBR)
2)Memory address register (MAR)
 Memory Organization
Memory is divided into number of words. If it is a 16 bit word then it has
16 memory cells.
Word to be written is first entered in MBR. Word read from memory is
also first entered in MBR.
The location in the memory where a word is to be stored is called the
address of the word. To retrieve a word from memory, its address is to be
specified. The address is generated within the computer itself by the
relative address given by the program.
The address is entered in MAR.
After read operation the information is stored in MBR.
 Memory Organization
A memory is an array of m bits
storage locations 0
– Each with a unique address 1
2
• Address is unsigned-binary 3
4
encoded
:
– n address bits ⇒ 2n locations :
• All locations the same size :
-2n × m bit memory 2n-2
2n-1
 Memory Organization
16 bits
word

51
5
1023

MAR
Read
Memory
Control
MBR Write
Block Diagram of a memory
This memory is assumed to store 1024 words(i.e. 1K words) with 16bits
per word.
 Memory Organization
The time interval between the initiation of a read signal and the availability
of the required word in MBR is known as access time of the memory.
The time interval between the initiation of a write signal and the storing of
the word in the specified address in the memory is called the write time of
the memory.
If reading a word from memory is destructive, then it is necessary to write
it back in memory. The time required for this combined read and write
operations is called memory cycle time.
Even if reading from memory is non-destructive the time that should
elapse between two successive references to memory read or write is
larger than the access time. This time is the cycle time of memory.
 Memory Organization
Read / Write time
t0 : address in MAR
t1 : word in MBR
t2 : ready for next access

t0 t1 t2 time

Access Rewrite
time time

Cycle time
 Memory Organization
 Memory systems may be constructed with IC flip-
flops in such a way that the access time is
independent of the address of the word. Such a
memory is known as a random access memory.
 In contrast to this if the binary cells are on the
surface of a magnetic disk, then the access time
would depend on its actual physical location.
 Memory Organization

Volatile memory – Memory system in which
stored data is lost when the power is turned off,
or in which it is lost with elapse of time e.g. a
memory made of IC flip-flops.

Non-volatile memory – Memory in which data is
permanently stored e.g. magnetic disk memory.
 Memory Organization
Semiconductor memory Cell -
In earlier generation computers magnetic cores were used as
the storage elements of the main random access memory of the
computer.
With the rapid development of integrated circuits,
semiconductor storage elements have replaced magnetic
cores.
There are two types of semiconductor storage elements:
1) Dynamic memory cell
2) Static memory cell
 Memory Organization

Dynamic memory cell uses a capacitor  Static memory cell uses a RS flip-flop
to store data. fabricated with transistors to store data.

Memory that is made of dynamic 
Memory that is made of static memory
memory cells is called Dynamic cells is called Static Random Access
Random Access Memory (DRAM). Memory (SRAM).

DRAM cells are slower.

SRAM cells are faster.

Cost per cell is low

Cost per cell is high.

DRAM must be continuously refreshed.

SRAM does not need continuous
refreshing resulting in better
performance and lower power usage
The DRAM is, however, preferred for fabricating main memories as it is
possible to realize an order of magnitude more memory cells per chip
compared to SRAM.
 Memory Organization
Dynamic memory cell function :
Data is stored in capacitors.
It incorporates a transistor T (called a pass transistor) which controls the
charging of a capacitor C. The capacitor can either be charged or
discharged; these two states represent the two values of a bit, 0 and 1.
A cell is selected for writing or reading by applying voltage V to the
address line.
To write a 1 in the cell a voltage V is applied Address line
to the bit/sense line. This switches on T
and C is charged to voltage V. T
If 0 voltage is applied to the bit/sense line
then if C is charged it will discharge
and a 0 is stored. C
Bit/Sense line
 Memory Organization
The capacitor has a very large but finite leakage resistance. Thus the
charge stored in C when a 1 is written can slowly leak away (in a few
milliseconds) and the data will be lost. i.e. after some time charge starts
decaying in capacitor. It is therefore necessary to rewrite the data
periodically. This is called refreshing.
To read a cell, the address line is selected and a voltage V is applied to it.
This switches on the pass transistor T.
If a 1 is stored in the cell, the voltage of the bit/sense line will tend to go up
to V and if a 0 is stored in the cell it will tend to go down to 0.
The direction of change of voltage in the bit/sense line is sensed by the
amplifier. A positive change is taken as a 1 and a negative change as a 0.
The read operation is destructive and a write should follow a read.
 Memory Organization
The capacitor has a very large but finite leakage resistance. Thus the
charge stored in C when a 1 is written can slowly leak away (in a few
milliseconds) and the data will be lost. i.e. after some time charge starts
decaying in capacitor. It is therefore necessary to rewrite the data
periodically. This is called refreshing.
To read a cell, the address line is selected and a voltage V is applied to it.
This switches on the pass transistor T.
If a 1 is stored in the cell, the voltage of the bit/sense line will tend to go up
to V and if a 0 is stored in the cell it will tend to go down to 0.
The direction of change of voltage in the bit/sense line is sensed by the
amplifier. A positive change is taken as a 1 and a negative change as a 0.
The read operation is destructive and a write should follow a read.
 Memory Organization
Static memory cell function :
Data is stored in transistors(a semiconductor device) and requires a
constant power flow. A static RAM will hold its data as long as power is
supplied to it. Because of the continuous power, SRAM doesn’t need to be
refreshed to remember the data being stored. It is used in cache memories.
A static memory cell is a flip-flop. The flip-flop consisting of transistors T 1
and T2 can be in one of the two stable states.
1) One stable state is with T1 conducting and T2 non-conducting.
2) Other is with T2 conducting and T1 non-conducting.
 Memory Organization
1) When T1 is conducting the voltage at
the point P is nearly 0. This voltage is Memory
applied to the base of transistor T2 which cell
V
keeps it switched off. The voltage at Q is
thus at V. In this state the memory
cell is said to be storing a 0. Bit/Sense Bit/Sense
wire P Q wire

B B
0 T3 T1 T2 T4 1

2) When T2 is conducting the voltage at

P would be V (logic 1) and that at Q will
be 0 (logic 0). In this state the memory
cell is said to store a 1.
W Word wire
 Memory Organization
IC Chips for Organization of
RAMs: A0
A12
Millions of memory cells are packaged A A13
A14
into a chip which forms the building !A2 A15
block for the organization of large size A3 A16
RAMs whose capacity can be in the A4
A5
256 K x 1 A17
order of several hundreds of MB or a
few GB. A6 Chip Vcc
Vss
This chip has 24 pins and internally A7
A8 E
contains 256K addressable memory A9
cells. Each of the cells is 1 bit in size D
A10
and is individually addressable. There A11
Q
are 18 address pins to select one out of W
256K cells.
256 K x 1 RAM chip pin out representation
 Memory Organization
Each cell when read or written stores one bit. This memory
chip is packaged as a 24-pin integrated circuit.

Pin Name Functions Pin Name Functions

A0 - A17 Address input Q Data output

E Chip enable Vcc +5V supply
W Write or Read enable Vss Ground
D Data input
 Memory Organization
The truth table for selecting a chip when it is used as a part of a large
memory and for reading and writing. This chip’s access time is around 15
nano seconds.

E W Mode Output Cycle

High Don’t care Not selected High impedence __
Low High Read Data out Read
Low Low Write High impedence Write
 Memory Organization
Write Enable

Data in Draw an abbreviated diagram for an IC

18 chip that has 16-M addressable
Address
elements where each element is a 4-
Data out bit group (half of a byte) of memory
cells i.e. 16 M x 4 chip.

Chip Enable

Abbreviated representation of an IC memory chip.

 Memory Organization
2D Organization :
Let us suppose that we organize a 4 MB memory using the chips 256K x 1. If we
put 8 such chips in a row, each chip contributing one bit of a byte then we can
construct a 256 KB memory system (word size = 8 bits). This 256 KB memory
will need a 18 bit address. The address lines can be fed as A0 to A17 to each of
the 8 chips in a row so as to select one out of 256 K elements.
(4MB = 4 x 1024KB = 4 x 4 x 256 KB = 16 x 256 KB)
Since we need 4 MB memory, sixteen rows can be used together to make up the
total memory.
22
A memory with 4 MB capacity will need a 22-bit address, as 2 = 4MB.
The high order 4 bits of the 22 bit address can then be used to select one out of
16 rows in the memory organization.
 18 18-bit address bus
A
A

Chip Internal
0
R/W

Address
1

1 2 8
18 18 18
A17
A18 R E
Row O
address A W
21

D 9 10 16
E
In a 2D organized C E
memory system O
D
the chips are laid E
out as several 121 122 128
rows and several 2 2 2
Data
columns. E
in out

MBR
 Memory Organization
A 4-bit decoder is used to decode the high order 4-bits of the
MAR.
The decoder output will select one of the 16 rows. The 16
decoder outputs are connected to the 16 rows of chips, one
output for each row.
The decoder will select one out of the 16 rows and all the chips
in the selected row will be enabled for reading or writing.
The 8 bits coming from the 8 chips in the selected row are
routed to the 8 bits of the MBR of this memory system.
 Memory Organization
3D Organization :
It uses one plane to represent one bit of a word.
 Memory Organization

For an n-bit MAR in 2D organization the word lines are linearly selected and hence
n
the number of decoder gates is 2 .
n/2

By contrast, in 3D organization, the number of decoder gates reduces to 2.2 for x
= y = n/2. Such saving in the circuit cost has motivated the designers to design 3D
organized memory cell array.

The n-bit address is divided into two parts having x and y number of bits. For a
n/2
square array, each half is decoded and 2 X and Y drive lines are fed into each
array of bit plane.

For b-bit word memory, there are b number of planes each referring to a bit.

Corresponding to each bit plane there is a sense/write circuit. The read/write
operations in 3D organization is same as to 2D with the modifications that a cell in
a bit plane is selected by activating X and Y drive lines simultaneously, and bit
information is passed through the selected cell in a bit plane.
 Memory Organization

Thus each cell in the array needs 3 terminals – X, Y and bit line connected to
sense/write circuit.

More the number of terminals (wires) through a cell, larger the cell size and
consequently switching speed is less. Also, the design of the overall circuit
becomes very complex.
Commercially available memories are packaged with multiple IC chips on a printed
circuit board in such a way that all the pins form a single line. They are known as
SIMM or single in-line memory module. They can be easily plugged into the
motherboard of a computer system connecting the memory system to the system
bus.

30 pin single in-line memory module (SIMM)

 Memory Organization
Memory Hierarchy:
The memory hierarchy system consists of all storage devices contained in a
computer system.
• Secondary storage
–Stores data and programs that are not actively needed
• Main memory
–Should store currently needed program instructions and data only
• Cache memory
–Extremely high speed
–Usually located on processor itself
–Most-commonly-used data copied to cache for faster access
–Small amount of cache still effective for boosting performance
• CPU registers
–Stores data and instructions during processing.
 Memory Organization
Memory Hierarchy:
Capacity
 Memory Organization
ROM (Read Only Memory):

It is one in which data is permanently stored.

Data stored in ROM can be accessed as fast as in RAM made with similar memory
storage cells.

Writing of data into ROM is impossible after it is stored.

It has higher density of packing memory cells in it.

It is cheaper than RAM.

ROM is a Programmable Logic Device. In ROM the AND array of the PLD is fixed and the
OR array is programmable.

All the 8 minterms corresponding to the 3-bit input bits are generated. It means addressing
8 words in the ROM.

The output bits are programmed by blowing fuses selectively in the OR array.
 Memory Organization
MAR MBR
I2 I1 I0 O3 O2 O1 O0 X X
0 0 0 1 0 1 0 X X X
X X X
0 0 1 0 1 1 1
X X
0 1 0 1 0 1 1
3 8 X X
0 1 1 0 1 1 0 X X
MAR Row
1 0 0 0 1 0 1 Decoder
1 0 1 1 0 0 1 X X X
1 1 0 0 0 0 0 X CMOS gates
1 1 1 1 1 0 1 MDR

Contents of ROM of this figure A 3-bit input, a 4-bit output Read Only Memory (ROM)
 Memory Organization
Types of ROM:
There are 4 types of ROMs-
1) The factory programmed ROM in which the links are placed
during fabrication and cannot be altered later. The data is
stored permanently. It is reliable and least expensive.
2) User programmable ROM (PROM)- In this the factory
supplies the PROM with fusable links. Whenever a 0 is to be
stored, the link may be fused by the user by sending high
current through the link. Once a link is fused it is permanent.
 Memory Organization
3) Ultravoilet Erasable Programmable ROM (UVEPROM)-
This ROM is supplied by the manufacturer with links
which can all be disconnected by shining intense ultra voilet
light. Links can then be grown selectively by the user by
selecting a word and applying voltage on the bit wire. This is
the most flexible ROM.
4) Electrically erasable and reprogrammable (EEPROM)-
This is also known as a writable control store and is
used to store microprograms of the control units of CPUs.
 Memory Organization
Applications of ROMs:
They are very useful in designing digital systems.

Code converter- ROMs for common code conversions such as NBCD code to
7-segment display code are readily available. In general, a ROM with an n-bit
MAR and m-bit MBR can realize any n input, m output combinational circuit.

Function generators- Tables for commonly used functions such as sine,
cosine, and arctangent may be stored in ROMs. The arguments are entered in
MAR and the function values appear in the output register.

Character generators- Character displays in DOT matrix form use ROMs for
decoding and activating the display.

In microcomputers ROMs are used to store programs, particularly those which
are for dedicated applications, such as washing machines, motor cars, etc.
 Memory Organization
Flash Memory:

It is a non-volatile memory chip used for storage and for transferring
data between a personal computer (PC) and digital devices.

It has the ability to be electronically reprogrammed and erased.

Flash memory is a distinct type of EEPROM, which is programmed and
erased in large blocks.

Flash memory uses special CMOS transistor (which has a second gate
called a floating gate) to store data. Floating-gate transistor(FGMOS) is
capable of holding an electrical charge in a memory device that is used
to store data. Use of this special CMOS gate makes flash memory non-
volatile and allows erasing and re-writing almost a million times.
 Memory Organization
Flash Memory:

A flash memory device typically consists of one or more flash memory
chips (each holding many flash memory cells), along with a separate
flash memory controller chip.

Flash memory has fast read access time, but it is not as fast as static
RAM or ROM.

It is highly suitable for use in mass-storage devices, such as USB
flash drives, memory cards and solid-state drives (SSD). These
devices store data using multiple flash memory chips.
 Memory Organization
High Speed Memories:
 Cache Memory
 Associative Memory
 Memory Interleaving
 Memory Organization
Cache Memory:

Cache Memory is a special very high-speed memory. It is used to speed up and
synchronize with high-speed CPU.

Cache memory is more costly than main memory or disk memory but economical
than CPU registers.

Cache memory is an extremely fast memory type that acts as a buffer between RAM
and the CPU.

It holds frequently requested data and instructions so that they are immediately
available to the CPU when needed.

It is located closer to a processor core and stores copies of the data from frequently
used main memory locations.

A memory cache, is made of high-speed static memory cells (SRAM).

A cache memory is maintained by a special processor subsystem called cache
controller.
 Memory Organization
Structure of Cache Memory
 Both the cache and the main memory are divided into small blocks of equal sizes.
 16 words to 128 words per block are normally used.
 Data is moved between the cache and the main memory in integral number of blocks.
 A block of words stored and retreived from the cache is termed as cache line.
 The structure of the cache memory is formed by grouping all these blocks together into
cache sets.
Mapping Techniques for Cache Memory
The mapping techniques are used to determine how the memory blocks are
mapped to cache blocks. The following three types of cache mapping techniques
are commonly used −
 Direct Mapping − Direct mapping is a simple cache mapping technique in
which each memory block is mapped into a certain cache block. Although, this
technique can lead to a high rate of conflicts.
 Fully Associative Mapping − In this mapping technique, each memory block
can be placed in any cache block, hence this technique has high flexibility.
However, it requires additional hardware.
 Set Associative Mapping − This mapping technique is a combination of direct
and fully associative mappings. In this technique, the cache memory is divided
into cache sets, and each memory block can be placed in any cache block
within its corresponding cache set.
Direct Mapping
In direct mapping, the cache consists of
normal high-speed random-access memory.
Each location in the cache holds the data, at
a specific address in the cache.

This address is given by the lower
significant bits of the main memory
address. This enables the block to be
selected directly from the lower significant
bits of the memory address.

The remaining higher significant bits of
the address are stored in the cache with
the data to complete the identification of
the cached data.
Direct Mapping
Whenever the memory is referenced, the following sequence of events occurs

The index is first used to access a word in the cache.

The tag stored in the accessed word is read.

This tag is then compared with the tag in the address.

If two tags are same this indicates cache hit and required data is read from
the cache word.

If the two tags are not same, this indicates a cache miss. Then the reference
is made to the main memory to find it.
In direct mapping, the corresponding blocks with the same index in the main
memory will map into the same block in the cache, and hence only blocks with
different indices can be in the cache at the same time. It is important that all
words in the cache must have different indices. The tags may be the same or
different.
Fully associative mapping
 In fully associative type of cache memory, each location in cache stores both
memory address as well as data. Let us suppose that there are N locations.
 Whenever a data is requested, the incoming memory address a simultaneously
compared with all stored addresses using N different comparators.
 If a match is found, the corresponding block is read out. Otherwise, the main memory
is accessed if address is not found in cache.

 It is considered to be the fastest

and most flexible mapping form but
costly.

 Fully associative mapping provides

complete freedom in placing a MB
into a CB whereas direct mapping
provides no freedom at all.
Set Associative Mapping - Set associative mapping is a combination of both the
direct mapping and fully associative mapping.
In set associative mapping a cache is
divided into a set of blocks. The number
of blocks in a set is known as
associativity or set size. Each block in
each set has a stored tag. This tag
together with index completely identify
the block.
Thus, set associative mapping allows a
limited number of blocks, with the same
index and different tags.
An example of four way set associative
cache having four blocks in each set is
shown in the following figure.
Set Associative Mapping
In this type of cache, the following steps are used to access the data from a
cache:

The index of the address from the processor is used to access the set.

Then the comparators are used to compare all tags of the selected set
with the incoming tag.

If a match is found, the corresponding location is accessed.

If no match is found, an access is made to the main memory.
Suppose that memory has 4096 blocks and cache memory has 16 sets with
four blocks per set. Then 256 memory blocks can be mapped into one set.
The mapping resembles direct mapping. But the 256 MB mapped into one
set can be placed into any of its CB namely CB0, CB1, CB2, or CB3. In this
way it resembles associative mapping.
Types of Cache –
1) Primary Cache (L1 cache)
A primary cache is always located on the processor chip. This cache is small and its
access time is comparable to that of processor registers.
2) Secondary Cache (L2 cache)
Secondary cache is placed between the primary cache and the main memory. Often,
the Level 2 cache is also housed on the processor chip. It is larger and slower then
L1.
Cache Replacement Algorithms

When a memory block is required to be accessed into a cache block that is already
occupied, then a cache replacement algorithm is needed to determine which memory
block should be replaced to free up space in the cache memory for the new memory
block.
The following three are the common cache replacement algorithms −
➢ First-In First-Out (FIFO) Algorithm − This algorithm replaces the memory block that
exists in the cache memory the longest.
➢ Least Recently Used (LRU) Algorithm − This algorithm replaces the memory block
that has been fetched least recently.
➢ Random Replacement (RR) Algorithm − This algorithm replaces any memory block
randomly.
 Memory Organization
Associative Memory:

It is a content-addressed( rather than location addressed) storage which has a
cycle time much faster than primary storage.

This type of memory is accessed simultaneously and in parallel on the basis of
data content rather than by specific address or location.

It is a special type of memory that is optimized for performing searches through
data, instead of providing a simple direct access to the data based on the
address.

It is a semi-conductor memory.

Associative storage is deigned to search its entire memory in a single
operation.

It is much faster than RAM.

It has its own comparison circuit to detect a match in searching process.

Additional circuit increases its size which increases its cost and increases power
dissipation since every comparison circuit is active on every clock cycle. It is
used in high speed searching applications.
 Memory Organization

When a write operation is performed on associative memory, no
address or memory location is given to the word. The memory itself
is capable of finding an empty unused location to store the word.


On the other hand, when the word is to be read from an associative
memory, the content of the word, or part of the word, is specified.
The words which match the specified content are located by the
memory and are marked for reading.
Associative Memory:
Memory Organization

It consists of memory array and logic for m words with
n-bits per word, and registers.

The argument register (A) and key register (K) each
have n-bits per word.

The key register (K) provides a mask for choosing a
particular field or key in the argument word.

The match register M consists of m bits, one for each
memory word.

The words which are kept in the memory are compared
in parallel with the content of the argument register.

The words match with the word stored in the argument
register set corresponding bits in the match register.

Therefore, reading can be accomplished by a
sequential access to memory for those words whose
corresponding bits in the match register have been set.
The key register provides a mask or identifying piece of information
which specifies how the reference to memory is made.

Example:
Register A 101 10101
Register K 101 00000

Word1 in memory 100 10101 No match

Word2 in memory 101 10111 Match

 Memory Organization
 A bit Aj in the argument register is compared with all the bits in
column j of the array provided that Kj = 1. This process is done for all
columns j = 1, 2, 3......, n.

If a match occurs between all the unmasked bits of the argument and
the bits in word i, the corresponding bit Mi in the match register is set
to 1. If one or more unmasked bits of the argument and the word do
not match, Mi is cleared to 0.

In general, the instructions which are available in a special kind of
memories like cache, ROM and Virtual memory are addressed by
content and not by address location.
Match Logic
First, we neglect the key bits and compare the argu­ment in A with the bits
stored in the cells of the words.
Word i is equal to the argument in A if Ai = Fij for j = 1, 2, . . . , n . Two bits are
equal if they are both 1 or both 0. The equality of two bits can be expressed
logically by the Boolean function
Xj = AiFij+Ai‘Fij’
where xi = 1 if the pair of bits in position j are equal; otherwise, xi = 0.
For a word i to be equal to the argument in A we must have all xi
variables equal to 1. This is the condition for setting the corresponding match bit
Mi to 1. The Boolean function for this condition is
Mi = x 1 x 2 x 3 . . . x n
and constitutes the AND operation of all pairs of matched bits in a word.
We now include the key bit Kj in the comparison logic. The requirement is that if Kj = 0,
the corresponding bits of Aj and Fij need no comparison.
Only when Kj = 1 must they be compared. This requirement is achieved by ORing each
term with Kj’, thus:

{
xj if Kj = 1
x j + K j' =
1 if Kj = 0
When Kj = 1, we have Kj‘ = 0 and xj + 0 = xj . When Kj = 0, then Kj‘= 1 and
Xj + 1 = 1.
A term (xj + Kj’) will be in the 1 state if its pair of bits is not compared. This is necessary
because each term is ANDed with all other terms so that an output of 1 will have no
effect. The comparison of the bits has an effect only when Kj = 1 .
The match logic for word i in an associative memory can now be expressed
by the following Boolean function:
Mi = (x1 + K1’ )(x2 + K2’)(x3 + K3’ ) · · · (xn + Kn’ )
Each term in the expression will be equal to 1 if its corresponding Kj = 0
 Memory Organization
Advantages of Associative memory :-

It is used where search time needs to be less or short.

It is suitable for parallel searches.

It is often used to speedup databases.

It is used in page tables used by the virtual memory and used in neural
networks.
Disadvantages of Associative memory :-

It is more expensive than RAM.

Each cell must have storage capability and logical circuits for matching its
content with external argument.
 Memory Organization
Memory Interleaving:
It is a Technique which divides memory into a number of modules such that
Successive words in the address space are placed in the different modules.

Memory interleaving is a concept which divides the main memory into a
number of modules or banks with each module interacting with processor
independent of others.

Successive words in the address space are placed in the different modules.

Each memory module has its own memory address register and data
register. Memory Address Register(AR) is connected with common
unidirectional memory bus and data register(DR) is connected with
common data bus.
 Memory Organization
Memory
Interleaving:
 Memory Organization
Memory Interleaving:
How does CPU determines in which memory bank or module data resides?
To understand this scenario, we take an example of a two way interleaved
memory.

In this, main memory is divided into two modules in such a way that all
the positive addresses are in first module and rest all odd addresses are
in second module.

So, all the positive addresses go to first module and so on. We can also
say that, least significant bit of the memory address specifies the address
of the module.

That is if LSB is 0, first module is selected and if LSB is 1, second module
is selected.
 Memory Organization

If it is a four way interleaved memory then least two significant bits of
memory address is used to specify the memory module.

When CPU requests a data, it sends the address to memory via
common memory bus. The address is saved in the memory address
register. The data is retrieved from module and kept in data register,
from where it is sent to the CPU via common data bus.