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IC 555 Timer

The 555 timer combines a relaxation oscillator, two comparators, an R-S flip-flop, and a discharge capacitor. It produces accurate timing pulses by charging and discharging the capacitor. The flip-flop switches states based on the comparator outputs to produce a high or low output. In astable mode, external resistors and a capacitor determine the timing of the high and low output pulses.

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24 views6 pages

IC 555 Timer

The 555 timer combines a relaxation oscillator, two comparators, an R-S flip-flop, and a discharge capacitor. It produces accurate timing pulses by charging and discharging the capacitor. The flip-flop switches states based on the comparator outputs to produce a high or low output. In astable mode, external resistors and a capacitor determine the timing of the high and low output pulses.

Uploaded by

aditya pandey
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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555 Timer Basics:

The 555 timer combines a relaxation oscillator, two comparators, an R-S flip-
flop, and a discharge capacitor.

S-R-Flip Flop

As shown in the figure, two transistors T1 and T2 are cross-coupled. The


collector of transistor T1 drives the base of transistor T2 through the resistor Rb2.
The collector of transistor T2 drives the base of transistor T1 through resistor
Rb1. When one of the transistors is in the saturated state, the other transistor will
be in the cut-off state. If we consider the transistor T1 to be saturated, then the
collector voltage will be almost zero. Thus there will be a zero base drive for
transistor T2 and will go into cut-off state and its collector voltage approaches
+Vcc. This voltage is applied to the base of T1 and thus will keep it in
saturation.
S-R Flip Flop Symbol

Now, if we consider the transistor T1 to be in the cut-off state, then the collector
voltage of T1 will be equal to +Vcc. This voltage will drive the base of the
transistor T2 to saturation. Thus, the saturated collector output of transistor T2
will be almost zero. This value when fed back to the base of the transistor T1
will drive it to cut-off. Thus, the saturation and cut-off value of any one of the
transistors decides the high and low value of Q and its complement. By adding
more components to the circuit, an R-S flip-flop is obtained. R-S flip-flop is a
circuit that can set the Q output to high or reset it low. Incidentally, a
complementary (opposite) output Q is available from the collector of the other
transistor. The schematic symbol for a S-R flip flop is also shown above. The
circuit latches in either the Q state or its complimentary state. A high value of S
input sets the value of Q to go high. A high value of R input resets the value of
Q to low. Output Q remains in a given state until it is triggered into the opposite
state.
The internal resistors act as a voltage divider network, providing (2/3)Vcc at the
non-inverting terminal of the upper comparator and (1/3)Vcc at the inverting
terminal of the lower comparator. In most applications, the control input is not
used, so that the control voltage equals +(2/3) VCC. Upper comparator has a
threshold input (pin 6) and a control input (pin 5). Output of the upper
comparator is applied to set (S) input of the flip-flop. Whenever the threshold
voltage exceeds the control voltage, the upper comparator will set the flip-flop
and its output is high. A high output from the flip-flop when given to the base of
the discharge transistor saturates it and thus discharges the transistor that is
connected externally to the discharge pin 7. The complementary signal out of
the flip-flop goes to pin 3, the output. The output available at pin 3 is low.
These conditions will prevail until lower comparator triggers the flip-flop. Even
if the voltage at the threshold input falls below (2/3) VCC, that is upper
comparator cannot cause the flip-flop to change again. It means that the upper
comparator can only force the flip-flop’s output high.

To change the output of flip-flop to low, the voltage at the trigger input must
fall below + (1/3) Vcc. When this occurs, lower comparator triggers the flip-
flop, forcing its output low. The low output from the flip-flop turns the
discharge transistor off and forces the power amplifier to output a high. These
conditions will continue independent of the voltage on the trigger input. Lower
comparator can only cause the flip-flop to output low.

From the above discussion, it is concluded that for the having low output from
the timer 555, the voltage on the threshold input must exceed the control voltage
or + (2/3) VCC. This also turns the discharge transistor on. To force the output
from the timer high, the voltage on the trigger input must drop below +(1/3)
VCC. This turns the discharge transistor off.

A voltage may be applied to the control input to change the levels at which the
switching occurs. When not in use, a 0.01 nano Farad capacitor should be
connected between pin 5 and ground to prevent noise coupled onto this pin from
causing false triggering.
Connecting the reset (pin 4) to a logic low will place a high on the output of
flip-flop. The discharge transistor will go on and the power amplifier will output
a low. This condition will continue until reset is taken high. This allows the
synchronization or resetting of the circuit’s operation. When not in use, reset
should be tied to +VCC.

555 Timer Astable Multivibrator Circuit Diagram

An Astable Multivibrator can be designed by adding two resistors (RA and RB


in circuit diagram) and a capacitor (C in circuit diagram) to the 555 Timer IC.
These two resistors and the capacitor (values) are selected appropriately so as to
obtain the desired ‘ON’ and ‘OFF’ timings at the output terminal (pin 3). So
basically, the ON and OFF time at the output (i.e the ‘HIGH’ and ‘LOW’ state
at the output terminal) is dependent on the values chosen for RA,RB and C. We
will see more about this on the astable multivibrator design section given below.

Note:- The capacitor C2 (0.01uF) is connected to pin number 5 (Control


Voltage Terminal) in all 555 IC based circuits in which that particular pin (pin 5
– control voltage terminal)is not used. This capacitor is used to avoid noise
problems that could arise in the circuit if that pin is left open.
A monostable multivibrator (MMV) often called a one-shot multivibrator, is a
pulse generator circuit in which the duration of the pulse is determined by the
R-C network,connected externally to the 555 timer. In such a vibrator, one state
of output is stable while the other is quasi-stable (unstable). For auto-triggering
of output from quasi-stable state to stable state energy is stored by an externally
connected capacitor C to a reference level. The time taken in storage determines
the pulse width. The transition of output from stable state to quasi-stable state is
accomplished by external triggering. The schematic of a 555 timer in
monostable mode of operation is shown in figure.

555-timer-Monostable-multivibrator

Pin 1 is grounded. Trigger input is applied to pin 2. In quiescent condition of


output this input is kept at + VCC. To obtain transition of output from stable state
to quasi-stable state, a negative-going pulse of narrow width (a width smaller
than expected pulse width of output waveform) and amplitude of greater than
+ 2/3 VCC is applied to pin 2. Output is taken from pin 3. Pin 4 is usually
connected to + VCC to avoid accidental reset. Pin 5 is grounded through a 0.01 u
F capacitor to avoid noise problem. Pin 6 (threshold) is shorted to pin 7. A
resistor RA is connected between pins 6 and 8. At pins 7 a discharge capacitor is
connected while pin 8 is connected to supply VCC.

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