Aircraft Data Network and

Avionics Integration
-ARINC 664 and IMA Integration: Part 1

Dr H. Jia
Department of Aerospace Engineering
Cranfield University
25 January 2021
 IMA Terminology
• Aircraft Function
– The capability of the aircraft that may be provided by the
hardware and the software of the systems on the aircraft;
• Application
– software and/or application-specific hardware with a defined set
of interfaces that, when integrated with the platform, performs a
function
• Component
– A self-contained hardware, software part, database or
combination thereof that is configuration controlled. A
component does not provide an aircraft function by itself;
• Core Software
– The operating system and support software that manage IT resources
to provide an environment in which applications are executed. Core
Software is a necessary component of the platform which typically
consists of one or more modules;
© Dr H.Jia 2 25-Jan-21
 IMA Terminology
● IMA Module
– A component or collection of components that may be accepted by
themselves or in the context of IMA. A module may also comprise other
modules. A module may be software, hardware, or a combination of
hardware and software, which provides resources to the IMA-hosted
applications. Modules may be distributed across the aircraft or may be
co-located;
● IMA Platform
– Module or group of modules, including core software, which manages
resources in a manner sufficient to support at least one application. IMA
hardware resources and core software are designed and managed in a
way that provides computational, communication and interface
capabilities for hosting at least one application. Platforms by themselves
do not provide any aircraft functionality. The IMA platform may be
accepted independently of hosted applications.
● IMA System
– It consists of (an) IMA platform(s) and a defined set of hosted
applications;
© Dr H.Jia 3 25-Jan-21
 IMA Terminology
• Incremental acceptance
– A process for obtaining credit towards approval and certification by
accepting or finding that an IMA module, application, and/or off aircraft
IMA system complies with specific requirements.
– This incremental acceptance is divided into tasks. Credit granted for
individual tasks contributes to the overall certification goal. Incremental
acceptance provides the ability to integrate and to accept new
applications and/or modules in an IMA system and to maintain existing
applications and/or modules without the need for reacceptance;
• Interoperable
– The capability of several integrated modules to operate together to
accomplish a specific goal or function. This requires defined interface
boundaries between the modules and allows the use of other
interoperable components. To describe this concept in physical terms,
an IMA platform may include interoperable modules and components,
such as physical devices (processor, memory, electrical power,
Input/Output (I/O) devices), and logical elements, such as an operating
system, and communication software;

© Dr H.Jia 4 25-Jan-21
IMA System Design
 IMA System Development
• Analyse and define requirements for IMA
systems Aircraft Level

Aircraft-Level Decomposed &

IMA Systems Develop
IMA Systems IMA System
Requirements Allocated to Requirements Level

IMA Platform
Level

IMA System Development

LRM Level

RTCA RTCA RTCA

ARINC 653 ARINC 664 ARINC 651 ARINC 659
DO-297 DO-254 DO-178C

© Dr H.Jia 6 25-Jan-21
 Modern AND: In the late 1990s, open integrated
modular avionics (IMA)
Open IMA with AFDX 1 3

In 2001, the Hercules C-130 Aircraft

Modernization Program (AMP) was
announced. The program is widely
regarded as the first truly integrated 2
modular avionics (IMA) 4

Display-2 Sensor-2 Actuator-2

● Common Core System (CCS)
● Faster avionics data buses ARINC 664/AFDX
IMA
Computing
Platform-2 Sensor-1
Sensor-3
IMA Switch IMA
Computing Computing Actuator-1
Actuator-3
Platform-3 Platform-1

Display-3 Display-1

© Dr H.Jia 7 25-Jan-21
 IMA Architecture Design
IMA Software Architecture

Partition 1 Partition 2 Partition 3

Application Programme Interface
Real Time Operating System
Partitioning, Scheduling, health
Motoring Platform
Hardware

LRM (Avionics Computer)

FMS Air Data Display
F-n
IMA Box
API RTOS Partition
Core Processor
End System (ES)
Redundant Backplane
ES LRM Buses, e.g. VME, cPCI

© Dr H.Jia 8 25-Jan-21
 Typical ARINC 653 Architecture
● Support Various Applications

© Dr H.Jia 9 25-Jan-21
Typical ARINC 653 Architecture

© Dr H.Jia 10 25-Jan-21
 IMA Software Architecture
• An example of ARINC 653 RTOS, VxWorks 653

Flight Control Navigation Graphics Generator Display

User (FC) Application Application Application Application Thread
Mode Level A Level B Level C Level D Scheduling
ARINC 653 POSIX VxWorks Ada/C++ Only
Partition OS Partition OS Partition OS Partition OS

Partition
Scheduling
VxWorks 653
XML Configuration Data Only
Application Executive
Kernel
Mode Board Support Package
Architecture Support Package (ASP)
(BSP)

Hardware

© Dr H.Jia 11 25-Jan-21
 IMA Design
● IMA racks are connected via AFDX network
● Airborne sensors can be shared by various avionics functions

© Dr H.Jia 12 25-Jan-21
 Modular Open
System Approach

power

Processor

Control I/O

© Dr H.Jia 13 25-Jan-21
 IMA Frame
• FAA TSO-C153/ETSO 2C153 define the basic IMA
modules in IMA
– CLASS RH: Rack Housing CLASS DS : Data Storage
CLASS IF : Interface
– CLASS PR : Processing
CLASS PS : Power Supply
– CLASS GP : Graphical Processing CLASS DH: Display Head

Rack
2C153
Class RH
LRM 1

LRM 2

LRM 4

LRM 5

LRM 3
2C153 2C153 Non ESTO 2C153 2C153
Class PR+IF Class GP Module Class DS Class PS

© Dr H.Jia 14 25-Jan-21
 A Typical AFDX/IMA System
• IMA avionics application systems
• Switches
• End System
B1 B2 A3 C1 C2 C3 G1 G2 G3 H1 H2 H3

ARINC 653 OS ARINC 653 ARINC 653 ARINC 653

A1 A2 A3 I1 I2 I3

ARINC 653 ARINC 653

ARINC 664
Network

D1 D2 D3
K1 K2 K3
ARINC 653
ARINC 653

E1 E2 E3 F1 F2 F3 L1 L2 L3 J1 J2 J3

ARINC 653 ARINC 653 ARINC 653 ARINC 653

© Dr H.Jia 15 25-Jan-21
AFDX/ARINC 664:
Basic Frame
 AFDX/ARINC 664
• ARINC 664 implements some layers of IEEE 802.3
Open Systems Interconnection (OSI) Reference Model
Application
Application 1 Applicaiton 2 Application 3 User Applicaitons
Ports
Application Protocol
API
Data Unit

APEX Service L7 Network Application

BSD APEX Protocol

API Data Unit
Transport
TCP
Ports UDP Services L4 Transport
Services
Transport Protocol
Data Unit

IP Services L3 Network
Network Protocol
Data Unit
MAC Services MAC Services
L2 MAC
Network 1 Network 2

PHY 1 PHY 2 L1 PHY

MAC/Ethernet Frame

© Dr H.Jia 17 25-Jan-21
 ARINC 664 Physical View
• The peer-to-peer relationship
Network 1
T11 T13

Avionics Sub System

(Sender)
Switch
AFDX
T12 Hub 1 T14 End System

AFDX Switch AFDX Switch

Router

AFDX AFDX
End System End System
T21 Switch T23
Hub 2 Sub System (Receiver) Sub System (Receiver)

T22 T24
Network 2

© Dr H.Jia 18 25-Jan-21
 ARINC 664 Physical View
• AFDX 664 Topology

© Dr H.Jia 19 25-Jan-21
 AFDX/664 Frame
• The AFDX frame format is compliant with IEEE Std 802.3 (Ethernet).
• AFDX frame length can vary from 64 to 1518 bytes (plus a 7-byte
frame preamble, frame start byte, and 12-byte inter-frame gap
(IFG), with a data payload between 1 and 1471 bytes (payload must
be padded to a minimum length of 17 bytes).
64 bytes (frame) + 7 bytes (Preamble) + 1 byte (SFD) + 12 bytes (IFG) =
84 bytes to transmit at 100 Mbits/s.

MAC MAC
Destination Source
Address Address

© Dr H.Jia 20 25-Jan-21
 AFDX/664 Frame
• Preamble - A seven octet field used to allow the physical
layer signalling (PLS) circuitry to achieve steady-state
synchronization with the received timing frame, 10101010.
• Start Frame Delimiter - A fixed sequence of bits that
indicate the start of a frame, 10101011.
• MAC Destination Address - The length is 48 bits
(consistent with the Source Address length). The first
(least significant) bit distinguishes between an individual
or group address. The second bit distinguishes between
locally or globally administered addresses.
• MAC Source Address - The length is 48 bits (consistent
with the Destination Address length). The first bit is
reserved and set to zero. The second bit distinguishes
between locally or globally administered addresses.
© Dr H.Jia 21 25-Jan-21
 AFDX/664 Frame
• Length/Frame Type – This two octet field has two meanings, depending on
its numeric value. If the value is less than 1536 decimal, it indicates the
number of Logical Link Control data octets in the data field (used by OSI
protocol stacks). If the value is greater than or equal to 1536 decimal, the
number indicates the MAC client protocol. This is known as the type field
common in Internet Protocol (IP) and other non-OSI stack networks.
• Data and Pad (payload)- User data as a sequence of octets. Full
transparency is provided so that any arbitrary sequence of bits can occur. If
the number of octets in the packet is less than the minimum required to
ensure sufficient propagation and collision detection times, a pad field is
added to the end of the data field.
• Frame Check Sequence (FCS) - The FCS field contains a 32 bit Cyclic
Redundancy Check (CRC) value. The transmit and receive algorithms each
generate CRC values which are then compared.

© Dr H.Jia 22 25-Jan-21
 AFDX/664 Frame
• MAC Destination Address

• MAC Source Address

© Dr H.Jia 23 25-Jan-21
 AFDX/664 End System Tx
• Transmitting
Channel

© Dr H.Jia 24 25-Jan-21
 AFDX/664 End System Rx
• Receiving
Channel

© Dr H.Jia 25 25-Jan-21
 AFDX/ARINC 664:
Switch and End System
 FADX/664 Switch
• Main AFDX Switch Functions

Data Packages Data Packages

Switch
from/to ES from/to ES
· Receive data packages from
all ESs and check data
Data Packages integrity Data Packages
from/to ES · Transmit the received data to from/to ES
destination ESs according the
destination addresses
Data Packages Data Packages
· Manage configuration table
from/to ES from/to ES

© Dr H.Jia 27 25-Jan-21
 FADX/664 Switch
• Main Functional Blocks of the AFDX Switch

End System

Configuration Monitoring
Tables Function
Switching Function
Filtering and
Policing Function

© Dr H.Jia 28 25-Jan-21
 AFDX/664 Switch
• Functional Blocks of the AFDX Switch
Sub System (Receiver)
AFDX
End System

Rx Buffer Tx Buffer Rx Buffer Rx Buffer

Tx Buffer Rx Buffer Tx Buffer Tx Buffer

AFDX AFDX
Processing Processing
Unit Switch Unit Switch

Rx Buffer Forwarding Rx Buffer Forwarding

Configuration Configuration
Tx Buffer Table Tx Buffer Table

© Dr H.Jia 29 25-Jan-21
 AFDX Switch
The switch is a heart of an AFDX network
AFDX Switch
Architecture
● Each port comprises two twisted pairs
— one pair for transmit (Tx) and one
pair for receive (Rx).
● The Rx and Tx buffers are both
capable of storing multiple incoming/
outgoing packets in FIFO order.
● AFDX packages contains destination
address.
● The CPU read the packages to
determine its destination address, and
moves packets from the incoming Rx
buffers to the outgoing Tx buffers.
● Switch has Forwarding Table to
determine which Tx buffers are to
receive the packet.

2
3

Full-duplex Switched Ethernet eliminates

the possibility of transmission collisions

© Dr H.Jia 30 25-Jan-21
 Network Integrity
⚫ End-to-end data
integrity
– CRC,
– message sequence,
– message structure,
– identity checks
⚫ Determinism is
assured by the switch.
⚫ End nodes are integral
part of the global
network integrity

© Dr H.Jia 31 25-Jan-21
 AFDX End System
End-System Architecture

IP & UDP Layers

Integrity Checking
MAC Detection and elimination
Layer Redundancy Mag. Applications
of invalid frames
Elimination of
Integrity Checking
MAC redundant frames Network mag.
Detection and elimination
Layer
of invalid frame

Dual Redundant Connect Arriving message is

appended to the queue
Tx End- Network A Rx End-
System Network B System
M1
M2 Queuing Port at Receiver
Arriving message Message 1 Application reading a
overwrites the message from the port M3
current message Freshness does not remove the Application reading a
stored in the Indicator message message from the port
remove the message
Sampling Port at Receiver

© Dr H.Jia 32 25-Jan-21