Synopsys EDA Tool Flow for

Front-End Digital IC Design

Professor: Sci.D., Professor

Vazgen Melikyan

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Synopsys EDA Tool Flow for Front-End Digital IC Design
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Course Overview

 Digital Design Flow

 2 lectures
 Logic Simulation
 2 lectures
 Logic Synthesis
 4 lectures
 Formal Verification
 4 lectures
 Static Timing Analysis
 4 lectures

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Synopsys EDA Tool Flow for Front-End Digital IC Design
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Digital Design Flow

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Semiconductor Chips Usage

 Semiconductor chips are used in:

 Computers
 Cellular phones
 iPADs
 iPhones
 Gaming systems
 DVD players, TVs
 Watches
 Cars
 Medical devices
 Pacemakers and coffee pots
 Space stations
 Greeting cards
 ...

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Synopsys EDA Tool Flow for Front-End Digital IC Design
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Phases of IC Design

Specification Design process IC design Manufacturing

IC
process

9 bit  resolution  10
bit

18 MHz  conversion
rate  30 MHz

18 MHz  clock
frequency  30 MHz

Integral nonlinearity 
1 LSB

. . . . . . . .

Circuit Layout Other data

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Design Levels

System

Add

Input
Accumulator Register-Transfer Level
Command Register (RTL)
+1
Command Counter

& &
1 Gate Level
J TT
C
K
(Logic circuit)

Circuit Level
(Schematic)

Layout
n+

p
n +

n
+
p

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Design Flow Concept
Data from the
Specification previous level

Level 1

Design steps Design

Level 2

no Meets the Verification

spec?

yes
Level n
Next level

Completed
Design

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Types of Design

 Automated
 All design problems are formalized
 Not fully Automated (Custom)
 A part of design problems is formalized,
and some problems are unformalized

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Digital IC Synthesis
Circuit
description
y : output;
a,b,c,d,e : input; Standard cells
y= (a+b)*(c^d)*e; AND

OR

Synthesis
Design rules

Min spacing = 0,2u

Min width = 0,3u

a
b y
c
d
e
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Basics of Digital IC Design
y=(a+b)&(c⊕d)&e
RTL design

y : output;
Circuit description a,b,c,d,e : input;
y= (a+b)*(c^d)*e;

Design
Logic Synthesis Compiler Standard cells
a AND
Logic Circuit b y
c OR
IC d
Physical Synthesis
Compiler e
Layout of finished
design

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Synopsys EDA Tool Flow for Front-End Digital IC Design
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Digital Design Flow
Specification

Cell description coding

Digital Design Flow
Logic  Starts at RTL level and
simulation

Logic Synthesis
end with layout
Formal
 Only design description
Verification
(RTL) is created manually
Static Timing
Analysis (STA)  All other levels of design
Physical Synthesis
are synthesized
Physical  Used for digital ICs
Verification

Static Timing
Analysis (STA)

Finished design

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Specification
Specification
Specification is the list of goals that should be achieved
Cell description coding
in the given design.
Logic
simulation
Specification
Logic Synthesis
Design Description
Formal Circuit must turn lights when a button is pressed, or ask for recharge
Verification if battery charge is low
N0 Parameter description Min Typ Max Units
Static Timing
Analysis (STA) 1. Process 3.3V IO devices in TSMC 0.11
2. Voltage 1.08 1.2 1.32 V
Physical Synthesis 0C
3. Temperature -40 125
Physical
4. Power Dissipation 100 mW
Verification
5. Die Area 2 um2
Static Timing
Analysis (STA) 6. Clock frequency 1GHz
…. …. …. …. …. ….
Finished design

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Design Description
Specification
Design description (behavior) must be translated to
Cell description coding Hardware Description Language (HDL) understandable
Logic
by EDA tools.
simulation
Specification
Logic Synthesis
Design Description
Formal Circuit must turn lights when a button is pressed, or ask for recharge
Verification if battery charge is low
N0 Parameter description Min Typ Max Units
Static Timing
Analysis (STA) 1. Process 3.3V IO devices in TSMC 0.11
2. Voltage 1.08 1.2 1.32 V
Physical Synthesis
3. Temperature if-40button1_pressed
125 0C

Physical if (battery_charge > 10)

Verification 4. Power Dissipation 100 mW
turn_on_light();
5. Die Area 2 um2
else
Static Timing
Analysis (STA) 6. Clock frequency prompt_for_recharge();
1GHz
…. …. …. …. …. ….
Finished design

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Logic Simulation
Specification

Cell description coding

Logic
simulation

Logic Synthesis

Formal
Verification

Static Timing
Analysis (STA)

Physical Synthesis

Physical
Verification

Static Timing
Analysis (STA)

Finished design

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Logic Synthesis
Specification
Standard
Cell description coding RTL
cells
Logic
y : output; AND
simulation
a,b,c : input;
Logic Synthesis y= (a+b)*c;
OR
Formal
Verification
Logic
Static Timing
Analysis (STA) Synthesis
Physical Synthesis
Logic Circuit
Physical
Verification a
b
Static Timing c
Analysis (STA)

Finished design

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Formal Equivalence Check
Specification Formal verification checks that two
Cell description coding different levels of design implement the
Logic same function
simulation

Logic Synthesis RTL Logic Circuit

Formal y : output; a
Verification a,b,c : input; b
y= (a+b)*c; c
Static Timing
Analysis (STA)

Physical Synthesis Formal

Physical
Equivalence
Verification Check
Static Timing
Analysis (STA)
Equivalent
Finished design Yes/No ?

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Static Timing Analysis (STA)
Specification
Total delays of every path is calculated using
Cell description coding
delays of separate gates.
Logic
O=max[sum(B,D22),sum(C,D21)]
simulation
C D21
Logic Synthesis
D22 O
A
Formal
D1
Verification B=sum(A,D1)

Static Timing
Analysis (STA)

Physical Synthesis
0 2 4 6
Physical
Verification

Static Timing STA runs much quicker than HSPICE simulation but
Analysis (STA)
calculated delays are different and no accurate
Finished design

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Physical Synthesis
Specification Physical synthesis is the process that produces
Cell description coding layout of logic circuit.
Logic Standard cell
simulation Circuit layouts
Logic Synthesis
a AND
Formal b
Verification
c OR
Static Timing
Analysis (STA)
Physical synthesis
Physical Synthesis

Physical
Verification

Static Timing
Analysis (STA)

Finished design

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Synopsys EDA Tool Flow for Front-End Digital IC Design
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Physical Synthesis
Specification

Cell description coding

Logic
simulation

Logic Synthesis

Formal
Verification

Static Timing
Analysis (STA)
Design Rule
Physical Synthesis Check (DRC)

Physical
Verification Layout vs.
Schematic
(LVS)
Static Timing
Analysis (STA)

Finished design

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Post-layout STA
Specification

Cell description coding

Logic
simulation

Logic Synthesis
After layout is created STA is run again with
Formal
Verification taking into account parasitics, too
O=max[sum(B,D22),sum(C,D21)]
Static Timing
Analysis (STA) C D21

D22 O
Physical Synthesis A
D1
Physical B=sum(A,D1)
Verification

Static Timing
Analysis (STA)

Finished design 0 2 4 6

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Digital Design Toolchain
Specification

Cell description coding

Logic
simulation VCS

Logic Synthesis Design Compiler

Formal Formality
Verification

Static Timing
Analysis (STA)
Prime Time

Physical Synthesis IC Compiler / IC Compiler II

Physical
Verification
IC Validator

Static Timing Prime Time

Analysis (STA)

Finished design

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Digital Design Toolchain (2)
Specification

Cell description coding

VCS Logic
simulation
Design Compiler Logic Synthesis
Front-End
Formality Formal
Verification

Static Timing
Prime Time Analysis (STA)

IC Compiler Physical Synthesis

IC Validator Physical
Verification
Back-End
Prime Time Static Timing
Analysis (STA)

Finished design

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Synopsys EDA Tool Flow for Front-End Digital IC Design
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Summary

 IC could be represented at different levels from System

to layout
 Design process is always represented by some design
flow from some step to layout
 Digital design flows is composed of front-edn and back-
end parts
 Each design flow has its own set of steps and tools used
for their implementation

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Synopsys EDA Tool Flow for Front-End Digital IC Design
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