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Synopsys Eda Tool Flow Front-End Digital Ic Design Lecture 2

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34 views17 pages

Synopsys Eda Tool Flow Front-End Digital Ic Design Lecture 2

Uploaded by

finny. femy
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Synopsys EDA Tool Flow for

Front-End Digital IC Design

Professor: Sci.D., Professor


Vazgen Melikyan

Synopsys University Courseware


Copyright © 2018 Synopsys, Inc. All rights reserved.
Synopsys EDA Tool Flow for Front-End Digital IC Design
Lecture - 2
1 Developed By: Vazgen Melikyan
Course Overview

 Digital Design Flow


 2 lectures
 Logic Simulation
 2 lectures
 Logic Synthesis
 4 lectures
 Formal Verification
 4 lectures
 Static Timing Analysis
 4 lectures

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Copyright © 2018 Synopsys, Inc. All rights reserved.
Synopsys EDA Tool Flow for Front-End Digital IC Design
Lecture - 2
2 Developed By: Vazgen Melikyan
Logic Simulation

Professor: Sci.D., Professor


Vazgen Melikyan

Synopsys University Courseware


Copyright © 2018 Synopsys, Inc. All rights reserved.
Synopsys EDA Tool Flow for Front-End Digital IC Design
Lecture - 2
3 Developed By: Vazgen Melikyan
Digital Design Toolchain
Specification

Cell description coding

VCS Logic
simulation
Design Compiler Logic Synthesis
Front-End
Formality Formal
Verification

Prime Time Static Timing


Analysis (STA)

Physical Synthesis

Physical
Verification

Static Timing
Analysis (STA)

Finished design

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Copyright © 2018 Synopsys, Inc. All rights reserved.
Synopsys EDA Tool Flow for Front-End Digital IC Design
Lecture - 2
4 Developed By: Vazgen Melikyan
Inputs and Outputs of Logic
Simulator
Library of
descriptions of
standard cells

Stimuli Simulation
Timing
and program
diagrams
control

Simulation deck

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Copyright © 2018 Synopsys, Inc. All rights reserved.
Synopsys EDA Tool Flow for Front-End Digital IC Design
Lecture - 2
5 Developed By: Vazgen Melikyan
Logic Simulation Goals

 Functional correctness
 circuit does what is anticipated
 validation using lots of input stimuli
 Performance
 circuit runs fast enough
 no hazards or races
 validation using lots of stimuli
 Test generation
 simulation of faulty circuits
 verification of output faults

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Copyright © 2018 Synopsys, Inc. All rights reserved.
Synopsys EDA Tool Flow for Front-End Digital IC Design
Lecture - 2
6 Developed By: Vazgen Melikyan
Logic Simulation
 Simulation of temporal behavior of logic design
 Logic design description
 Netlist, network A D
 Components B E
 AND, OR, etc. C
 Component interconnections
 Logic models A
 Component behavior
 Interconnect behavior B
 Signal values C
 Timing models D
 Component behavior
 Interconnect behavior E
 Signal delays
Time
Synopsys University Courseware
Copyright © 2018 Synopsys, Inc. All rights reserved.
Synopsys EDA Tool Flow for Front-End Digital IC Design
Lecture - 2
7 Developed By: Vazgen Melikyan
VCS

Synopsys University Courseware


Copyright © 2018 Synopsys, Inc. All rights reserved.
Synopsys EDA Tool Flow for Front-End Digital IC Design
Lecture - 2
8 Developed By: Vazgen Melikyan
VCS Overview

 VCS supports multiple languages


 Verilog
 VHDL
 C/C++
 SystemC
 SystemVerilog
 OpenVera
 Analog
 Intuitive GUI help find bugs quickly
 Assertions
 Testbench
 Coverage
 Post-simulation analysis

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Synopsys EDA Tool Flow for Front-End Digital IC Design
Lecture - 2
9 Developed By: Vazgen Melikyan
Invoking VCS Interactive Mode

 Starting from compilation


 The VCS interface is called discovery visual environment (DVE).

-R Runs executable immediately after compilation (optional)


-gui Enables DVE
-debug Enables command line debugging (no line stepping)
-debug_all Enables command line debug including line tracing
(optional)
%vcs source.v –R –gui –debug_all

 From the command line, open DVE


%dve

Synopsys University Courseware


Copyright © 2018 Synopsys, Inc. All rights reserved.
Synopsys EDA Tool Flow for Front-End Digital IC Design
Lecture - 2
10 Developed By: Vazgen Melikyan
VCS Features

 The most used features are:


 Tracing the Cause of Failed
Assertion
 Trace drivers and loads of a
signal at any time to see the
drivers and loads that caused a
value change and see all the
drivers/loads that possibly
contributed to a signal value.
 RTL and Gate Signal
Comparison
 Highlighting the net in gate-
level schematic and Verilog

Synopsys University Courseware


Copyright © 2018 Synopsys, Inc. All rights reserved.
Synopsys EDA Tool Flow for Front-End Digital IC Design
Lecture - 2
11 Developed By: Vazgen Melikyan
DVE Top-Level Window
Filter

Schematic window

Hierarchy Data Pane


Pane Source window

Tcl Command line Status

Panes

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Copyright © 2018 Synopsys, Inc. All rights reserved.
Synopsys EDA Tool Flow for Front-End Digital IC Design
Lecture - 2
12 Developed By: Vazgen Melikyan
Tracing the Cause of Failed Assertion

Trace
Driver/Load
Icons

Next Current Driver


Driver

Drivers/Loads
Pane

Synopsys University Courseware


Copyright © 2018 Synopsys, Inc. All rights reserved.
Synopsys EDA Tool Flow for Front-End Digital IC Design
Lecture - 2
13 Developed By: Vazgen Melikyan
RTL and Gate Signal Comparison

Design 1 Design 2

Synopsys University Courseware


Copyright © 2018 Synopsys, Inc. All rights reserved.
Synopsys EDA Tool Flow for Front-End Digital IC Design
Lecture - 2
14 Developed By: Vazgen Melikyan
Gate-Level Path Schematic

Previous View

Trace -> Highlight -> Selected by Color

Synopsys University Courseware


Copyright © 2018 Synopsys, Inc. All rights reserved.
Synopsys EDA Tool Flow for Front-End Digital IC Design
Lecture - 2
15 Developed By: Vazgen Melikyan
User Defined Radixes

 Toolbar menu: Signal -> Set Radix->User-Defined->Edit

 To create a user-defined radix , click New , enter a radix


name, then press Return
Synopsys University Courseware
Copyright © 2018 Synopsys, Inc. All rights reserved.
Synopsys EDA Tool Flow for Front-End Digital IC Design
Lecture - 2
16 Developed By: Vazgen Melikyan

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