3PD5651E

High-speed, 10-Bit, 125MSPS, CMOS Digital-to-Analog Converter

FEATURES PRODUCT DESCRIPTION

 125 MSPS Update Rate The 3PD5651E offers exceptional AC and DC performance while
 10-Bit Resolution supporting update rates up to 125 MSPS. The 3PD5651E’s flexible
 Linearity: 1/4 LSB DNL single-supply operating range of +2.7V to +5.5V and low power
 Linearity: 1/2 LSB INL dissipation are well suited for portable and low power applications. Its
 Differential Current Outputs: 2 mA to 20 mA power dissipation can be further reduced to 45mW, without a
 SFDR to Nyquist at 40MHz Output: 62 dBc significant degradation in performance, by lowering the full-scale
 Fast Settling: 35 ns Full-Scale Settling to 0.1% current output. In addition, a power-down mode reduces the standby
 On-Chip 1.10 V Reference power dissipation to approximately 20mW.
 Edge-Triggered Latches The 3PD5651E is manufactured on an advanced CMOS process. A
 Power Dissipation: 175 mW @ 5 V to 45 mW @ 3 V
segmented current source architecture is combined with a proprietary
 Power-Down Mode: 20 mW @ 5 V
switching technique to reduce spurious components and enhance
 Single +5 V or +3 V Supply Operation
dynamic performance. Edge-triggered input latches and a
 Green, 28-Lead TSSOP Package
 Pin Compatible with TI and ADI Communication DAC Family temperature compensated bandgap reference have been integrated
to provide a complete monolithic DAC solution. Flexible supply
options support +3V and +5V CMOS logic families.
APPLICATIONS The 3PD5651E is a current-output DAC with a nominal full-scale
 Communications Transmit Channel output current of 20mA and > 100kΩ output impedance.
 Signal Reconstruction Differential current outputs are provided to support single-ended or
 Direct Digital Synthesis (DDS) differential applications. The current outputs may be directly tied to an
 Instrumentation output resistor to provide two complementary, single-ended voltage
 Video Reconstruction outputs. The output voltage compliance range is 1.25V.
The 3PD5651E contains a 1.10V on-chip reference and reference
PRODUCT HIGHLIGHTS control amplifier, which allows the full-scale output current to be
simply set by a single resistor. The 3PD5651E can be driven by a
 Manufactured on a CMOS process, the 3PD5651E uses a variety of external reference voltages.
proprietary switching technique that enhances dynamic The 3PD5651E’s full-scale current can be adjusted over a 2mA to
performance well beyond 8- and 10-bit video DACs. 20mA range without any degradation in dynamic performance. Thus,
 On-chip, edge-triggered input CMOS latches readily interface to the 3PD5651E may operate at reduced power levels or be adjusted
+3V and +5V CMOS logic families. The 3PD5651E can support over a 20dB range to provide additional gain ranging capabilities.
update rates up to 125MSPS. The 3PD5651E is available in 28-Lead TSSOP package. It is
 A flexible single-supply operating range of +2.7V to +5.5V and specified for operation over the industrial temperature range.
a wide full-scale current adjustment span of 2mA to 20mA
allows the 3PD5651E to operate at reduced power levels (i.e.,
45mW) without any degradation in dynamic performance.
 A temperature compensated, 1.10V bandgap reference is
included on-chip providing a complete DAC solution. An
external reference may be used.
 The current output(s) of the 3PD5651E can easily be
configured for various single-ended or differential applications. FUNCTIONAL BLOCK DIAGRAM

Figure 2. Functional Block Diagram

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3PD5651E
High-speed, 10-Bit, 125MSPS, CMOS Digital-to-Analog Converter

PIN CONFIGURATION
Pin No. Name Description
1 DB9 Most Significant Data Bit (MSB).
2–9 DB8–DB1 Data Bits 1–8.
10 DB0 Least Significant Data Bit (LSB).
11–14,25 NC No Internal Connection
Power-Down Control Input. Active High. Contains active pull-down circuit, thus may be left unterminated if not
15 SLEEP
used.
16 REFLO Reference Ground when Internal 1.10 V Reference Used. Connect to AVDD to disable internal reference.
Reference Input/Output. Serves as reference input when internal reference disabled (i.e., Tie REFLO to
17 REFIO AVDD). Serves as 1.10 V reference output when internal reference activated (i.e., Tie REFLO to ACOM).
Requires 0.1 F capacitor to ACOM when internal reference activated.
18 FS ADJ Full-Scale Current Output Adjust.
19 COMP1 Bandwidth/Noise Reduction Node.Add 0.1 F to AVDD for optimum performance.
20 ACOM Analog Common.
21 IOUTB Complementary DAC Current Output. Full-scale current when all data bits are 0s.
22 IOUTA DAC current Output. Full-scale current when all data bits are 1s.
23 COMP2 Internal Bias Node for Switch Driver Circuitry. Decouple to ACOM with 0.1 F capacitor.
24 AVDD Analog Supply Voltage (+2.7 V to +5.5 V).
26 DCOM Digital Common.
27 DVDD Digital Supply Voltage (+2.7 V to +5.5 V).
28 CLOCK Clock Input. Data latched on negative of clock of 3PD5651 and positive edge of clock of 3PD5651E.

ORDERING GUIDE

Model Temperature Range Package Transport Media, Quantity

3PD5651E –40°C to +85°C 28-Lead TSSOP Tape and Reel, 2500

ABSOLUTE MAXIMUM RATINGS *

Parameter With Respect to Min Typ. Max Units

VDD ACOM –0.3 6.5 V
DVDD DCOM –0.3 6.5 V
ACOM DCOM –0.3 0.3 V
AVDD DVDD –6.5 6.5 V
CLOCK, SLEEP DCOM –0.3 DVDD+ 0.3 V
Digital Inputs DCOM –0.3 DVDD+0.3 V
IOUTA, IOUTB ACOM –1.0 AVDD+ 0.3 V
COMP1, COMP2 ACOM –0.3 AVDD+ 0.3 V
REFIO, FS ADJ ACOM –0.3 AVDD+ 0.3 V
REFLO ACOM –0.3 0.3 V
Junction Temperature 150 °C
Storage Temperature –65 150 °C
Lead Temperature (10 sec) 300 °C
ӨJA Thermal Resistance 97.9 °C/W
ӨJC of 28-Lead TSSOP 14.0 °C/W

*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional
operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum ratings for extended periods may effect device reliability.

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High-speed, 10-Bit, 125MSPS, CMOS Digital-to-Analog Converter

ELECTRICAL CHARACTERISTICS

DC SPECIFICATIONS
(TMIN to TMAX, AVDD = +5V, DVDD = +5V, IOUTFS = 20mA, unless otherwise noted)

Parameter Min Typ Max Units

RESOLUTION 10 Bits
MONOTONICITY GUARANTEED OVER SPECIFIED TEMPERATURE RANGE
DC ACCURACY1
Integral Linearity Error (INL) –1 ± 1/2 +1 LSB
Differential Nonlinearity (DNL) –1/2 ± 1/4 +1/2 LSB
ANALOG OUTPUT
Offset Error –0.025 +0.025 % of FSR
Gain Error(Without Internal Reference) –10 ±2 +10 % of FSR
Gain Error (With Internal Reference) –10 ±1 +10 % of FSR
Full-Scale Output Current2 2 20.0 mA
Output Compliance Range –1.0 1.25 V
Output Resistance 100 kΩ
Output Capacitance 5 pF
REFERENCE OUTPUT
Reference Voltage 1.08 1.10 1.12 V
Reference Output Current3 100 nA
REFERENCE INPUT
Input Compliance Range 0.1 1.25 V
Reference Input Resistance 1 M
Small Signal Bandwidth (w/o CCOMP1)4 1.4 1.4 MHz
TEMPERATURE COEFFICIENTS
Offset Drift 0 ppm of FSR/°C
Gain Drift (Without Internal Reference) ± 50 ppm of FSR/°C
Gain Drift (With Internal Reference) ± 100 ppm of FSR/°C
Reference Voltage Drift ± 50 ppm/°C
POWER SUPPLY
Supply Voltages of AVDD5 2.7 5 5.5 V
Supply Voltages of DVDD 2.7 5 5.5 V
Analog Supply Current (IAVDD) 25 30 mA
Digital Supply Current (IDVDD)6 3 6 mA
Supply Current Sleep Mode (IOUTB) 8.5 mA
Power Dissipation6 (5 V, IOUTFS = 20 mA) 140 175 mW
Power Dissipation7 (5 V, IOUTFS = 20 mA) 190 mW
Power Dissipation7 (3 V, IOUTFS = 2 mA) 45 45 mW
Power Supply Rejection Ratio—AVDD –0.4 +0.4 % of FSR/V
Power Supply Rejection Ratio—DVDD –0.025 +0.025 % of FSR/V
OPERATING RANGE –40 +85 °C

NOTES
1. Measured at IOUTA, driving a virtual ground.
2. Nominal full-scale current, IOUTFS, is 32 x the IREF current.
3. Use an external buffer amplifier to drive any external load.
4. Reference bandwidth is a function of external cap at COMP1 pin.
5. For operation below 3 V, it is recommended that the output current be reduced to 12mA or less to maintain optimum performance.
6. Measured at fCLOCK = 50MSPS and fOUT = 1.0MHz.
7. Measured as unbuffered voltage output into 50Ω RLOAD at IOUTA and IOUTB, fCLOCK = 100MSPS and fOUT = 40MHz. Specifications subject to
change without notice.

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High-speed, 10-Bit, 125MSPS, CMOS Digital-to-Analog Converter

DYNAMIC SPECIFICATIONS (Specifications subject to change without notice.)

(TMIN to TMAX, AVDD = +5V, DVDD = +5V, IOUTFS = 20mA, Single-Ended Output, IOUTA, 50Ω Doubly Terminated, unless otherwise noted)
Parameter Min Typ Max Units
DYNAMIC PERFORMANCE
Maximum Output Update Rate (fCLOCK) 100 125 MSPS
Output Settling Time (tST) (to 0.1%)1 35 ns
Output Propagation Delay (tPD) 1 ns
Glitch Impulse 5 pV-s
Output Rise Time (10% to 90%)1 2.5 ns
Output Fall Time (10% to 90%)1 2.5 ns
Output Noise (IOUTFS = 20 mA) 50 pA/√Hz
Output Noise (IOUTFS = 2 mA) 30 pA/√Hz
AC LINEARITY TO NYQUIST
Total Harmonic Distortion
fCLOCK = 10 MSPS, fOUT = 1.00 MHz -72 dBc
fCLOCK = 25 MSPS, fOUT = 1.00 MHz -72 dBc
fCLOCK = 50 MSPS, fOUT = 1.00MHz -72 dBc
fCLOCK = 50 MSPS, fOUT = 2.00MHz -70 dBc
fCLOCK = 100 MSPS, fOUT = 2.00 MHz -70 dBc
Spurious-Free Dynamic Range to Nyquist
fCLOCK = 10 MSPS, fOUT = 1.00 MHz 79 dBc
fCLOCK = 50 MSPS, fOUT = 1.00 MHz 77 dBc
fCLOCK = 50 MSPS, fOUT = 5.02 MHz 71 dBc
fCLOCK = 100 MSPS, fOUT = 5.01 MHz 69 dBc
fCLOCK = 100 MSPS, fOUT = 25.01 MHz 61 dBc

NOTES (Specifications subject to change without notice.)

1. Measured single ended into 50 load.

DIGITAL SPECIFICATIONS (Specifications subject to change without notice.)

(TMIN to TMAX, AVDD = +5V, DVDD = +5V, IOUTFS = 20mA, unless otherwise noted)

Parameter Min Typ Max Units

DIGITAL INPUTS
Logic “1” Voltage @ DVDD = +5 V 3.5 5 V
Logic “1” Voltage @ DVDD = +3 V 2.1 3 V
Logic “0” Voltage @ DVDD = +5 V 0 1.3 V
Logic “0” Voltage @ DVDD = +3 V 0 0.9 V
Logic “1” Current –10 10 uA
Logic “0” Current –10 10 uA
Input Capacitance 5 pF
Input Setup Time (tS) 2 ns
Input Hold Time (tH) 1.5 ns
Latch Pulsewidth (tLPW) 3.5 ns

Figure 3. Timing Diagram

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High-speed, 10-Bit, 125MSPS, CMOS Digital-to-Analog Converter

DEFINITIONS OF SPECIFICATIONS

Linearity Error (Also Called Integral Nonlinearity or INL) per degree C. For reference drift, the drift is reported in ppm per
Linearity error is defined as the maximum deviation of the actual degree C.
analog output from the ideal output, determined by a straight line
drawn from zero to full scale. Power Supply Rejection
The maximum changes in the full-scale output as the supplies are
Differential Nonlinearity (or DNL) varied from nominal to minimum and maximum specified voltages.
DNL is the measure of the variation in analog value, normalized to
full scale, associated with a 1 LSB change in digital input code. Settling Time
The time required for the output to reach and remain within a
Monotonicity specified error band about its final value, measured from the start of
A D/A converter is monotonic if the output either increases or the output transition.
remains constant as the digital input increases.
Glitch Impulse
Offset Error Asymmetrical switching times in a DAC give rise to undesired output
The deviation of the output current from the ideal of zero is called transients that are quantified by a glitch impulse. It is specified as
offset error. For IOUTA, 0mA output is expected when the inputs are all the net area of the glitch in pV-s.
0s. For IOUTB, 0mA output is expected when all inputs are set to 1s.
Spurious-Free Dynamic Range
Gain Error (the difference between the actual and ideal output span) The difference, in dB, between the RMS amplitude of the output
The actual span is determined by the output when all inputs are set signal and the peak spurious signal over the specified bandwidth
to 1s minus the output when all inputs are set to 0s.
Signal-to-Noise and Distortion (S/N+D, SINAD) Ratio
Output Compliance Range SINAD is the ratio of the RMS value of the measured output signal
The range of allowable voltage at the output of a current-output DAC. to the RMS sum of all other spectral components below the Nyquist
Operation beyond the maximum compliance limits may cause either frequency, including harmonics but excluding DC. The value for
output stage saturation or breakdown resulting in nonlinear SINAD is expressed in decibels.
performance.
Total Harmonic Distortion
Temperature Drift THD is the ratio of the RMS sum of the first six harmonic
Temperature drift is specified as the maximum change from the components to the RMS value of the measured output signal. It is
ambient (+25°C) value to the value at either TMIN or TMAX. For offset expressed as a percentage or in decibels.
and gain drift, the drift is reported in ppm of full-scale range (FSR)

Figure 4. Basic AC Characterization Test Setup

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 3PD5651E
High-speed, 10-Bit, 125MSPS, CMOS Digital-to-Analog Converter
TYPICAL CHARACTERIZATION CURVES
AVDD = +3 V, DVDD = +3 V, 50Ω Doubly Terminated Load, Single-Ended Output, IOUTA, IOUTFS = 20mA, TA = +25°C, unless otherwise noted.

Figure 5. SFDR vs. fOUT @ 0dBFS Figure 6. SFDR vs. fOUT @ 25 MSPS

Figure 7. THD vs. fCLOCK, fOUT = 2MHz Figure 8. Differential/Single Ended SFDR vs. fOUT @ 100 MSPS

Figure 9. Typical INL Figure 10. Typical DNL

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High-speed, 10-Bit, 125MSPS, CMOS Digital-to-Analog Converter

Figure 11. Single-Tone SFDR Figure 12. Dual-Tone SFDR

Figure 13. Four-Tone SFDR

FUNCTIONAL DESCRIPTION

The 3PD5651E consists of a large PMOS current source array capable of providing up to 20mA of total current. The array is divided into 32
equal currents that make up the five most significant bits (MSBs). The remaining 3 LSBs are also implemented with equally weighted current
sources whose sum total equals 7/8th of an MSB current source. Implementing the upper and lower bits with current sources helps maintain
the DAC’s high output impedance (i.e. > 100 kW). All of these current sources are switched to one or the other of the two output nodes (i.e.,
IOUTA or IOUTB) via PMOS differential current switches. The switches are based on a new architecture that drastically improves distortion
performance.
The analog and digital sections of the 3PD5651E have separate power supply inputs (i.e., AVDD and DVDD) that can operate independently
over a 2.7 volt to 5.5 volt range. The digital section, which is capable of operating up to a 125MSPS clock rate, consists of edge-triggered
latches and segment decoding logic circuitry. The analog section includes the PMOS current sources, the associated differential switches, a
1.10V bandgap voltage reference and a reference control amplifier.
The full-scale output current is regulated by the reference control amplifier and can be set from 2mA to 20mA via an external resistor, RSET. The
external resistor, in combination with both the reference control amplifier and voltage reference VREFIO, sets the reference current IREF, which is
mirrored over to the segmented current sources with the proper scaling factor. The full-scale current, IOUTFS, is thirty-two times the value of IREF.
DAC TRANSFER FUNCTION

The 3PD5651E provides complementary current outputs, IOUTA and IOUTB. IOUTA will provide a near full-scale current output, IOUTFS, when all bits
are high (i.e., DAC CODE = 255), while IOUTB, the complementary output, provides no current. The current output appearing at IOUTA and IOUTB
are a function of both the input code and IOUTFS and can be expressed as:

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High-speed, 10-Bit, 125MSPS, CMOS Digital-to-Analog Converter

IOUTA = (DAC CODE/256) * IOUTFS

IOUTB = (255 – DAC CODE)/256 * IOUTFS
where DAC CODE = 0 to 255 (i.e., Decimal Representation).
As previously mentioned, IOUTFS is a function of the reference current IREF, which is nominally set by a reference voltage VREFIO and external
resistor RSET. It can be expressed as:
IOUTFS = 32* IREF
Where IREF = VREFIO/RSET
VOUTA = IOUTA*RLOAD
VOUTB = IOUTB *RLOAD

Note the full-scale value of VOUTA and VOUTB should not exceed the specified output compliance range to maintain specified distortion and
linearity performance.

The differential voltage, VDIFF, appearing across IOUTA and IOUTB is:
VDIFF = (IOUTA – IOUTB) * RLOAD

Substituting the values of IOUTA, IOUTB, and IREF; VDIFF can be expressed as:

VDIFF = {(2 DAC CODE – 255)/256}/ *(32 RLOAD/RSET) *VREFIO

VOLTAGE REFERENCE AND CONTROL AMPLIFIER

The 3PD5651E contains an internal 1.10V bandgap reference that can be easily disabled and overridden by an external reference. REFIO
serves as either an input or output depending on whether the internal or an external reference is selected. If REFLO is tied to ACOM, as
shown in Figure 14, the internal reference is activated and REFIO provides a 1.10 V output. In this case, the internal reference must be
compensated externally with a ceramic chip capacitor of 0.1F or greater from REFIO to REFLO. Note that REFIO is not designed to drive any
external load. It should be buffered with an external amplifier having an input bias current less than 100nA if any additional loading is required.

Figure 14. Internal Reference Configuration

The internal reference can be disabled by connecting REFLO to AVDD. In this case, an external reference may then be applied to REFIO as
shown in Figure 15. The external reference may provide either a fixed reference voltage to enhance accuracy and drift performance or a
varying reference voltage for gain control. Note that the 0.1F compensation capacitor is not required since the internal reference is disabled,
and the high input impedance (i.e., 1 MΩ) of REFIO minimizes any loading of the external reference.
The small signal bandwidth of the reference control amplifier is approximately 1.8MHz and can be reduced by connecting an external capacitor
between COMP1 and AVDD. The output of the control amplifier, COMP1, is internally compensated via a 50pF capacitor that limits the control
amplifier small-signal bandwidth and reduces its output impedance. Any additional external capacitance further limits the bandwidth and acts
as a filter to reduce the noise contribution from the reference amplifier. If IREF is fixed for an application, a 0.1F ceramic chip capacitor is
recommended.
IREF can be varied for a fixed RSET by disabling the internal reference and varying the common-mode voltage over its compliance range of
1.25V to 0.10V. REFIO can be driven by a single-supply amplifier or DAC, thus allowing IREF to be varied for a fixed RSET. Since the input
impedance of REFIO is approximately 1MΩ, a simple R-2-R ladder DAC configured in the voltage mode topology may be used to control the
gain. Note another 3PD5651E could also be used as the gain control DAC since it can also provide a programmable unipolar output up to
1.2V.

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 3PD5651E
High-speed, 10-Bit, 125MSPS, CMOS Digital-to-Analog Converter

Figure 15. External Reference Configuration

ANALOG OUTPUTS AND OUTPUT CONFIGURATIONS

The 3PD5651E produces two complementary current outputs, IOUTA and IOUTB, which may be converted into complementary single-ended
voltage outputs, VOUTA and VOUTB, via a load resistor, RLOAD, as described in the DAC TRANSFER FUNCTION section. Figure 16 shows the
3PD5651E configured to provide a positive unipolar output range of approximately 0V to +0.5V for a double terminated 50Ω cable for a
nominal full-scale current, IOUTFS, of 20mA. In this case, RLOAD represents the equivalent load resistance seen by IOUTA or IOUTB and is equal to
25Ω. The unused output (IOUTA or IOUTB) can be connected to ACOM directly or via a matching RLOAD. Different values of IOUTFS and RLOAD can
be selected as long as the positive compliance range is adhered to.

Figure 16. 0 V to +0.5 V Unbuffered Voltage Output

Alternatively, an amplifier could be configured as an I-V converter thus converting IOUTA or IOUTB into a negative unipolar voltage. Figure 17
shows a buffered singled-ended output configuration in which the op amp, U1, performs an I-V conversion on the 3PD5651E output current.
U1 provides a negative unipolar output voltage and its full-scale output voltage is simply the product of RFB and IOUTFS. The full-scale output
should be set within U1’s voltage output swing capabilities by scaling IOUTFS and/or RFB. An improvement in ac distortion performance may
result with a reduced IOUTFS, since the signal current U1 will be required to sink and will be subsequently reduced. Note, the ac distortion
performance of this circuit at higher DAC update rates may be limited by U1’s slewing capabilities.

Figure 17. Unipolar Buffered Voltage Output

IOUTA and IOUTB also have a negative and positive voltage compliance range that must be adhered to in order to achieve optimum performance.
The positive output compliance range is slightly dependent on the full-scale output current, IOUTFS. It degrades slightly from its nominal 1.25V
for an IOUTFS = 20mA to 1.00V for an IOUTFS = 2mA. Applications requiring the 3PD5651E’s output (i.e., VOUTA and/or VOUTB) to extend up to its
output compliance range should size RLOAD accordingly. Operation beyond this compliance range will adversely affect the 3PD5651E’s linearity.
The differential voltage, VDIFF, existing between VOUTA and VOUTB may also be converted to a single-ended voltage via a transformer or
differential amplifier configuration. Refer to the DIFFERENTIAL OUTPUT CONFIGURATION section for more information.

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High-speed, 10-Bit, 125MSPS, CMOS Digital-to-Analog Converter

DIGITAL INPUTS

The 3PD5651E’s digital input consists of eight data input pins and a clock input pin. The 8-bit parallel data inputs follow standard positive binary coding
where DB7 is the most significant bit (MSB) and DB0 is the least significant bit (LSB). The digital interface is implemented using an edge-triggered
master slave latch. The 3PD5651 output is updated following the falling edge of the clock and 3PD5651E output is updated following the rising edge as
shown in Figure 3 and is designed to support a clock rate as high as 125MSPS. The clock can be operated at any duty cycle that meets the specified
latch pulse-width. The setup-and-hold times can also be varied within the clock cycle as long as the specified minimum times are met; although the
location of these transition edges may affect digital feed-through and distortion performance.
The digital inputs are CMOS compatible with logic thresholds, VTHRESHOLD set to approximately half the digital positive supply (DVDD) or
VTHRESHOLD = DVDD/2 (±20%)
Figure 18 shows the equivalent digital input circuit for the data and clock inputs. The sleep mode input is similar, except that it contains an active
pull-down circuit, thus ensuring that the 3PD5651E remains enabled if this input is left disconnected. The internal digital circuitry of the 3PD5651E is
capable of operating over a digital supply range of 2.7 V to 5.5 V. As a result, the digital inputs can also accommodate TTL levels when DVDD is set to
accommodate the maximum high level voltage, VOH(MAX), of the TTL drivers. A DVDD of 3 V to 3.3 V will typically ensure upper compatibility of most
TTL logic families.

Figure 18. Equivalent Digital Input

Since the 3PD5651E is capable of being updated up to 125 MSPS, the quality of the clock and data input signals are important in achieving the
optimum performance. The drivers of the digital data interface circuitry should be specified to meet the minimum setup-and-hold times of the
3PD5651E as well as its required min/max input logic level thresholds. Typically, the selection of the slowest logic family that satisfies the above
conditions will result in the lowest data feed-through and noise. Digital signal paths should be kept short and run lengths matched to avoid propagation
delay mismatch. The insertion of a low value resistor network (i.e., 20Ω to 100Ω) between the 3PD5651E digital inputs and driver outputs may be
helpful in reducing any overshooting and ringing at the digital inputs that contribute to data feed-through. For longer run lengths and high data update
rates, strip line techniques with proper termination resistors should be considered to maintain “clean” digital inputs. Also, operating the 3PD5651E with
reduced logic swings and a corresponding digital supply (DVDD) will also reduce data feed-through. The external clock driver circuitry should provide
the 3PD5651E with a low jitter clock input meeting the min/max logic levels while providing fast edges. Fast clock edges will help minimize any jitter
that will manifest itself as phase noise on a reconstructed waveform. However, the clock input could also be driven by via a sine wave, which is
centered around the digital threshold (i.e., DVDD/2), and meets the min/max logic threshold. This may result in a slight degradation in the phase noise,
which becomes more noticeable at higher sampling rates and output frequencies. Note, at higher sampling rates the 20% tolerance of the digital logic
threshold should be considered since it will affect the effective clock duty cycle and subsequently cut into the required data setup-and-hold times.

SLEEP MODE OPERATION

The 3PD5651E has a power-down function that turns off the output current and reduces the supply current to less than 8.5mA over the specified supply
range of 2.7 V to 5.5 V and temperature range. This mode can be activated by applying a logic level “1” to the SLEEP pin. This digital input also contains an
active pull-down circuit that ensures the 3PD5651E remains enabled if this input is left disconnected. The SLEEP input with active pull-down requires
<40A of drive current.
The power-up and power-down characteristics of the 3PD5651E are dependent on the value of the compensation capacitor connected to COMP2 (Pin 23).
With a nominal value of 0.1F, the 3PD5651E takes less than 5s to power down and approximately 3.25ms to power back up.

POWER DISSIPATION

The power dissipation, PD, of the 3PD5651E is dependent on several factors, including:
(1) AVDD and DVDD, the power supply voltages;
(2) IOUTFS, the full-scale current output;
(3) fCLOCK, the update rate;
(4) the reconstructed digital input waveform.
The power dissipation is directly proportional to the analog supply current, IAVDD, and the digital supply current, IDVDD. IAVDD is directly

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High-speed, 10-Bit, 125MSPS, CMOS Digital-to-Analog Converter

proportional to IOUTFS, as shown in Figure 19, and is insensitive to fCLOCK.

Figure 19. IAVDD vs. IOUTFS Figure 20. IDVDD vs. Ratio @DVDD=5V Figure 21. IDVDD vs. Ratio @DVDD=3V

Conversely, IDVDD is dependent on both the digital input waveform, fCLOCK, and digital supply DVDD. Figures 20 and Figures 21 show IDVDD as a
function of full-scale sine wave output ratios (fOUT/fCLOCK) for various update rates with DVDD = 5V and DVDD = 3V, respectively. Note, how
IDVDD is reduced by more than a factor of 2 when DVDD is reduced from 5 V to 3V.

POWER AND GROUNDING CONSIDERATIONS

In systems seeking to simultaneously achieve high speed and high performance, the implementation and construction of the printed circuit
board design is often as important as the circuit design. Proper RF techniques must be used in device selection placement and routing and
supply bypassing and grounding. The evaluation board for the 3PD5651E, which uses a four layer PCB, serves as a good example for the
above mentioned considerations. The evaluation board provides an illustration of the recommended printed circuit board ground, power and
signal plane layouts.
Proper grounding and decoupling should be a primary objective in any high speed system. The 3PD5651E features separate analog and
digital supply and ground pins to optimize the management of analog and digital ground currents in a system. In general, AVDD, the analog
supply, should be decoupled to ACOM, the analog common, as close to the chip as physically possible. Similarly, DVDD, the digital supply,
should be decoupled to DCOM as close as physically as possible.
For those applications requiring a single +5 V or +3 V supply for both the analog and digital supply, a clean analog supply may be generated
using the circuit shown in Figure 22. The circuit consists of a differential LC filter with separate power supply and return lines. Lower noise can
be attained using low ESR type electrolytic and tantalum capacitors.

Figure 22. Differential LC Filter for Single +5V or +3V Applications

Maintaining low noise on power supplies and ground is critical to obtaining optimum results from the 3PD5651E. If properly implemented,
ground planes can perform a host of functions on high speed circuit boards: bypassing, shielding, current transport, etc. In mixed signal design,
the analog and digital portions of the board should be distinct from each other, with the analog ground plane confined to the areas covering the
analog signal traces, and the digital ground plane confined to areas covering the digital interconnects.
All analog ground pins of the DAC, reference and other analog components, should be tied directly to the analog ground plane. The two ground planes should
be connected by a path 1/8 to 1/4 inch wide underneath or within 1/2 inch of the DAC to maintain optimum performance. Care should be taken to ensure that
the ground plane is uninterrupted over crucial signal paths. On the digital side, this includes the digital input lines running to the DAC as well as any clock signals.
On the analog side, this includes the DAC output signal, reference signal and the supply feeders.
The use of wide runs or planes in the routing of power lines is also recommended. This serves the dual role of providing a low series impedance power supply to
the part, as well as providing some “free” capacitive decoupling to the appropriate ground plane. It is essential that care be taken in the layout of signal and
power ground interconnects to avoid inducing extraneous voltage drops in the signal ground paths. It is recommended that all connections be short, direct and
as physically close to the package as possible in order to minimize the sharing of conduction paths between different currents. When runs exceed an inch in

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High-speed, 10-Bit, 125MSPS, CMOS Digital-to-Analog Converter

length, strip line techniques with proper termination resistor should be considered. The necessity and value of this resistor will be dependent upon the logic
family used.
For applications requiring the optimum dynamic performance and/or a bipolar output swing, a differential output configuration is suggested. A differential output
configuration may consist of either an RF transformer or a differential op amp configuration. The transformer configuration is well suited for ac coupling
applications. It provides the optimum high frequency performance due to its excellent rejection of common-mode distortion (i.e., even-order harmonics) and
noise over a wide frequency range. It also provides electrical isolation and the ability to deliver twice the power to the load (i.e., assuming no source termination).
The differential op amp configuration is suitable for applications requiring dc coupling, a bipolar output, signal gain, and/or level shifting.
Figure 23 shows the 3PD5651E in a typical transformer coupled output configuration. The center-tap on the primary side of the transformer must be connected
to ACOM to provide the necessary dc current path for both IOUTA and IOUTB. The complementary voltages appearing at IOUTA and IOUTB (i.e., VOUTA and VOUTB)
swing symmetrically around ACOM and should be maintained within the specified output compliance range of the 3PD5651E. A differential resistor, RDIFF, may
be inserted in applications in which the output of the transformer is connected to the load, RLOAD, via a passive reconstruction filter or cable. RDIFF is determined
by the transformer’s impedance ratio and provides the proper source termination. Note that approximately half the signal power will be dissipated across RDIFF.

Figure23. Differential Output Using a Transformer

An op amp can also be used to perform a differential to single-ended conversion as shown in Figure 24. The 3PD5651E is configured with two equal
load resistors, RLOAD, of 25Ω. The differential voltage developed across IOUTA and IOUTB is converted to a single-ended signal via the differential op amp
configuration. An optional capacitor can be installed across IOUTA and IOUTB forming a real pole in a low-pass filter. The addition of this capacitor also
enhances the op amps distortion performance by preventing the DACs high slewing output from overloading the op amp’s input.

Figure 24. DC Differential Coupling Using an Op Amp

The common-mode rejection of this configuration is typically determined by the resistor matching. In this circuit, the differential op amp circuit is
configured to provide some additional signal gain. The op amp must operate off a dual supply since its output is approximately ±1.0 V. A high speed
amplifier capable of preserving the differential performance of the 3PD5651E while meeting other system level objectives (i.e., cost, power) should be
selected. The op amps differential gain, its gain setting resistor values and full-scale output swing capabilities should all be considered when optimizing
this circuit.
The differential circuit shown in Figure 25 provides the necessary level-shifting required in a single supply system. In this case, AVDD, which is the
positive analog supply for both the 3PD5651E and the op amp, is also used to level-shift the differential output of the 3PD5651E to mid-supply (i.e.,
AVDD/2).

Figure 25. Single-Supply DC Differential Coupled Circuit

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 3PD5651E
High-speed, 10-Bit, 125MSPS, CMOS Digital-to-Analog Converter

OUTLINE DIMENSIONS
28-Lead Thin Shrink Small Outline Package (TSSOP) --Dimensions are shown in millimeters and inches.

Dimensions In Millimeters Dimensions In Inches

Symbol
Min Max Min Max
D 9.600 9.800 0.378 0.386
E 4.300 4.500 0.169 0.177
b 0.190 0.300 0.007 0.012
c 0.090 0.200 0.004 0.008
E1 6.250 6.550 0.246 0.258
A 1.200 0.047
A2 0.800 1.000 0.031 0.039
A1 0.050 0.150 0.002 0.006
e 0.65 (BSC) 0.026 (BSC)
L 0.500 0.700 0.020 0.028
H 0.25 (TYP) 0.01 (TYP)
θ 1° 7° 1° 7°

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3PD5651E
High-speed, 10-Bit, 125MSPS, CMOS Digital-to-Analog Converter

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