Quiz Date: 25th September 2023, 4th hour.

Quiz-1 The following is the Syllabus for Embedded Systems Design Course

Chapter 1. Introduction to Embedded Systems

Definition of Embedded Systems

Firmware

Features of Embedded Systems

Applications

Consumer Appliances, Office Automation, Industrial Automation

Medical Electronics, Computer Networking, Telecommunication

Wireless Technologies, Instrumentation, Security, Finance

Categories of Embedded Systems

Stand Alone, Real time, Network, Mobile Devices

Overview of Embedded System Architecture

Hardware, Software (OS, and Application Software)

Simplified Hardware Architecture

CPU, Memory, Input, Output

Communication Interfaces

Application Specific Circuitry

Specialities of Embedded Systems

Reliability, Ruggedness, Performance, Power, Cost, Size

Limited User Interface, Software Upgradation

Recent Trends in Embedded Systems

Processor Power, Memory, OS

Communication Interfaces and Networking Capabilities

Programming Languages, Development Tools

Programmable hardware: PLD and FPGA

Chapter 2. Embedded System Architecture

Embedded System Arch consists of Hardware Architecture and Software Architecture

2.1 Hardware Architecture

CPU: General Purpose Processor, DSP,

CPU Internal Architecture,

 Vonn-Neumann Architecture, Harward Architecture

Memories: RAM, ROM, Mixed Type

Input Devices: ADC, Keypad,

Output Devices: DAC, LCD, LED

Communication Interfaces: RS232, I2C, SPI, UART, etc

Special Circuitry: Sensors, Clock Circuitry, Chip Select, WDT, Debug Port

2.2 Interrupts

2.3 Software Architecture: Application program, OS

UART: Configuration and controlling of UART Interface of LPC2148 Device for serial communication
Detailed Syllabus

Chapter 1. Introduction to Embedded Systems

Definition of Embedded Systems

Firmware

Features of Embedded Systems

Applications

Consumer Appliances

Office Automation

Industrial Automation

Medical Electronics

Computer Networking

Telecommunication

Wireless Technologies

Instrumentation

Security

Finance

Categories of Embedded Systems

Stand Alone

Real time

Network

Mobile Devices

Overview of Embedded System Architecture

Hardware

Software – OS, and Application Software

Simplified Hardware Architecture

CPU

Memory

Input

Output

Communication Interfaces
 Application Specific Circuitry

Specialities of Embedded Systems

Reliability

Ruggedness

Performance

Power

Cost

Size

Limited User Interface

Software Upgradation

Recent Trends in Embedded Systems

Processor Power

Memory

OS

Communication Interfaces and Networking Capabilities

Programming Languages

Development Tools

Programmable hardware

PLD and FPGA

Chapter 2. Embedded System Architecture

Hardware Architecture and Software Architecture

2.1 Hardware Architecture

CPU: General Purpose Processor, DSP, CPU Internal Architecture,

Vonn-Neumann Architecture, Harward Architecture

Memories: RAM, ROM, Mixed Type

Input Devices: ADC, Keypad,

Output Devices: DAC, LCD, LED

Communication Interfaces: RS232, I2C, SPI, UART, etc

Special Circuitry: Sensors, Clock Circuitry, Chip Select, WDT, Debug Port

2.2 Interrupts
 Priority Interrupts

Interrupt Controller

2.3 Software Architecture

Application program

OS

CDAC nation wide workshop for

National coordinator for that

CDAC will setup a lab with Vega processor KITS

Points in FAME

>>

2. Budget? Afternoon, 11th Sept 2023

Friends did Ph.D. in VLSI

Suggest sections/sub-sections for writing a paper with title “High Speed Fixed-point Multiplier: A
Survey”

Vega uses which version of the RISC architecture?

3x1024

NN

3x1024

NN

FPGA
Chips
Platform Xilinx Quartus Altera Xilinx Xilinx
Virtex-7 Pro Cyclone V Zync 7000 Zync 7000
Stratix 10
Precision Fix-16 Fix-8 Hybrid-16 Fix-8 Fix-8
Vector-Size 256x1 8x1 8x1 8x1
DSP used 1944 4368 8 20 40
 DSP per Approx. 16 1 2.5 5
Cell
Freq (MHz) 200 260 91 112 112
Latency 0.02 ms 3 ms 30.04 ms 166 ns 255 ns
Power (W) 22 62 3.31 0.266 0.36
Throughput 131.10 4790 189.69 224.72 112.36
(GOPs)

Feature LSTM Network Estimated Estimated

Vector Size Size Resources Resources
(Avg. DSP (Total
Slices per DSP Slices
Cell) Cells)
[1] 775X1 3 Cells X 3*x
[2] 775X1 3 Cells X 3*x
[3]

775

1s gives 775X1 Vector

RxC = Rx775

Each gate has a weight matrix and it is multiplied with both ht-1, and xin,t. then the resultant vectors
are added element wise, followed wise one more element wise addition with bias vector. So, at least
one multiplier and one adder are required per one gate. A total of four gates, require four
multipliers and four adders. Other computations in the LSTM Tail, need two more multipliers, and
adders. So, the total number of multipliers, and adders is six each.

If the multiplier and adder are fixed-point ones, then the resource requirement of one LSTM can
estimated as follows.

Multiplier Adder

Does the size of the feature vector changes from target to target in the radar based
FPGA Family/Model Number of DSP Slices

Xilinx Virtex UltraScale+ Up to 5,520 DSP slices

Xilinx Kintex UltraScale+ Up to 2,880 DSP slices

Intel (Altera) Stratix 10 Up to 5,760 DSP slices

Intel (Altera) Arria 10 Up to 1,600 DSP slices

Lattice ECP5 Up to 104 DSP slices

FPGA Family/Model Number of DSP Slices

Xilinx Virtex Up to 5,520 DSP slices*
UltraScale+
Xilinx Kintex Up to 2,880 DSP slices*
UltraScale+
Intel (Altera) Stratix 10 Up to 5,760 DSP slices
Intel (Altera) Arria 10 Up to 1,600 DSP slices
Lattice ECP5 Up to 104 DSP slices

Zynq UltraScale+ MPSoC ZCU106 Evaluation Kit

Zynq UltraScale+ XCZU7EV-2FFVC1156 MPSoC 1728 DSP slices, $3,234.00 = 3 Lakhs

Zynq UltraScale+ RFSoC ZCU216 Evaluation Kit

Zynq UltraScale+ XCZU49DR-2FFVF1760 RFSoC 4272 DSP slices, $15,546.00 = 13.5 Lakhs

775x3x2 = 4650

XCZU7EV-2FFVC1156I Datasheet PDF, Pricing Xilinx Inc. | Easybom

Research work

Implementation

Project Staff:
 TRL
(Technology
Milestones and Readiness Types of Equipment
Year/Quarter Deliverables Description Level) Required

Year 1

Train project staff in relevant

areas, including FPGA/ASIC
design, radar technology, and Training Materials,
Q1-Q2 Staff Training UAV applications. TRL 0 Workshops

Develop a high-level design

Initial Design and and simulate the LSTM Simulation Software,
Q3 Simulation accelerator. TRL 3 Workstation/PC

FPGA/ASIC
Begin prototyping the Development Board,
FPGA/ASIC hardware accelerator on the Test Equipment (e.g.,
Q4 Prototyping chosen platform. TRL 4 oscilloscope)

Year 2

Accelerator Radar Data Source,

Integration with Interface the accelerator with FPGA/ASIC
Q1 Radar Data radar data for initial testing. TRL 4 Development Board

Accelerator FPGA/ASIC
Optimization and Optimize hardware design and Development Board,
Q2 Tuning performance. TRL 4 Simulation Software

Test the accelerator's UAV Simulation

functionality and performance Environment,
Initial Testing and in a simulated UAV FPGA/ASIC
Q3 Validation environment. TRL 5 Development Board
 TRL
(Technology
Milestones and Readiness Types of Equipment
Year/Quarter Deliverables Description Level) Required

Firmware and Develop necessary firmware

Software and software for UAV Software Development
Q4 Development communication and control. TRL 5 Tools, Workstation/PC

Year 3

Integrate the hardware Radar Data Source,

Real Radar Data accelerator with real radar FPGA/ASIC
Q1 Integration data sources. TRL 6 Development Board

Real-World UAV Conduct field tests with small- Small UAVs, Radar Data
Q2 Testing sized UAVs and collect data. TRL 6 Source

Data Analysis and Analyze collected data, refine

Algorithm algorithms, and optimize Workstation/PC, Data
Q3 Refinement performance. TRL 6 Analysis Tools

Hardware and Integrate hardware

Software accelerator with UAV systems UAV Hardware, Software
Q4 Integration and software. TRL 7 Development Tools

Year 4

Conduct comprehensive
Demonstration and system testing and evaluation Test Environments,
Q1 Evaluation in real-world scenarios. TRL 7 Evaluation Tools

Prepare project
Documentation documentation, including Documentation Tools,
Q2 and Reporting reports and manuals. TRL 7 Workstation/PC

Review project outcomes and

Project Review and make any necessary
Q3 Refinement refinements. TRL 7 Workstation/PC

Perform final testing,

Final Testing and validation, and system Evaluation Tools, Test
Q4 Evaluation optimization. TRL 8 Equipment

Year 5

Wrap up the project, complete

documentation, and publish Documentation Tools,
Q1 Project Conclusion findings. TRL 8 Workstation/PC
 TRL
(Technology
Milestones and Readiness Types of Equipment
Year/Quarter Deliverables Description Level) Required

Share knowledge, collaborate

Knowledge with the community, and
Transfer and Future explore potential research Collaboration and
Q2 Research directions. TRL 9 Communication Tools

In this revised plan, the first two quarters of Year 1 are dedicated to staff training. The TRLs are
adjusted to reflect the progress made after training. The rest of the project schedule remains largely
the same, with the training period incorporated into the timeline.

Year Quarterly Milestones

1st 1st Quarter: Training the JRF on Radar technology, and Data converters (ADC)
2nd Quarter: ADC interfacing with Preprocessing Module (Vega Processor)

3rd Quarter: Design and Simulation of Radar Signal Processing Algorithms

4th Quarter: Training the JRF on Digital Desing using Verilog. And Design and
Simulation of LSTM cell
2nd 1st Quarter: Design and Simulation of Small Sized LSTM Networks (8x8,
16x16)

2nd Quarter:
Design and Simulation of Full LSTM Networks
3rd Quarter:
Design and Simulation of Neural Network classifier

4th Quarter:
Interfacing the LSTM
and NN classifier and
Initial Testing and Validation of Detection Accelerator (LSTM)
3rd 1st Quarter:
Prototyping of Target Detection Accelerator using Neural Network

2nd Quarter:

Optimization and Tuning of Target Detection Accelerator (LSTM)

3rd
Quarter:
 Design and Simulation of Target Localizer (using LSTM and Neural Network) to
test it functionality

4th Quarter:
Integration of
Target Detector and Localizer modules and Prototyping of Target Classifier and
Localizer

4th 1st Quarter: Integration/interfacing of

Target Detector and Localizer modules (on FPGA) and Radar Data
Preprocessor modules (on VEGA processor/FPGA)

2nd Quarter: Initial Testing and Validation of Overall Integrated

Radar Target Detection and Classifier System

3rd Quarter: Real Radar Data Integration and Testing and Validation of Overall
Integrated
Radar Target Detection and Classifier System

4th Quarter: Output Data Analysis and Further Optimization of the Radar Detector
and Classifier System

5th 1st Quarter: Final Testing and Validation of Overall Integrated

Radar Target Detection and Classifier System

2nd Quarter: Complete documentation, user manual

3rd Quarter: Project Review and Refinement, Conclusion

4th Quarter: Knowledge Transfer and Future Research: May be a workshop.

>>

What is the difference between "Radar Signal Processing Design" and "Radar Signal Processing
Prototyping" mentioned in the project plan?

>>

The terms "Radar Signal Processing Design" and "Radar Signal Processing Prototyping" in the project
plan represent different phases of developing the radar signal processing block (Block 1) of the project.
Here's an explanation of the key differences between these two phases:

1. Radar Signal Processing Design:

 Description: This phase focuses on the initial conceptualization and design of the
radar signal processing block. It involves defining the architecture, algorithms, and
specifications for the block.
  Activities: During this phase, the project team will:

 Define the requirements and objectives of the radar signal processing block,
including the types of radar data to be processed and the desired signal
processing techniques.

 Develop a high-level design and architecture for the block, outlining the major
components and their interactions.

 Specify the algorithms and processing methods to be implemented within the

block.

 Deliverable: The primary deliverable of this phase is a detailed design document that
describes the architecture, algorithms, and specifications of the radar signal
processing block.

2. Radar Signal Processing Prototyping:

 Description: This phase involves creating a functional prototype of the radar signal
processing block based on the design specifications developed in the previous phase.
It aims to validate the design and assess its performance in a real-world context.

 Activities: During this phase, the project team will:

 Implement the designed radar signal processing algorithms in hardware or

software, depending on the project requirements.

 Build a working prototype of the block using appropriate development tools,

platforms, or hardware components (e.g., FPGA/ASIC boards).

 Conduct initial testing and validation of the prototype to ensure that it can
process radar data as expected.

 Deliverable: The main deliverable of this phase is a functional prototype of the radar
signal processing block that demonstrates its capabilities and performance in handling
radar data.

In summary, "Radar Signal Processing Design" is the phase where the conceptual design and
specifications for the signal processing block are established, while "Radar Signal Processing
Prototyping" is the subsequent phase where these designs are translated into a working prototype for
validation and testing. The prototyping phase ensures that the designed signal processing algorithms
can be effectively implemented and perform as intended in real-world applications.

>>

Do we need high sampling frequency or rate ADCs for processing radar received signals?
>>
The choice of ADC (Analog-to-Digital Converter) sampling frequency in radar systems depends on
several factors, including the characteristics of the radar system, the requirements of the application,
and the trade-offs between accuracy and complexity. Here are some considerations:
1. Signal Bandwidth: The required sampling frequency is typically determined by the signal
bandwidth of the radar system. According to the Nyquist-Shannon sampling theorem, the
sampling frequency should be at least twice the signal's bandwidth to avoid aliasing and
accurately reconstruct the signal. In radar systems, the signal bandwidth is influenced by factors
such as pulse duration and modulation.
2. Range Resolution: Higher sampling frequencies can provide finer range resolution in radar
systems. This means that the radar can distinguish between objects that are closer together in
range. If high range resolution is a critical requirement, a higher sampling frequency may be
necessary.
3. Doppler Processing: For radar systems that perform Doppler processing to detect moving
targets, the choice of sampling frequency affects the Doppler resolution. Higher sampling
frequencies can provide finer Doppler resolution, enabling the radar to distinguish between
targets with different velocities.
4. Dynamic Range: The dynamic range of the ADC is also a consideration. In radar systems,
there can be a wide range of signal amplitudes, from weak returns to strong reflections. A higher
bit-depth ADC can capture a broader dynamic range, which can be important for accurately
detecting weak signals while avoiding saturation for strong returns.
5. Processing Complexity: Higher sampling frequencies can lead to increased data processing
requirements. This can affect the complexity of the radar system, including the computational
resources needed for signal processing.
6. Cost and Power Consumption: ADCs with higher sampling frequencies often come at a
higher cost and may consume more power. The choice of ADC should align with the project's
budget and power constraints.
7. Antenna and System Design: The design of the radar antenna and the overall system
architecture can influence the required sampling frequency. It's essential to ensure that the
ADC's sampling rate is compatible with the rest of the radar system.
In summary, the required sampling frequency for radar signal processing depends on the specific radar
system's characteristics and application requirements. While higher sampling frequencies can provide
benefits in terms of resolution and accuracy, they also come with increased complexity and cost. It's
essential to carefully evaluate the trade-offs and select an ADC sampling frequency that best meets the
needs of the radar system and application.

>>
If we assume the RF signal is converted to the baseband signal, then we need an ADC to convert the
analog signal to the digital signal for further processing. Suggest the ADC specification required.
>>
If we assume the RF signal is converted to the baseband signal. After converting to the baseband signal,
we need an ADC to convert the analog signal to the digital signal for further processing. Suggest the
ADC specification required.
>>
When converting an RF signal to the baseband signal in radar systems and subsequently digitizing it
using an ADC (Analog-to-Digital Converter), selecting the right ADC specifications is crucial for
accurate signal processing. Here are the key ADC specifications to consider for this scenario:
1. Sampling Frequency: The ADC's sampling frequency should be chosen based on the Nyquist-
Shannon sampling theorem. It should be at least twice the bandwidth of the baseband signal to
avoid aliasing. Ensure that the chosen sampling frequency meets the signal bandwidth
requirements of your radar system.
2. Resolution (Bit Depth): The ADC's resolution determines the number of discrete digital levels
it can represent. Higher bit-depth ADCs provide better dynamic range and accuracy. For radar
applications, ADCs with 12 to 16 bits of resolution are common, but the choice may depend on
the specific requirements of your system.
3. Signal-to-Noise Ratio (SNR): The SNR of the ADC should be sufficient to capture the
dynamic range of the radar signal accurately. A higher SNR ensures that weak radar returns are
not lost in noise. Typically, an ADC with an SNR greater than 70 dB is desirable for radar
applications.
4. Spurious-Free Dynamic Range (SFDR): SFDR measures the ADC's ability to handle large
out-of-band signals without distortion or spurious responses. High SFDR is crucial to avoid
interference from strong adjacent signals or harmonics.
5. Input Voltage Range: Ensure that the ADC can accommodate the peak-to-peak voltage range
of the baseband signal without clipping or saturation. The input range should match the
expected amplitude of the baseband signals.
6. Linearity: The ADC should exhibit excellent linearity to accurately represent the analog signal
across its entire input range. Non-linearity can introduce distortion into the digitized signal.
7. Sample-and-Hold (S/H) Performance: Pay attention to the ADC's sample-and-hold circuitry,
as it impacts the effective sampling performance. Low aperture jitter and minimal droop are
essential for accurate sampling.
8. Power Consumption: Consider the power consumption of the ADC, especially if your radar
system operates in battery-powered or energy-efficient environments.
9. Interface: Ensure that the ADC's output interface (e.g., parallel, serial) is compatible with your
signal processing hardware, microcontroller, or FPGA.
10. Temperature Range: Verify that the ADC can operate within the required temperature range
of your radar system, especially if it's exposed to extreme environmental conditions.
11. Latency: Depending on your radar application, latency may be a critical consideration. Some
ADCs introduce latency in the conversion process, which may affect real-time processing.
Low-latency ADCs are preferable for applications requiring rapid response times.
12. Data Rate: The ADC's data rate should match the processing capabilities of downstream
components, such as DSPs or FPGAs.
Remember that the specific ADC specifications you choose will depend on the unique requirements of
your radar system, including signal bandwidth, target detection range, and desired accuracy. It's
advisable to perform a detailed system-level analysis and simulation to determine the optimal ADC
specifications for your application. Additionally, consider factors such as cost and power consumption
when selecting an ADC for your radar system.

What would be the baseband signal bandwidth for various targets, as per the exiting examples in your
database?
>>
Base band signal and bandwidth requirement:
The baseband signal bandwidth in radar systems can vary significantly depending on the specific radar
application, target types, and radar design. There isn't a fixed or universal value for baseband signal
bandwidth, as it is determined by several factors, including the following:
1. Radar Type: Different radar types have different signal bandwidth requirements. For example:
 Weather radars may have relatively wide bandwidths to detect precipitation.
 Automotive radars typically operate at lower bandwidths for object detection and
collision avoidance.
 Military radars can have a wide range of bandwidths depending on their intended use,
from narrowband for target tracking to wideband for surveillance.
2. Target Characteristics: The type and size of targets being detected affect the required signal
bandwidth. Smaller or faster-moving targets may require wider bandwidth for accurate
detection.
3. Resolution Requirements: The desired range and azimuth resolution play a significant role in
determining the required signal bandwidth. Higher resolution typically requires wider
bandwidth.
4. Signal Processing Techniques: The choice of signal processing techniques, such as pulse
compression or frequency-modulated continuous-wave (FMCW), can influence the required
bandwidth. For example, FMCW radar typically uses a linear frequency sweep to determine
range and velocity, and the sweep bandwidth determines the resolution.
5. Interference and Clutter: The presence of interference and clutter in the radar environment
can also impact the required bandwidth. Wider bandwidth can help discriminate between
targets and unwanted signals.
6. Regulatory and Spectrum Allocation: Radar systems must comply with regulatory
requirements and spectrum allocations, which can limit the available bandwidth in certain
frequency bands.
7. Cost and Hardware Constraints: The cost and hardware limitations of the radar system can
influence the choice of bandwidth. Wideband systems often require more complex hardware
and may be more expensive.
As a result of these factors, the baseband signal bandwidth can range from kilohertz (kHz) to gigahertz
(GHz) in different radar applications. Specific examples would include:
  Weather radar systems may operate in the hundreds of megahertz (MHz) to several gigahertz
(GHz) range.
 Automotive radar systems typically operate in the 24 GHz or 77-81 GHz frequency bands with
bandwidths on the order of hundreds of megahertz.
 Military radar systems can have a wide range of bandwidths depending on their intended use,
from narrowband for tracking to wideband for surveillance.
To determine the appropriate baseband signal bandwidth for a specific radar application, it's essential
to conduct a detailed system design analysis, considering the factors mentioned above and the specific
requirements of the radar system. Simulations and modeling can also help optimize the bandwidth for
the desired performance.

>>
For UAVs, what is the range of baseband bandwidth?
>>
The range of baseband signal bandwidth for Unmanned Aerial Vehicles (UAVs) can vary widely
depending on the type of UAV, its mission, and the specific radar system employed. UAVs serve
various purposes, ranging from surveillance and reconnaissance to communication relay and scientific
research, each with its own radar requirements. Here are some general considerations:
1. Small UAVs (sUAVs): Small UAVs, often referred to as sUAVs or drones, are typically used
for tasks like aerial photography, monitoring, and inspection. Radar systems for these UAVs
tend to have lower bandwidth requirements. Baseband signal bandwidth for sUAV radar
systems might range from a few megahertz (MHz) to tens of megahertz.
2. Medium-sized UAVs: Medium-sized UAVs are more versatile and can support a wider range
of missions, including surveillance and reconnaissance. The baseband signal bandwidth for
radar systems on medium-sized UAVs might be in the range of tens of megahertz to a few
hundred megahertz.
3. Large UAVs: Large UAVs often have the capacity to carry more extensive radar systems,
allowing for a broader range of applications. Radar systems on large UAVs might have
baseband signal bandwidths that range from hundreds of megahertz to several gigahertz.
4. Military UAVs: Military UAVs can vary significantly in size and mission, but they frequently
require radar systems with wide bandwidths to support tasks such as target tracking, ground
mapping, and electronic warfare. Baseband signal bandwidth for military UAV radar systems
might range from hundreds of megahertz to several gigahertz.
5. Specialized UAVs: Some UAVs are designed for specific applications, such as scientific
research or environmental monitoring. The required baseband signal bandwidth for these UAVs
will depend on the scientific or data collection goals.
6. Spectrum Regulations: The choice of baseband signal bandwidth may also be influenced by
spectrum regulations and allocations, especially for UAVs operating in controlled airspace.
It's important to note that the bandwidth requirements for UAV radar systems are closely tied to the
specific radar application and mission objectives. The design of the radar system, including the choice
of waveform, modulation, and signal processing techniques, will influence the required bandwidth.
Additionally, considerations such as range resolution, target detection capabilities, and clutter rejection
play a role in determining the appropriate bandwidth.
Ultimately, the baseband signal bandwidth for a UAV's radar system should be carefully evaluated as
part of the overall system design to ensure it meets the mission's requirements while considering the
constraints of the UAV's payload capacity and power budget.

>>

Consider small UAV target detection by radar, as the

radar systems for these UAVs tend to have lower
bandwidth requirements. Baseband signal bandwidth for
sUAV radar systems might range from a few megahertz
(MHz) to tens of megahertz. Suggest commercial ADCs.
>>
For small UAV (sUAV) radar systems with lower baseband signal bandwidth requirements in the range
of a few megahertz (MHz) to tens of megahertz, you can consider several commercial ADCs (Analog-
to-Digital Converters) that offer suitable specifications for radar signal digitization. Here are a few
ADCs that may be suitable for your application:
1. Texas Instruments ADCs:
 ADS4249: This is a 14-bit, 250 MSPS (Mega Samples Per Second) dual-channel ADC
with a wide input bandwidth. It can digitize signals up to 125 MHz per channel and is
suitable for lower bandwidth radar applications.
2. Analog Devices ADCs:
 AD9250: This is a 14-bit, 250 MSPS ADC with a selectable input bandwidth. It offers
excellent SNR and SFDR performance and can be configured for lower bandwidth
operation.
3. Maxim Integrated ADCs:
 MAX12000: This is a 12-bit, 500 MSPS ADC with a wide input bandwidth. It can
handle input signals well beyond your specified bandwidth range and offers flexibility
for radar applications.
4. NXP Semiconductors ADCs:
 ADC12DJ3200: This is a high-speed, 12-bit, 3.2 GSPS ADC with a wide input
bandwidth. While it has high-speed capabilities, it can be configured for lower
bandwidth operation, making it suitable for radar applications.
5. Renesas Electronics ADCs:
 ISLA112P50: This is a 12-bit, 1.5 GSPS ADC with selectable input bandwidth. It
offers a wide range of options for bandwidth and resolution, making it adaptable to
various radar requirements.
 6. Microchip Technology ADCs:
 MCP37D31: This is a 16-bit, 250 kSPS (kilo Samples Per Second) ADC with a lower
speed, suitable for applications where lower bandwidth is sufficient.
When selecting an ADC, consider the following factors:
 Resolution: Choose an ADC with sufficient resolution based on your radar system's
requirements for dynamic range and accuracy.
 Sampling Rate: Ensure the ADC's maximum sampling rate is compatible with your radar's
bandwidth needs, and it can be configured to operate within the desired bandwidth range.
 SNR and SFDR: Look for ADCs with good Signal-to-Noise Ratio (SNR) and Spurious-Free
Dynamic Range (SFDR) performance to capture weak radar returns accurately.
 Power Consumption: Consider the power budget of your sUAV and choose an ADC that
meets your power constraints.
 Input Range: Ensure the ADC's input range can accommodate the amplitude of the radar
signals without clipping.
 Interface: Check that the ADC interface (parallel, serial, LVDS, etc.) is compatible with your
signal processing hardware.
It's essential to perform thorough testing and evaluation to confirm that the selected ADC meets your
specific radar system's performance and bandwidth requirements. Additionally, consider factors such
as cost, power consumption, and the overall system design when making your final selection.

Regards,
Nodal Institute CI & Co-CIs:
Dr, Chinthala Ramesh, ECE Dept, Amrita Vishwa Vidyapeetham, Bengaluru
Dr. Vivek Venugopal, ECE Dept, Amrita Vishwa Vidyapeetham, Bengaluru
Dr. Nijampatnam Neelima, ECE Dept, Amrita Vishwa Vidyapeetham, Bengaluru
Participating Institute CI:
Dr. Sarda, ECE Dept. Vignan University, Guntur, Andhra Pradesh
(21) Sarada Musala | LinkedIn

End user company:

RadSpan