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Assignment

The document summarizes exercises involving the design and implementation of finite state machines (FSMs) using logic gates and flip-flops. Specifically, it involves: 1) Designing a 3-bit counter that counts in a specified sequence using JK flip-flops and logic gates. 2) Minimizing a state table and drawing the corresponding state graph. 3) Implementing the state graph using D flip-flops and logic gates with a one-hot state encoding. 4) Representing an FSM with both Moore and Mealy outputs using an ASM chart. 5) Implementing a state graph using a 3-bit parallel loading counter.

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86 views7 pages

Assignment

The document summarizes exercises involving the design and implementation of finite state machines (FSMs) using logic gates and flip-flops. Specifically, it involves: 1) Designing a 3-bit counter that counts in a specified sequence using JK flip-flops and logic gates. 2) Minimizing a state table and drawing the corresponding state graph. 3) Implementing the state graph using D flip-flops and logic gates with a one-hot state encoding. 4) Representing an FSM with both Moore and Mealy outputs using an ASM chart. 5) Implementing a state graph using a 3-bit parallel loading counter.

Uploaded by

zahidjanjua160
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Exercise Ch.

4-6

1. Use a Decoder, JK flip-flops and/or any necessary logic gates to design a counter that counts
output “Z2Z1Z0”as the below sequence when input ‘w’ is high. (Hint: The counter holds its state
when input ‘w’ is low.) Write the truth table and draw the complete circuit diagram.

110 -> 000 -> 101 -> 011 -> 010


2. Minimize State Table. Construct the state table and draw the state graph after minimization.

Present State Next State Output (y) Output (z)


Input (x) = 0 Input (x) = 1
A F A 0 0
B A B 0 0
C D C 0 1
D A B 1 1
E D E 0 0
F E B 1 1
G C E 1 1
3. Implement the given state graph using D flip-flops and logic gates. Use a one-hot assignment. Write the
logic equations by inspecting the state graph. Draw the complete circuit diagram.
4. The Finite State Machine (FSM) has both Moore and Mealy outputs with one input ‘X’ as indicated in the
state diagram below. Represent this FSM in the form of an ASM chart.

5. A state graph for a single-input sequential circuit is given. Implement the circuit using a three-
bit parallel loading counter that has the given operation table. Label the counter outputs Q 2, Q1,
Q0, where Q0 is the least significant bit and the parallel inputs P2, P1, P0.
(Hint: Because the Ld signal overrides the Cnt signal, the counting sequence can easily be
changed by doing a parallel load at the appropriate times.)

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