I

I
I
I
I
I
I
I
I
I
WD37C65C
I
I
I
Floppy Disk Subsystem I
I
Controller Device I
I
I
I
I
I
I
I
I
I
I
I

• I
I
I
I

I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
S:2:E WESTERN DIGITAL I
I
I
I
I
I
I
 WD37C65C

TABLE OF CONTENTS
Section Title Page
1.0 INTRODUCTION 25-1
1.1 Features 25-1

2.0 SIGNAL DESCRIPTIONS 25-3

3.0 ARCHITECTURE 25-7

4.0 HOST INTERFACE 25-9

5.0 CONTROL REGISTER · 25-11

6.0 MASTER STATUS REGISTER · 25-13

6.1 Master Status Register 1 (MSR1--Write Only) · 25-13

7.0 DATA REGISTER · 25-19

8.0 OPERATIONS REGISTER · 25-20

9.0 BASE, SPECIAL, AND AT/EISA MODES · 25-21

9.1 Base Mode · 25-21
9.2 Special Mode · 25-21
9.3 AT/EISA Modes · 25-21

10.0 POLLING ROUTINE .25-22.

11.0 DEVICE RESETS · 25-23

12.0 DATA SEPARATOR · 25-24

13.0 WRITE PRECOMPENSATION · 25-25

14.0 CLOCK GENERATION .25-26

15.0 COMMAND PARAMETERS · 25-27

11/18/91 25-i
WD37C65C

Section Title Page

16.0 COMMAND DESCRIPTIONS .25-36
16.1 Read Data .25-36
16.2 Write Data .25-37
16.3 Write Deleted Data .25-37
16.4 Read Deleted Data .25-37
16.5 Read A Track .25-38
16.6 ReadlD .25-38
16.7 Format A Track .25-38
16.8 Scan Commands .25-39
16.9 Seek .25-40
16.10 Recalibrate .25-40
16.11 Sense Interrupt Status .25-41
16.12 Sense Drive Status .25-42
16.13 Invalid .25-42

17.0 DC ELECTRICAL SPECIFICATIONS .25-44

17.1 Maximum Ratings .25-44
17.2 Standard Test Conditions .25-44
17.3 DC Operating Characteristics .25-45

18.0 AC TIMING CHARACTERISTICS .25-46

25-ii 11/18/91
 WD37C65C

LIST OF ILLUSTRATIONS
Figure Title Page

3-1 WD37C65C Block Diagram ....... . 25-7

3-2 Typical WD37C65 System ....... . 25-8
9-1 Flow Diagram Base, Special, and AT/EISA Modes · 25-21
10-1 Drive Select Polling Timing . . . . . . .25-22
13-1 WD92C32 Simplified Block Diagram . . · 25-25
14-1 Crystal Oscillator Circuits for 44-Pin PLCC · 25-26
16-1 Seek, Recalibrate, and Sense Interrupt · 25-42
16-2 WD37C65C FM Mode Format · 25-43
16-3 WD37C65C MFM Mode Format · 25-43
18-1 Read Timing · 25-48
18-2 Write Timing · 25-48
18-3 DMATiming · 25-49
18-4 Terminal Count Timing · 25-49
18-5 Reset Timing · 25-50
18-6 Disk Drive Timing · 25-50
18-7 Clock Timing · 25-51

II

11/18/91 25-iii
WD37C65C

LIST OF TABLES
Table Title Page

5-1 Control Register Configuration -16 MHz . 25-11

5-2 Control Register Configuration -32 MHz . 25-11
5-3 Control Register Configuration -Options .25-12
5-4 Control Register Configuration -AT/EISA Mode .25-12
6-1 AT/EISA Mode. Master Status Register 1 Config. .25-13
6-2 Master Status Register Bits .25-14
6-3 Status Register 0 Bits .25-15
6-4 Status Register 1 Bits .25-16
6-5 Status Register 2 Bits .25-17
6-6 Status Register 3 Bits .25-18
7-1 Master Status and Data Registers Relationships .25-19
8-1 Operations Register .25-20
14-1 Clock Data Rate . . . .25-26
15-1 WD37C65C Commands .25-27
15-2 Read Data .25-27
15-3 Read Deleted Data .25-28
15-4 Write Data .25-28
15-5 Write Deleted Data .25-29
15-6 Read a Track .25-29
15-7 ReadlD .25-30
15-8 Format a Track .25-30
15-9 Scan Equal . .25-31
15-10 Scan Low or Equal .25-31
15-11 Scan High or Equal .25-32
15-12 Recalibrate .25-32
15-13 Sense Interrrupt Status .25-32
15-14 Specify . . . . . .25-33
15-15 Sense Drive Status . . .25-33
15-16 Seek ...... . .25-33
15-17 Command Symbol Descriptions .25-34
16-1 Transfer Capacity .25-36
16-2 C, H, R, and N Values . . . .25-37
16-3 N, SC, and GPL Relationship .25-39
16-4 Status of Bits SH and SN .25-40
16-5 Interrupt Cause ..... .25-41
16-6 Difference Between WD37C65/AiB and WD37C65C .25-43

25-iv 11118/91
INTRODUCTION WD37C65C

1.0 INTRODUCTION
The WD37C65C Floppy Disk Subsystem Control- Register provides support logic that latches the
ler is an LSI device that provides all the needed two LSBs used to select the desired data rate that
functionality between the host processor and the controls internal clock generation. The Operations
floppy disk drive. This "superchip" integrates the Register replaces the standard latched port used
following functions: formatter/controller, data in floppy subsystems. These registers are incor-
separation, write precompensation, data rate porated into the WD37C65C.
selection (to a maximum of 1Mbit per second),
and clock generation. It also provides interface All Clock Generation: SCLK - Sampling Clock,
drivers and receivers for the floppy drive. WCLK-Write Clock, and MCLK - Master Clock,
are included in the WD37C65C. XTAL oscillator
The WD37C65C is functionally compatible pin-for- circuits provide the necessary signals for internal
pin with the WD37C65A/B. In addition the timing when using the 44 pin PLCC. If the 40 pin
WD37C65C supports a power down mode for lap- DIP is used, the TTL level clock inputs must be
top and portable systems. Refer to Table 16-6 for provided. There are two oscillator inputs to the
a descripion of functional differences between the WD37C65C. The first at 32 MHz that handles all
WD37C65A!B and the WD37C65C. standard data rates (1MB/sec, 500, 250, and 125
kb/sec or 16MHz to handle 500, 250, and 125
On the disk drive interface, the WD37C65C in- Kb/sec). The second oscillator is at 9.6 MHz to
cludes data separation designed to address high support the 300 kb/sec data rate used in PC AT
performance error rates on floppy disk drives. It designs.
contains all the necessary logic to achieve classi-
cal 2nd order, type 2, phase locked loop perfor- Some AT compatibles use two-speed disk drives.
mance. Write precompensation is included, in ad- If a two-speed disk drive is used, the DRV input
dition to the usual formatting, encoding/decoding, should be grounded along with the CLK2 input.
stepper motor control, and status sensing func-
tions. All inputs are TTL compatible Schmitt Trig-

•
ger line receivers, and outputs are high current, 1.1 FEATURES
open drain, with 48 rnA drivers which meet the
ANSI specification. • IBM PC AT compatible format (single and
double density)
The host interface supports an 8 or 12 MHz, 286 -Provides "on chip" floppy control and
microprocessor bus without the use of wait states. operations
The inputs are Schmitt Triggers. Output drive -Provides required signal qualification to
capability is 20 LSTTL loads, allowing direct inter- DMA channel when in PC AT mode
connection to bus structures without the use of
-BIOS compatible
buffers or transceivers. For PC, PC AT and EISA
applications, qualification of interrupt request and -Supports dual speed spindle drives
DMA request is provided. • CMOS low power consumption (typically 300
mW at 32 MHz)
Traditionally, data rate selection, drive selection, • Power down mode with low standby current
and stepper motor control have been output ports (ICC = 100!!A maximum)
of the host processor architecture. In the
• Address mark detection circuitry (internal to
WD37C65C, these functions are latched into
floppy disk controller)
registers addressed within the I/O mapping of the
system. The WD37C65C has eight internal • Multi-sector and multi-track transfer capability
registers. The eight bit main status register con- • Direct floppy disk drive interface (no buffers
tains status information about the WD37C65C needed)
and may be accessed any time. Another four -48 rnA sink output drivers
status registers under system control also give
-Schmitt Trigger line receivers
various status and error information. The Control

Reprinted with permission of and licensed by NEC Electronics Inc. © 1985 NEC Electronics Inc.

11/18/91 25-1
WD37C65C INTRODUCTION

• Compatible with PD8080/85, PD8086, 8088,

80286, 80386SX, 80386, and PD780 (Z80)
AD 40 VCC
microprocessors
WR 2 39 IDX
On chip clock generation CS 3 38 TROO
• Two TTL clock inputs for 40-pin DIP AO 4 37 WP
DACK 5 36
- --
RWC, RPM
• Two XTAL oscillator circuits for 44-pin PLCC
TC 6 35 HDL
- ---
• Automatic write precompensation DBO 7 34 M02, DS4
-Disable option DB1 8 33 M01, DS3
-Pin selectable inner track values of 125 or DB2 9 32 DS2
187 nanoseconds DB3 10 31 VSS
• Integrated high-performance DPLL data DB4 11 30 DS1
separator DB5 12 29 STEP
-Industry standard error rates of 10<E-9 DB6 13 28 DIRC
DB7 14 27 WD
-Data rates of 125, 250, 300, 500
DMA 15 26 WE
Kbits/second and 1MbiVsecond
IRQ 16 25 HS
-Option to select 150 Kbits/second FM and LDOR 17 24 PC VAL
300 Kbits/second MFM data rates only LDCR 18 23 CLK1
• Enhanced host interface RST 19 22 DRV
-20 LSTTL output drive capability RDD 20 21 CLK2
-TTL Schmitt trigger inputs
• User programmable track stepping rate and 40 PIN DIP
head load/unload times
• Supports four floppy or Micro Floppydisk drives
with·external decode logic
• Data transfer in DMA or non-DMA mode
• Parallel seek operation on a maximum of four
drives
• Internal power up reset circuitry
• Single +5V DC power supply
DBO
DB1
• 39
38
RWC, RPM
HDL
DB2 37 M02, DS4
DB3 36 M01, DS3
DB4 35 DS2
DB5 34 VSS
DB6 33 DS1
DB7 32 STEP
DMA 31 DIRC
IRQ 30 WD
DCHGEN 29 WE
1819202122232425262728

44 PIN PLCC

25-2 11118191
SIGNAL DESCRIPTIONS WD37C65C

2.0 SIGNAL DESCRIPTIONS

DIP PIN MNEMONIC SIGNAL NAME I/O FUNCTION

NUMBER
1 /1 RD READ Control signal for transfer of data or status onto the
data bus by the WD37C65C.

212 WR WRITE Control signal for latching data from the bus into the
WD37C65C Buffer Register.

3/3 CS CHIP SELECT

- -
Selected when 0 (low) allowing RD or WR operation
from the host.

4/4 AO ADDRESS LINE Address line selecting data e.:!l or status (=0) infor-
mation. (AO = logic 0 during WR is illegal except in
Power Down mode.)

5/5 DACK DMA Used by the DMA controller to transfer data from
ACKNOWLEDGE the W037C65C onto the bus. Logical equivalent to
CS and AO=1. In Special or AT/EISA mode, this sig-
nal is qualified by DMAEN from the Operations
Register.

6/6 TC TERMINAL- This signal indicates to WD37C65C that data trans-

COUNT fer is complete. If DMA operational mode is selected
for command execution, TC will be qualified by
DACK, but not in the programmed I/O execution. In
AT/EISA or Special mode, qualification by DACK re-
quires the Operations Register signal DMAEN to be
logically true. Note also that in AT/EISA mode, TC
will be qualified by DACK, whether in DMA or non-
DMA host operation. Programmed I/O in AT/EISA
mode will cause an abnormal termination error at
the completion of a command.
II
7-14/ DBO thru DATA BUS 0 thru I/O 8-Bit, bi-directional, tri-state, data bus. DO is the
7-14 DB7 DATA BUS 7 least significant bit (LSB). 07 is the most significant
bit (MSB).

15/15 DMA DIRECT 0 DMA request for byte transfers of data. In Special or
MEMORY AT/EISA mode, this pin is tri-stated, enabled by the
ACCESS DMAEN signal from the Operations Register. This
pin is driven in the Base mode.

16/16 IRQ INTERRUPT 0 Interrupt request indicating the completion of com-

mand execution or data transfer requests (in non-
DMA mode). Normally driven in base mode. In Spe-
cial or AT/EISA mode, this pin is tri-stated, enabled
by the DMAEN signal from the Operations Register.

*Only in the PLCC version of the WD37C65C. Not connected in the DIP package.

11/18/91 25-3
WD37C65C SIGNAL DESCRIPTIONS

D/P PIN MNEMONIC SIGNAL NAME I/O FUNCTION

NUMBER
/17 DCHGEN* DISK CHANGE This input must be at Logic = 0 to enable DCHG
ENABLE input status at pin 40 to be placed on bit 7 of the
data bus during a RD = 0 of LDCR = o. It has Inter-
nal pull-up.

17/18 LDOR LOAD Address decode which enables the 10adin.flQ!.the

OPERATIONS Operations Register. Internally gated with WR
REGISTER creates the strobe which latches the data bus into
the Operations Register.

18/19 LDCR LOAD CONTROL Address decode which enables loading of the Con-
REGISTER trol Register. Internally gated with WR creates the
strobe which latches the two LSBs from the data
bus into the Control Register.

19/20 fiST RESET Resets controller, placing microsequencer in idle.

Resets device outputs. Puts device in Base mode,
not PC AT or Special mode.

20/21 RDD READ DISK This is the raw serial bit stream from the disk drive.
DATA Each falling edge of the pulses represents a flux
transition of the encoded data.

21/ CLK2 CLOCK2 TTL level clock input used for non-standard data
rates; is 9.6MHz for 300 kb/s, and can only be
selected from the Control Register.

/22 XT2 XTAL2 0 XTAL oscillator drive output for 44 pin PLCC (See
Figure 6). Should be left floating if TTL inputs used
at pin 23.

/23 XT2 XTAL2 XTAL oscillator input used for non-standard data
rates. It may be driven with a TTL level signal.

22/24 DRV DRIVE TYPE Drive type input indicates to the device that a
twospeed spindle motor is used if logic is o. In that
case, the second clock input will never be selected
and must be grounded.

23/ CLK1 CLOCK1 TTL level clock input is used to generate all internal
timings for standard data rates. Frequency must be
16MHz ± 0.1% or 32MHz ± 0.1%, and may have
40/60 or 60/40 duty cycle.

/25 XT1 XTAL1 0 XTAL oscillator drive output for 44 pin PLCC (See
Figure 6). Should be left floating if TTL inputs are
used at pin 26.

/26 XT1 XTAL1 XTAL oscillator input requiring 16MHz or 32M Hz

crystal. This oscillator is used for all standard data
rates, and may be driven with a TTL level signal.

·Only in the PLCC version of the WD37C65C. Not connected in the DIP package.

25-4 11/18/91
SIGNAL DESCRIPTIONS WD37C65C

DIP PIN MNEMONIC SIGNAL NAME 1/0 FUNCTION

NUMBER
24/27 PCVAL PRECOMPEN- Precompensation value select input. This pin deter-
SATIONVALUE mines the amount of write precompensation used
on the inner tracks of the diskette. Logic 1 = 125ns,
Logic 0 = 187ns. If the defeat option is used,
PCVAL is unimportant and precompensation is dis-
abled.

25/28 HS HEAD SELECT 0 High current driver (HCD) output selects the head
(side) of the floppy disk that is being read or written.
Logic 1 = side O. Logic 0 = side 1.

26/29 WE WRITE ENABLE 0 This HCD output becomes true, active low, just prior
to writing on the diskette. This allows current to flow
through the write head.

27/30 WD WRITE DATA 0 This HCD output is WRITE DATA. Each falling edge
of the encoded data pulse stream causes a flux tran-
sition on the media.

28/31 DIRC DIRECTION 0 This HCD output determines the direction of the
head stepper motor. Logic 1 = outward motion.
Logic 0 = inward motion.

29/32 STEP STEP PULSE 0 This HCD output issues an active low pulse for
each track to track movement of the head.

30/33 DS1 DRIVE SELECT 1 0 This HCD output, when active low, is DRIVE
SELECT 1 in AT/EISA mode. It enables the inter-
face to this disk drive. This signal comes from the
Operations Register. In Base, or Special mode, this
output is #1 of the four decoded Unit Selects, as
specified in the device command syntax.
II
31/34 VSS GROUND -- Ground.

32135 DS2 DRIVE SELECT 2 0 This HCD output, when active low, is DRIVE
SELECT 2 in AT/EISA mode, enables the interface
to this disk drive. This signal comes from the Opera-
tions Register. In Base or the Special mode, this out-
put is #2 of the four decoded Unit Selects as
specified in the device command syntax.

33/36 M01, DS3 MOTOR ON 1, 0 This HCD output, when active low, is MOTOR ON
DRIVE SELECT 3 enable for disk drive #1, in AT/EISA mode. This sig-
nal comes from the Operations Register. In the
Base or Special mode, this output is #3 of the four
decoded Unit Selects as specified in the device
command syntax.

*Only in the PLCC version of the WD37C65C. Not connected in the DIP package.

11/18191 25-5
WD37C65C SIGNAL DESCRIPTIONS

D/P PIN MNEMONIC SIGNAL NAME I/O FUNCTION

NUMBER
34/37 M02,DS4 MOTOR ON 2, 0 This HCD output, when active low, is MOTOR ON
DRIVE SELECT 4 enable for disk drive #2, in AT/EISA mode. This sig-
nal comes from the Operations Register. In the
Base or Special mode, this output is #4 of the four
decoded Unit Selects as specified in the device
command syntax.

35/38 HDL HEAD LOADED 0 This HCD output, when active low, causes the head
to be loaded against the media in the selected drive.

36/39
- ---
RWC, RPM REDUCED 0 This HCD out~ut, when active low, causes a
WRITE REDUCED WRITE CURRENT, when bit density is
CURRENT, increased toward the inner tracks, becoming active
REVOLUTIONS when tracks >28 are accessed. This condition is
PER MINUTE valid for Base or Special mode, and is indicative of
when write precompensation is necessary. In the
AT/EISA mode, this signal will be active when
CRO=1.

/40 DCHG* DISK CHANGE This Schmitt Trigger (ST) input senses status from
the drive. Active low indicates that drive door is
open or that the diskette has possibly changed
since the last drive selection. It has internal pull-up.

37/41 WP WRITE This ST input senses status from the disk drive in-
PROTECTED dicating active low when a diskette is WRITE
PROTECTED.

38/42 TROO TRACK 00 This ST input senses status from disk drive, indicat-
ing active low when the head is positioned over the
outermost track, TRACK 00.

39/43 lOX INDEX This ST input senses status from the disk drive, in-
dicating active low when the head is positioned over
the beginning of a track marked by an index hole.

40/44 VCC +5VDC -- Input power supply.

'Only in the PLCC version of the WD37C65C. Not connected in the DIP package.

25-6 11/18/91
ARCHITECTURE WD37C65C

3.0 ARCHITECTURE
The WD37C65C Floppy Disk Subsystem Control- Figure 3-1 illustrates a block diagram of the
ler is an LSI device that provides all the needed WD37C65C Floppy Disk Subsystem Controller.
functionality between the host processor and the
floppy disk drive. This "superchip" integrates: for- Figure 3-2 illustrates a typical WD37C65C sys-
matter/controller, data separation, write precom- tem.
pensatioh, data rate selection, clock generation,
drive interface drivers and receivers.

8 BIT
DATA
BUS

-I[--+--+~

•
DRV Fffi
RiSL
STEP
ROM 5iiiC
1K X 16 RWC
001-4
AO
fRoii
DACR iDx
TC
'----r-~- WP
DMA
IRQ iSCFiG'
[iiCR
050R
L-~-+----------------~mID
CLK1
'-----------------~WE

CLK2 WRITE WD
PRECOMPENSATION PCVAL

'PLCC version of WD37CB5C only

FIGURE 3-1. WD37C65C BLOCK DIAGRAM

11/18/91 25-7
WD37C65C ARCHITECTURE

+ 5V

(/)
WD37C65C
::l
m ... 40 VCC WE 26
...J
WD 27
~
w
1 RD
STEP 29 a:
:r 2 WR w
Q. DIRC 28 ...I
[[ 4 AO ...I
HDL 35 0
w 16 IRQ a:
Q. HS 25 I-
19 RST z
Q.
7-14.DBO-DB7 -
DS130 8
::l
w
DS232 (.)
§ 15DMA DS3-M01 33 if
a:
:r w
5 DACK DS4-M0234 I-
RWC-RPM 36 ~
6 TC
>
a:
0
ROD 20
..A w
(/)a:
(/)w
wo 3 CS WP 37
:1 Q.
~
a:o 0
0(,) 17 LDOR
Il')
oq-
ow TROO 38
<0 18 LDCR (}j
lOX 39
Lsv
GN..!lL - 22DRV DCHG 40
t + sv

~
GN..!lL -
24 PCVAL VSS 31
... Indicates
CLOCK 23 CLK1 '!I' 150 ohm
CKTS 21 CLK2 'pull-up
PLCC version of WD37C65 only.

FIGURE 3·2. TYPICAL WD37C65 SYSTEM

25-8 11/18/91
HOST INTERFACE WD37C65C

4.0 HOST INTERFACE

The host interface is the Host Microprocessor Note that in the non-DMA mode it is necessary to
Peripheral Bus. This bus is composed of eight examine the Main Status Register to determine
control signals and eight data signals. In the Spe- the cause of the interrupt since it could be a data
cial or AT/EISA modes, IRQ and DMA request are interrupt or a command termination interrupt,
tri-stated and qualified by DMA enable which is either normal or abnormal. If the WD37C65C is in
provided by the Operations Register. The data the DMA mode, no interrupt signals are generated
bus, DMA, and I RQ outputs are designed to hand- during the Execution phase. The WD37C65C
le 20 LSTTL loading. Inputs are Schmitt Trigger generates DMA's (DMA Requests) when each
receivers and can be hooked up to a bus or back- byte of data is available. The DMA Controller
plane without any additional buffering. responds to this request with both DACK=O (DMA
Acknowledge) and an RD=O (Read signal). When
During the Command or Result phases, the Main the DMA Acknowledge signal goes low
Status Register must be read by the processor (DACK=O), the DMA Request is cleared (DMA=...Ql
before each byte of information is written into or If a Write Command has been issued, then a WR
read from the Data Register. After each byte of signal will appear instead of RD. After the Execu-
data is read from or written into the Data Register, tion phase has been completed (Terminal Count
the CPU waits for 12 Ils before reading the Main has occurred) or the EOT sector read/written,
Status Register. Bits 06 and 07 in the Main then an Interrupt will occur (I RQ = 1). This sig-
Status Register must be in a 0 and 1 state, nifies the beginning of the Result phase. When
respectively, before each byte of the command the first byte of data is read during the Result
word may be written into the WD37C65C. Many of phase, the interrupt is automatically cleared (IRQ
the commands require multiple bytes. As a result, = 0).
the Main Status Register must be read prior to
each byte transfer to the WD37C65C. During the Note that in PC AT usage, non-DMA Host trans-
Result phase, Bits 06 and 07 in the Main Status fers are not the normal procedure. If the user
Register must both be 1's (06=1 and 07=1) chooses to do so, the WD37C65C will successful-
before reading each byte from the Data Register. ly complete commands, but will always give ab- , .
Note that this reading of the Main Status Register normal termination error status since TC is·
before each byte transfer to the WD37C65C is qualified by an inactive DACK.
required only in the Command and Result
phases, and not during the Execution phase. Note The RD or WR signals should be asserted while
also that DB6 and DB7 in the MSR can be polled DACK is true. The CS signal is used in conjunc-
instead of waiting 121ls. tion with RD and WR as a gatl!:!g function during
programmed I/O operations. CS has no effect
During the Execution phase, the Main Status durinq DMA operations. If the non-DMA mode is
Register need not be read. If the WD37C65C is in chosen, the DACK signal should be pulled up to
the non-DMA Mode, then the receipt of each data Vcc. Note that during the Result phase all bytes
byte (WD37C65C is reading data from the FDD) shown in the Command Table must be read. The
is indicated by an interrupt signal on P!!:LJ 6 Read Data Command, for example, has several
(IRQ=1). The generation of a Read signal (RD = bytes of data in the Result phase. All seven bytes
0) clears the interrupt and sends the data onto the must be read in order to successfully complete
data bus. If the processor cannot handle inter- the Read Data command. The WD37C65C will
rupts fast enough (every 13 ILs for the MFM mode not accept a new command until all seven bytes
and 27 I!S for the FM mode), then it may poll the have been read. Other commands may require
Main Status Register and bit 07 (RQM) functions fewer bytes to be read during the Result phase.
as the Interrupt si9r:@1. If a Write Command is in The WD37C65C contains five Status Registers.
process then the WR signal performs the reset to The Main Status Register mentioned may be read
the Interrupt signal. by the processor at any time. The other four
Status Registers (STO, ST1, ST2, and ST3) are
All timings mentioned above double for mini flop- available only during the Result phase and may
py data rates. be read only afler completing a command. The
particular command that has been executed

11/18/91 25-9
WD37C65C HOST INTERFACE

determines how many of the Status Registers will No foreshortening of the Command or Result
be read. phases is allowed. After the last byte of data in the
Command phase· is sent to the WD37C65C, the
The bytes of data which are sent to the Execution phase automatically starts. In a similar
WD37C65C to form the Command phase, and are fashion, when the last byte of data is read out in
read out of the WD37C65C in the Result phase, the Result phase, the command is automatically
must occur in the order shown in the Command ended and the WD37C65C is ready for a new
Table. The command code must be sent first and command.
the other bytes sent in the prescribed sequence.

25-10 11118191
CONTROL REGISTER WD37C65C

5.0 CONTROL REGISTER

The Control Register is a write only register that is is used. Switching of this clock must be "glitch-
used to set the data transfer rate and disable write less" or the device will need to be reset. Table 5-1
precompensation. It provides support logic that and Table 5-2 present the Control Register con-
latches the two..1§.8§...Qf the data bus upon receiv- figuration for 16 MHz and 32 MHz frequencies,
ing LDCR and WR. CS should not be active when respectively.
this happens. These bits are used to select the
desired data rate, which in turn controls the inter- The WD37C65C optionally supports 150 kb/s FM
nal clock generation. Clock switchover is internal- data transfer rate. The Control Register configura-
ly "deglltched," allowing continuous operation tion is shown in Table 5-3. The 150 kb/s data rate
after changing data rates. If the Control Register can be selected by using a 9.6 MHz XTAL or TTL
is not used, the data rate is governed by the sup- level clock input on pin 26 (44pin PLCC) or pin 23
plied clock or crystal. The frequency must be 64 (40 pin DIP). Only two data transfer rates can be
times the desired MFM data rate. This implies a selected with this configuration: 150 kb/s FM and
maximum data rate of 250 kb/s for a frequency of 300 kb/s MFM.
16 MHz or a maximum data rate of 500 Kb/s for a
frequency bf 32 MHz, unless the Control Register

CR1 CRO DRV DATA RATE COMMENTS RPM

[{AT/EISA MODE}
0 0 x 500 K MFM 1
0 0 x 250 K FM 1
0 1 0 250 K MFM 0
0

1
1
1

0
0
1

x
x
300

250 K
125 K
K MFM,(9.6 MHz XTAL} 0

MFM, RST Default

FM, RST Default
TABLE 5-1. CONTROL REGISTER CONFIGURATION -16 MHZ
1
1 •
CR1 CRO DRV DATA RATE COMMENTS RPM
(AT/EISAMODE)
0 0 x 1M MFM 1
0 0 x 500 K FM 1
0 1 0 900 K MFM 0
0 1 1 300 K MFM,(9.6 MHz XTAL} 0

1 0 x 500 K MFM, RST Default 1

TABLE 5-2. CONTROL REGISTER CONFIGURATION - 32 MHz

11118191 25-11
WD37C65C CONTROL REGISTER

In AT/EISA mode, write precompensation can be

disabled by a logic high on bit 2 of the Control
Register. (See Table 5-4).

CR1 CRO DRV DATA RATE COMMENTS RPM

I(AT/EISA MODE)
0 0 x 300 K MFM 1
0 0 x 150 K FM 1
TABLE 5-4. CONTROL REGISTER CONFIGURATION - OPTIONS

Bit SIGNAL NAME AND RESET CONDITION CLOCK QUALIFIER

FUNCTION
0 Data Rate 0 None
1 Data Rate 0 None
2 No Write Precompensation 0 None
3-7 Reserved None None
TABLE 5-3. CONTROL REGISTER CONFIGURATION - AT/EISA MODE

25-12 11/18/91
MASTER STATUS REGISTER WD37C65C

6.0 MASTER STATUS REGISTER

The Master Status Register is an eight-bit, in Table 6-2.The bits in Status. Register 1 are
read/write register that contains the status infor- listed in Table 6-3.The bits in Status Register 2
mation of the FOC. It can be accessed at any are listed in Table 6-4.The bits in Status Register
time. The W035C65C provides a write only 3 are listed in Table 6-5.
register, called Master Status Register 1 (MSR1)
which is used only to select power down mode. In
power down mode the XTAL oscillator, controller 6.1 MASTER STATUS REGISTER 1
circuitry and all linear circuitry are turned off so (MSR1-WRITE ONLy)
that the controller draws very low current. Normal
operation is restored by asserting reset to the The W037C65C will enter power down mode,
W037C65C. See Master Status Register 1. when bit 0 of MSR1 is set to logical "1" and the
following conditions are met:
Only the Master Status Register may be read and
used to facilitate the transfer of data between the 1. The RST pin to the FOC is inactive.
processor and W037C65C. The 010 and ROM
bits in the Master Status Register indicate when 2. Bit 2 in the Operations Register is "SRST/= 1".
data is ready and in which direction data will be
transferred on th~ata-...lli!s. The maximum time 3. The W037C65C is awaiting a command from
between the last RO or WR during a Command or the host.
Result phase and the setting of 010 and ROM is
12 Ils if 500 kb/s MFM data rate is selected. (If The W037C65C can also be programmed with
250 kb/s MFM is selected, the delay is 24 Ils. If 1 external logic to automatically enter power down
Mb/s is selected, the delay is 6 IlS.) For this mode a few msec after the beginning of idle
reason, every time the Master Status Register is mode.
read, the CPU should wait 12 Ils. The maximum
time from the trailing edge of the last RO in the
result phase to when OB4 (FOC busy) goes low is
12 Ils.

The bits in the Master Status Register are listed in

Table 6-1. The bits in Status Register 0 are listed
Normal operation is restored when the RST pin to
the FOC is active and the FOC is reset. This in
turn resets bit 0 of MSR1 register to logic o.
The bits in the Master Status Register are listed in
Table 6-2.
..
BIT SIGNAL NAME & RESET CONDITION CLOCK QUALIFIER
FUNCTION
0 Power down mode (POM) 0 None
1-7 Reserved None None
TABLE 6-1. AT/EISA MODE. MASTER STATUS REGISTER 1 CONFIG.

11/18/91 25-13
WD37C65C MASTER STATUS REGISTER

BIT
NO. NAME SYMBOL DESCRIPTION

DBO FDD o BUSY DOB FDD number is 0 in the Seek Mode. If any of the
bits is set, FDC will not accept READ or WRITE
commands.

DB1 FDD 1 BUSY D1B FDD number 1 is in the Seek Mode. If any of the
bits is set, FDC will not accept READ or WRITE
commands.

DB2 FDD 2 BUSY D2B FDD number 2 is in the Seek Mode. If any of the
bits is set, FDC will not accept READ or WRITE
commands.

DB3 FDD 3 BUSY D3B FDD number 3 is in the Seek Mode. If any of the
bits is set, FDC will not accept READ or WRITE
commands.

DB4 FDC BUSY CB A READ or WRITE command is in progress. FDC

will not accept any other command.

DB5 EXECUTION EXM This bit is set only during Execution phase in non-
MODE DMA mode. When DB5 goes low Execution phase
has ended and Results Phase has started. It
operates only during non-DMA mode of operation.

DB6 DATA INPUT DIO Indicates direction of data transfer between FDC
and Data Register. If D10=1, then transfer is from
Data Register to the processor. If DIO=O, then trans-
fer is from the pr~cessor to Data Register.

DB? REOUESTFOR ROM Indicates Data Register is ready to send or receive

MASTER data to or from the processor. Both bits DIO and
ROM should be used to perform the handshaking
functions of "ready" and "'direction" to the processor.

TABLE 6-2. STATUS REGISTER 0 BITS

25-14 11/18/91
MASTER STATUS REGISTER WD37C65C

BIT
NO. NAME SYMBOL DESCRIPTION

D7 INTERRUPT IC D7=0 and D6=0. Normal termination of command

CODE was completed and properly executed. D7=0 and
D6=1. Abnormal termination of command, (AT). Ex-
ecution of command was started but was not suc-
cessfully completed.

D6 D7=1 and D6=0. Invalid command issue, (IC). Com-

mand which was issued was never started.

D5 SEEK END SE When the FDC completes the SEEK command, this
flag is set to 1 (high).

tD4 EQUIPMENT EC If the Track 0 signal fails to occur after 77step pul-
CHECK ses per Recalibrate Command, then this flag is set.

tD3 NOT READY NR Since drive Ready is always presumed true, this will
always be a logic O.

D2 HEAD SELECT HS This flag is used to indicate the state of the head at
interrupt.

01 UNIT SELECT 1 US1 This flag is used to indicate a Drive Unit Number at
interrupt.

DO UNIT SELECT 0 USO This flag is used to indicate a Drive Unit Number at
interrupt.

TABLE 6-3. STATUS REGISTER 1 BITS

11118191 25-15
WD37C65C MASTER STATUS REGISTER

BIT
NO. NAME SYMBOL DESCRIPTION

D7 END OF EN When the FDC tries to access a sector beyond the

CYLINDER final sector of a cylinder, this flag is set.

D6 Not used. This bit is always 0 (low).

D5 DATA ERROR DE When the FDC detects a 'CRC error in either the ID
field or the data field, this flag is set.

D4 OVERRUN OR If the FDC is not serviced by the host system duriOig

data transfers within a certain time interval, this flag
is set.

D3 Not used. This bit is always 0 (low).

D2 NO DATA ND During execution of READ DATA, WRITE

DELETED DATA, or SCAN command, if the FDC
cannot find the sector specified in the "IDR
Register, this flag is set.

During execution of the READ ID command, if the

FDC cannot read the ID field without an error, then
this flag is set.

During execution of the READ A TRACK command,

if the starting sector cannot be found, then this flag
is set.

D1 NOT WRITEABLE NW During execution of WRITE DATA, WRITE

DELETED DATA or FORMAT A TRACK commands,
if the FDC detects a WP signal from the FDD, then
this flag is set.

DO MISSING MA If the FDC cannot detect the ID Address Mark after

ADDRESS MARK encountering the index hole twice, then this flag is
set.

If the FDC cannot detect the Data Address Mark or

Deleted Data Address Mark, this flag is set. At the
same time the MD (Missing Address Mark in data
field) of Status Register 2 is set.

TABLE 6-4. STATUS REGISTER 2 BITS

25-16 11/18/91
MASTER STATUS REGISTER WD37C65C

BIT
NO. NAME SYMBOL DESCRIPTION
D7 Not Used. This bit is always 0 (low).
D6 CONTROL MARK CM During execution of the READ DATA or SCAN Com-
mand, if the FDC encounters a sector which con-
tains a Deleted Data Address Mark, this flag is set.
D5 DATA ERROR DD If the FDC detects a CRC error in the data field,
then this flag is sel.
D4 WRONG WC This bit is related to the ND bit, and when the con-
CYLINDER tents of •• ·C on the medium is different from that
stored in the IDR, this flag is set.
D3 SCAN EQUAL SH During execution of the SCAN command, if the con-
dition of "equal" is satisfied, this flag is sel.
D2 SCAN NOT SN During execution of the SCAN command, if the
FDC cannot find a sector on the cylinder which
meets the condition, then this flag is set.
D1 BAD CYLINDER BC This bit is related to the ND bit, and when the con-
tents of C on the medium is different from that
stored in the IDR and the contents of C is FF, then
this flag is set.
DO MISSING MD When data is read from the medium, if the FDC can-
ADDRESS MARK not find a Data Address Mark or Deleted Data Ad-
IN DATA FIELD dress Mark, then this flag is set.

~----------'. TABLE 6-5. STATUS REGISTER 3 BITS

11118/91 25-17
 WD37C65C MASTER STATUS REGISTER

BIT
NO. NAME SYMBOL DESCRIPTION
tD? Not used. Will always be logic o.
D6 WRITE WP This bit is used to indicate the status of the WRITE
PROTECTED PROTECTED signal from the FDD.
tD5 READY RY This bit will always be a logic 1. Drive is presumed
to be ready.
D4 TRACK 0 TO This bit is used to indicate the status of the Track 0
signal from the FDD.
tD3 WRITE WP This bit is used by the WD3?C65C to indicate the
PROTECTED status of the WRITE PROTECTED signal from the
FDD.
D2 HEAD SELECT HS This bit is used to indicate the status of the Side
Select signal to the FDD.
D1 UNIT SELECT 1 US1 This bit is used to indicate the status of the Unit
Select 1 signal to the FDD.
DO UNIT SELECT 2 USO This bit is used to indicate the status of the Unit
Select 0 signal to the FDD.

TABLE 6-6. MASTER STATUS REGISTER BITS

* CRC - Cyclic Redundancy Check * * * C - Cylinder

. * * lOR - Internal Data Register t - Different from NEC765

25-18 11/18/91
DATA REGISTER WD37C65C

7.0 DATA REGISTER

The eight-bit Data Register stores data, com- The relationship between the Master Status
mands, parameters, and FDD status information. Register and the Data Register' and the signals
Data bytes are read out of, or written into, the RD, WR, and AO are shown in Table 7-1.
Data Register in order to program or obtain the
results after a particular command.

AO RD WR FUNCTION
0 0 1 Read Main Status Register
0 1 0 Illegal
0 0 0 Illegal
1 0 0 Illegal
1 0 1 Read from Data Register
1 1 0 Write into Data Reaister
TABLE 7-1. MASTER STATUS AND DATA REGISTERS RELATIONSHIPS

11/18/91 25-19
WD37C65C OPERATIONS REGISTER

8.0 OPERATIONS REGISTER

The Operations Register provides supportJQg!Q to control disk drive spindle motors and to select
that latch~the data bus upon receiving LDOR the desired disk drive. Table 8-1 represents the
and WR. CS should not be active when this hap- Operations Register.
pens. The Operations Register replaces the typi-
cal latched port found in floppy subsystems used

NO. SYMBOL DESCRIPTION

ORO DSEL Drive Select, if low and MOEN1= 1, then DS1 is active. If high and MOEN2 =
1, then DS2 is active, but only in the AT/EISA mode.
OR1 (x) This must be a loaic 0 for DS1 and DS2 to become active.
OR2 SRST Soft reset, active low.
OR3 DMAEN DMA enable, active in Special and AT/EISA modes. Qualifies DMA and IRQ
outputs and DACK input.
OR4 MOEN1 Motor On enable, inverted output M01 is active only in AT/EISA mode.
OR5 MOEN2 Motor On enable, inverted output M02 is active only in AT/EISA mode.
ORS I(X) Has no defined function. A spare.
OR? (MSEL) Mode Select. During a soft reset condition, may be used to select between
Special mode (1) and AT/EISA mode (0).
TABLE 8-1. OPERATIONS REGISTER

25-20 11118/91
BASE, SPECIAL, AND AT/EISA MODES WD37C65C

9.0 BASE, SPECIAL, AND AT/EISA MODES

Base, Special, PC AT and EISA modes allow sub- performed after a hardware reset, or in the Base
tle differences which the user may find desirable. mode, initiates AT/EISA mode. AT/EISA mode can
The Control Register may be used in any mode also be entered from Special mode by loading the
without altering functionality. Operations Register with (0 X 0 0 X 0 X X), setting
Mode Select to a logic 0, disabling MOEN1 and
MOEN2, and causing SRST to be active. Then a
9.1 BASE MODE read of the Control Register address sets the
device into AT/EISA mode. The DS outputs are
After a hardware reset, RST active. the replaced with the DSEL and MOEN signals buf-
WD37C65C will be held in soft reset, SRST ac- fered from the Operations Register. DMAEN and
tive, with the normally driven signals, DMA re- SRST are sJmQQrted and compatible with the cur-
quest and IRQ request outputs tri-stated. Base rent BIOS. RWC pin function is now RPM so that
mode may be initiated at this time by a chip ac- users with two-speed drives may reduce spindle
cess by the host. Although this may be any read speed from a nominal 360 revolutions per minute
or write, it is strongly recommended that the Base to 300 revolutions per minute when active low. It
mode user's first chip access be a read of the can also be used to reduce write current when a
Master Status Register. Once Base mode is slower data rate is selected for a given drive. Fig-
entered, the soft reset is released, and IRQ and ure 9-1 illustrates the relationship among the
DMA are driven. Base mode prohibits the use of three modes.
the Operations Register, hence there can be no
qualifying by DMAEN and no soft resets. The
Drive Select outputs, DS1 to DS4, offer a 1 of 4
decoding of the Unit Select bits resident in the
command structure. Pin RWC represents Reduce
Write Current and is indicative of when write
precompensation is necessary. Hardware
Reset

9.2 SPECIAL MODE

Read Master
Special mode allows use of the Operations Status Reg.
Register for the DMAEN signal as a qualifier and
to do a software driven device reset, SRST. To
enter Special mode, the Operations Register is
loaded with (1 X 0 0 X 0 X X), setting mode Select
to a logic 1 disabling MOEN1 and MOEN2 and
causing SRST to be active. Then a read of the
Control Register address, LDCR and RD, places
the device in Special mode. The DS1 through
DS4 is again offered in this mode, as is RWC.

9.3 AT/EISA MODES

For AT/EISA compatibility, usel§....write to the
Operations Register, LDOR and WR; this action,

FIGURE 9·1. FLOW DIAGRAM BASE, SPECIAL

& AT/EISA MODES

11/18/91 25-21
WD37C65C POLLING ROUTINE

10.0 POLLING ROUTINE

After..rurueset the WD37C65C, (a hard RST or ready set and pending when finally enabled onto
soft SRST) , will automatically go into a Polling the bus. The polling of the Ready line by the
routine. In between commands (and between step WD37C65C occurs continuously between com-
pulses in the SEEK Command), the WD37C65C mands. Each drive is polled every 1.024ms, ex-
polls all four FDDs looking for a change in the cept during the READIWRITE commands. For
Ready line from any of the drives. Since the drive mini-floppies, the polling rate is 2.048ms. The
is always presumed Ready, an interrupt will only drive polling sequence is 1-2-4-3. Note that in the
be generated following a reset. This occurs be- AT/EISA mode, the user will not see the polling at
cause a reset forces Not Ready status, which the Drive Select signals. Figure 10-1 illustrates
then promptly becomes Ready. Note that in Spe- the Drive Select Polling Timing.
cial, AT/EISA modes, if DMAEN is not valid 1ms
after reset goes inactive, then IRQ may be al-

DS1 \ /
DS2
\ /
DS4 \ I
DS3 \,--------,1
FIGURE 10-1. DRIVE SELECT POLLING TIMING

25-22 11/18/91
DEVICE RESETS WD37C65C

11.0 DEVICE RESETS

The WD37C65C supports both hardware reset drive. RST and SRST will not affect the values set
(RST) pin (19) and a software reset (SRST) for the internal timers - HUT, HTL, and SRT.
through use of the Operations Register. The RST
pin will cause a device reset for the active dura- If the XTAL oscillators are used, instead of the
tion. RST causes a default to Base mode, and TTL driven clock inputs, the hardware RST active
selects 250kb MFM (or 125kb FM, code depend- time requirement will be extended. The oscillator
ent) as the data rate (16 MHz input clock). The circuit is designed so that RST will bootstrap the
default data rate for a 32 MHz input clock is 500kb circuit into guaranteed oscillation in a fixed
MFM. SRST will reset the microcontroller as did amount of time. The extended reset time allows
the RST, but will not affect the current data rate the growth of the oscillation to produce stable in-
selection or the mode. RST, when active, will dis- ternal clock timing.
able the high current driver outputs to the disk

11/18/91 25-23
WD37C65C DATA SEPARATOR

12.0 DATA SEPARATOR

The Data Separator is a WD92C32 Digital Phase loop performance. Figure 3-1 illustrates the
Lock Loop Floppy Disk Data Separator (DPLL). It WD92C32 used as the Data Separator in the
was designed to address high performance error WD37C65C system. Figure 13-1 illustrates the
rates on floppy disk drives, and to provide supe- WD92C32 simplified block diagram. The bit jitter
rior performance in terms of available bit jitter tolerance for the data separator is 60%, which
tolerance. It contains the necessary logic to guarantees an error rate of <1 OE-9.
achieve classical 2nd order, type 2, phase locked

25-24 11118191
WRITE PRECOMPENSATION WD37C65C

13.0 WRITE PRECOMPENSATION

The WD37C65C maintains the standard first level coding. There is no write precompensation for
algorithm to determine when write precompensa- FM. If PCVAL = 0, and if a track inside number 28
tion should be applied. The EARLY and LATE sig- is accessed, then ± 187ns precompensation will
nals are used internally to select the appropriate be generated. For frequencies other than 16 MHz
delay in the write data pulse stream. The encoded or 32 MHz on the CLK1 pin, the precompensation
WRITE DATA signal is synchronized to the 16 values will be two and three clock cycles respec-
MHz or 32 MHz clock if this is the frequency on tively.
CLK1 pin (23), and clocked through a shift
register. Signals EARLY, NOM, and LATE deter- When the non-standard 300 kb/s data rate using
mine the amount of delay through the shift CLK2 is chosen, the MFM precompensation will
register before a multiplexer gates the chosen bit always be two clock cycles. For 9.6 MHz, this is ±
to the output. The output data pulse width has a 208ns. In this case, the PCVAL function is dis-
25% duty cycle, i.e., one fourth of the bit cell abled.
period, and equal to one half the WCLK period.
Write precompensation can be disabled by bit 2 of
When PCVAL pin (24) = 1, all data will be precom- the Control Register for the AT/EISA. The PCVAL
pensated by ± 125ns, regardless of track number input to WD37C65C is ignored if there is no write
and data rate. However, this is only for MFM en- precompensation.

I
DSKD ...
DATA
SYNCHRONIZATION
I II RDATA
RE SYNCHRONIZATION
I
I

•
I t
L~ 0
TRANSIENT
RESPONSE
STATE
PHASE
CORRECTIONS
~I SUMMER I
I
_ SEPCLK

t3w FILTERING
>-
w

tf i i
0
w

-
(J)
<!
--0
I
11. STEADY INC
DIGITAL
CONTROLLED
-
STATE OSCILLATOR
FREQUENCY DEC
- FILTERING

REFCLK ...
~ CLOCK GENERATOR
I • SCLK

I I
t
CD1
t
CDO

FIGURE 13-1. WD92C32 SIMPLIFIED BLOCK DIAGRAM

11/18/91 25-25
WD37C65C CLOCK GENERA TlON

14.0 CLOCK GENERATION

This logical block provides all the clocks needed Figure 14-1 illustrates the XTAL oscillator circuits
by the WD37C65C. They are: Sampling Clock for the 44-pin PLCC configuration.
(SCLK), Write Clock (WCLK), and the Master
Clock (MCLK). In power down mode the XTAL oscillator and the
clock circuitry are turned off.
SCLK drives the WD92C32 Data Separator used
during data recovery. This clock's frequency· is al-
ways 32 times the selected data rate. DATA CODE SCLK MCLK WCLK
RATE MHz MHz
WCLK is used by the encoder logic to place MFM 8.0
1 Mb/s MFM 32.0 2.0 MHz
or FM on the serial WD-stream to the disk. WCLK
always has a frequency two times the selected 500 kb/s MFM 16.0 4.0 1.0 MHz
data rate. 500 kb/s FM 16.0 8.0 1.0 MHz
250 kb/s FM 8.0 4.0 500 KHz
MCLK is used by the microsequencer. MCLK and
MCLK clock all latches in a two-phase scheme.
250 kb/s MFM B.O 2.0 500 KHz
One microinstruction cycle is four MCLK cycles. 125 kb/s FM 4.0 2.0 250KHz
MCLK has a frequency equal to eight times the 300 kb/s MFM 9.6 2.4 600 KHz
selected MFM data rate or 16 times the FM data TABLE 14-1. CLOCK DATA RATE
rate. Table 14-1 presents the Clock Data Rate.

SERIES RESONANT
XT2
26 9.6 MHz;!; 100 ppm
XT1 R series = 30 ohm max
c==:J C shunt = 10 pf max
25
XT1 C1 = 68 pf 5% mica
*C3 C2 = 56 pf 5% mica
23
XT2 SERIES RESONANT
c==:J ~C2 XT1
22
XT2 16.0 MHz ± 100 ppm 32 MHz ± ppm
R series = 30 ohm max R series = 47.2 ohm
C shunt = 10 pf max C shunt = 2 pf max
C3 = 47 pf 5% mica C3 = 30 pf 5% mica
C4 = 15 pf 5% mica C4 = 30 pf 5% mica

FIGURE 14-1. CRYSTAL OSCILLATOR CIRCUITS FOR 44-PIN PLCC

25-26 11/18/91
COMMAND PARAMETERS WD37C65C

15.0 COMMAND PARAMETERS

The WD37C65C is capable of performing 15 dif- READ DATA
ferent commands. Each command is initiated by a READ DELETED DATA
multibyte transfer from the processor. The results WRITE DATA
after execution of the command may also be a WRITE DELETED DATA
multibyte transfer back to the processor. The com- READATRACK
mands consist of- three phases: Command phase, READ 10
Execution phase, and the Result phase. FORMAT A TRACK
Command phase - The Floppy Disk SCAN EQUAL
Controller (FDC) receives all information SCAN LOW OR EQUAL
required to perform a particular operation from SCAN HIGH OR EQUAL
the processor RECALIBRATE
SENSE INTERRUPT STATUS
Execution phase - The FDC performs the SPECIFY
operation it was instructed to do. SENSE DRIVE STATUS
Result phase - After completion of the SEEK
operation, status and other housekeeping TABLE 15·1. WD37C65C COMMANDS
information are made available to the
processor. Tables 15-1 through 15-16 are presented to show
the required parameters and results for each com-
Table 15-1 lists the 15 WD37C65C commands.
mand. Most commands require nine command
bytes and return seven bytes during the result
phase. The "W" to the left of each byte indicates a
command phase byte to be written. An "R" indi-
cates a result byte.

PHASE

COMMAND
RIW D7

W
W
W
W
W
MT
X
C
H
R
D6

MF
X
C
H
R
D5

SK
X
C
H
R
D4

0
X
C
H
R
D3

0
X
C
H
R
D2

1
HS
C
H
R
D1

1
US1
C
H
R
DO

0
usa
C
H
R
REMARKS

Command Codes

Sector 10 information prior to

command execution. The four
bytes are compared against
•
W N N N N N N N N header on floppy disk.
W EOT EOT EOT EOT EOT EOT EOT EOT
W GPL GPL GPL GPL GPL GPL GPL GPL
W DTL DTL DTL DTL DTL DTL DTL DTL
EXECUTION Data transfer between FDD and
main system.
RESULTS R STO STO STO STO STO STO STO STO Status information after com-
R ST1 ST1 ST1 ST1 ST1 ST1 ST1 ST1 mand execution.
R ST2 ST2 ST2 ST2 ST2 ST2 ST2 ST2
R C C C C C C C C
R H H H H H H H H Sector 10 information after com-
R R R R R R R R R mand execution.
R N N N N N N N N
TABLE 15·2. READ DATA

11/18/91 25-27
WD37C65C COMMAND PARAMETERS

PHASE RlW D7 D6 DS D4 D3 D2 D1 DO REMARKS

COMMAND W MT MF SK a 1 1 a a Command Codes

W X X X X X HS US1 usa
w C C C C C C C C Sector 10 information prior to
W H H H H H H H H command execution. The four
W R R R R R R R R bytes are compared against
W N N N N N N N N header on floppy disk.
W EOT EOT EOT EOT EOT EOT EOT EOT
W GPL GPL GPL GPL GPL GPL GPL GPL
W DTL DTL DTL DTL DTL DTL DTL DTL
EXECUTION Data transfer between FDD and
main system.
RESULTS R STa STa STa STa STa STa STa STa Status information after com-
R ST1 ST1 ST1 ST1 ST1 ST1 ST1 ST1 mand execution.
R ST2 ST2 ST2 ST2 ST2 ST2 ST2 ST2
R C C C C C C C C
R H H H H H H H H Sector 10 information after com-
R R R R R R R R R mand execution.
R N N N N N N N N
TABLE 1S-3.READ DELETED DATA

PHASE RIW D7 D6 DS D4 D3 D2 D1 DO REMARKS

COMMAND W MT MF a a a
1 a 1 Command Codes
W X X X X X
HS US1 usa
w C C C C C C C C Sector 10 information prior to
W H H H H H H H H command execution. The four
W R R R R R R R R bytes are compared against
W N N N N N N N N header on floppy disk.
W EOT EOT EOT EOT EOT EOT EOT EOT
W GPL GPL GPL GPL GPL GPL GPL GPL
W DTL DTL DTL DTL DTL DTL DTL DTL
EXECUTION Data transfer between FDD and
main system.
RESULTS R STa STa STa STa STa STa STa STa Status information after com-
R ST1 ST1 ST1 ST1 ST1 ST1 ST1 ST1 mand execution.
R ST2 ST2 ST2 ST2 ST2 ST2 ST2 ST2
R C C C C C C C C
R H H H H H H H H Sector 10 information after com-
R R R R R R R R R mand execution.
R N N N N N N N N

TABLE 15-4. WRITE DATA

25-28 11/18/91
COMMAND PARAMETERS WD37C65C

PHASE RIW D7 D6 D5 D4 D3 D2 D1 DO REMARKS

COMMAND W MT MF 0 01 0 0 1 Command Codes
W X X X X X HS US1 usa
w C C C C C C C C Sector ID infor.mation prior to
W H H H H H H H H command execution. The four
W R R R R R R R R bytes are compared against
W N N N N N N N N header on floppy disk.
W EOT EOT EOT EOT EOT EOT EOT EOT
W GPL GPL GPL GPL GPL GPL GPL GPL
W DTL DTL DTL DTL DTL DTL DTL DTL
EXECUTION Data transfer between FDD and
main system.
RESULTS R STO STO STO STO STO STO STO STO Status information after com-
R ST1 ST1 ST1 ST1 ST1 ST1 ST1 ST1 mand execution.
R ST2 ST2 ST2 ST2 ST2 ST2 ST2 ST2
R C C C C C C C C
R H H H H H H H H Sector ID information after com-
R R R R R R R R R mand execution.
R N N N N N N N N
TABLE 15-5. WRITE DELETED DATA

PHASE RIW D7 D6 D5 D4 D3 D2 D1 DO REMARKS

COMMAND W 0 MF SK 0 0 10 0 Command Codes
W X X X X X US1
HS US1
W C C C C C CC CSector ID information prior to
W H H H H H HH Hcommand execution.
W R R R R R RR R
W N N N N N NN N
W EOT EOT EOT EOT EOT EOT EOT
EOT
W GPL GPL GPL GPL GPL GPL GPL
GPL
W DTL DTL DTL DTL DTL DTL DTL
DTL
EXECUTION Data transfer between FDD and
main system. FDD reads all data
fields from index hole to EOT.
RESULTS R STO STO STO STO STO STO STO STO Status information after com-
R ST1 ST1 ST1 ST1 ST1 ST1 ST1 ST1 mand execution.
R ST2 ST2 ST2 ST2 ST2 ST2 ST2 ST2
R C C C C C C C C
R H H H H H H H H Sector 10 information after com-
R R R R R R R R R mand execution
R N N N N N N N N
TABLE 15-6. READ ATRACK

11/18/91 25-29
WD37C65C COMMAND PARAMETERS

PHASE RIW 07 06 05 04 03 02
01 00 REMARKS
COMMAND W 0 MF 0 0 1 10 0 Command Codes
W X X X X HS US1 usa
X
EXECUTION The first correct ID information on
the cylinder is stored in Data
Register.
RESULTS R STO STO STO STO STO STO STO STO Status information after command
R ST1 ST1 ST1 ST1 ST1 ST1 ST1 ST1 execution.
R ST2 ST2 ST2 ST2 ST2 ST2 ST2 ST2
R C C C C C C C C
R H H H H H H H H Sector ID information read during
R R R R R R R R R Execution Phase from floppy
R N N N N N N N N disk.
TABLE 15·7. REAO 10

PHASE RIW 07 06 05 04 03 02 01 00 REMARKS

COMMAND W 0 MF 0 0 1 1 0 1 Command Codes
W X X X X X HS US1 USO
W N N N N N N N N Bytes/Sector
W SC SC SC SC SC SC SC SC SectorslTrack
W GPL GPL GPL GPL GPL GPL GPL GPL Gap 3
W D D D D D D D D Filler~te
EXECUTION Floppy Disk Controller (FDC) for-
mats an entire track.
RESULTS R STO STO STO STO STO STO STO STO Status information after com-
R ST1 ST1 ST1 ST1 ST1 ST1 ST1 ST1 mand execution.
R ST2 ST2 ST2 ST2 ST2 ST2 ST2 ST2
R C C C C C C C C
R H H H H H H H H In this case, the ID information
R R R R R R R R R has no meaning.
R N N N N N N N N
TABLE 15·8. FORMAT A TRACK

25-30 11/18/91
COMMAND PARAMETERS WD37C65C

PHASE RIW 07 06 05 04 03 02 01 00 REMARKS

COMMAND W MT MF SK 1 a a a 1 Command Codes
W X X X X X HS US1 usa
W C C C C C C C C SectorlD information prior to
W H H H H H H H H command execution.
W R R R R R R R R
W N N N N N N N N
W EOT EOT EOT EOT EOT EDT EOT EOT
W GPL GPL GPL GPL GPL GPL GPL GPL
W STP STP STP STP STP STP STP STP
EXECUTION Data compared between FDD
and main system.
RESULTS R STa STa STa STa STa STa STa STa Status information after com-
R ST1 ST1 ST1 ST1 ST1 ST1 ST1 ST1 mand execution.
R ST2 ST2 ST2 ST2 ST2 ST2 ST2 ST2
R C C C C C C C C
R H H H H H H H H Sector ID information after com-
R R R R R R R R R mand execution.
R N N N N N N N N
TABLE 15--3. SCAN EQUAL

PHASE RIW 07 06 05 04 03 02 01 00 REMARKS

COMMAND W MT MF SK 1 1 a a 1 Command Codes
W X X X X X HS US1 usa
W C C C C C C C C Sector ID information prior to
W H H H H H H H H command execution.
W R R R R R R R R
W N N N N N N N N
W EDT EOT EDT EOT EDT EDT EDT EDT
W GPL GPL GPL GPL GPL GPL GPL GPL
W STP STP STP STP STP STP STP STP
EXECUTION Data compared between FDD
and main system.
RESULTS R STa STa STa STa STa STa STa STa Status information after com-
R ST1 ST1 ST1 ST1 ST1 ST1 ST1 ST1 mand execution.
R ST2 ST2 ST2 ST2 ST2 ST2 ST2 ST2
R C C C C C C C C
R H H H H H H H H Sector ID information after com-
R R R R R R R R R mand execution
R N N N N N N N N
TABLE 15-10. SCAN LOW OR EQUAL

11118191 25-31
WD37C65C COMMAND PARAMETERS

PHASE RJW 07 06 05 04 01
03 02 00 REMARKS
COMMAND W MT MF SK 1 1
a 1 1 Command Codes
W X X X X X
US1 HS usa
W C C C C C
C C C Sector 10 information prior to
W H H H H H
H H H command execution.
W R R R R R R R R
W N N N N N N N N
W EOT EOT EOT EOT EOT EOT EOT EOT
W GPL GPL GPL GPL GPL GPL GPL GPL
W STP STP STP STP STP STP STP STP
EXECUTION Data compared between FDD
and main system.
RESULTS R STO STa STa STO STa STa STa STa Status information after command
R ST1 ST1 ST1 ST1 ST1 ST1 ST1 ST1 execution.
R ST2 ST2 ST2 ST2 ST2 ST2 ST2 ST2
R C C C C C C C C
R H H H H H H H H Sector 10 information after com-
R R R R R R R R R mand execution.
R N N N N N N N N
TABLE 15-11. SCAN HIGH OR EQUAL

PHASE RIW 07 06 05 04 03 02 01 00 REMARKS

COMMAND W 0 0 a a a 1 1 1 Command Codes
W X X X X X a US1 usa
EXECUTION Head retracted to Track zero.
TABLE 15-12. RECALIBRATE
The WD37C65C issues 77 step pulses, the same
as the NEC765.

PHASE RIW 07 06 05 04 03 02 01 00 REMARKS

COMMAND W a a a a 1 a a a Command Codes
RESULTS R STa STO STO STa STa STa STa STa Status information about the FDC
R PCN PCN PCN PCN PCN PCN PCN PCN at the end of seek operation
TABLE 15-13. SENSE INTERRUPT STATUS

25-32 11/18/91
COMMAND PARAMETERS WD37C65C

PHASE RIW 07 06 05 04 03 02 01 DO REMARKS

COMMAND W 0 0 0 0 0 0 1 1 Command Codes
W SRT SRT SRT SRT HUT HUT HUT HUT
W HLT HLT HLT HLT HLT HLT HLT NO
TABLE 15-14. SPECIFY

PHASE RIW 07 06 05 04 03 02 01 DO REMARKS

COMMAND W a a a a a a a a Command Codes
W X X X X X HS US1 usa
RESULTS R ST3 ST3 ST3 ST3 ST3 ST3 ST3 ST3 Status information about the
FDC.
TABLE 15-15.SENSE DRIVE STATUS

PHASE
COMMAND
RIW 07
W a
06
a
05
a 1 1
04
a1 1
03 02 01
Command Codes
DO REMARKS II
W X X X X X HS US1 usa
w NCN NCN NCN NCN NCN NCN NCN NCN
EXECUTION Head is positioned over
proper cylinder on the
diskette.

TABLE 15-16. SEEK

11/18/91 25-33
WD37C65C COMMAND PARAMETERS

Table 15-17 defines, in alphabetical order, the symbols used in Command Tables 15-1 through 15-16.

SYMBOL NAME DESCRIPTION

AO ADDRESS LINE 0 AO controls selection of Main Status Register (AO=O) or Data Register
(AO=1).

C CYLINDER NUMBER C stands for the current/selected cylinder (track) numbers 0 through 255
of the medium.

D DATA D stands for the data pattern which is going to be written into a sector.

D7 - DO DATA BUS 8-bit DATA BUS, where D7 stands for a most significant bit, and DO
stands for a least significant bit.

DTL DATA LENGTH When N is defined as 00, DTL stands for the DATA LENGTH which users
are going to read out or write into the sector.

EOT END OF TRACK EOT stands for the final sector number on a cylinder. During Read or
Write operations, FDC will stop data transfer after a sector number equal
to EOT.

GPL GAP LENGTH GPL stands for the length of Gap 3. During the FORMAT Command, it
determines the size of Gap 3.

H HEAD ADDRESS H stands for head number 0 or 1 as specified in the ID field.

HLT HEAD LOAD TIME HLT stands for the HEAD LOAD TIME· in FDD (2 to 254ms in 2ms incre-
ments).

HS HEAD SELECT HS stands for a selected head number 0 or 1 and controls the polarity of
pin 25 (in 40 pin DIP) or pin 28 (in 44 pin PLCC).

HUT HEAD UNLOAD TIME HUT stands for the HEAD UNLOAD TIME after a Read or Write operation
has occurred (16 to 240ms in 16ms increments).

MF FMor MFM If MF is low, FM mode is selected. If it is high, MFM mode is selected.

MT MULTITRACK If MT is high, a MULITRACK operation is performed. If MT=1 after finish-

ing ReadlWrite operation on side 0, FDC will automatically start searching
for sector 1 on side 1.

N NUMBER N stands for the NUMBER of data bytes written in a sector.

NCN NEW CYLINDER NCN stands for a NEW CYLINDER NUMBER which is going to be
NUMBER reached as a result of the Seek operation. Desired position of head.

ND NON-DMA MODE ND stands for operation in the NON-DMA MODE.

PCN PRESENT CYLINDER PCN stands for the cylinder number at the completion of the SENSE IN-
TERRUPT STATUS Command. Position of head at present time.

TABLE 15·17. COMMAND SYMBOL DESCRIPTIONS

25-34 11/18/91
COMMAND PARAMETERS WD37C65C

SYMBOL NAME DESCRIPTION

R RECORD R stands for the sector number which will be read or written.

RIW READIWRITE RIW stands for either READ or WRITE signal.

SC SECTOR SC indicates the number of sectors per cylinder.

SK SKIP SK stands for SKIP Deleted Data Address mark.

SRT STEP RATE TIME SRT stands for the Stepping Rate for the FDD (1 to 16ms in 1ms incre-
ments). Stepping Rate applies to all drives. In 2's complement format,
F(Hex)=1ms, E(Hex)=2ms, etc.

STO STATUS 0 STO-3 stands for one of four registers which store the STATUS informa-
ST1 STATUS 1 tion after a command has been executed. This information is available
ST2 STATUS 2 during the result phase after command execution. These registers should
ST3 STATUS 3
not be confused with the Main Status Register (selected by AO=O). STO-3
may be read only after a command has been executed and contains infor-
mation relevant to that particular command.

STP During a SCAN operation, if STP=1, the data in contiguous sectors is com-
pared byte by byte with data sent from the processor (or DMA); if STP=2,
then alternate sectors are read and compared.

USO,US1 UNIT SELECT US stands for a selected drive; binary encoded, 1 of 4.

•
TABLE 15-17. COMMAND SYMBOL DESCRIPTIONS (CONTINUED)

11/18/91 25-35
WD37C65C COMMAND DESCRIPTIONS

16.0 COMMAND DESCRIPTIONS

16.1 READ DATA a~ Sector 1, Side 0 and completing at Sector L,

A set of nine byte words are required to place the Side 1 (Sector L = last sector on the side). Note,
FDC into the Read Data Mode. After the Read this function pertains to only one cylinder (the
Data command has been issued, the FDC loads same track) on each side of the diskette.
the head (if it is in the unloaded state), waits the
specified head settling time (defined in the Specify When N = 0, then DTL defines the data length
Command), and begins reading ID Address Marks which the FDC must treat as a sector. If DTL is
and ID fields. When the current sector num- smaller than the actual data length in a sector, the
b~r("R") stored in the ID Register(IDR) compares
data beyond DTL in the sector is not sent to the
with the sector number read off the diskette, then Data Bus. The FDC reads (internally) the com-
the FDC outputs data (from the data field) byte-to- plete sector performing the CRC check, and
byte to the main system via the data bus. depending upon the manner of command termina-
tion, may perform a Multi-Sector Read operation.
After completion of the read operation from the When N is non-zero, then DTL has no meaning
current sector, the Sector Number is incremented and should be set to FF hexidecimal.
by one, and the data from the next sector is read
and output on the data bus. This continuous read At the completion of the Read Data command the
function is called a "Multi-sector Read Operation." head is not unloaded until after Head Unload
The Re~d Data Com.mand may be terminated by Time Interval (specified in the Specify command)
the receipt of a Terminal Count signal. TC should has elapsed. If the processor issues another com-
be issued at the same time that the DACK for the mand before the head unloads, then the head set-
last byte of data is sent. Upon receipt of this sig- tling time may be saved between subsequent
nal, the FDC stops outputting .data to the reads. This time out is particularly valuable when
processor, but will continue to read data from the a diskette is copied from one drive to another.
current sector, check CRC (Cyclic Redundancy
Count) bytes, and then at the end of the sector If the FDC detects the Index Hole twice without
terminate the Read Data command. The amount finding the right sector, (indicated in 'R'), then the
of data which can be handled with a single com- FDC sets the ND (No Data) flag in Status Register
mand to the FDC depends upon MT (multitrack), 1 to a 1 (high), and terminates the Read Data
MF (MF~/FM), and N (number of bytes/sector). command. (Status Register 0 also has bits 7 and
Table 31 lists the Transfer Capacity. 6 set to 0 and 1 respectively.)

Multl- MFMI Bytes Maximum Transfer Final Sector Read After reading the ID and Data Fields in each sec-
Track FM ISect Capacity From tor, the FDC checks the CRC bytes. If a read error
MT MF or (ByteS/Seclor) Diskettes
N Number of Sectors
is detected (incorrect CRC in ID field), the FDC
(128)(26)=3,328
sets the DE (Data Error) flag in Status Register 1
0 0 00 26 at Side 0 or
0 1 01 (256)(26)=6,656 26 at Side 1 to 1 (high). If a CRC error occurs in the Data
(128)(52)=6,656
Field, the FDC also sets the DD (Data Error in
1 0 00 26 at Side 1
1 1 01 (256)(52)=13,312 Data Fiel?) flag in Status Register 2 to a 1 (high),
and terminates the Read Data command. (Status
0 0 01 (256)(15)=3,840 15 at Side 0
0 1 (512)(15)=7,680 Register 0 also has bits 7 and 6 set to 0 and 1
02
respectively. )
1 0 01 (256)(30)=7,680 15 at Side 1
1 1 02 (512)(15)= 15,360
If the FDC reads a Deleted Data Address Mark off
0 0 02 (512)(8)=4,096 8 at Side 1 or
(1024)(8)=8,192 the diskette, and the SK bit (bit D5 in the first
0 1 03 8 at Side 1
Command Word) is not set (SK = 0), then the
1 0 02 (512)(16)=8,192 8 at Side 1
(1024)(16)=16,384
FDC sets the CM (Control Mark) flag in Status
1 1 03
Register 2 to a 1 (high), and terminates the Read
TABLE 16·1. TRANSFER CAPACITY Data command, after reading all the data in the
sector. If SK = 1, the FDC skips the sector with
The "multi-track" function (MT) allows the FDC to the Deleted Data Address Mark and reads the
read data from both sides of the diskene. For a next sector. The CRC bits in the deleted data field
particular cylinder, data will be transferred starting are not checked when SK = 1.

25-36 11/18/91
COMMAND DESCRIPTIONS WD37C65C

During disk data transfers between the FDC and field. If the Terminal Count signal is received while
the processor, via the data bus, the FDC must be a data field is being written, then the remainder of
serviced by the processor every 27 ~s in the FM the data field is filled with zeros.
mode, and every 13 ~s in the MFM mode, or the
FDC sets the OR (Overrun) flag in Status Register The FDC reads the 10 field of each sector and
1 to a 1 (high), and terminates the Read Data checks the CRC bytes. If the FDC detects a read
command. error (CRC error) in one of the 10 fields, it sets the
DE (Data Error) flag of Status Register 1 to a 1
If the processor terminates a read (or write) (high) and terminates the Write Data command.
operation in the FDC, then the 10 information in (Status Register 0 also has bits 7 and 6 set to 0
the Result phase is dependent upon the state of and 1 respectively.)
the MT bit and EOT byte. Table 16-2 shows the
values for C, H, R, and N, when the processor The Write command operates in much the same
terminates the command. manner as the Read command. The following
items are the same, and one should refer to the
Final Sector
MT HO Transferred 10 Information at Result
Read Data command for details:
to Procesor Phase
C H R N • Transfer capacity
0 0 Less than EOT NC NC R+1 NC
• EN (End of Cylinder) flag
0 0 Equal to EOT C+1 NC R=O NC
0 1 Less than EOT NC NC R+1 NC
• NO (No Data) flag
0 1 Equal to EOT C+1 NC R=O NC • Head Unload Time interval
1 0 Less than EOT NC NC R+1 NC • 10 Information when the processor terminates
1 0 Equal to EOT NC LSB R=O NC command
1 1 Less than EOT NC NC R+1 NC • Definition of DTL when N =0 and when N i'O
1 1 Equal to EOT C+1 LSB R=O NC

TABLE 16·2. C, H, R, AND N VALUES In the Write Data mode, data transfers between
Notes: the processor and FDC via the data bus, must , .
NC (No Change): The same value as the one at the beginning of occur every 27 ~s in the FM mode and every 13
command execution. ~s in the MFM mode. If the time interval between
LSB (Least Significant bit): The least significant bit of H is com-
plemented. data transfers is longer than this, then the FDC
sets the OR (Overrun) flag in Status Register 1 to
a 1 (high) and terminates the Write Data com-
mand. (Status Register 0 also has bits 7 and 6 set
16.2 WRITE DATA to 0 and 1 respectively.)
A set of nine bytes is required to set the FDC into
the Write Data mode. After the Write Data com-
mand has been issued the FDC loads the head (if 16.3 WRITE DELETED DATA
it is in the unloaded state), waits the specified
head settling time (defined in the Specify com- This command is the same as the Write Data
mand), and begins reading 10 fields. When all four command except a Deleted Data Address mark is
bytes loaded during the command (C, H, R, N) written at the beginning of the data field instead of
match the four bytes of the 10 field from the dis- the normal Data Address mark.
kette, the FDC takes data from the processor
byte-by-byte via the data bus and outputs it to the
FDD. 16.4 READ DELETED DATA
This command is the same as the Read Data
After writing data into the current sector, the sec-
command except that when the FDC detects a
tor number stored in 'R' is incremented by one,
Data Address mark at the beginning of a data field
and the next data field is written into. The FDC
(and SK = 0 [low]), it will read all the data in the
continues this 'Multisector Write Operation' until
sector and set the CM flag in Status Register 2 to
the issuance of a Terminal Count signal. If a Ter-
a 1 (high), and then terminate the command. If SK
minal Count signal is sent to the FDC it continues
= 1, then the FDC skips the sector with the Data
writing into the current sector to complete the data
Address mark and reads the next sector.

11/18/91 25-37
WD37C65C COMMAND DESCRIPTIONS

16.5 READ A TRACK 16.7 FORMAT A TRACK

This command is similar to the Read Data com- The Format command allows an entire track to be
mand except that this is a continuous Read formatted. After the index hole is detected, data is
operation where the entire data field from each of written on the diskette; Gaps, Address marks, ID
the sectors is read. Immediately after sensing the fields and data fields, all per the IBM System 34
index hole, the FDC starts reading all data fields (double density) or System 3740 (single density)
on the track as continuous blocks of data. If the format are recorded. The particular format which
FDC finds an error in the ID or Data CRC check will be written is controlled by the values
bytes, it continues to read data from the track. programmed into N (number of bytes/sector), SC
The FDC compares the ID information read from (sectors/cylinder), GPL (gap length), and D (data
each sector with the value stored in the IDR and pattern) which are supplied by the processor
sets the ND flag of Status Register 1 to a 1 (high) during the Command phase. The data field is
if there is no comparison. Multitrack or skip opera- filled with the byte of data stored in D. The ID field
tions are not allowed with this command. for each sector is supplied by the processor; that
is, four data requests per sector are made by the
This command terminates when the number of FDC for C (cylinder number), H (head number), R
sectors read is equal to EDT. If the FDC does not (sector number) and N (number of bytes/sector).
find an 10 Address mark on the diskette after it This allows the diskette to be formatted with non-
senses the index hold for the second time, it sets sequential sector numbers, if desired.
the MA (Missing Address mark) flag in Status
Register 1 to a 1 (high) and terminates the com- The processor must send new values for C, H, R,
mand. (Status Register 0 has bits 7 and 6 set to 0 and N to the WD37C65C for each sector on the
and 1 respectively.) track. If FDC is set for the DMA mode, it will issue
four DMA requests per sector. If it is set for the
Interrupt mode, it will issue four interrupts per sec-
16.6 READ ID tor and the processor must supply C, H, R, and N
loads for each sector. The contents of the R
The Read ID command is used to give the register are incremented by 1 after each sector is
present position of the recording head. The FOC formatted; thus, the R register contains a value of
stores the values from the first ID field it is able to R when it is read during the Result phase. This
read. If no proper ID Address mark is found on the incrementing and formaning continues for the
diskette before the index hole is encountered for whole track until the FDC detects the index hole
the second time, then the MA (Missing Address for the second time, whereupon it terminates the
mark) flag in Status Register 1is set to a 1 (high), command.
and if no data is found then the ND (No Data) flag
is also set in Status Register 1 to a 1 (high). The
command is then terminated with bits 7 and 6 in
Status Register 0 set to 0 and 1 respectively.
During this command there is no data transfer
between FDC and the CPU except during the
result phase.

25-38 11118191
COMMAND DESCRIPTIONS WD37C65C

Table 16-3 shows the relationship between N, SC, 16.8 SCAN COMMANDS
and GPL for various sector sizes. The Scan commands allow data which is being
read from the diskette to be compared against
data which is being supplied from the main sys-
Format Sector Size N SC GPL GPL tem. The FOC compares the data on a byte-by-
Bytes/sector 1 2,3 byte basis and looks for a sector of data which
8" Standard Floppy meets the conditions of OFOO = OProcessor, OFDO::;
128 00 1A 07 18 OProcessor, or OFDO :e: OProcessor. The hexidecimal
byte of FF either from memory or from FOO can
256 01 OF OE 2A be used as a mask byte because it always meets
512 02 08 18 3A the condition of the comparison. Ones comple-
FM Mode
1024 03 04 47 8A ment arithmetic is used for comparison (FF =
2048 04 02 C8 FF largest number, 00 = smallest number). After a
whole sector of data is compared, if the conditions
4096 05 01 C8 FF are not met, the sector number is incremented (R
256 01 1A OE 36 + STP -8 R), and the scan operation is continued.
512 02 OF 18 54 The scan operation continues until one of the fol-
MFM lowing conditions occur: the conditions for scan
1024 03 08 35 74
Mode are met (equal, low, or high), the last sector on the
2048 04 04 99 FF
track is reached (EOT), or the terminal count sig-
4096 05 02 C8 FF nal is received.
8192 06 01 C8 FF
5 114" Minifloppy If the conditions for scan are met, then the FOC
sets the SH (Scan Hit) flag of Status Register 2 to
128 00 12 07 09
a 1 (high) and terminates the Scan command. If
128 00 10 10 19 the conditions for scan are not met between the
256 01 08 18 30 starting sector (as specified by R) and the last
FM Mode
512 02 04 46 87 sector on the cylinder (EOT), then the FOC sets
the SN (Scan Not Satisfied) flag of Status
1024 03 02 C8 FF
Register 2 to a 1 (high) and terminates the Scan
2048 04 01 C8 FF command. The receipt of a Terminal Count signal
256 01 12 OA OC from the processor or OMA controller durring the
256 01 10 20 32 scan operation will cause the FOC to complete
MFM the comparison of the particular byte which is in
512 02 08 2A 50
process and then to terminate the command.
Mode
1024 03 04 80 FO Table 16-4 shows the status of bits SH and SN
2048 04 02 C8 FF under various conditions of Scan.
4096 05 01 C8 FF
3112" Sony Microfloppv
128 0 OF 07 18
FM Mode 256 1 09 OE 2A
512 2 05 18 3A
256 1 OF OE 36
MFM 512 2 09 18 54
Mode
1024 3 05 35 74
TABLE 16-3. N, SC AND GPL RELATIONSHIP
Notes:
1. Suggested values of GPL in Read 0, Write commands to
avoid splice pOint between data field and 10 field of contiguous
sections.
2. Suggested values of GPL in format command.
3. All values except sector size are hexadecimal.
4 In MFM mode FOG cannot perform a ReadlWritelformat
operation with 126 bytes/sector. (N=OO)

11/18/91 25-39
WD37C65C COMMAND DESCRIPTIONS

Command StatUI! Begil!te[ 2 Comments the command with bits 7 and 6 of Status Register
Bit 2=SN Bit 3=SH o set to 0 and 1, respectively.
Scan Equal 0 1 DFFD=D Processor

Scan Equal 1 0 DFFO:tD Processor

Scan Low or 0 1 DFFO:;:;;;D Processor 16.9 SEEK

Equal The ReadlWrite head within the FDD is moved
Scan Low or 0 0 DFFD<D Processor from cylinder to cylinder under control of the Seek
Equal command. FDC has four independent Present
Scan Low or 1 0 DFFD>D Processor Cylinder Registers for each drive. They are
Equal cleared only after the Recalibrate command. The
FDC compares the PCN (Present Cylinder Num-
Scan Low or 0 1 DFFO=D Processor
ber) which is the current head position with the
Equal
NCN (New Cylinder Number), and if there is a
Scan High or 0 0 DFFD>D Processor
difference, performs the following operations:
Equal PCN < NCN: Direction signal to FDD set to a 1
Scan High or 1 0 DFFD<D Processor (high), and step pulses are issued.
Equal (Step In)
TABLE 16-4. STATUS OF BITS SH AND SN peN> NCN: Direction signal to FDD set to a 0
(low), and step pulses are issued.
If the FDC encounters a Deleted Data Address (Step Out)
mark on one of the sectors (and SK = 0), then it The rate at which step pulses are issued is con-
regards the sector as the last sector on the trolled by SRT (Stepping Rate Time) in the
cylinder, sets the CM (Control mark) flag of Status Specify command. After each step pulse is issued
Register 2 to a 1 (high) and terminates the com- NCN is compared against PCN, and when NCN =
mand. If SK = 1, the FDC skips the sector with the PCN, the SE (Seek End) flag is set in Status
Deleted Address mark and reads the next sector. Register 0 to a 1 (high), and the command is
In the second case (SK = 1), the FDC sets the terminated. At this point FDC interrupt goes high.
CM (Control mark) flag of Status Register 2 to a 1 Bits DoB-D3B in the Main Status Register are set
(high) in order to show that a deleted sector had during the Seek operation and are cleared by the
been encountered. Sense Interrupt Status command.

When either the STP (contiguous sectors = 01, or During the command phase of the Seek operation
alternate sectors = 02) sectors are read or the MT the FDC is in the FDC Busy state; but during the
(Multitrack) is programmed, it is necessary to Execution phase, it is in the non-busy state. While
remember that the last sector on the track must the FDC is in the non-busy state, another Seek
be read. For example, if STP = 02, MT = 0, the command may be issued, and in this manner
sectors are numbered sequentially 1 through 26 parallel Seek operations may be done on up to
and the Scan command is started at sector 21, four drives at once. No other command can be
the following will happen: sectors 21, 23, and 25 issued as long as the FDC is in the process of
will be read, then the next sector (26) will be sending step pulses to any drive.
skipped and the index hole will be encountered
before the EOT value of 26 can be read. This will If the time to write three bytes of Seek command
result in an abnormal termination of the com- exceeds 150 ).lS, the timing between the first two
mand. If the EOT had been set at 25 or the scan- step pulses may be shorter than that set in the
ning started at sector 20, then the Scan command Specify command by as much as 1ms.
would be completed in a normal manner.

During the Scan command, data is supplied by 16.10 RECALIBRATE

either the processor or DMA controller for com-
parison against the data read from the diskette. In The function of this command is to retract the
order to avoid having the OR (Overrun) flag set in Read/Write head within the FDD to the Track 0
Status Register 1, it is necessary to have the data position. The FDC clears the contents of the PCN
available in less than 27 ).ls (FM mode) or 13 ).lS counter and checks the status of the Track 0 sig-
(MFM mode). If an Overrun occurs, the FDC ends nal from the FDD. As long as the Track 0 signal is

25-40 11/18/91
COMMAND DESCRIPTIONS WD37C65C

low, the Direction signal remains 0 (low) and step Seek End Interru~t Code
pulses are issued. When the Track 0 signal goes BillS
Bit 6 Bit 7 Cause
high, the SE (Seek End) flag in Status Register 0 Ready Line changed state, either
0 1 1
is set to a 1 (high) and the command is ter- polarity
minated. If the Track 0 signal is still low after 255 1 0 0 Normal Termination of Seek or
step pulses have been issued, (for the WD37C65 Recalibrate command

and the WD37C6SA) or 77 step pulses 1 1 0 Abnormal Termination of Seek or

Recalibrate command
(WD37C658/C), the FOC sets the SE (Seek End)
and EC (Equipment Check) flags of Status TABLE 16-5. INTERRUPT CAUSE
Register 0 to both 1s (highs), and terminates the
command after bits 7 and 6 of Status Register 0 The Sense Interrupt Status command is used in
are set to 0 and 1 respectively. conjunction with the Seek and Recalibrate com-
mands which have no Result phase. When the
The ability to do overlap Recalibrate commands to disk drive has reached the desired head position,
multiple FDDs and the loss of the Ready signal, the WD37C65C will set the Interrupt line true. The
as described in the Seek command, also applies host CPU must then issue a Sense Interrupt
to the Recalibrate command. Status command to determine the actual cause of
the interrupt, which could be Seek End or a
change in ready status from one of the drives.
16.11 SENSE INTERRUPT STATUS See Figure 16-1 .

An Interrupt signal is generated by the FDC for The Specify command sets the initial values for
one of the following reasons: each of the three internal timers. The HUT (Head
Unload Time) defines the time from the end of the
1. Upon entering the Result phase of: Execution phase of one of the ReadIWrite com-
a. Read Data command mands to the head unload state. This timer is
b. Read A Track command programmable from 16 to 240ms in increments of
c. Read 10 command 16ms (01 = 16ms, 02 =32 ms ... OF16 = 240ms).
d. Read Deleted Data command The SRT (Step Rate Time) defines the time i n t e r - I I
val between adjacent step pulses. This timer is
e. Write Data command programmable from 1 to 16 ms in increments of 1
f. Format A Cylinder command ms (F = 1ms, E = 2ms, 0 = 3ms, etc.). The HlT
g. Write Deleted Data command (Head load Time) defines the time between when
h. Scan commands the Head load signal goes high and the
Read/Write operation starts. This timer is
2. Ready line of FDD changes state programmable from 2 to 254 ms in increments of
2 ms (01 = 2ms, 02 = 4ms, 03 = 6ms ... 7F =
3. End of Seek or Recalibrate command 254ms).

4. During Execution phase in the non-DMA mode The time intervals mentioned above are a direct
function of the clock (elK on pin 23). Times indi-
Interrupts caused by reasons 1 and 4 above cated above are for a 16MHz clock; if the clock
occur during normal command operations and are was reduced to 8MHz, then all time intervals are
easily discernible by the processor. During an Ex- increased by a factor of 2. If the clock was in-
ecution phase in non-DMA mode, 085 in the Main creased to 32 MHz, then all time intervals are
Status Register is high. Upon entering the Result decreased by half.
phase, this bit gets cleared. Reasons 1 and 4 do
not require Sense Interrupt Status commands. The choice of DMA or non-DMA operation is
The interrupt is cleared by Reading/Writing data made by the NO (Non-DMA) bit. When this bit is
to the FDC. Interrupts caused by reasons 2 and 3 high (NO = 1), the Non-DMA mode is selected;
above may be uniquely identified with the aid of and when NO = 0, the DMA mode is selected.
the Sense Interrupt Status command. This com-
mand, when issued, resets the Interrupt signal
and via bits 5, 6, and 7 of Status Register 0 iden-
tifies the cause of the interrupt.

11/18/91 25-41
WD37C65C COMMAND DESCRIPTIONS

INT
F seek or (Recalibrate) Command~ense Interrupt Status command

Command Phase~ Execution Phase -+-command Phase+Result Phase

I I Ll_ _ _ ~_ _ _ _ _ __
1
cs -insuuu-W- i LnJ Llru u-t1
AO

RD
-irSLUnLJ~
U LrlJ
1J Il
U
~ IL
lflJ
U ~
Lflj-
WR -----, I Ir i l , - - - - - - - - - - - - , , - - - - - - - - - -
U U U U
D10U
LrlJ U
RQM~ n n

rI r
cO
.QL()
Oco
::10
c
<D
E
~O
0
L()
co
0
i rI
cO
.Q L()
Oco
::10
ti:;;
~o
(J)<Il
<Il
>.
.0
-0
<1l~
<DO
~~ r-- ~<D

C')
~e a:gJ
L()
co -co co
:s: 0 0
Zr--
0
s: :s: Ole..
<D
Z~
Oe
.20 <DC') .$2.9 a:~ a:e..
~
<DE >0 <DC
-0.-
i§S: -0.- <Il
Oc Oc 2~
oJg 0.9 c oJg .l!l<D
J: .!;; <D
:;:: (J)a:
a.."t:: n.".:;:
OS: ~ os:
Z
0
Z

FIGURE 16-1. SEEK, RECALIBRATE, AND SENSE INTERRUPT

16.12 SENSE DRIVE STATUS and 7 (010 and ROM) in the Main Status Register
This command may be used by the processor to are both high (1), indicating to the processor that
obtain the status of the FOOs. Status Register 3 the W037G65G is in the Result phase and the
contains the Drive Status information stored inter- contents of Status Register 0 (STO) must be read.
nally in FOG registers. When the processor reads Status Register 0, it
will find an 80 hex, indicating an Invalid command
was received.
A Sense Interrupt Status command must be sent
16.13 INVALID after a Seek or Recalibrate interrupt; otherwise
If an Invalid command is sent to the FOG (a com- the FOG will consider the next command to be an
mand not defined above), then the FOG will ter- invalid command. In some applications, the user
minate the command after bits 7 and 6 of Status may wish to use this command as a No-Op com-
Register 0 are set to 1 and 0 respectively. No mand to place the FOG in a standby or No Opera-
interrupt is generated during this condition. Bits 6 tion state.

25-42 11/18/91
COMMAND DESCRIPTIONS WD37C65C

Index Repeat N Times - - - - - - - - 1

FIGURE 16-2. WD37C65C FM MODE FORMAT

Index f - - - - - - - - - - - Repeat N Times

FIGURE 16-3. WD37C65C MFM MODE FORMAT

No. WD37C651 AlB WD37C65/C

1. 2 XTAL oscillators. 2 XTAL oscillators.
- 16 MHz for standard data rate - 32 MHz for standard data rate
(up to 500kb/s MFM). (up to 1 Mb/s MFM) or 16 MHz for
standard data rate (up to 500kb/s MFM).
- 9.6 MHz for non-standard rate. - 9.6 MHz for non-standard rate.
.(300 kb/s PCAT) (300 kb/s AT/EISA)
2. Supports data rate up to 500 Kb/s. Supports data rate up to 1 Mb/s
3. Does not support power down mode. Supports power down mode feature,
standby ICC = 100 IlA max.
4. PCVAL pin for selecting the precomp PCVAL pin for selecting the precomp values
values. and a feature to disable write precomp.
TABLE 16-6. DIFFERENCES BETWEEN WD37C65/A/B AND WD37C65C

11118/91 25-43
WD37C65C DC ELECTRICAL SPECIFICA T/ONS

17.0 DC ELECTRICAL SPECIFICATIONS

17.1 MAXIMUM RATINGS 17.2 STANDARD TEST CONDITIONS
Operating Temperature OOC (32°F) to 70°C The characteristics below apply for the following
(158°F) standard test conditions, unless otherwise noted.
All voltages are referenced to ground.
Storage Temperature -55°C (-67°F) to
+125°C (257°F)
Voltage on any pin with -0.3V to VCC +0.3V
Operating temperature OOC (32°F) to 70°C
respect to ground
range m\") (158F)
Supply Voltage with 7V
Power supply voltage +5V ± 10%
respect to ground
(VCC)

NOTE

Maximum limits indicate where permanent device

damage occurs. Continuous operation at these
limits is not intended and should be limited to
those conditions specified in the DC Operating
Characteristics.

25-44 11/18/91
DC ELECTRICAL SPECIFICA T/ONS WD37C65C

17.3 DC OPERATING CHARACTERISTICS

SYMBOL PARAMETER MIN MAX UNITS

VCC +5VDC Power Supply 4.5 5.5 V
VIL Input Low Voltage - Data Bus & XTOSC --- 0.8 V
VIH Input High Volt - Data Bus & XTOSC 2.0 --- V
VILT Input Low Threshold - Schmitt Trigger 0.8 1.1 V
VIHT Input High Threshold - Schmitt Tri~mer 1.7 2.0 V
VHYS Schmitt Trigger Hysterisis 0.45 --- V
VOL Output Low- DBx,IRQ,DMA,; 10 = 24.0mA --- 0.4 V
VOH Output High - DBx,IRa,DMA,; 10 = -5.0mA 2.8 --- V
VOLHC Output Low - High Current; 10 = 48.0mA --- 0.4 V
ILUL Latch Up Current Low 40.0 --- mA

SYMBOL PARAMETER MIN MAX UNITS

ILUH Latch Up Current High -40.0 --- mA
ILL Leakage Current Low --- 10.0 !1A
ILH Leakage Current High --- -10.0 !1A
ICC SUpjlly Current - 100 !1A Source Loads --- 60.0 mA
ICCHL Supply Current - 5.0 mA Source Loads --- 120.0 mA
ICCPDM Supply Current in Power Down Mode --- 100.0 IlA1
PD Power Dissipation- ICC Max --- 600.0 mW3
PDHL Power Dissipation - ICCHL Max --- 750.0 mW2 ,3
VPQR Power Qualified Reset Threshold 2.8 4.35 V

Note 1. Vin = VCC or GND, 10 = 0 mAo Note 3. Includes open drain high current drivers at
Vol = O.4V.
Note 2. Includes DBx, IRQ and DMA; 10 = -5.0 mA
source loads.

11118/91 25-45
WD37C65C AC TIMING CHARACTERISTICS

18.0 AC TIMING CHARACTERISTICS

The following notes apply to all parameters 4. CY = CLK1 or XT1 period
presented in this section: 5. MCY = MCLK period, dependent on selected
data rate
1.TA = OoC (32°F) to 70°C (15SoF) 6. WCY = WCLK period, dependent on selected
2.VCC = +5V ± 10% data rate
3. CL = 100 pf

SYMBOL PARAMETER MIN MAX UNITS

tCY Clock Period 31 --- nS
tPH Clock Active (Hioh or Low) 13.5 --- nS
tR Clock Rise Time (Vin O.S to 2.0) --- 2 nS
tF Clock Fall Time (Vin 2.0 to O.S) --- 2 nS
tAR AO,CS,DACK Set Up Time to RD Low 0 --- nS
tRA AO,CS,DACK Hold Time to RD High 0 --- nS
tRR RD Width 90 --- nS
tRD Data Access Time From RD Low --- 90 nS
tDF DB To Float Delay From RD High 10 65 nS
tAW AO,CS,DACK,LDCR,LDOR, Set Up Time To WR 0 --- nS
Low
tWA AO,CS,DACK,LDCR,LDOR, Hold Time From WR 0 --- nS
Hioh
tWW WRWidth 60 --- nS
tDW Data Set Up Time To WR HiOh SO --- nS
tWD Data Hold Time From WR High 0 --- nS
tRI IRQ Reset Delay Time From RD High 1MCY
+150nS
tWI IRQ Reset Delay Time From WR High 1MCY
+150nS
tMCY DMA Cycle Time 52 MCY
tAM DMA Reset Delay Time From DACK Low --- 140 nS
tMA DACK Delay Time From DMA High 0 --- nS
tAA DACKWidth 90 --- nS
tTC TCWidth 60 --- nS
tRST Reset Width - TTL Driven CLK1 60 --- nS
tSRST Reset Width - Software Reset 5 --- MCY
tRDD RDD Active Time Low 40 --- nS
tWDD WD Write Data Width Low 1/2 (TYP) --- WCY
tDST DIRC Hold & Set Up To STEP Low 4 --- MCY
tSTU DSX Hold Time From STEP Low 20 --- MCY
tSTP STEP Active Time Low 24 --- MCY
tSC STEP Cycle Time 132 --- MCY
tSTD DIRC Hold Time After STEP 96 --- MCY
tlDX IDX Index Pulse Width 2 --- MCY
tMR RD Delay From DMA 0 --- nS
tMW WR Delay From DMA 0 --- nS

25-46 11/18/91
AC TIMING CHARACTERISTICS WD37C65C

SYMBOL PARAMETER MIN MAX UNITS

tMRW RD Or WR Response From DMA High --- 48 MCY
tCA Chip Access Delay From RST Low - TTL 32 --- MCY
tCAS Chip Access Delay From tSRST Low 40 --- MCY
tXCA Chip Access Delay From RST-OSC XT1 at 16 MHz 500 --- IuS
tXTS XT2 Access Delay After RST 9.6 MHz 1000 --- IuS
tTCR TC Delay From Last DMA Or IRO, RD 0 192 MCY
tTCW TC Delay From DMA Or IRO, WR 0 384 MCY
Tcycle Clock Cycle 60 --- nS
Tp-high Clock HiQh 25 --- nS
Tp-Iow Clock Low 25 --- nS
Trise Rise Time --- 5 nS;
Vin.8 to 2.0
Tfall Fall Time --- 5 nS;
Vin 2.0 to.8

11/18/91 25-47
WD37C65C AC TIMING CHARACTERISTICS

--t-~R1
AO, CS
DACK

RD
tRR t_1-L..--_
tRA

____t=_t_RD=:j ~tDF~,..---_
DATA X Data Valid I )'(
- - - , - -_ _- - - - - J ~tRI~ ' - - - - -
IRQ

'\-----

FIGURE 18-1. READ TIMING

AO, CS
DACK x
------' C:~w-.l tWW
X
~tWA~ ' - - - - - -
WR
't 1.-
___t=_IDW=:j ~W~ ______
DATA
_ _ _- - - - - J
X Data Valid I )'(
~tWI~ ' - - - - -
IRQ

'\'----

FIGURE 18-2. WRITE TIMING

25-48 11/18/91
AC TIMING CHARACTERISTICS WD37C65C

}, ~Cy ~ }.---_

~:~-~ ~'MA *' UlM ~ -----1;./1------

RD or WR
I.
~tMR~
'MRW -----1/ . r - - - - -
rtMW~tRD=ttWD~ I
DATA _ _ _ _ _ _ _---=-I_______)\Data validl X------
I ~:~~~

'---------------'- FIGURE 18-3. DMA TIMING ..

DMA or IRQ!

tTCR
tTCW

_T_c_ _ _ _ _ _ _ _ _ _~!;.i;I---tTC ---~~\'__ _ __

FIGURE 18-4. TERMINAL COUNT TIMING

11/18/91 25-49
WD37C65C AC TIMING CHARACTERISTICS

R_E_S_E_T_ _ _ _~/' tRST--~"",\

~tcA=1
CS

FIGURE 18-5. RESETTIMING

"'-----

~
_D_'R_C_ _ ___.-t-DS-T--I . 1--. tSTD=4
STEP -'t-tSTP----1- :1'----
[ I tSC _ _---'
...

DSx '\ ~tSTU-t

IDX "ttlDX

RDD ttRDD=-f

WD ttWDD=i'

FIGURE 18-S. DISK DRIVE TIMING

25-50 11118191
AC TIMING CHARACTERISTICS WD37C65C

1 4 - - - - - Tcycle - - - - . j

16 MHz CLOCK / I~
~ T p-high -+-=-:;:"Tp-_1o-w-_-J
Trise

I- tCY~

32 MHz CLOCK);j-- tR --I'J- tF Ir-- -1't- tPHy~--

tPH

FIGURE 18-7. CLOCK TIMING

11/18/91 25-51