GENERATION OF CLOCK SIGNAL IN VERILOG Using forever keyword The forever construct, is a procedural statement that should typically only be used in test-bench code. It can occur within always and initial blocks and other statements, but cannot occur directly within a module, One should be very careful in using a forever statement: if no timing construct is present in the forever statement, simulation could hang, It is equivalent to while(1) It can be terminated using disable statement. Forever is not syntesizeable. Bample initial begin clock = 1'b0; forever begin #5 clock = ~clock; end initial #100 $finish; endmodule Using Always keyword Always is in active region so always can be used in module. Always runs until simulation completion. it is synthesizeable. In Verilog, the always block is one of the procedural blocks. Statements inside an always block are executed sequentially. An always block always executes, unlike initial blocks that execute only once at the beginning of the simulation. The always block should have a sensitive list or a delay associated with it. Example = initial begin clock = 'b0; always begin ‘#5 clock = ~clock; end endmodule Using repeat loop It's a loop which repeat a block of code or statement certains no of times as we specify. Itis synthesizable under certain condition. The number of executions is set by the expression or constant value. If expression evaluates to high impedance or un-known, then statement will not be executed. Example = initial begin clock = 1'b0; repeat(16) begin #5 clock = ~clock; end end Scanned with CamScannerUsing while loop The while loop is used to repeat a section of code an unknown number of times until a specific condition is ‘met. The statements inside while loop execute until the condition is true. Clock signal is generated using while loop by making the condition inside the wile loop always true and setting it to 1 so that it runs continuously and never stops. Itis non synthesizable, hence can only be used in behavioural coding. The statements within the while loop will be executed continuously untii the condition within the while loop is not false. In case of multiple statements, we have to use begin-end and the statements within the while loop will be executed sequentially. ample initial begin clock = 1'b0; while(t) begin #10 clock =~clock: end initial #500 Sfinish; end Scanned with CamScannerCLASS ASSIGNMENT 2 date : 01-06-2022 QUESTIONS 1. Difference between Sdisplay and $strobe and Smonitor with code 2. Write a verilog code for generating 5 random between 1.0 and 2.0. 3. write RTL for 3:8 decoder using shift operator 4. Write an RTL for N bit shift register using for loop? 1) DIFFERENCE BETWEEN $DISPLAY AND $STROBE AND $MONITOR WITH CODE Sdisplay 1. Sdisplay is used to display values of variables or strings or expressions. 2. Itinserts a new line at the end of the string by default. 3. $display without any argument produces a new line. EXAMPLE CODE 17 ROL nodule test_t(a,b,e,xy)s input a,b,¢5 output reg x.y3 always@(*) begin endrodule U/ TeSTBENCH nodule test(); reg a,b.ci wire x,y; test_t DUT(a,b,c4x,Y) 5 initial begin #10 a = 1"b1; #90 b = 1°b9; 10 ¢ = 1"b9; end Scanned with CamScannerinitial $display("inputs = Xb Xd Xd outputs = Xb Xd",a,b,c,x,y)5 // $display is used to display values of asbeKy initial 5@ $finish(); endrodule $strobe 1. Strobing is done with system task called $strobe. 2. $strobe is much similar to Sdisplay except,if multiple statements and Sdisplay are executed at same time unit the execution of Sdisplay is non-deterministic,where as §strobe is executed after all other assignment statements complete the execution. 3. $strobe provides synchronization in simulation environment ,that is, data is displayed only after other assignment statements which impact the values displayed by Sstrobe are executed EXAMPLE CODE WRT module test_t(clk,b,d,2,¢); Anput ck, b,d5 output reg asc; always@(posedge clk) begin ab; cng end enduodule 11 TESTBENCH module test (); reg bd, clk; test_t DUT(clk,b,d,2,¢)5 initial begin repeat (5) lk = 1°be; #5 clk = ~clk; end initial begin Scanned with CamScanner#0 b = 2°15 #10 € = 1°95 #19 b = 1°09; c= end always@(posedge clk) Sstrobe(“display a = %b,¢ = %",2,0)3 bs endrodule ‘Smonitor 1. Mechanism to monitor a signal when it changes it value is provided by $monitor task. 2. Format used by §monitoris similar to that of $display. 3. It continuously monitors the parameter of signals mentioned and displays all parameters in the list whenever the value of any one variable changes. Unlike Sdisplay , Smonitor gets invoked only once. additional tasks called Smonitoron and $monitoroff are used to start and terminate $monitor task mid-way through the simulation, EXAMPLE CODE nodule test(); reg clk, rst; initial begin repeat (5) 5 clk = 1'bt; sae clk = 1°ba; end initial begin rst = 1°b9; #20 rst m0 rst “bas bo; end initial $nonitor(Stime,"value of clock signal = ib reset = %b",clk rst); enduodule 2) WRITE A VERILOG CODE FOR GENERATING 5 RANDOM BETWEEN 1.0 AND 2.0. CODE Scanned with CamScannermodule test(y); output reg ys integer i; always@(*) begin for(1=0;1¢6; 4-141) y = {$random}%a.0 + 1.0; end endnodule 3) WRITE AN RTL CODE FOR 3:8 DECODER USING SHIFT OPERATOR CODE nodule decoder(d,y); input [2:0] 45 output reg [7:0] y = 8'peveeede; always@(*) begin case(é) aboee : aboot : eds 3 abet + ab168 s*bie1 a*biie : a*bini : default: endease end endnodule 4) WRITE AN RTL FOR N BIT SHIFT REGISTER USING FOR LOOP CODE module shift_reg(d,y); input 4; output reg [9:0] y = 10"boeee111101;// initialized the output to 10 bit binary eoee111101 Anteger 4; always@(*) ici0;i-141) 2€]}5 // assigning input to LSB everytine new value is entered to d Scanned with CamScanner‘Scanned with CamScanner‘Scanned with CamScanner‘Scanned with CamScanner