PNR #1:

Floorplanning, Power Planning and Placement

Islam Ahmed, Hossam Hassan

1
 The Big Picture..

Moving from Logical to Physical

RTL Logic Synthesis

Gatelevel Placed and Routed design
Place and Route
netlist
Behavioral, verified, DFT- - Timing, area, power requirements are met
- Structural Verilog netlist consists
friendly and synthesizable Removing all ideal assumptions! with signoff criteria obtained from foundary
of connected cells from the used and customer.
RTL Verilog code →Actual clock skew is calculated and taken into
SC library. account for timing analysis. - Design rules are met.
-Timing, power and area requirements →Actual interconnect parasitics is calculated -- LVS clean
are met under some assumptions: after placement and routing. -- IR drop and electromigration requirements
→Clock skew = 0! →Actual IR drop is calculated and checked. are met.
→Ideal voltage is supplied to all cells! Design rules are considered.
[IR drop = 0] Congestion and cell density are considered.
→Estimated interconnect parasitics,
regardless to actual placement and
routing!

2
PnR: a process view

SC .libs
Floorplan Prefloorplan netlist (.v)
Constraints SC MW library .TLUplus files Tech. file
constraints

PnR (ICC)

Legally placed and routed

design MW Cell

-Post-layout .v netlist.
-LEF.
-GDS.

3
 Timing Prefloorplan SC .libs
Floorplan .TLUplus files Tech. file
Constraints netlist SC MW library
constraints

Floorplanning

Power Planning & boundary cell insertion

Placement

CTS
Post-CTS optimization

Routing

4
 Floorplanning

5
Floorplanning
 Floorplannning is deciding the major design objects size and placement!

Who is involved in
Floorplanning?

Digital Frontend
Digital Backend
Analog-mixed signal designer
Project Manager
……

6
Floorplanning

Chip floorplanning
IO cells placement
Macro placement
Bump placement (for flip chip designs)
RDL routing (for flip chip designs)
Power Delivery Network

7
Multiple Domain Design

core

IP PD1
RAM

PD2
PD3
ROM

8
IO Pads
 Input/Output circuits used as intermediate structures
connecting internal signals from the core of the IC to
the external pins of the chip package.
 Typically organized into an IO ring at the
periphery of the chip. IO pins are
connected to each other through
abutment.
 Multiple power pads are often used for core
voltage(s) and IO voltage.
 IOs usually consists of:
 Level shifters and buffers
 ESD protection circuitry.

9
IO Pads
 Types of IOs:
 Signal IOs: in, out, or inout.
 Power IOs: core supply/ground, IO supply
ground.
 Corner IOs: used for IO ring continuity at
the corners.
 Filler IOs: used to keep continuity of IO
ring.

10
IO Pads

11
IO Pads
PAD limited design Core limited design

 The area of die is determined by the • The area of the die is determined by the needed
area for the core logic and for macros.
periphery needed for the IO ring.
• Small number of IOs, plenty of space for IO ring.
 This can increase the chip size
significantly even if logic is small -> • Usually chips of this type has large number of
macros or logic is implemented in huge count of
placement utilization is very low! gates.
 Avoided by using IO clusters/area IO
floorplanning.

12
Floorplanning

Chip floorplanning

Typical Power network for an SoC.

For our lectures, we will focus

only on IP floorplanning!

13
Floorplanning

IP floorplanning
Die area and core area
Hard IPs/Macros placement
Power delivery
Voltage domains
Pin placement

14
 Floorplanning: Port Locations
 Ports can be placed automatically by ICC around the boundary (Die area), or explicitly set by the designer.
 The core area is where cells are placed.
 Die area represents the boundary of the IP, where ports area placed.
 Terminals are physical representation of the ports. A

Die area

Terminals (ports implementation )

Core area Core

15
Creation of Site Rows
 Placement requires grid in which cells will be placed: Site Rows.
 Site Rows are created based on ‘unit tile’, to fill the core area. They are used later by the placement engine to
place cells.
 ‘unit tile ’is defined by a library developer and library cells are designed to be multiple of unit tile

Creation of sites for

FF
detailed placement

NOR BUF

INV

unit tile
(site)

16
Standard Cell Placement
 Cells are placed in rows, next to each other
 One cells structure continue previous one
 Cells on neighbor rows are flipped so that they can share same supply

VDD VDD VDD VDD VDD

DFFSR1

AOI221
JKFF
AND2

INV1
Placement Rows

VSS VSS VSS VSS VSS

VSS VSS VSS VSS VSS VSS VSS
BUF2B

MUX21

NA21

NOR3
XOR2
INV1

INV1
VDD VDD VDD VDD VDD VDD VDD

17
Routing Tracks (Wire Tracks)

Layers have
Routing is done Insufficient number of
perpendicular
on tracks tracks bring congestion
directions
Minimu Minimum
m width spacing

Metal Routing Tracks

Metal pitch

18
Floorplanning: Aspect Ratio
 Aspect ratio is the height to width ratio of a block
 Defines the block shape
 Default aspect ratio is 1

width width

height
height

19
 Floorplanning: Area Utilization
• Utilization refers to the percentage of core area that is taken up by standard cells

• High Utilization can make it difficult to close routing!

• It will make it also difficult to change the design in the future..

Utilization =
 cellArea
CoreArea

Low standard-cell High standard-cell

utilization utilization
20
Exercise

 Please find out an initial floorplan and σ 𝑐𝑒𝑙𝑙𝐴𝑟𝑒𝑎

𝑈𝑡𝑖𝑙𝑖𝑧𝑎𝑡𝑖𝑜𝑛 =
calculate the required area accordingly for 𝐶𝑜𝑟𝑒𝐴𝑟𝑒𝑎
your IP; knowing that:
 You usually have total area of 125,000 um2 after
synthesis.
 You have 1 analog Macro with area of:
400um*400um, required to have a blockage
surrounding it by 20um from all sides.
 Required initial floorplan utilization is 35%.

21
 Design Import

Placement Blockages and Halos Floorplan

Placement

CTS
• Placement blockage are areas that Route

the tools should not place any cells. Finish Design

Keepout margin
• These, too, have several types:
• Partial Blockage – an area with lower
utilization.
• Halo (padding) – an area outside a
macro that should be kept clear of
standard cells. RAM5

Pins are on left

and right
22
 Routing Blockage
CTS
• A routing blockage Route

is defined for a Finish Design

given layer, in a (75,95)

specific area.

Routing
blockage

(20,20)

23
Routing Blockage

http://www.signoffsemi.com/floorplan-placement-2/

24
 Guidelines for a good floorplan
Single large Use blockage to
Macros out of improve pin
core area accessibility
the way in the
corner
Large
RAM 1 RAM 2

RAM 3
Finish
routing
channels RAM 4 RAM 5 RAM 6
RAM

Standard cells area

RAM

RAM Avoid many pins

•q in the narrow
channel. RAM 7 RAM 8
Rotate for pin
PLL MY_SUB_BLOCK accessibility

Pins away
from corners
25
Macro placement

http://www.signoffsemi.com/floorplan-placement-2/

26
How to qualify Macro placement?
1. All macros should be placed at the boundaries.
2. Check the orientation and pin direction of all macros, all pins should
point towards the core logic.
3. Spacing between macros should be sufficient for routing and power
grid.
4. Good congestion and QoR results.

27
Technology File
 It contains physical information
required for physical synthesis.
Technology {
• Physical characteristics of each unitTimeName = "ns"

layer/via, timePrecision = 1000

unitLengthName = "micron"
• Design rules for each layer/via, ...
}
• Units (example: time, capacitance, Layer “M1" {

distance), layerNumber = 16
defaultWidth = 0.23
• And more minWidth = 0.23
...
}
ContactCode "VIA_1_2" {
 A technology file, as a rule, is provided contactCodeNumber = 31

by vendor. cutLayer = "VIA1"

lowerLayer = "M1"

 The file extension used is .tf upperLayer = "M2"

...
}

28
MW Techfile: Technology Section
 Unit Precision and Range
To measure capacitance down to 0.0001 picofarad (pF), need
to set unit capacitance to pF and capacitance precision to Technology {
10,000. /* define units */
dielectric = 0.000000e+00
unitLengthName = "micron"
lengthPrecision = 1000
 Defining Routing Rule Modes gridResolution = 50
unitTimeName = "ns"
Attributes to control physical synthesis timePrecision = 100
unitCapacitanceName = "pf"
capacitancePrecision = 10000
...
/* routing rule modes */
minLengthMode = 0
minAreaMode = 0
fatTblMinEnclosedAreaMode = 0
minEdgeMode = 0
cornerSpacingMode = 0
fatTblSpacingMode = 0
parallelLengthMode = 0
fatWireExtensionMode = 0
}

29
MW Techfile: Layer Section
 Layout attributes
 Layout attributes associate a physical layer in the layout with the display
layer.
Layer “M1" {
 Display attributes
/* layout attributes */
 Display attributes specify how objects on the layer are displayed. layerNumber = 8
 Design rule attributes isDefaultLayer = 0
maskName = "metal1"
 Design rule attributes define the layer-specific design rules associated with pitch = 2.2
objects on the layer. /* display attributes */
 Physical attributes color = "blue"
lineStyle = "solid"
 Physical attributes define physical characteristics of the layer and need to pattern = "dot“
be specified if you are using timing-driven layout. /* design rule attributes */
maxWidth = 1.0
minWidth = 1.0
minArea = 1.0
...
/* physical attributes */
unitMinThickness = 0
unitNomThickness = 0
unitMaxThickness = 0
...
}

31
MW Techfile: VIA

ContactCode “VIA12" {
y /* physical attributes */
0.8 contactCodeNumber = 1
contactSourceType = 0
0.05 cutLayer = “VIA1"
Metal 1 lowerLayer = "M1"
upperLayer = "M2"
isDefaultContact = 1
Metal 2 x cutWidth = 0.8
0.1 cutHeight = 0.8

/* design rule attributes */

upperLayerEncWidth = 0.05
upperLayerEncHeight = 0.1
lowerLayerEncWidth = 0.1
lowerLayerEncHeight = 0.05 ...
/* parasitic attributes */
unitMinResistance = 0.00025
unitNomResistance = 0.00025
...
}

32
MW Techfile: Design Rules

W <= Q
DesignRule {
L layer1 = "Metal2" A3
layer2 = "Via1"
Via endOfLineEncWidthThreshold = Q
endOfLineEncTblSize = 2
X1 endOfLineEncSideThreshold = (S0, S1)
endOfLineEncTbl = (E0, E1)
X2 }
Metal

if min {X1, X2} <= S0,

then L >= E0
if S0 < min {X1, X2} <= S1,
then L >= E1 (E1 < E0)

33
Modeling Parasitics
 TLUPlus Models contain C/R look-up tables

TLU+
(ICC)
Interconnect 010
100
Technology File
(ITF)

nxtgrd
(StarRC)
010
100

34
tech2itf Map File Creation

Milkyway Map File ITF

Techfile

metal1 conducting_layers M1
metal2 metal1 M1 M2
metal3 metal2 M2 M3
via1 metal3 M3 v1
via2a v2
via_layers
via1 v1
via2 v2

remove_layers

35
Synopsys Milkyway Database/Library

 The Milkyway database was originally developed by Avanti Corporation,

which has since been acquired by Synopsys. It was first released in
1997.
 Milkyway is the database underlying most of Synopsys' physical design
tools.
 Milkyway stores topological, parasitic and timing data. Having been used
to design thousands of chips, Milkyway is very stable and production
worthy.

36
 Milkyway Database

• A milkyway database contains both Layout and

Abstract views
1. Layout (CEL view) contains drawn mask layers
required for fabrication.

2. Abstract (FRAM view) contains only minimal data

needed for PnR tools. [pin shapes, obstructions]

The difference between both views is like the

difference between .GDS and .LEF views.

37
Resolving References
 Gate-level netlists contain references to standard cells and macros which are stored
in the logical libraries as well as other hierarchical logic blocks
 Before placing one must ensure that all references can be resolved

nand nor
inv ff

pci_core
Checking of all references
risc_core
Gate-Level Netlist(s) sdram, ..

38
FRAM (Abstract) View Content
 Abstract view contain physical information of standard and macro cells necessary for placement

PR Boundary

VDD VDD

A B
A B
Blockage
Pins
(direction, layer
and shape)
Y Y
Symmetry
(X, Y, or 90º)

NAND_1
⌟
GND GND
origin
Layout View (typically 0,0) Abstract View

39
Preparing the Design
 The IC Compiler tool uses a Milkyway design library to store your design and
its associated library information.

40
Setting Up the Logic Libraries
 The IC Compiler tool uses logic libraries to provide timing and functionality
information for all standard cells. In addition, logic libraries can provide timing
information for hard macros, such as RAMs.
 In each session, you must set up the logic libraries by defining the search path,
link libraries, and target libraries.

41
Setting Up the Physical Libraries
 The IC Compiler tool uses Milkyway reference libraries and technology files
to obtain physical library information.
 The Milkyway reference libraries contain physical information about the
standard cells and macro cells in your logic library.
 The technology file provides technology-specific information, such as the
name and characteristics of each metal layer.

42
 Power planning

43
Power planning
 Power planning is deciding how we will deliver power to the
design’s standard cells!

What is the importance of having a power network with low

impedance?
All analysis and optimization done in logic synthesis and PnR are based on that cells are
supplied with ideal voltage..
If the actual circuit supply is different significantly, cell operation will be different than
the behavior characterized in the .libs, which will cause all types of timing violations!

44
 IR Drop

• The drop in supply voltage over the length of the supply line
• A resistance matrix of the power grid is constructed
• The average current of each gate is considered
• The matrix is solved for the current at each node,
to determine the IR-drop.

Ideal voltage level

Minimum
Tolerance
Level
Actual voltage level
45
 IR Drop

• The power supply (VDD and VSS) in a chip is uniformly distributed through the
metal rails and stripes which is called Power Delivery Network (PDN).
• Each metal layers used in PDN has finite resistivity.

V2 = V1 - I.R

Consequences of IR drop
A. poor performance of the chip due to the increase of delay of standard cells
B. functional failure of the chip due to setup/hold timing violation.

46
IR Drop

Possible reasons of IR drop

1. Poor design of power delivery network.
1. lesser metal width and more separation in the power stripes).
2. inadequate via in power delivery network.
2. Inadequate number of decap cells availability.
3. High cell density and high switching in a particular region.
A. Insufficient number of voltage sources.
B. High RC value of the metal layer used to create the power delivery network.

47
 Hot Spots

• We generally map the IR drop of a chip using a color map to

highlight “hot spots”, where the IR drop is bad.

Initial IR Drop Mapping

48
 Design Import

Electromigration (EM) Floorplan

Placement

CTS

• Electromigration refers to the gradual displacement of the Route

metal atoms of a conductor as a result of the current flowing Finish Design

through that conductor.

• Transfer of electron momentum
• Can result in catastrophic failure do to either
• Open : void on a single wire
• Short : bridging between to wires
• Even without open or short,
EM can cause performance degradation
• Increase/decrease in wire RC

49
 Electromigration (EM)

• When a high current density passes through a metal interconnect, the momentum of current-
carrying electrons may get transferred to the metal ions during the collision between them.
• Due to the momentum transfer, the metal ions may get drifted in the direction of motion of
electrons. Such drift of metal ions from its original position is called the electromigration effect.

• Depending on the current density, the subjected metal ion started drifting in the opposite direction
of the electric field. If the current density is high, the interconnect may get affected of EM instantly
or some times the effect may come after months/years of operation depending on current density.

• Mean-time-to-failure [MTTF]
Where A = Cross-Section area
J = Current density
N = Scaling factor (normally set to 2)
Ea = Activation energy
K = Boltzmann's constant
T = Temperature in Kelvin

50
Top-level Power Network More (Wider) Power Lines:
• Less Static (IR) drop
 User can specify
• Less Dynamic (dI/dt) drop
 Number of straps: Min, max
• Less Electromigration
 Width of straps: Min, Max

BUT
 Width of ring
 Layers
More (Wider) Power Lines:
• Fewer (signal) routing
resources
(i.e., higher congestion)

51
 Design Import

Power and Ground Routing Floorplan

Placement

CTS

• Each standard cell or macro has power and ground Route

signals, i.e., VDD (power) and GND (ground) Finish Design

• Power/Ground mesh will allow multiple paths

from P/G sources to destinations
• Less series resistance
• Hierarchical power and ground meshes
from upper metal layers to lower metal layers
• Multiple vias between layers
• In general, P/G routings are pretty regular
• P/G routing resources are usually reserved

52
 Power Grid Creation

• Tradeoff IR drop and EM versus routing resources

• Require power budget Power lines
• Initial power estimation
• Average current, max current density
• Need to determine Mx Mx
• General grid structure (gating or multi-voltage?)
• Number and location of power pads (per voltage) Mx-1 Mx-1
• Metal layers to be used
• Width and spacing of straps Mx-2 Mx-2
• Via stacks versus available routing tracks
• Rings / no rings
• Hierarchical block shielding
• Run initial power network analysis to confirm design
53
Signal routing area
 Placement

54
 Placement
• Placement is the stage of the design flow, during which
each instance (standard cell) is given an exact location.
• Inputs:
• Netlist of gates and wires.
• Floorplan and Technology constraints
• Output:
• All cells located in the floorplan.
• Goal
• Provide legal location of entire netlist
• Avoiding routing congestion, to enable
easy detailed routing of all nets
• Meet timing, area, and power targets

55
 Placement
• Placement is the process of placing the standard cells inside the core
boundary in an optimal location.
• The tool tries to place the standard cell in such a way that the design should
have minimal congestions and the best timing.
Placement
Synthesis Netlist

56
 Placement Flow
• In general, most tools partition the placement task into two stages:
• Global placement:

• Quickly divide each cell into “bins” to try and minimize the number of
connections between groups.
• In this stage, the tool will not check any overlap of instances
Good Placement
• Detailed placement:
• Provide a legal placement for each instance
• Try and minimize wirelength (or other cost metrics)
• Try to finish with uncongested design.

Coarse
Placement

Legalized
Placement
57
7
 High Fanout Synthesis [HFS]
• Initially, there are some nets which have very high numbers of fanout.
• We have a constraint of maximum fanout, so we need to distribute the sinks on
nets to different drivers.
• The process of adding buffers and splitting the fanout is called high fanout
net synthesis (HFNS).

58
7
Placement Optimizations

 Global placement aims to get a rough placement solution that may violate some placement constraints
[there might be overlaps or cells not assigned to a row.]
 Optimize timing and reduce transition
 Placement has huge impact one timing closure.
 High input transition leads to increased delay, being more prone to crosstalk, and getting inaccurate calculations
for STA.
 Global placement enhances timing and fixes high transition nets using:
 Reducing wirelength, placing cells close to each other.
 Dividing long nets using buffers/inverters.
 Layer promotion: setting extra NDR rules for some nets.
 Resizing gates to meet timing, reduce power, or reduce high transition.
 Advanced techniques in recent PnR tools: logical restructuring, CCD everywhere.

 Fix high Fanout nets

 Tie Cell insertion
 Scan-chain reordering

59
 Tie-cell insertion
• Why can’t we use power network to connect 1b’1/1b’0?
• To avoid damaging the gate oxide under the poly gate .
• if the polysilicon gate connects directly to VDD or VSS it can be damaged due to power
noise.

• Connecting an input of logic cell that is the gate of a transistor directly to vdd or vss is not
recommended to avoid power noise. [drop in VDD and bounce in VSS]
• So In this step tool places tie high and tie low cells which is basically a single output logic cell,
and it connects the input of the logic gate which needs to connect vdd or vss respectively.

60
7
 Tie-cell insertion
Tie cell schematic

• The tie cell has no input pin and only one output pin.
• The output of the tie-high cell is always high and the output of the tie-low cell is always low and it
is the glitch-free output that connects to the input of any logic gates.
• In this step tool places tie high and tie low cells which is basically a single output logic cell, and it
connects the input of the logic gate which needs to connect vdd or vss respectively.

61
7
 Scan-chain reordering
• It’s the process of reconnecting the scan chains in a
design to optimize for routing by reordering the scan
connection which improve timing and congestion.

• Logic synthesis arbitrarily connects the scan chain

• Based on timing and congestion PnR tool optimally
places standard cells.
• While doing so, if scan chains are detached, it can
break the chain ordering originally made by DFT
compiler, and reorder to optimize it & it maintains
the number of flops in a chain.

• This way; we get easier routing of scan chain and

reduced congestion.

• Because of scan chain reordering patterns generated

earlier is of no use. But this is not a problem as ATPG
can be redone by reading the new netlist.
62
7
 Logical restructuring

• Restructuring means gate composition or decomposition.

• Placement engine can use it to enhance WNS or TNS.
• It can be used also if there is a power gain.

63
7
 Congestion
• Congestion occurs when the number of required
routing tracks exceeds the number of available tracks.
Overflow on each edge =
• Congestion can be estimated from
Routing Demand - Routing Supply
the results of a quick global route. 0 (otherwise)
• Global bins with routing overflow Total Overflow
can be identified.
Global Bin
=  overflow
all edges

29/28
Nets crossing the
Global Bin global routing cell
Global (GRC) edge per
Edge 39/35 40/35
routing grid available routing
tracks

Routing demand = 3 28/28

Routing tracks
Assume routing supply is 1,
64
overflow = 3 - 1 = 2 .
 Adam Teman,
 Design Import
Congestion Map

Congestion Floorplan
Congestion
hot spot
Placement

CTS
•Issues with Congestion Route

• If congestion is not too severe, the actual route Finish

n

can be detoured around the congested area Desig

Detour
• The detoured nets will have worse RC delay
• In highly congested areas, delay estimates during
placement will be optimistic. ≥2 ≥3 ≥4 ≥5 ≥6 ≥7

• Not routable or severely congested design

• It is important to minimize or eliminate congestion before continuing
• Severe congestion can cause a design to be un-routable

65
 Congestion Maps
• Congestion maps are displayed by the backend tool to help us evaluate
the total congestion, identify and fix congestion hot spots.

66
 Congestion-driven Placement
Shorter Wire length
Channel Density: 3
• Congestion Reduction (track: 3)
• The tool tries to evaluate congestion hotspots
and spread the cells (lower utilization) in the
area to reduce congestion. A B C D
• The tool can also choose cell location based
on congestion, rather than wire-length.
(channel capacities:2) E F G H
Unroutable Layout

D B C A
Longer Wire length
Channel Density: 2
(track: 2)
E F G H
67
 Reasons for congestion
o High standard cell density in a small area
o Placement of standard cells near macros
o High pin density at the edge of the macro
o High utilization inside power domain fence in muti-voltage
designs
o Macro pins near core area boundary
o Blind double spacing/width for cts in lower metal layers near
pins (hard pin access)
o Bad floorplan

68
Placement Constraints
Used to reduce/avoid congestion, or to enhance timing.
1) Placement blockages
 Area where standard cell placement is prevented in.
A) Hard PB: all cells are prevented in the specified bbox.
Ex. create_placement_blockage -boundary {10 20 100 200} –name pb0
B) Soft PB: during optimizations; bufs/invs can be placed in it.
Ex. create_placement_blockage -boundary {10 20 100 200} –name pb1 –type soft
C) Partial PB: limits the cell density in the specified bbox.
Ex. create_placement_blockage –boundary {10 20 100 200} –type partial \
-blocked_percentage 40
D) Keepout margins: It is a region around the boundary of fixed cells in a block
in which no other cells are placed.
2) Placement bounds
It is a fixed region in which we placed a set of cells. Usually useful for cells of
timing critical paths.
Ex. create bound –name b1 –type soft –boundary {10 10 20 20} instance_2
69
 Strategies to Fix Congestion
CTS

Modify the floorplan: Route Finish Design

• Mark areas for low utilization.

• Alignment of bus signal pins
• Increase of spacing between macros
• Add blockages and halos
• Core aspect ratio and size
x1 y1
• Making block taller to add more horizontal routing resources
• Increase of the block size to reduce overall congestion
• Power grid
• Fixing any routed or non-preferred layers

70
39  Adam Teman,
 Congestion recommendations in Floorplanning
o Placement of standard cells near macros
o Macro pins near core area boundary
o create_placement_blockage -bbox $bbox -type hard -name $name

71
 Congestion recommendations in Floorplanning

o Checkerboard blockages: use hard placement blockages between

cells
o blockages limit sites available for cell placement

72
No Hold Time Fixing in Placement

◼ By default place_opt tries to fix only setup time

violations - No hold time fixing
◼ Hold time will be addressed during clock tree synthesis

◼ All timing calculations are based on ideal

clocks (clock skew = 0). Therefore, it is a
common practice to give more constrainted
timing to placement engine with:
A. Extra uncertainty
B. Frequency Overdrive
73
Thank You!

74