DFT, Logical equivalence checking

Islam Ahmed, Hossam Hassan

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DFT Problem

 Designing with taking into

consideration test problem
 What kind of problems we focus on
in DFT?
 DFT Challenges
DFT Problem

 Designing with taking into

consideration test problem
 What kind of problems we focus on
in DFT?
 DFT Challenges
DFT Problem

 Designing with taking into

consideration test problem
 What kind of problems we focus on
in DFT?
 DFT Challenges
Ex. Physical Defects
Fault Models
 A logical model representing the effects of a physical defect
❖ Stuck-at
❖ At-speed
❖ Quiescent Current
❖ Bridge
Ex. STUCK AT
 A signal, or gate output/input, is stuck at a 0 or 1 value, independent
of the inputs to the circuit
D-Algorithm
 D-Algorithm (Discrepancy Algorithm) is a systematic approach that is suitable
for computer programing
 D-Algebra consists of 5 logic values 1, 0, D, D’, X
 D-Algebra rules:

0∩0=0∩x=x∩0=0
1∩1=1∩x=x∩1=1
x∩x=x
1∩0=D
0 ∩ 1 = D’
D-Algorithm
 Singular Cover (SC) of any logic gate is the compact form of truth-table.
This is done using don’t cares (x).
 AND Gate SC is produced as the following table:
D-Algorithm

 Primitive D-cube of a Fault

(PDCF) is used to specify the
minimum input conditions
required at inputs of a gate to
produce an error at its output.
 PDCF can be derived from the
intersection of singular covers of
gates in faulty and non-faulty
conditions having different
outputs.
D-Algorithm

Sa0 Fault for AND Gate

 Primitive D-cube of a Fault
(PDCF) is used to specify the
minimum input conditions
required at inputs of a gate to
produce an error at its output.
 PDCF can be derived from the
intersection of singular covers of
gates in faulty and non-faulty
conditions having different
outputs.
D-Algorithm

 Primitive D-cube of a Fault Sa0 Fault for AND Gate

(PDCF) is used to specify the

minimum input conditions
required at inputs of a gate to
produce an error at its output.
 PDCF can be derived from the
intersection of singular covers of
gates in faulty and non-faulty
conditions having different
outputs.
{a, b, out} = {1, 1, D}
 PDCF of this faulty AND gate is
But How will we achieve this on circuit level?
Multiplexed Flop Scan

 “compile –scan” command in Design Compiler causes the normal flops to be scan-replaced during the synthesis
process
 Adding scan flop in the design and connecting DFT circuit is called Scan Insertion
Scan Ready Design

 Shift in – Capture – Shift out

Automatic Test Pattern Generation “ATPG”

 Automatic generation of test

patterns for scan ready design
 Tools for pattern generation:
Synopsys Tetramax
Siemens (Mentor) Tessent
Cadence Modus DFT
 ATPG tool is used for
generating test pattern file and
testbench for simulating test
patterns
 Test patterns are loaded into
automatic test equipment to
classify functioning / faulty ICs.
Automatic Test Pattern Generation “ATPG”

 Automatic generation of test

patterns for scan ready design
 Tools for pattern generation:
Synopsys Tetramax
Siemens (Mentor) Tessent
Cadence Modus DFT
 ATPG tool is used for
generating test pattern file and
testbench for simulating test
patterns
 Test patterns are loaded into
automatic test equipment to
classify functioning / faulty ICs.
 Formal Verification
(Formality)

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What is Formal Verification?
 Formal verification is an alternative to verification through simulation.
 As designs become larger and more complex and require more simulation vectors,
regression testing with traditional simulation tools becomes a bottleneck in the design
flow.
 A 100% coverage
 Equivalence checkers prove or disprove that one design representation is
logically equivalent to another. In other words, two circuits exhibit the
same exact behavior under all conditions despite different representations-.

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What is Formality?
 The purpose of Formality is to detect unexpected differences that might have
been introduced into a design during development.
 It uses a formal verification comparison engine to prove or disprove the
equivalence of two given designs and presents any differences for follow-
on detailed analysis.
Design level 1 Design process Design level 2

Formality
Equivalent
Yes/No ?

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Key Concepts
 Main concepts in Formality are
 Compare Point
 Primary output of a circuit
 Registers within a circuit
 Input to black boxes within a circuit
 Logic Cone
 A block of combinational logic which drives a compare point

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Equivalence Checking Verification Process
 Equivalence checking is a four-phase process:
 Reading and elaborating language descriptions into logical representations
 Setting Up Designs to Preempt Differences
 Mapping of corresponding compare points between pairs of designs (Matching)
 Comparison of logic cones that drive the compare points (Verification)

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 0. Guidance (Load Automated Setup File)

 Before specifying the reference and implementation designs, an automated
setup file (.svf) can be optionally loaded into Formality. The automated setup
file helps Formality process design changes caused by other tools used in the
design flow. Formality uses this file to assist the compare point matching and
verification process. For each automated setup file that is loaded, Formality
processes the content and stores the information for use during the name-
based compare point matching period.

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Formality Flow Overview

Start
Setup

Read Reference
Design + Libs Match
Debug
Read Implementation Verify
Design + Libs

No
Success?

Yes

End

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Guidance (Loading of Automated Setup File)
 The purpose of automated file (.svf) is to help Formality process design
changes caused by other tools, which it should have access to as the changes
are made.

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 Exercise

-If a netlist ECO was wrongly implemented, removing one

of the following cells by mistake.. When will it cause
formality to fail?
-An inverter.
-A buffer.
-An unconnected net.

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 Exercise

- What are the possible causes that can cause formal

verification to fail? [list at least 2]

-Is providing an .svf file mandatory for successful formal

verification? Matching?

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 Static Timing Analysis Gatelevel Timing Simulation
Usage check timing requirements: setup, hold, recovery, Functional and timing simulation, checking functionality by
removal, Logical DRCs. comparing output VS expected output.

More accurate
Much faster than timing-driven simulation. Can catch issues like glitches.
Exhaustive, checks every possible constrained
timing path.
No vector generation is required.
The signal at the input is propagated through the
gates at each level till it reaches the output

Limitations Only useful for synchronous digital circuits, can’t Analysis quality can be dependent on stimulus vectors
analyze asynchronous systems Takes a lot if time and computational power.
Less accurate Non-exhaustive.
Must define timing requirements, false paths..etc.

Required inputs gatelevel netlist, .lib files, .sdc, derates, .spef gatelevel netlist, library .v, .sdf, test vectors, expected output.

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 Logical DFT LVS
equivalence
(Formality)
Usage Verify different Observability and Checking spice after
Pros
implementations Controllability to validate physical synthesis is match
match each other fabrication has completed GDS: devices are matching,
(RTL VS netlist, properly according to
netlist VS netlist) "stuck-at" Model.

Limitations Only checking Extra area and power. Check physical correctness
functionality/logic Coverage usually is not only not logical or
didn't change after 100%. functionality, nor STA.
design stages. Testing equipment and
testing time.
Required gatelevel netlist, Synthesize design post-PnR .gds, post-PnR .v
inputs
.lib, RTL/gatelevel Scan strategy/constraints netlist, SC library .spice,
netlist, .svf macros .spice (if you have
macros), LVS .ruleset.

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