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Module 3b Verilog Constructs To GATES

The document discusses various Verilog constructs for modeling digital logic gates and circuits, including continuous and procedural assignment statements, blocking and non-blocking assignments, logical and relational operators, conditional expressions like if/else statements and case/casex/casez, always blocks and loops for modeling latches and flip-flops, functions, tasks, module instantiation, and parameterized designs.

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Balaji B Surendran
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22 views79 pages

Module 3b Verilog Constructs To GATES

The document discusses various Verilog constructs for modeling digital logic gates and circuits, including continuous and procedural assignment statements, blocking and non-blocking assignments, logical and relational operators, conditional expressions like if/else statements and case/casex/casez, always blocks and loops for modeling latches and flip-flops, functions, tasks, module instantiation, and parameterized designs.

Uploaded by

Balaji B Surendran
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Verilog HDL 18EC55

Module 3b
Verilog constructs to Gates

11/25/2020 DEPT. ECE, BGSIT-ACU 1


Continuous Assignment statement

11/25/2020 DEPT. ECE, BGSIT-ACU 2


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Procedural Assignment statement

11/25/2020 DEPT. ECE, BGSIT-ACU 5


Blocking Procedural assignment

11/25/2020 DEPT. ECE, BGSIT-ACU 6


11/25/2020 DEPT. ECE, BGSIT-ACU 7
Non-blocking procedural assignment

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Blocking vs. Non-blocking assignments

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Blocking vs. Non-blocking assignments

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Target of Assignment

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Assignment Restrictions

11/25/2020 DEPT. ECE, BGSIT-ACU 23


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Logical operators

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Arithmetic Operators

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Relational Operators

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Equality operators

11/25/2020 DEPT. ECE, BGSIT-ACU 33


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Shift operators

11/25/2020 DEPT. ECE, BGSIT-ACU 35


Vector operations

11/25/2020 DEPT. ECE, BGSIT-ACU 36


Part-selects

11/25/2020 DEPT. ECE, BGSIT-ACU 37


Bit-selects

11/25/2020 DEPT. ECE, BGSIT-ACU 38


Conditional Expression

11/25/2020 DEPT. ECE, BGSIT-ACU 39


Always statement

11/25/2020 DEPT. ECE, BGSIT-ACU 40


If statement

11/25/2020 DEPT. ECE, BGSIT-ACU 41


11/25/2020 DEPT. ECE, BGSIT-ACU 42
Case statement

11/25/2020 DEPT. ECE, BGSIT-ACU 43


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11/25/2020 DEPT. ECE, BGSIT-ACU 45
Casex

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Casez

11/25/2020 DEPT. ECE, BGSIT-ACU 48


11/25/2020 DEPT. ECE, BGSIT-ACU 49
11/25/2020 DEPT. ECE, BGSIT-ACU 50
Inferring latches

11/25/2020 DEPT. ECE, BGSIT-ACU 51


11/25/2020 DEPT. ECE, BGSIT-ACU 52
Loop statement

11/25/2020 DEPT. ECE, BGSIT-ACU 53


11/25/2020 DEPT. ECE, BGSIT-ACU 54
11/25/2020 DEPT. ECE, BGSIT-ACU 55
Modeling Flip-flops

11/25/2020 DEPT. ECE, BGSIT-ACU 56


11/25/2020 DEPT. ECE, BGSIT-ACU 57
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Functions

11/25/2020 DEPT. ECE, BGSIT-ACU 60


11/25/2020 DEPT. ECE, BGSIT-ACU 61
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Tasks

11/25/2020 DEPT. ECE, BGSIT-ACU 63


11/25/2020 DEPT. ECE, BGSIT-ACU 64
11/25/2020 DEPT. ECE, BGSIT-ACU 65
11/25/2020 DEPT. ECE, BGSIT-ACU 66
11/25/2020 DEPT. ECE, BGSIT-ACU 67
Using values x and z

11/25/2020 DEPT. ECE, BGSIT-ACU 68


11/25/2020 DEPT. ECE, BGSIT-ACU 69
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Gate level modeling

11/25/2020 DEPT. ECE, BGSIT-ACU 72


11/25/2020 DEPT. ECE, BGSIT-ACU 73
Module Instantiation Statement

11/25/2020 DEPT. ECE, BGSIT-ACU 74


11/25/2020 DEPT. ECE, BGSIT-ACU 75
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Parameterized Designs

11/25/2020 DEPT. ECE, BGSIT-ACU 77


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