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CO Unit 5

The document discusses the organization and operation of a basic CPU. It describes the main components of a CPU as the ALU, control unit, and registers. It explains the roles of each in fetching instructions from memory, interpreting operations, performing computations, and writing data. It also outlines the stages of an instruction cycle as fetching, interpreting, and executing instructions, as well as handling interrupts.

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20 views12 pages

CO Unit 5

The document discusses the organization and operation of a basic CPU. It describes the main components of a CPU as the ALU, control unit, and registers. It explains the roles of each in fetching instructions from memory, interpreting operations, performing computations, and writing data. It also outlines the stages of an instruction cycle as fetching, interpreting, and executing instructions, as well as handling interrupts.

Uploaded by

yadavsandeep84841
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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I Processor Organization

~• Reading data from memory or 1/0 module.

\--------.J·~ -~
• Execution of instruction may require performing
some arithmetic or logical operation on data.

Write Data

• Result of execution may require writing data to


memory of 1/0 module.
I Processor Organization

• To perform these tasks, the processor needs to store some


data temporarily.
• It needs to store instructions and data temporarily while an
instruction is being executed.
• The processor needs a small internal memory.
I Processor Organization

• Components of the processor:


• Arithmetic - Logic Unit (ALU): The ALU does the actual
computation or processing of data.
• Control Unit (CU): The control unit contro ls the movement of data
and instructions from and to the processo r & controls the
o p erat ion o f A LU.
I CPU with System Bus

Rrgl41lten

ALU
Control
unit

Control Data ,\ddress


bu.~ bu.~ bus
"-.. .----v---.1
Syst~m
I Internal Structure of the CPU
Arf~bra 11'c ...a lapr 111111

•
•
SMflff •

....
Arilluarlk

•• Pr •
I Register Organization

• User - visible Registers:


• Enable the machine or assembly language programmer to
minimize main memory references by optimizing use of registers.

• Control and Status Registers:


• Used by the contro l unit to contro l the operation of the p rocessor
and by privileged operating system programs to control the
execution of programs.
I Instruction Cycle
• An instruction cycle includes the following stages:
---
~
• Read the next instruction from memory and load into
the processor
•

• Interpret the operation code (o pcode) and p erform


the d esig nated operatio n.

• If enabled and occu rred, the current process state is


saved and CPU beg ins to serve the interru pt.
I The Instruction Cycle
Felda
• Two sub-cycles:

• Indirect Cycle

lnlernpt lndired • Interrupt Cycle

Exea1te
I The Indirect Cycle
• Execution of an instruction may involve 1 or m9 re operands in
memory, each requiring a memory access.
• If indirect addressing is used, then additional memory accesses
will be required.
• The fetching of t hose indirect addresses would require more instruction
stages.
• After an inst ruction is fetched, it is examined to determine if any
indirect addressing is involved. The required operands are tt-.' ,
fetched using the indirect addressino.
Instruction Cycle State Diagram

~lultipk Mialliplc
opcraath mu.I~

J
l1NNC1i1.1n complete. Rcrurn tar ~ns No
fc~dl "61 aiiWU.:llOD OI \ i&!Clur ~ lnrcft\lpc
I Data Flow - Fetch Cycle
CPU

PC
> ~L\R >
.
F\
~

Control
unit

,,, - ...
IR ~

... ~tBR <...


•

,\dd~ Data Control


bus bus bu.,
~IBR • ~tcmory buffer rcgi~t«
1

~IAR = ~len\nry adJn:s~ rcgi~tcr


IR • ln~1ion rcgi~cr
PC • Program count« _ _ _ _ _ _ _ _ _ _ _ _ ____..
I Data Flow - Interrupt Cycle
CPU

..) MAR - Memory AddNU Register


PC ~IAR
- MIR - Memory Buffer Register
/\ f'- l\temory PC - Program Counter
·1 t
Control ~
.........
Unit ...
~;

.......
~IBK
..
... ~
...
=:,

Address Data Control


--- bus
. ____________________ ~
bus bus

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