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All ICC2 Top Commands

The document describes the steps to perform placement optimization in IC design. It details commands to read design files, create placement floors, add power rails, perform legalization and optimize placement, and report results.

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Agnathavasi
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100% found this document useful (5 votes)
6K views4 pages

All ICC2 Top Commands

The document describes the steps to perform placement optimization in IC design. It details commands to read design files, create placement floors, add power rails, perform legalization and optimize placement, and report results.

Uploaded by

Agnathavasi
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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create_lib rp_top_MV -ref_lib

"/home/deva/ICC2_28NM_TECH2/tcbn28hpcplusbwp30p140hvt.ndm/
/home/deva/ICC2_28NM_TECH2/ts1n28hpcpuhdhvtb2048x129m4swbso_170a.ndm/
/home/deva/ICC2_28NM_TECH2/tsdn28hpcpuhdb4096x33m4mwa_170a.ndm" -technology
/home/deva/ICC2_28NM_TECH2/tsmcn28_9lm4X2Y2RUTRDL.tf

read_verilog
/home/guepd08030susdp21/scripting/synthesis/rp_top_top/outputs/rptop_netlist_april.vg

read_sdc /home/guepd08030susdp21/scripting/synthesis/rp_top_top/outputs/rptop_netlist_april.sdc

set_attribute [get_layers {M3 M5 M7 M9}] routing_direction veritcal

set_attribute [get_layers {M1 M2 M4 M6 M8 MRDL}] routing_direction horizontal

initialize_floorplan -control_type core -core_utilization 0.7 -shape R -orientation N -side_length


{1380 710} -core_offset {1.48 2.2 1.48 2.2} -flip_first_row true -coincident_boundary true

create_pin_guide -boundary {{1.4800 42.2850} {0.0000 122.0550}} -name tp_guide [get_ports -


filter "direction == in"] -pin_spacing 1

place_pins -ports [get_ports -filter "direction == in"]

create_pin_guide -boundary {{1382.9450 161.1850} {1381.4600 205.7600}} -name rgt_guide


[get_ports -filter "direction == out"] -pin_spacing 1

place_pins -ports [get_ports -filter "direction == out"]

#for removing pin boundary (remove_pin_guide -all)

set macros [get_cells -hierarchical -filter "is_hard_macro == true"]

create_placement -floorplan

create_keepout_margin -type hard -tracks_per_macro_pin 0.5 -min_padding_per_macro 5


[get_cells -physical_context -filter "is_hard_macro == true"]

#for all sides ^

#create_keepout_margin -tracks_per_macro_pin 0.5 [get_cells -physical_context -filter


"is_hard_macro == true"]

#create_mode func

#create_mode scan

#get_modes

#to change modes

#current_mode func #if it is in scan mode


#creating corners

create_corner ss0p88125_rcw

create_corner ss0p88m40_cw

create_corner ff0p88125_cb

create_corner ff0p88m40_rcb

#get_corners

#changing corners

#current_corner

current_corner ss0p88125_rcw

set_process_number 1

set_voltage 0.88

set_temperature 125

#for all 4 corners ^

#report_corners ss0p88125_rcw / do same for all corners

#give pg.tcl

source ../scripts/pg.tcl

#if we get drc's

connect_pg_net -automatic

check_pg_drc

check_pg_missing_vias

#for removing ENDCAP/TAPCELLS

get_cells -filter "ref_name =~ TAP*" / "ref_name=~ ENDCAP*"

remove_cells [get_cells -filter "ref_name =~ TAP*"] / ENDCAP*

#placing endcap cells/boundary cells

get_lib_cells
create_boundary_cells -left_boundary_cell
tcbn28hpcplusbwp30p140hvt/BOUNDARY_LEFTBWP30P140 -right_boundary_cell
tcbn28hpcplusbwp30p140hvt/BOUNDARY_RIGHTBWP30P140 -prefix ENDCAP

#placing tapcells

get_lib_cells TAP*

create_tap_cells -lib_cell tcbn28hpcplusbwp30p140hvt/TAPCELLBWP30P140 -distance 30 -


pattern stagger -prefix TAPCELL -skip_fixed_cells

#creating ports of VDD & VSS

create_port -direction in VDD

create_port -direction in VSS

create_net -power VDD

create_net -ground VSS

#connct pg to ports

connect_pg_net -net VDD [get_ports VDD]

connect_pg_net -net VSS [get_ports VSS]

#connecting pg to std cells

connect_pg_net -net VDD [get_pins -physical_context */VDD]

connect_pg_net -net VSS [get_pins -physical_context */VSS]

#app_options
ex:report_app_options *pg* =>shows all the options havng pg*

#to change any options in app_options

set_app_options -name place_opt.flow.trials_clock_tree -value false/true

#to turn off our hold* when it is in true

set_scenario_status -active false -hold false [get_scenarios *hold*]

#not including driving cells given below


set_lib_cell_purpose -include none {CK* DEL* *D24* *D18* *D16* *D20*}

get_lib_cells *BUFFD8*

add_buffer [remove_from_collection [get_ports] {VDD VSS clk spi_clk}] -new_cell_names


PORTBUFF -lib_cell tcbn28hpcplusbwp30p140hvt/BUFFD8BWP30P140HVT

sizeof_collection [get_cells PORTBUFF*] 418

sizeof_collection [get_ports] 426

magnet_placement [get_ports] -cells [get_cells PORTBUFF*] -mark_legalize_only

###legalize_placement -cells [get_cells *PORTBUFF*]

connect_pg_net -automatic

report_app_options *prefix*

set_app_options -name opt.common.user_instance_name_prefix -value initial_place

place_opt -to initial_place

sizeof_collection [get_cells *initial_place*] 0

set_app_options -name opt.common.user_instance_name_prefix -value hfns

place_opt -from initial_drc

sizeof_collection [get_cells *hfns*] 994

#we can change utilization at app_options


set utilization to 70% (set_app_options)

place_opt -to initial_place

report_congestion

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