Memory Interface

Microprocessors (66322) 1 Dr. Aladdin Masri

Memory Pin Connections
1. Address inputs
2. Data outputs or
input/outputs
3. Selection input M
Write
4. At least one Enable

control input to
select a read or Chip Output
Select Enable
write operation

Microprocessors (66322) 2 Dr. Aladdin Masri

Address Connections
• Select a memory location within the memory device.
• Almost always labeled from A0, the least significant
address input, to An
– where subscript n can be any value
• Always labeled as one less than total number of
address pins
– A 1K memory device has 10 address pins labeled from A0
to A9
• 10 address inputs are used to select any of its 1024 memory
locations
– A 12-bit address: A0-A11 ⇒ 212 = 4096 = 4K memory
locations
Microprocessors (66322) 3 Dr. Aladdin Masri
Data Connections
• All memory devices have a set of data outputs (ROM) or
input/outputs (RAM).
• An 8-bit-wide memory device is often called a byte-wide
memory
– Data pins on memory devices are labeled D0 through D7 for an
8-bit-wide memory device.
• Catalog listings of memory devices often refer to memory
locations times bits per location.
– A memory device with 1K memory locations and 8 bits in each
location is often listed as a 1K × 8 by the manufacturer
– A 4K x 8 memory contains 4,096 (4K) memory locations, each
containing 8-bits
– A 16M x 4 memory has 16 M memory locations, each being 4-
bits wide

Microprocessors (66322) 4 Dr. Aladdin Masri

Control/Selection Connections
• Each memory device has at least one input that selects or
enables the memory device.
– Often called a chip select ( ), chip enable ( ) or simply select
( ̅)
– If more than one connection is present, all must be activated
to read or write data.
• ROM has a control pin, an output enable ( ) or gate ( ̅ ).
– pin enables and disables a set of tri-state buffers to read data.
• RAM has either one or two control inputs, a read-write
(R/ ) or write enable (or ) and read enable ( ) or
( ̅ ).
– When the two controls are present, they must never both be
active at the same time
– While if both inputs are inactive, data are neither written nor
read.
Microprocessors (66322) 5 Dr. Aladdin Masri
ROM: Read Only Memory
• Non Volatile data storage (remains valid after power off)
• For permanent storage of system software and data
• Can be:
1. ROM: programmed during fabrication at the factory
2. PROM: Programmable ROM (Programmed once)
– Programmed in a PROM programmer that burns fuses
– Once programmed, can not be erased for reprogramming
3. EPROM: Erasable Programmable ROM (Programmed many)
– Reprogrammed in an EPROM programmer
– Erased by exposure to UV light for about 20 minutes before reprogramming
4. EEPROM: Electrically Erasable Programmable ROM (Programmed
many)
– Other names: RMM (Read mostly memory), NOVRAM (Non Volatile RAM),
Flash memory
– Electrically erasable in the system, but they require more time to erase than
normal RAM
– BIOS, memory for digital cameras and MP3, USB storage devices …
Microprocessors (66322) 6 Dr. Aladdin Masri
EPROM Example: The 2716
• 2K x 8 read only memory
Address
– 1 bit + 10 bits = 11 Address inputs
– 8 Data outputs
• Members of the 27XXXX family:
– 2704 : 512 x 8
– 2708 : 1K x 8 Control
– 2716 : 2K x 8
– 2732 : 4K x 8
– 2764 : 8K x 8
– 27128 : 16K x 8
– 27256 : 32K x 8 Data
– 27512 : 64K x 8
– 271024: 128K x 8
• = Memory capacity in K bits
• PD/PGM = /P
= READ/Program ≈ /W

Microprocessors (66322) 7 Dr. Aladdin Masri

RAM Memory
• RAM: Random Access Memory
– better Read/Write Memory RWM
– Volatile data storage (data disappears after power off)
– For temporary storage of application software and data
• Can be
1. SRAM: Static RAM
– Essentially uses flip-flops to store charge (transistor circuit)
– As long as power is present, transistors do not lose charge (no
refresh)
– Very fast (no sense circuitry to drive nor charge depletion)
– Complex construction
– Large bit circuit
– Expensive
– Used for Cache RAM because of speed and no need for large
volume
Microprocessors (66322) 8 Dr. Aladdin Masri
Static RAM
Example: The 4016 (2K x 8 RAM )

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RAM Memory
‘High’ Voltage at Y
2. DRAM: Dynamic RAM allows current to flow
from X to Z or Z to X
– Bits stored as charge in
capacitors Y
– Simpler construction
– Smaller per bit
X Z
– Less expensive
– Slower than SRAM
– Typical application is
main memory
one transistor and
– Essentially analogue one capacitor per bit
• Level of charge determines
value

Microprocessors (66322) 10 Dr. Aladdin Masri

DRAM Example: The 4464
• 64 K x 4 DRAM
– 16 bits memory address
– But only 8 address lines on the chip!
• 16 address lines split into row and column
8-bit parts:
MSB 15 …9 8 7 … 2 1 0 16-bit Address
Row Column
• MS 8-bit row address is first latched in
using the input (Row Address Select)
• Then 8-bit column address is latched in
using the input (Column Address
Select)
– This loads the 16-bit address into a latch
on the chip
• also acts as (chip select)
• ̅ (Read)
• is
Microprocessors (66322) 11 Dr. Aladdin Masri
Accessing DRAMs
DRAM Block Diagram
CAS

Addr[7:0] Column decoder

Row decoder
RAS Storage Array

Microprocessors (66322) 12 Dr. Aladdin Masri

DRAM Memory Modules
1. SIMM: Single In-Line Memory Module
– Devices and connection pins mounted on one
side.
– Available in 2 types:
• Older 30-Pin SIMMs
• Newer 72-Pin SIMMs
2. DIMM: Dual In-Line Memory Module
– Devices and pins mounted on both sides.
• DIMM 168-pin
• DIMM 184-pin (DDR SDRAM)
• DIMM 240-pin (DDR2 SDRAM and DDR3
SDRAM)
• SDRAM: Synchronous Dynamic RAM
• DDR: Double Data Rate
• Memory may have also a parity bit.
– Example: 4M x 9 bits = 4M x (8 data + 1 Parity)
Microprocessors (66322) 13 Dr. Aladdin Masri
SRAM vs. DRAM
Static Random Access Memory Dynamic Random Access Memory
(SRAM) (DRAM)

Storage
element

1. Fast 1. High density and less expensive

Advantages 2. No refreshing operations

1. Large silicon area 1. Slow

Disadvantages
2. expensive 2. Require refreshing operations

Applications High speed memory applications, Main memories in computer

Such as cache systems

Microprocessors (66322) 14 Dr. Aladdin Masri

10–2 Address Decoding
Why Decode Memory?
• Memory devices interfaced are usually of
smaller storage capacity than the full
address space of the processor
– In order to splice a memory device into the
address space of the processor, decoding is
necessary.
– Decoding makes the memory function at a
unique section or partition of the memory map.
• For example, the 8088 has 20 address
connections but the 2716 EPROM has 11
address connections only.
• However, the 8088 sends out a 20-bit memory address whenever it
reads or writes data.
– because the 2716 has only 11 address pins, there is a mismatch that must be
corrected
• The decoder corrects the mismatch by decoding address pins that do
not connect to the memory component.
Microprocessors (66322) 15 Dr. Aladdin Masri
Address Decoding Steps
1. Determine range of address for each device:
– Find starting address (base address)
– Find memory system size (more than one device)
• Number of bytes provided per device group
– Find ending address
2. Determine which address lines go to decoder
– Find number of address lines on device
• Goes direct from microprocessor to memory
– Find required pattern to decode
• Remaining address lines go to memory decoder
3. Design decoder to detect the required address bus pattern
– Write starting address in binary
– Write ending address in binary
– High order address bits that go to decoder must match in both starting and
ending addresses
– Find the enabling signals used at each memory or I/O device
– Draw circuit to detect these high order bits

Microprocessors (66322) 16 Dr. Aladdin Masri

Address Decoding Techniques
1. Using a NAND Gate
– CS is active low
• Problems with using a NAND:
– Small memory devices require large NAND gates
– Need one NAND gate for each memory device
– Not ideal for a block of several contagious
memory chips

Microprocessors (66322) 17 Dr. Aladdin Masri

Address Decoding Techniques
NAND Example 1
• Design the decoding circuit for interfacing 8KB EPROMs with a basic
8088 system at address 00000H, using NAND gate.
• Solution:
1. Since ROM size is 8 KB, number of address lines on device:
– 8K = 213 from Ao to A12
– From 0000 to 1FFFH
2. The microprocessor has 20 address bins, so:
– Address pins Ao to A12 will be connected directly to the memory
– Address pins A13 to A19 will be used to decode address
3. Complete address:
A19 A13 A12 Ao
• Starting address: 0000 000 0 0000 0000 0000
• Ending address: 0000 000 1 1111 1111 1111
Common part makes the 7 selector bits
(NAND inputs) =
• Enabling signals: IO/ and
Microprocessors (66322) 18 Dr. Aladdin Masri
 Address Decoding Techniques
NAND Example 1

IO/

Microprocessors (66322) 19 Dr. Aladdin Masri

Address Decoding Techniques
NAND Example 2
• Use a NAND gate to interface a 2KB EPROM at top of
the memory map
• Solution:
• 2K = 211 from Ao to A10
• Address pins A11 to A19 will be used to decode address
A19 A11 A10 Ao
• Ending address: 1111 1111 1 111 1111 1111
• Starting address: 1111 1111 1 000 0000 0000
Common part makes the
9 selector bits (NAND inputs)

• Enabling signals: IO/ and

Microprocessors (66322) 20 Dr. Aladdin Masri
Address Decoding Techniques
NAND Example 2

Microprocessors (66322) 21 Dr. Aladdin Masri

Address Decoding Techniques
NAND Example 3
• A 64KB RAM is to be interfaced to a 8088-based
system at address 40000H. Use NAND gate.
• Solution:
• 64K = 216 from Ao to A15
• Address pins A16 to A19 will be used to decode address
A19 A16 A15 Ao
• Starting address: 0100 0000 0000 0000 0000
• Ending address: 0100 1111 1111 1111 1111
Common part makes the 4 selector bits
(NAND inputs) =

• Enabling signals: IO/ and

Microprocessors (66322) 22 Dr. Aladdin Masri
 Address Decoding Techniques
NAND Example 3

IO/

Microprocessors (66322) 23 Dr. Aladdin Masri

Address Decoding Techniques
NAND Example 4
• Design a full address decoder using NAND Memory Address Range
for a 8088-based system that contains: RAM 4 E0000 – FFFFF
1. 512KB of EPROM starting at address RAM 3 C0000 – DFFFF
00000H composed of 64KB IC (8 chips)
RAM 2 A0000 – BFFFF
2. 512KB of RAM starting at address
80000H composed of128KB IC (4 chips) RAM 1 80000 – 9FFFF
• Solution: EPROM 8 70000 – 7FFFF
• For the EPROM each device has a size of EPROM 7 60000 – 6FFFF
64KB = 216 (Ao – A15) EPROM 6 50000 – 5FFFF
• For the RAM each device has a size of EPROM 5 40000 – 4FFFF
128KB = 217 (Ao – A16)
EPROM 4 30000 – 3FFFF
• Enabling signals: IO/ and
Each EPROM/RAM must be connected to a EPROM 3 20000 – 2FFFF
NAND gate EPROM 2 10000 – 1FFFF
EPROM 1 00000 – 0FFFF
Microprocessors (66322) 24 Dr. Aladdin Masri
Address Decoding Techniques
2. Using Decoders
– More appropriate than NAND
– The selection of devices is
determined by the physical wiring
– Disadvantage: All the memory
blocks must have the same size
• Two common decoders are the
74LS138 and the 74LS139
– The '138 is a 3-to-8 decoder with 3
enable inputs
– The '139 is a dual 2-to-4 decoder
with only 1 enable input for each
half

Microprocessors (66322) 25 Dr. Aladdin Masri

Address Decoding Techniques
Decoder Example 1
• Design a 1MB memory system consisting of
256KB multiple memory chips using decoder
• Solution:
• Since memory chip size is 256 KB, number of
address lines on device: 256K = 218
– Address pins Ao to A17 will be connected directly to
the memory
– Address pins A18 and A19 will be used as input lines for
the decoder
– IO/ will be used at the enable of the decoder
– Use 74LS139 decoder

Microprocessors (66322) 26 Dr. Aladdin Masri

Address Decoding Techniques
Decoder Example 1

256KB 256KB 256KB 256KB

CS CS CS CS

Addr[17:0]

Addr[18] 74LS139
2-to-4
decoder
Addr[19]
CS

IO/M

Microprocessors (66322) 27 Dr. Aladdin Masri

Address Decoding Techniques
Decoder Example 2
• Build a 32KB memory system by using four 8KB memory chips. The starting address of the 32KB
memory system is 30000H.
• Solution:
• Since the memory chips size is 8k=213; address pins Ao to A12 will be connected directly to the memory
• However, we have 4 chips, so we need one 74LS139 decoder, which means the two address lines A13
and A14 will be the input lines.
• The resting lines (A15 – A19) in addition to IO/ will be connected to NAND to enable the decoder

= 0011 0 11 1 1111 1111 1111 Address and select

0011 0 11 0 0000 0000 0000 of Chip 4
Chip 4
36000H
0011 0 10 1 1111 1111 1111 Address and select
Chip 3 of Chip 3
34000H 0011 0 10 0 0000 0000 0000
Chip 2
32000H 0011 0 01 1 1111 1111 1111 Address and select
Chip 1 of Chip 2
30000H 0011 0 01 0 0000 0000 0000
0011 0 00 1 1111 1111 1111 Address and select
0011 0 00 0 0000 0000 0000 of Chip 1

Microprocessors (66322) 28 Dr. Aladdin Masri

 Address Decoding Techniques
Decoder Example 2

IO/

Microprocessors (66322) 29 Dr. Aladdin Masri

Address Decoding Techniques
Decoder Example 3
• Given an 8088 system with 512KB RAM composed of 64KB (8
chips) starting at address 00000H, and 128KB ROM composed of
32KB (4 chips) starting at address E0000H, using decoders.
• Solution:
Memory Address Range
1. For the RAM memory:
• Chip size 64K=216; address pins Ao to A15 RAM 8 70000 – 7FFFF
will connected directly to the memory RAM 7 60000 – 6FFFF
• Since we have 8 chips, so we need one RAM 6 50000 – 5FFFF
74LS138 decoder:
RAM 5 40000 – 4FFFF
– The three address lines A16 – A18 will be the
input lines. RAM 4 30000 – 3FFFF
– The resting line A19 ( ) in addition to IO/ RAM 3 20000 – 2FFFF
will be connected to enable the decoder
– connected to (for a READ operation) RAM 2 10000 – 1FFFF
– connected to (for a WRITE operation) RAM 1 00000 – 0FFFF

Microprocessors (66322) 30 Dr. Aladdin Masri

Address Decoding Techniques
Decoder Example 3
2. For the ROM memory:
• Chip size 32K=215; address pins Ao to A14 will be
connected directly to the memory
• Since we have 4 chips, so we need one 74LS139 decoder,
– The two address lines A15 and A16 will be the input lines.
– The resting lines (A17 – A19) in addition to IO/ will be
connected to NAND to enable the decoder
• What happens if we have 74LS138 decoders only?
Memory Address Range
ROM 4 F8000 – FFFFF
ROM 3 F0000 – F7FFF
ROM 2 E8000 – EFFFF
ROM 1 E0000 – E7FFF

Microprocessors (66322) 31 Dr. Aladdin Masri

Address Decoding Techniques
Decoder Example 3

IO/

IO/

Microprocessors (66322) 32 Dr. Aladdin Masri

Address Decoding Techniques
Decoder Example 3
• If a 74LS138 decoder was used to interface the ROM
memory:
– The two address lines A15 – A17 will be the input lines.
• Hence, A17 must be always 1
– The resting lines A18 and A19 in addition to IO/ will be
connected to the decoder

IO/

Microprocessors (66322) 33 Dr. Aladdin Masri

Partial Decoding – Shadowing
• Not all the address space is implemented, only a
subset of the address lines are decoded to select
the memory or I/O device
– Less cost for decoding circuit
• Major disadvantage is when some address lines
are not used by the decoder or memory chip
(partial address decoding), mirror images occur
– Shadowing
• Each physical memory location is identified by
several possible addresses
– Using all combinations of the address lines that were
not used
Microprocessors (66322) 34 Dr. Aladdin Masri
Partial Decoding – Example
• From the previous example, given an 8088 system with 128KB ROM composed of
32KB (4 chips), if the NAND is not connected (address pins A17 – A19), explain
what happens?
• Solution:
• This device will be accessed regardless the address lines A17 – A19. So, the
address range will be:
1st starting address: 000 0 0 000 0000 0000 0000
1st ending address: 000 1 1 111 1111 1111 1111
• Or, all possible addresses will be:
1. 00000H – 1FFFFH
2. 20000H – 3FFFFH
3. 40000H – 5FFFFH
4. 60000H – 7FFFFH
5. 80000H – 9FFFFH
IO/
6. A0000H – BFFFFH
7. C0000H – DFFFFH
8. E0000H – FFFFFH

Microprocessors (66322) 35 Dr. Aladdin Masri

Address Decoding Techniques
3. Using PLD Decoders (Programmable logic devices)
– Many modern systems use programmable logic decoders in
place of integrated decoders
– They give total freedom in decoding different addresses for
individual memory devices
• Programmable logic devices may be called:
– PLA: Programmable logic array
– PAL: Programmable array logic
– FPGA: Field Programmable Gate Arrays
• A PAL is programmed with software such as PALASM,
the PAL assembler program.
• PLD design is accomplished using HDL (hardware
description language) or VHDL (Verilog HDL).
Microprocessors (66322) 36 Dr. Aladdin Masri
PAL16L8
• Has 10 fixed inputs, two fixed outputs, six pins
programmable as inputs or outputs and up to 16-
input wired AND.
• Chip comes with all cross points linked
– Programming removes all unwanted links, by blowing
out fused links
• It is ideal as a decoder because of its structure,
and because outputs are active low.
– AND-OR-INVERT (Inverted sum of Products)
• Active low outputs suit for inputs

Microprocessors (66322) 37 Dr. Aladdin Masri

PAL16L8

Microprocessors (66322) 38 Dr. Aladdin Masri

Address Decoding Techniques
PAL Example 1
• Given an 8088 based system with a 128KB RAM at address 00000, a
32KB RAM at address 40000H, and 256KB ROM composed of 64KB ICs
(4chips) at address 70000H. Write PAL equations. Draw the address
decoding logic using PAL16L8.
• Solution:
1. For the 128KB RAM memory:
• Chip size 128K=217; address pins Ao to A16 will connected directly to the
memory.
A19 A17 A16 Ao
Starting address: 000 0 0000 0000 0000 0000
Ending address: 000 1 1111 1111 1111 1111
Common part
• Address range: 00000 – 1FFFFH
• So, 128 = IO/

Microprocessors (66322) 39 Dr. Aladdin Masri

Address Decoding Techniques
PAL Example 1
2. For the 32KB RAM memory:
• Chip size 32K=215; address pins Ao to A14 will connected directly to the memory.
A19 A15 A14 Ao
Starting address: 0100 0 000 0000 0000 0000
Ending address: 0100 0 111 1111 1111 1111
Common part
• Address range: 40000 – 47FFFH
• So, 32 = IO/
3. For the 256KB ROM memory:
• Chip size 64K=216; address pins Ao to A15 will connected directly to the memory.
A19 A16 A15 Ao
1st chip starting address: 0111 0000 0000 0000 0000
1st chip ending address: 0111 1111 1111 1111 1111
Common part
• Address range: 70000 – 7FFFFH
• So, 1 = IO/
Microprocessors (66322) 40 Dr. Aladdin Masri
Address Decoding Techniques
PAL Example 1
A19 A16 A15 Ao
2st chip starting address: 1000 0000 0000 0000 0000
2st chip ending address: 1000 1111 1111 1111 1111
Common part

• Address range: 80000 – 8FFFFH

• So, 2 = IO/
A19 A16 A15 Ao
3st chip starting address: 1001 0000 0000 0000 0000
3st chip ending address: 1001 1111 1111 1111 1111
Common part

• Address range: 90000 – 9FFFFH

• So, 3 = IO/

Microprocessors (66322) 41 Dr. Aladdin Masri

Address Decoding Techniques
PAL Example 1
A19 A16 A15 Ao
4st chip starting address: 1010 0000 0000 0000 0000
4st chip ending address: 1010 1111 1111 1111 1111
Common part
• Address range: A0000 – AFFFFH
• So, 4 = IO/

A15 RAM128CS
A16 RAM32CS
A17 ROM1CS
A18 ROM2CS
A19 ROM3CS
IO/ ROM4CS

Microprocessors (66322) 42 Dr. Aladdin Masri

Address Decoding Techniques
PAL Example 2
• Given an 8088 based system with 128K RAM composed of 32KB ICs at
address 20000H, and 384K ROM composed of 64K ICs at address
A0000H. Write PAL equations. Draw the address decoding logic using
PAL16L8.
• Solution:
1. For the 128KB RAM memory:
• Chip size 32K=215; address pins Ao to A14 will connected directly to the
memory.
A19 A15 A14 Ao
1st chip starting address: 0010 0 000 0000 0000 0000
1st chip ending address: 0010 0 111 1111 1111 1111
Common part

• Address range: 00000 – 27FFFH

• So, 1 = IO/

Microprocessors (66322) 43 Dr. Aladdin Masri

Address Decoding Techniques
PAL Example 2
• RAM2 address range: 28000 – 2FFFFH
• So, 2 = IO/
• RAM3 address range: 30000 – 37FFFH
• So, 3 = IO/
• RAM4 address range: 38000 – 3FFFFH
• So, 4 = IO/

A15 RAM1CS
A16 RAM2CS
A17 RAM3CS
A18 RAM4CS
A19
IO/

Microprocessors (66322) 44 Dr. Aladdin Masri

Address Decoding Techniques
PAL Example 2
1. For the 384KB ROM memory:
• Chip size 64K=216; address pins Ao to A15 will connected directly to
the memory.
A19 A16 A15 Ao
1st chip starting address: 1010 0000 0000 0000 0000
1st chip ending address: 1010 1111 1111 1111 1111
Common part

• ROM1 Address range: A0000 – AFFFFH

• So, 1 = IO/
• ROM2 Address range: B0000 – BFFFFH
• So, 2 = IO/
• ROM3 Address range: C0000 – CFFFFH
• So, 3 = IO/
Microprocessors (66322) 45 Dr. Aladdin Masri
Address Decoding Techniques
PAL Example 2
• ROM4 Address range: D0000 – DFFFFH
• So, 4 = IO/
• ROM5 Address range: E0000 – EFFFFH
• So, 5 = IO/
• ROM6 Address range: F0000 – FFFFFH
• So, 6 = IO/

A16 ROM1CS
A17 ROM2CS
A18 ROM3CS
A19 ROM4CS
IO/ ROM5CS
ROM6CS

Microprocessors (66322) 46 Dr. Aladdin Masri

Address Decoding Techniques
Exercises
1. Repeat the solution of “Decoder Example 3”.
2. An 8088 based system composed of 128 KB RAM
composed of 32KB chips at address 00000, a single
256KB RAM chip at address 80000H and a 192KB ROM
composed of 32KB chips ending at the top of the 1MB
memory. Draw the complete memory map. Write PAL
equations. Draw the address decoding logic using
PAL16L8.
3. An 8088 based system composed of 256 KB RAM
composed of 32KB chips at address 20000H, and a 192KB
ROM composed of 64KB chips at address 90000H. Draw
the complete memory map. Write PAL equations. Draw
the address decoding logic using PAL16L8.

Microprocessors (66322) 47 Dr. Aladdin Masri

Interfacing EEPROM (Flash)
Memories
• Main Flash memory applications:
– Used when contents need to be changed only infrequently, e.g.:
1. Storing system BIOS
2. USB pen drives
3. MP3 audio players
• Similarities with SRAMs:
– Both need the 3 basic memory control inputs: , , and
• Differences with SRAMs:
1. EEPROM needs an additional programming controls and
programming (erasing) supply voltage.
– Used to be 25V or 12V, now 5V or even 3.3V.
2. EEPROM is much slower to write (erase) a byte: 0.4s vs.
10ns for SRAM
Microprocessors (66322) 48 Dr. Aladdin Masri
Interfacing EEPROM (Flash) to the
8088

Microprocessors (66322) 49 Dr. Aladdin Masri