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All VerilogLabs

The document describes writing Verilog code and test benches for various digital logic circuits. It includes: 1. Writing code for a bidirectional buffer and verifying it with a test bench. 2. Writing code for a 2-to-4 decoder using data flow and verifying it. 3. Writing code for a full adder using data flow and verifying it. 4. Writing additional code for half adders, muxes, priority encoders, and ripple carry adders along with corresponding test benches. The document provides RTL code, test bench code, sample waveforms, and discusses synthesis for each circuit designed. The goal is to learn how to model digital circuits in Ver

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0% found this document useful (0 votes)
365 views74 pages

All VerilogLabs

The document describes writing Verilog code and test benches for various digital logic circuits. It includes: 1. Writing code for a bidirectional buffer and verifying it with a test bench. 2. Writing code for a 2-to-4 decoder using data flow and verifying it. 3. Writing code for a full adder using data flow and verifying it. 4. Writing additional code for half adders, muxes, priority encoders, and ripple carry adders along with corresponding test benches. The document provides RTL code, test bench code, sample waveforms, and discusses synthesis for each circuit designed. The goal is to learn how to model digital circuits in Ver

Uploaded by

samruth
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
You are on page 1/ 74

LAB 1

1. Write a verilog code for bidirectional buffer and verify the same
using test bench

1. RTL code
//RTL
module triststebuf1( input ctrl,i,output reg y);

always@*
begin
if(ctrl)
y = i;
else
y = 'bz;
end
endmodule

module tristatebuf2( input ctrl,i,output reg y);


always@*
begin
if(!ctrl)
y = i;
else
y = 1'bz;
end
endmodule

module bidirect_buff(input ctrl_in,inout a,b);


assign b = (ctrl_in) ? a : 1'bz;
assign a = (~ctrl_in) ? b : 1'bz;

endmodule

2. Testbench code
//Test bench code:
module bidirect_buff_tb();

reg ctrl_in_tb;
reg tempa_tb,tempb_tb;
wire a_tb,b_tb;
integer i;

bidirect_buff DUT(ctrl_in_tb,a_tb,b_tb);
assign a_tb=(ctrl_in_tb==1'b1) ? tempa_tb:1'bz;
assign b_tb=(ctrl_in_tb== 1'b0) ? tempb_tb:1'bz;

initial
begin
for(i=0 ;i<8 ;i=i+1)
begin
{tempa_tb,tempb_tb,ctrl_in_tb} = i;
#10;
end
end

initial
begin
$monitor($time,"input tempa_tb = %b,tempb_tb = %b,output a = %b,b=
%b",tempa_tb,tempb_tb,a_tb,b_tb);
#100 $finish;
end

endmodule
3. Waveforms

4. Synthesis code
2. Write a verilog code for 2:4 decoder using data flow and verify using
test bench

1. RTL code
module decoder2_4(input I0, I1, output Y0, Y1, Y2, Y3);

assign Y0 = ~I1 & ~I0;


assign Y1 = ~I1 & I0;
assign Y2 = I1 & ~I0;
assign Y3 = I1 & I0;

endmodule
2. Testbench code

module decoder2_4_tb();
reg I1_tb, I0_tb;
wire Y0_tb, Y1_tb, Y2_tb, Y3_tb;
integer i;

//instantiation
decoder2_4 DEC(I1_tb, I0_tb, Y0_tb, Y1_tb, Y2_tb, Y3_tb);

//stimulus generation

initial
begin
for(i=0; i<4; i=i+1)
begin
{I1_tb, I0_tb} = i;
#10;
end
end

initial
$monitor("I1 = %b, I0 = %b,Y0 = %b,Y1 = %b,Y2 = %b,Y3 = %b",I1_tb, I0_tb, Y0_tb, Y1_tb,
Y2_tb, Y3_tb);

endmodule

3. Waveforms

4. Synthesis code
3. Write a verilog code for full adder using data flow and verify
using test bench
1. RTL code

module full_adder_data(input a_in, b_in, c_in, output sum_out, carry_out);

assign sum_out = a_in ^ b_in ^ c_in;


assign carry_out = a_in & b_in | b_in & c_in | a_in & c_in ;

endmodule

2. Testbench code
module full_adder_data_tb;

//Testbench global variables


reg a_tb,b_tb,c_tb;
wire sum_tb,carry_tb;

//Variable for loop iteration


integer i;

//Step1 : Instantiate the full adder with order based port mapping
full_adder FA(.a_in(a_tb), .b_in(b_tb), .c_in(c_tb), .sum_out(sum_tb), .carry_out(carry_tb));

//Process to initialize the variables at 0ns


/*initial
begin
a_tb = 1'b0;
b_tb = 1'b0;
c_tb = 1'b0;
end */

//Process to generate stimulus using for loop


initial
begin
for (i=0;i<8;i=i+1)
begin
{a_tb, b_tb, c_tb} = i;
#10;
end
end

//Process to monitor the changes in the variables


initial
$monitor(" a=%b, b=%b, c=%b, sum =%b, carry=%b",a_tb, b_tb, c_tb, sum_tb, carry_tb);

//Process to terminate simulation after 100ns


initial #100 $finish;

endmodule

3. Waveforms

4. Synthesis code
4. Write a verilog design code for a half adder using Data Flow abstraction
and verify using test bench

1. RTL code
module half_adder(input a_in ,b_in,
output sum_out,carry_out);

//Understand the Data-flow abstraction


assign sum_out = a_in ^ b_in;
assign carry_out = a_in & b_in;

endmodule

2. Testbench code
module half_adder_tb;

//Understand the Data-flow abstraction


reg a_tb, b_tb;
wire sum_tb, carry_tb;

//instantiation
half_adder DUT(a_tb, b_tb, sum_tb, carry_tb);
integer i;

//stimulus generation
initial
begin
for(i=0; i<4; i=i+1)
begin
{a_tb, b_tb} = i;
#10;
end
end

initial
$monitor("a=%b, b=%b, sum=%b, carry=%b",a_tb, b_tb, sum_tb, carry_tb);
Endmodule

3. Waveforms

4. Synthesis code
5. Write a verilog code for 4:1 mux using 2:1 multiplexers and
verify using test bench

1. RTL code
module mux2_1(input a_in, b_in, s_in, output y_out);

assign y_out = a_in & s_in | b_in & ~s_in;

endmodule

module mux4_1(input[3:0]i_in, input[1:0]s_in, output y_out);

wire w1,w2;

mux2_1 m1(i_in[0], i_in[1], s_in[0], w1);


mux2_1 m12(i_in[2], i_in[3], s_in[0], w2);
mux2_1 m3(w1, w2, s_in[1], y_out);

endmodule

2. Testbench code

module mux4_1_tb;

reg[3:0]i_tb;
reg[1:0]s_tb;
wire y_tb;

integer i;

//instantiation

mux4_1 MUX (i_tb, s_tb, y_tb);

//stimulus generation

initial
begin
for(i=0; i<64; i=i+1)
begin
{i_tb, s_tb} = i;
#10;
end
end

initial
$monitor("i=%b, s=%b, y=%b", i_tb, s_tb, y_tb);

endmodule

3. Waveforms

4. Synthesis code
6. Write a verilog code for 4x1 mux using decoder and tri state
buffer and verify the same using test bench

1. RTL code

module decoder2_4(I, Y);

input[1:0]I;
output[3:0]Y;

assign Y[0] = ~I[1] & ~I[0];


assign Y[1] = ~I[1] & I[0];
assign Y[2] = I[1] & ~I[0];
assign Y[3] = I[1] & I[0];

endmodule

module buffer(in, ctrl, out);

input in, ctrl;


output reg out;

always @ (*)
begin
if(ctrl)
out = in;
else
out = 1'bz;
end
endmodule

module mux4_1_decoder_buffer(i_in, sel_in, t_out, y_out);

input[3:0]i_in;
input[3:0]sel_in;
output[3:0]t_out;
output y_out;
wire[3:0]w;

decoder2_4 D1(sel_in, w);


buffer B0(i_in[0], w[0], t_out[0]);
buffer B1(i_in[1], w[1], t_out[1]);
buffer B2(i_in[2], w[2], t_out[2]);
buffer B3(i_in[3], w[3], t_out[3]);
assign y_out = t_out[sel_in];

endmodule

2. Testbench code

module mux4_1_decoder_buffer_tb;
reg[3:0]i_tb;
reg[1:0]sel_tb;
wire out_tb;
integer i;

//instantiation

mux4_1_decoder_buffer MDB(i_tb, sel_tb, out_tb);

//stimulus generaion

initial
begin
i_tb = 4'hb;
for(i=0; i<4; i=i+1)
begin
sel_tb = i;
#10;
end
end

initial
begin
#50 i_tb = 4'b0011;
for(i=0; i<4; i=i+1)
begin
sel_tb = i;
#10;
end
end

initial
begin
$monitor("i=%b, sel=%b, out=%b",i_tb, sel_tb, out_tb);
#100 $finish;
end

endmodule
3. Waveforms

4. Synthesis code
7. Write a verilog code for 8:3 priority encoder using structural model and
verify the same using test bench

1. RTL code
////RTL for 8:3 Priority encoder using structural modeling

module priority(i,h,idle);
input [7:0] i;
output [7:0] h;
output idle;
assign idle=(~i[0] & ~i[1] & ~i[2]& ~i[3]& ~i[4]& ~i[5]& ~i[6]& ~i[7]);
assign h[7]=i[7];
assign h[6]=i[6] & ~i[7];
assign h[5]=i[5] & ~i[6] & ~i[7];
assign h[4]=i[4] & ~i[5] & ~i[6] & ~i[7];
assign h[3]=i[3] & ~i[4] & ~i[5] & ~i[6] & ~i[7];
assign h[2]=i[2] & ~i[3] & ~i[4] & ~i[5] & ~i[6]& ~i[7];
assign h[1]=i[1] & ~i[2] & ~i[3] & ~i[4] & ~i[5]& ~i[6]& ~i[7];
assign h[0]=i[0] & ~i[1] & ~i[2] & ~i[3] & ~i[4]& ~i[5]& ~i[6]& ~i[7];

endmodule

///////////////binaryencoder
module binaryencoder(input [7:0]a, output [2:0]y);
assign y[0]=a[1] | a[3] | a[5] | a[7];
assign y[1]=a[2] | a[3] | a[6] | a[7];
assign y[2]=a[4] | a[5] | a[6] | a[7];

endmodule
///////////////////////priorityencoder
module priencoder8_3(input [7:0]i_in, output [2:0]y_out, output idle_out);
wire [7:0] w;
priority p(i_in,w,idle_out);
binaryencoder be(w,y_out);

endmodule

2. Testbench code
/////////////testbench

module priencoder8_3_tb;
reg [7:0]i_tb;
wire [2:0]y_tb;
wire idle_tb;

integer i;

/////task for encoder


task encode(input [7:0]k);
begin
i_tb=k;
end
endtask

///////task for delay


task delay;
begin
#10;
end
endtask

////////instantiation
priencoder8_3 dut(i_tb,y_tb,idle_tb);
initial
begin
for(i=0;i<256;i=i+1)
begin
encode(i);
delay;
end
end

initial
$monitor("i=%b,y=%b,idle=%b",i_tb,y_tb,idle_tb);

endmodule

3. Waveforms
4. Synthesis code

8. Write a verilog code for 4 bit Ripple carry adder using 1 bit full adder
and verify the same using test bench

1. RTL code
module RCA(A, B, cin, sum, cout);

input[3:0]A, B;
input cin;
output[3:0]sum;
output cout;
wire c1, c2, c3;

FA FA0(A[0], B[0], cin, sum[0], c1);


FA FA1(A[1], B[1], c1, sum[1], c2);
FA FA2(A[2], B[2], c2, sum[2], c3);
FA FA3(A[3], B[3], c3, sum[3], cout);

endmodule

module FA(input a_in, b_in, c_in, output sum_out, carry_out);

assign sum_out = a_in ^ b_in ^ c_in;


assign carry_out = a_in & b_in | b_in & c_in | a_in & c_in ;

endmodule

2. Testbench code

module RCA_tb;

reg[3:0]A_tb, B_tb;
reg c_tb;
wire[3:0] sum_tb;
wire cout_tb;

integer i, j;

//instantiation
RCA FA(A_tb, B_tb, c_tb, sum_tb, cout_tb);

//simulus generation

initial
begin
A_tb = 4'b0;
B_tb = 4'b0;
c_tb = 1'b0;
#10;
begin
for(i=0; i<16; i=i+1)
begin
A_tb = i;
for(j=0; j<16; j=j+1)
begin
B_tb = j;
#10;
end
end
end
end

initial
$monitor("A=%b, B=%b, c=%b, sum=%b, cout=%b",A_tb, B_tb, c_tb, sum_tb, cout_tb);

endmodule

3. Waveforms

4. Synthesis code
LAB 2

1.Write RTL and Test bench for ALU using arithmetic and logical
operators

1. RTL code

module alu(input [7:0]a_in,b_in,


input [3:0]command_in,
input oe,
output [15:0]d_out);

parameter ADD = 4'b0000, // Add two 8 bit numbers a and b.


INC = 4'b0001, // Increment a by 1.
SUB = 4'b0010, // Subtracts b from a.
DEC = 4'b0011, // Decrement a by 1.
MUL = 4'b0100, // Multiply 4 bit numbers a and b.
DIV = 4'b0101, // Divide a by b.
SHL = 4'b0110, // Shift a to left side by 1 bit.
SHR = 4'b0111, // Shift a to right by 1 bit.
AND = 4'b1000, // Logical AND operation
OR = 4'b1001, // Logical OR operation
INV = 4'b1010, // Logical Negation
NAND = 4'b1011, // Bitwise NAND
NOR = 4'b1100, // Bitwise NOR
XOR = 4'b1101, // Bitwise XOR
XNOR = 4'b1110, // Bitwise XNOR
BUF = 4'b1111; // BUF
//Internal variable used during ALU operation
reg [15:0]out;

/*Step1 : Write down the functionality of ALU based on the commands given above.
*Use arithmetic and logical operators* */
always@(command_in, a_in, b_in)
begin
case(command_in)
//--------- write the functionality here -------
ADD : out = a_in + b_in;
INC : out = a_in + 1'b1;
SUB : out = a_in - b_in;
DEC : out = a_in - 1'b1;
MUL : out = a_in * b_in;
DIV : out = a_in / b_in;
SHL : out = a_in << 1;
SHR : out = a_in >> 1;
INV : out = !(a_in);
AND : out = a_in && b_in;
OR : out = a_in || b_in;
NAND : out = ~(a_in & b_in);
NOR : out = ~(a_in | b_in);
XOR : out = a_in ^ b_in;
XNOR : out = ~a_in ~^ b_in;
BUF : out = a_in;

endcase
end

//Understand the tri-state logic for actual output


assign d_out = (oe) ? out : 16'hzzzz;

endmodule

2. Testbench code
module alu_tb();

//Testbench global variables


reg [7:0]a,b;
reg [3:0]command;
reg enable;
wire [15:0]out;

//Variables for iteration of the loops


integer m,n,o;

//Parameter constants used for displaying the strings during operation


parameter ADD = 4'b0000, // Add two 8 bit numbers a and b.
INC = 4'b0001, // Increment a by 1.
SUB = 4'b0010, // Subtracts b from a.
DEC = 4'b0011, // Decrement a by 1.
MUL = 4'b0100, // Multiply 4 bit numbers a and b.
DIV = 4'b0101, // Divide a by b.
SHL = 4'b0110, // Shift a to left side by 1 bit.
SHR = 4'b0111, // Shift a to right by 1 bit.
AND = 4'b1000, // Logical AND operation
OR = 4'b1001, // Logical OR operation
INV = 4'b1010, // Logical Negation
NAND = 4'b1011, // Bitwise NAND
NOR = 4'b1100, // Bitwise NOR
XOR = 4'b1101, // Bitwise XOR
XNOR = 4'b1110, // Bitwise XNOR
BUF = 4'b1111; // BUF

//Internal register for storing the string values


reg [4*8:0]string_cmd;

//Step1 : Instantiate the design ALU


alu DUT (a, b, command, enable, out);

//Step2 : Write a task named "initialize" to initialize the inputs of DUT


task initialize;
begin
{a, b, command, enable} = 0;
end
endtask

//Tasks used for generating stimulus


task en_oe(input i);
begin
enable=i;
end
endtask

task inputs(input [7:0]j,k);


begin
a=j;
b=k;
end
endtask

task cmd (input [3:0]l);


begin
command=l;
end
endtask

task delay();
begin
#10;
end
endtask

//Process to hold the string values as per the commands.


always@(command)
begin
case (command)
ADD : string_cmd = "ADD";
INC : string_cmd = "INC";
SUB : string_cmd = "SUB";
DEC : string_cmd = "DEC";
MUL : string_cmd = "MUL";
DIV : string_cmd = "DIV";
SHL : string_cmd = "SHL";
SHR : string_cmd = "SHR";
INV : string_cmd = "INV";
AND : string_cmd = "AND";
OR : string_cmd = "OR";
NAND : string_cmd = "NAND";
NOR : string_cmd = "NOR";
XOR : string_cmd = "XOR";
XNOR : string_cmd = "XNOR";
BUF : string_cmd = "BUF";
endcase
end

//Process used for generating stimulus by calling tasks & passing values
initial
begin
initialize;
en_oe(1'b1);
for(m=0; m<16; m=m+1)
begin
for(n=0; n<16; n=n+1)
begin
inputs(m,n);
for(o=0; o<16; o=o+1)
begin
command=o;
delay;
end
end
end
en_oe(0);
inputs(8'd20, 8'd10);
cmd(ADD);
delay;
en_oe(1);
inputs(8'd25, 8'd17);
cmd(ADD);
delay;
$finish;
end

//Process to monitor the changes in the variables


initial
$monitor("Input oe=%b, a=%b, b=%b, command=%s, Output out=%b",enable,a,b,string_cmd,out);

endmodule

3. Waveforms
4. Synthesis code

2. Working for operator


1. RTL code for operators
// logical_operators
module logical_operators();
reg A = 1'b1;
reg B = 1'b0;
// Initial statement is not synthesizable (test code only)
initial
begin
#10;

if (A || B)
$display("Either A or B is 1");
else
$display("Neither A or B is 1");

if (A && B)
$display("Both A and B are 1");
else
$display("A and r_B are not both 1");
if (!A)
$display("A is not 1");
else
$display("A is 1");
end
endmodule

// bitwise_operators
module bitwise_operators();
reg A = 1'b1;
reg B = 1'b0;
reg [3:0] X = 4'b0101;
reg [3:0] Y = 4'b1100;
wire [3:0] w_AND_VECTOR, w_OR_VECTOR, w_XOR_VECTOR, w_NOT_VECTOR;

assign w_AND_SCALAR = A & B;


assign w_OR_SCALAR = A | B;
assign w_XOR_SCALAR = A ^ B;
assign w_NOT_SCALAR = ~A;
assign w_AND_VECTOR = X & Y;
assign w_OR_VECTOR = X | Y;
assign w_XOR_VECTOR = X ^ Y;
assign w_NOT_VECTOR = ~X;

// Initial statement is not synthesizable (test code only)


initial
begin
#10;
// Scalar Tests:
$display("AND of 1 and 0 is %b", w_AND_SCALAR);
$display("OR of 1 and 0 is %b", w_OR_SCALAR);
$display("XOR of 1 and 0 is %b", w_XOR_SCALAR);
$display("NOT of 1 is %b", w_NOT_SCALAR);
#10;
// Vector Tests: (bit by bit comparison)
$display("AND of 0101 and 1100 is %b", w_AND_VECTOR);
$display("OR of 0101 and 1100 is %b", w_OR_VECTOR);
$display("XOR of 0101 and 1100 is %b", w_XOR_VECTOR);
$display("NOT of 0101 is %b", w_NOT_VECTOR);
end
endmodule

//conditional operators
module conditional_operators();
reg R = 1'b1;
wire W;
assign W = R ? 1'b1 : 1'b0;

initial begin
#10;
$display("OUTPUT: %s", R ? "VAISHNAVI" : "SUKKIREDDY");
$display("Value of conditional operators: %b", W);
$display("%h", (10 < 5) ? 16'hABCD : 16'h1234);
$display("%s", (1 == 1) ? "YES, ONE EQUALS ONE" : "HOW DID YOU GET
HERE");
end
endmodule

//shiftoperators
module shift_operator();
reg [3:0] Shift1 = 4'b1000;
reg signed [3:0] Shift2 = 4'b1000;

initial
begin
// Left Shift
$display("%b", Shift1 << 1);
$display("%b", $signed(Shift1) <<< 1); // Cast as signed
$display("%b", Shift2 <<< 1); // Declared as signed type // Right Shift
$display("%b", Shift1 >> 2);
$display("%b", $signed(Shift1) >>> 2); // Cast as signed
$display("%b", Shift2 >>> 2) ; // Declared as signed type
end
endmodule

// reduction_operators
module reduction_operators();
reg C;

// Initial statement is not synthesizable (test code only)


initial
begin
#10;
$display("AND Reduction of 4'b1101 is: %b", &4'b1101);
$display("AND Reduction of 4'b1111 is: %b", &4'b1111);
$display("NAND Reduction of 4'b1101 is: %b", ~&4'b1101);
$display("NAND Reduction of 4'b1111 is: %b", ~&4'b1111);
$display("OR Reduction of 4'b1101 is: %b", |4'b1101);
$display("OR Reduction of 4'b0000 is: %b", |4'b0000);

$display("NOR Reduction of 4'b1101 is: %b", ~|4'b1101);


$display("NOR Reduction of 4'b0000 is: %b", ~|4'b0000);

$display("XOR Reduction of 4'b1101 is: %b", ^4'b1101);


$display("XOR Reduction of 4'b0000 is: %b", ^4'b0000);

$display("XNOR Reduction of 4'b1101 is: %b", ~^4'b1101);


$display("XNOR Reduction of 4'b0000 is: %b", ~^4'b0000);

// A bitwise reduction can be stored in another reg.


C = |4'b0010;
$display("Reduction of 4'b0010 stored into a reg is: %b", C);
end
endmodule
2. Waveforms

LAB-3
1. Write behavioural description and test bench for 3:8 decoder.

1. RTL code
module dec3_8(input[2:0]i_in, output reg[7:0]y_out);

always@(i_in)
begin
case (i_in)
3'b000 : y_out = 8'b00000001;
3'b001 : y_out = 8'b00000010;
3'b010 : y_out = 8'b00000100;
3'b011 : y_out = 8'b00001000;
3'b100 : y_out = 8'b00010000;
3'b101 : y_out = 8'b00100000;
3'b110 : y_out = 8'b01000000;
3'b111 : y_out = 8'b10000000;
default : y_out = 'bz;
endcase
end

endmodule

2. Testbench code
//Testbench
module dec3_8_tb;

reg [2:0] i_tb;


wire [7:0] y_tb;
integer i;

//instantiation
dec3_8 DEC(i_tb, y_tb);

task dec_ip(input[2:0]k);
begin
i_tb=k;
end
endtask

task delay;
begin
#10;
end
endtask

//method 1
initial
begin
dec_ip({$random}%8);
delay;
dec_ip({$random}%8);
delay;
dec_ip({$random}%8);
delay;
dec_ip({$random}%8);
delay;
dec_ip({$random}%8);
delay;
dec_ip({$random}%8);
delay;
end
//method 2
/* initial
begin
for (i=0; i<8; i=i+1)
begin
dec_ip(i);
delay;
end
end
*/
initial
$monitor("i_tb=%b, y=%b", i_tb, y_tb);

endmodule

3. Waveforms

4. Synthesis code
2. Write behavioural description and test bench for 4:1 mux.
1. RTL code

module mux4_1(input[3:0] i_in, input[1:0] sel_in, output reg y_out);

//Step1 : Define the port directions with proper size & datatypes

//Step2 : Write the MUX behaviour as a parallel logic using "case"


always @ (i_in, sel_in)
begin
case (sel_in)
2'b00 : y_out = i_in [0];
2'b01 : y_out = i_in [1];
2'b10 : y_out = i_in [2];
2'b11 : y_out = i_in [3];
default : y_out = 'bz;

endcase
end
endmodule

2. Testbench code

module mux4_1_tb();

//Step1 : Write down the variables required for testbench


reg[3:0]i_tb;
reg[1:0]sel_tb;
wire y_tb;
integer i, j;

//Step2 : Instantiate the Design


mux4_1 MUX(i_tb, sel_tb, y_tb);

//Step3 : Declare a task to initialize inputs of DUT to 0


task mux4_1_ip(input[3:0]k);
begin
i_tb = k;
end
endtask

task sel_ip(input[1:0]j);
begin
sel_tb = j ;
end
endtask

task delay;
begin
#10 ;
end
endtask

//Step4 : Declare tasks with arguments for driving stimulus to DUT

//Step5 : Call the tasks from procedural process

//method1
/*initial
begin
mux4_1_ip({$random}%16);
sel_ip({$ramdom}%4);
delay;

mux4_1_ip({$random}%16);
sel_ip({$ramdom}%4);
delay;

mux4_1_ip({$random}%16);
sel_ip({$ramdom}%4);
delay;
end*/

//method2
initial
begin
for(i=0; i<4; i=i+1)
begin
sel_ip(i);
for (j=0; j<16; j=j+1)
begin
mux4_1_ip(j);
delay;
end
end
end
//Step6 : Use $monitor task to display inputs and outputs
initial
begin
$monitor("i=%b, sel=%b, y=%b",i_tb, sel_tb, y_tb);

//Step7 : Use $finish task to terminate the simulation at 100ns


#100 $finish;
end

endmodule

3. Waveforms

4. Synthesis code
3. Write behavioural description and test bench for 8:3 encoder
1. RTL code

module PriEn8_3(input[7:0]i_in, output reg[2:0]y_out, output reg valid_out);

always@(i_in)
begin
if (i_in[7])
begin
y_out = 3'b111;
valid_out = 1'b1;
end

else if (i_in[6])
begin
y_out = 3'b110;
valid_out = 1'b1;
end

else if (i_in[5])
begin
y_out = 3'b101;
valid_out = 1'b1;
end

else if (i_in[4])
begin
y_out = 3'b100;
valid_out = 1'b1;
end

else if (i_in[3])
begin
y_out = 3'b011;
valid_out = 1'b1;
end

else if (i_in[2])
begin
y_out = 3'b010;
valid_out = 1'b1;
end

else if (i_in[1])
begin
y_out = 3'b001;
valid_out = 1'b1;
end

else if (i_in[0])
begin
y_out = 3'b000;
valid_out = 1'b0;
end
end

endmodule

2. Testbench code
//Testbench

module PriEn8_3_tb;

reg[7:0]i_tb;
wire[2:0]y_out;
wire valid_out;

integer k;

PriEn8_3 PEN(i_tb, valid_tb, y_tb);

task PriEn_ip(input[7:0]k);
begin
i_tb = k;
end
endtask

task delay;
begin
#10;
end
endtask

initial
begin
PriEn_ip({$random}%256);
delay;
PriEn_ip({$random}%256);
delay;
PriEn_ip({$random}%256);
delay;
PriEn_ip({$random}%256);
delay;
PriEn_ip({$random}%256);
delay;
PriEn_ip({$random}%256);
delay;
end

initial
$monitor("i=%b, valid=%b, y=%b",i_tb, valid_tb, y_tb);

endmodule

3. Waveforms

4. Synthesis code
LAB 4

1. write an RTL description and test bench for D flipflop.

1. RTL code
module dff(input d_in, clk_in, rst_in, output reg q_out,output qb_out);

//Step1 : Declare Port Directions

/*Understand the Behaviour of D flip-flop &


check the coding style of synchronous reset*/

always@(posedge clk_in)
begin
if(rst_in)
q_out <= 1'b0;
else
q_out <= d_in;
end

//Step2 : Write the logic for qbar


assign qb_out = ~q_out;

endmodule

2. Testbench code
module dff_tb();

//Testbench global variables


reg d_tb, clk_tb , rst_tb;
wire q_tb, qb_tb;

//Step1 : Define a parameter with name "CYCLE" which is equal to 10

//Step2 : Instantiate the design


dff DFF(d_tb, clk_tb, rst_tb, q_tb, qb_tb);

//Understand the clock generation logic


initial
begin
clk_tb = 1'b0;
forever #10 clk_tb = ~clk_tb;
end

//Reset task
task rst_ip();
begin
@(negedge clk_tb);
rst_tb = 1'b1;
@(negedge clk_tb);
rst_tb = 1'b0;
end
endtask

//Data task
task d_ip(input i);
begin
@(negedge clk_tb);
d_tb = i;
end
endtask
//Process that generates stimulus by call by value method
initial
begin
rst_ip;
d_ip(0);
d_ip(1);
d_ip(0);
d_ip(1);
d_ip(1);
rst_ip;
d_ip(0);
d_ip(1);
#10;
$finish;
end

//Step3 : Use $monitor to display the various inputs and outputs

initial
$monitor("d=%b, clk=%b, rst=%b, q=%b, qb=%b",d_tb, clk_tb, rst_tb, q_tb, qb_tb);

endmodule

3. Waveforms

4. Synthesis circuit
2.write an RTL description and test bench for JK
flip flop using parameters declaration for the
respective scenarios HOLD,SET,RESET,TOGGLE

1. RTL code
//RTL code:

module jk_ff(input j,k,clk_in,rst_in,output reg q_out, outputqbar_out);

always@(posedge clk_in)
begin
if(rst_in)
q_out <= 1'b0;
else if(j==0 & k==0)
q_out <= q_out;
else if(j==0 & k==1)
q_out <= 1'b0;
else if(j==1 & k==0)
q_out <= 1'b1;
else q_out <= ~q_out;
end

assign qbar_out = ~q_out;

endmodule

2. Testbench code
//TEST BENCH:

module jk_ff_tb();

reg j_tb,k_tb,clk_tb,rst_tb;
wire q_tb,q_bar_tb;

jk_ff DUT(j_tb,k_tb,clk_tb,rst_tb,q_tb,q_bar_tb);
initial
begin
clk_tb = 1'b0;
forever #10 clk_tb = ~clk_tb;
end

task rst_ip;
begin
@(negedge clk_tb)
rst_tb = 1'b1;
@(negedge clk_tb)
#10 rst_tb = 1'b0;
end
endtask

task jk_ip(input i,input m );


begin
@(negedge clk_tb)
j_tb = i;
k_tb = m;
end endtask

initial
begin
rst_ip;
#100;
jk_ip(1'b0,1'b0);
jk_ip(1'b0,1'b1);

jk_ip(1'b1,1'b0);
jk_ip(1'b1,1'b1);

end

initial
begin
$monitor($time,"j_tb = %b,k_tb = %b,clk_tb = %b,rst_tb = %b,q_tb =%b,q_bar_tb =
$b",j_tb,k_tb,clk_tb,rst_tb,q_tb,q_bar_tb);
#400 $finish;
end

endmodule

3. Waveforms
4. Synthesis code

3. write an RTL description and test bench for MOD12


loadable binary up counter.

1.RTL code
//RTL for 4 bit up counter

module mod12_4bit(input[3:0]d_in, input l_in, rst_in, clk_in, output reg [3:0] d_out);

always@(posedge clk_in)
begin
if (rst_in)
d_out <= 4'b0000;
else if (l_in)
d_out <= d_in;
else if (d_out == 4’1011)
d_out <= 4’0000;
else
d_out <= d_out+1;

end

endmodule

2. Testbench code

module syn4bit_upcount_tb;

reg [3:0]d_tb;
reg l_tb, rst_tb, clk_tb;
wire [3:0] dout_tb;

syn4bit_upcount SBUC(d_tb, l_tb, rst_tb, clk_tb, dout_tb);

initial
begin
clk_tb = 1'b0;
forever #10 clk_tb = ~clk_tb;
end

task rst_ip;
begin
@(negedge clk_tb);
rst_tb = 1'b1;
@(negedge clk_tb);
rst_tb = 1'b0;
end
endtask

task d_ip(input [3:0]j);


begin
@(negedge clk_tb);
d_tb = j;
end
endtask

task l_ip(input k);


begin
@(negedge clk_tb);
l_tb = k;
end
endtask
initial
begin
rst_ip;
d_ip ({$random}%8);
l_ip('b0);
#10 d_ip({$random}%8);
l_ip ('b1);
#10
rst_ip;
d_ip ({$random}%8);
l_ip('b0);
#10 d_ip({$random}%8);
l_ip ('b1);

end

initial
begin
#200 $finish;
$monitor ("d=%b, l=%b, clk=%b, rst=%b, dout=%b", d_tb, l_tb, clk_tb, rst_tb, dout_tb);
end

endmodule
3. Waveforms

4. Synthesis circuit
4.write an RTL description and test bench for 4 bit siso
1. RTL code

module siso_4bit(input si_in, clk_in, rst_in, output so_out);

reg [3:0]temp;

always@(posedge clk_in)
begin
if(rst_in)
temp <= 4'b0000;
else
begin
temp[3] <= si_in;
temp[2] <= temp[3];
temp[1] <= temp[2];
temp[0] <= temp[1];
end
end

//Step2 : Write the logic for qbar


assign so_out = temp[0];

endmodule

2. Testbench code

module siso_4bit_tb();

//Testbench global variables


reg si_tb, clk_tb, rst_tb;
wire so_tb;
//Step1 : Define a parameter with name "CYCLE" which is equal to 10

//Step2 : Instantiate the design


siso_4bit SISO(si_tb, clk_tb, rst_tb, so_tb);

//Understand the clock generation logic


initial
begin
clk_tb = 1'b0;
forever #10 clk_tb = ~clk_tb;
end

//Reset task
task rst_ip();
begin
@(negedge clk_tb);
rst_tb = 1'b1;
@(negedge clk_tb);
rst_tb = 1'b0;
end
endtask

//Data task
task si_ip(input i);
begin
@(negedge clk_tb);
si_tb = i;
end
endtask

//Process that generates stimulus by call by value method


initial
begin
rst_ip;
si_ip(0);
si_ip(1);
end

//Step3 : Use $monitor to display the various inputs and outputs

initial
begin
$monitor("si=%b, clk=%b, rst=%b, so=%b",si_tb, clk_tb, rst_tb, so_tb);
#200 $finish;
end

endmodule

3. Waveforms
4. Synthesis code

5. Implement SR latch at gate level modeling and verify test bench


1. RTL code

module sr_lat(input s_in, r_in, output q_out, output qn_out);

//wire w1, w2;


nand n1(q_out, s_in, qn_out);
nand n2(qn_out, r_in, q_out);
endmodule

2. Testbench code

module sr_lat_tb;

reg s_tb, r_tb;


wire q_tb, qn_tb;

sr_lat SRL(s_tb, r_tb, q_tb, qn_tb);

initial
begin
s_tb <= 1'b0;
r_tb <= 1'b0;
#5
s_tb <= 1'b0;
r_tb <= 1'b1;
#5
s_tb <= 1'b1;
r_tb <= 1'b0;
#5
s_tb <= 1'b1;
r_tb <= 1'b1;

end

initial
begin

$monitor("s=%b, r=%b, q=%b, qn=%b",s_tb, r_tb, q_tb, qn_tb);


end

endmodule

3. Waveforms
4. Synthesis code

6.write an RTL description and test bench for 4 bit synchronous


loadable up counter .

1. RTL code
//RTL for 4 bit up counter

module syn4bit_upcount(input[3:0]d_in, input l_in, rst_in, clk_in, output reg [3:0] d_out);

always@(posedge clk_in)
begin
if (rst_in)
d_out <= 4'b0000;
else if (l_in)
d_out <= d_in;
else
d_out <= d_out+1;
end

endmodule

2. Testbench
module syn4bit_upcount_tb;

reg [3:0]d_tb;
reg l_tb, rst_tb, clk_tb;
wire [3:0] dout_tb;

syn4bit_upcount SBUC(d_tb, l_tb, rst_tb, clk_tb, dout_tb);

initial
begin
clk_tb = 1'b0;
forever #10 clk_tb = ~clk_tb;
end

task rst_ip;
begin
@(negedge clk_tb);
rst_tb = 1'b1;
@(negedge clk_tb);
rst_tb = 1'b0;
end
endtask

task d_ip(input [3:0]j);


begin
@(negedge clk_tb);
d_tb = j;
end
endtask

task l_ip(input k);


begin
@(negedge clk_tb);
l_tb = k;
end
endtask

initial
begin
rst_ip;
d_ip ({$random}%8);
l_ip('b0);
#10 d_ip({$random}%8);
l_ip ('b1);
#10
rst_ip;
d_ip ({$random}%8);
l_ip('b0);
#10 d_ip({$random}%8);
l_ip ('b1);

end

initial
begin
#200 $finish;
$monitor ("d=%b, l=%b, clk=%b, rst=%b, dout=%b", d_tb, l_tb, clk_tb, rst_tb, dout_tb);
end

endmodule
3. Waveforms

3. Synthesis circuit
7. write an RTL description and test bench for T flipflop using D flipflop.
1. RTL

//RTL tff using dff

module TFF_DFF(input T, CLK, RST, output Q, Q_B);

wire W = Q ^ T;

D_FF U1(.D(W), .CLK(CLK), .RST(RST), .Q(Q), .Q_B(Q_B));

endmodule

module D_FF(input D, CLK, RST, output Q, Q_B);

reg q;

always@(posedge CLK)
if(RST) begin
q <= 0;
end
else
begin
q <= D;
end
assign Q = q;
assign Q_B = ~q;

endmodule

2. Testbench
//testbench tff using dff
module T_D_TB();

reg CLK, RST, T;


wire Q, Q_B;

TFF_DFF DUT(.CLK(CLK), .RST(RST), .T(T), .Q(Q), .Q_B(Q_B));

task initialize;
begin
{T, CLK} = 0;
RST = 1;

$monitor("s_time = %t, T =%b, Q = %b, Q_B =%b", $time, T, Q, Q_B);


end
endtask

always begin
forever begin
#5 CLK = ~ CLK;
end
end

task rst;
begin
@(negedge CLK) RST = 1;
@(negedge CLK) RST = 0;
end
endtask

task load(input ip);


begin
@(negedge CLK) T = ip;
@(negedge CLK) T = 0;
end
endtask

initial begin
initialize;
rst;
@(negedge CLK) T = 1;
@(negedge CLK) T = 0;
@(negedge CLK) T = 1;
@(negedge CLK) T = 0;

#50 $stop;
end
endmodule

3. Waveforms
4. Synthesis Circuit

8.write an RTL description and test bench for 4 bit


loadable binary syncronous up down counter

1. RTL code
module updown_counter(input[3:0]d_in, input l_in, rst_in, clk_in, mode_ctrl, output reg[3:0] d_out);

always@(posedge clk_in)
if (rst_in)
d_out <= 4'b0000;
else if (l_in)
d_out <= d_in;
else
begin
case (mode_ctrl)
1'b0 : d_out <= d_out + 1;
1'b1 : d_out <= d_out - 1;
endcase
end

endmodule

2. Testbench code
module updown_counter_tb;

reg [3:0]d_tb;
reg l_tb, rst_tb, clk_tb, mode_ctrl_tb;
wire [3:0] dout_tb;

updown_counter UDC (d_tb, l_tb, rst_tb, clk_tb, mode_ctrl_tb, dout_tb);

initial
begin
clk_tb = 1'b0;
forever #10 clk_tb = ~clk_tb;
end

task rst_ip;
begin
@(negedge clk_tb);
rst_tb = 1'b1;
@(negedge clk_tb);
rst_tb = 1'b0;
end
endtask

task d_ip(input [3:0]j);


begin
@(negedge clk_tb);
d_tb = j;
end
endtask

task l_ip(input k);


begin
@(negedge clk_tb);
l_tb = k;
end
endtask

initial
begin
rst_ip;
d_ip ({$random}%8);
l_ip('b0);
mode_ctrl_tb = 1'b0;
#10 d_ip({$random}%8);
l_ip ('b1);
mode_ctrl_tb = 1'b1;
#10
rst_ip;
d_ip ({$random}%8);
l_ip('b0);
mode_ctrl_tb = 1'b1;
#10 d_ip({$random}%8);
l_ip ('b1);
mode_ctrl_tb = 1'b0;

end

initial
begin
#200 $finish;
$monitor ("d=%b, l=%b, clk=%b, rst=%b, dout=%b", d_tb, l_tb, clk_tb, rst_tb, dout_tb);
end

endmodule

3. Waveforms

4. Synthesis circuit
LAB 5

1. write an RTL description and test bench for a 8x16 asynchronous dual
port RAM

RTL code
module asyn8_16dpram
( input clk, //clock
input wr_en, //write enable for port 0
input [7:0] data_in, //Input data to port 0.
input [3:0] addr_in_0, //address for port 0
input [3:0] addr_in_1, //address for port 1
input port_en_0, //enable port 0.
input port_en_1, //enable port 1.
output [7:0] data_out_0, //output data from port 0.
output [7:0] data_out_1 //output data from port 1.
);

//memory declaration.
reg [7:0] ram[0:15];

//writing to the RAM


always@(posedge clk)
begin
if(port_en_0 == 1 && wr_en == 1) //check enable signal and if write enable is ON
ram[addr_in_0] <= data_in;
end

//always reading from the ram, irrespective of clock.


assign data_out_0 = port_en_0 ? ram[addr_in_0] : 'dZ;
assign data_out_1 = port_en_1 ? ram[addr_in_1] : 'dZ;
endmodule

1. Testbench code
module asyn8_16dpram_tb;

// Inputs
reg clk;
reg wr_en;
reg [7:0] data_in;
reg [3:0] addr_in_0;
reg [3:0] addr_in_1;
reg port_en_0;
reg port_en_1;

// Outputs
wire [7:0] data_out_0;
wire [7:0] data_out_1;

integer i;

// Instantiate the Unit Under Test (UUT)


dual_port_ram uut (
.clk(clk),
.wr_en(wr_en),
.data_in(data_in),
.addr_in_0(addr_in_0),
.addr_in_1(addr_in_1),
.port_en_0(port_en_0),
.port_en_1(port_en_1),
.data_out_0(data_out_0),
.data_out_1(data_out_1)
);

always
#5 clk = ~clk;

initial begin
// Initialize Inputs
clk = 1;
addr_in_1 = 0;
port_en_0 = 0;
port_en_1 = 0;
wr_en = 0;
data_in = 0;
addr_in_0 = 0;
#20;
//Write all the locations of RAM
port_en_0 = 1;
wr_en = 1;
for(i=1; i <= 16; i = i + 1) begin
data_in = i;
addr_in_0 = i-1;
#10;
end
wr_en = 0;
port_en_0 = 0;
//Read from port 1, all the locations of RAM.
port_en_1 = 1;
for(i=1; i <= 16; i = i + 1) begin
addr_in_1 = i-1;
#10;
end
port_en_1 = 0;
end

endmodule

2. Waveforms

3. Synthesis circuit
2. write an RTL design for 8x16 asynchronous single port RAM
memory and verified using test bench

1. RTL code
//8x16 async single port ram memory

module asyn8_16spram(addr_in,we_in,enable_in,data);

input [3:0]addr_in;
input we_in,enable_in;
inout [7:0]data;
reg [7:0]mem[15:0];

always@(data,we_in,enable_in,addr_in)
if(we_in && !enable_in)
mem[addr_in]=data;

assign data = (enable_in && !we_in) ? mem[addr_in] :8'hz;

endmodule

2. Testbench code
//async singleport ram8x16 test bench

module asyn8_16spram_tb();

wire [7:0]data_tb;
reg [3:0]addr_tb;
reg we_tb,enable_tb;
reg [7:0]tempb;

integer a;

asyn8_16spram RAM(addr_tb,we_tb,enable_tb,data_tb);

assign data_tb = (we_tb && !enable_tb) ? tempb :8'h0;

task initialized();
begin
we_tb=1'b0;
enable_tb=1'b0;
tempb=8'hz;
end
endtask

task stimulus(input [3:0]i,input [7:0]j);


begin
addr_tb = i;
tempb = j;
end
endtask

task write();
begin
we_tb=1'b1;
enable_tb = 1'b0;
end
endtask

task read();
begin
we_tb=1'b0;
enable_tb = 1'b1;
end
endtask

task delay;
begin
#10;
end
endtask

initial
begin
initialized;
delay;
write;

for(a=0;a<16;a=a+1)
begin
stimulus(a,a);
delay;
end

initialized ;
delay;
read;

for(a=0;a<16;a=a+1)
begin
stimulus(a,a);
delay;
end

$finish;
end

initial
$monitor("addr = %b,data_tb = %b,we_tb = %b,enable_tb =%b",addr_tb,data_tb,we_tb,enable_tb);

endmodule

3. Waveforms
4. Synthesis circuit

3. Write an RTL design for clock buffer and verified using test
bench.

1. RTL code
//RTL code:
module clk_buff(input I,output Y);
buf buff(Y,I);

endmodule

2. Testbench code
//Testbench code:

module clk_buff_tb;
reg clk_tb;
wire Y_tb;

clk_buff DUT(clk_tb,Y_tb); integer t1,t2,D;

initial
begin
clk_tb=1'b0;
forever #10 clk_tb=~clk_tb;
end

task initialization;
begin
t1=1'b0;
t2=1'b0;
D =1'b0;
end
endtask

initial
begin
fork
@(posedge clk_tb)
t1=$time;
@(posedge Y_tb)
t2=$time;
join
D=t2-t1;
if(D)
$display("t1=%d,t2=%d:the phase is difference",t1,t2);
else
$display("t1=%d,t2=%d:the phase is same",t1,t2);
end

initial
begin
#110$stop;
end

endmodule

3. Waveforms
4. Synthesis circuit

4. write an RTL description and test bench for a 16x8 synchronous


dual port RAM memory

1. RTL code
/sync dual port ram 16x8 mem
module syn16_8dpram(d_in,clk_in,rst_in,we_in,wr_add_in,re_in,rd_add_in,d_out);
input [3:0] wr_add_in,rd_add_in;
input [7:0]d_in;
input we_in,re_in,rst_in,clk_in;
output reg[7:0]d_out;
reg[7:0]mem[15:0];

integer i;

always@(posedge clk_in)
begin
if(rst_in)
begin
for(i=0;i<16;i=i+1)
begin
mem[i] = 'b0;
end
d_out = 'b0;
end
else
begin
if(we_in)
mem[wr_add_in] <= d_in;
if(re_in)
d_out <= mem[rd_add_in];
end
end endmodule

2. Testbench code
//Test bench code:
module syn16_8dpram_tb();
reg [3:0] wr_add_tb,rd_add_tb;
reg [7:0]d_tb;
reg we_tb,re_tb,rst_tb,clk_tb;
wire [7:0]d_out_tb;
syn16_8dpram DUT(d_tb,clk_tb,rst_tb,we_tb,wr_add_tb,re_tb,rd_add_tb,d_out_tb);
parameter cycle=10;
always
begin
#(cycle/2);
clk_tb = 0;
#(cycle/2) clk_tb = ~clk_tb;
end
task rst_ip;
begin
rst_tb = 1'b1; #10;
rst_tb = 1'b0;
end
endtask
task initialize ();
begin
we_tb = 1'b0;
re_tb = 1'b0;
end
endtask
task write(input i,input[3:0]j,input [7:0]k);
begin
@(negedge clk_tb)
we_tb = i;
wr_add_tb = j;
d_tb = k;
end
endtask
task read(input l,input [3:0]m);
begin
@(negedge clk_tb);
re_tb = l;
rd_add_tb = m;
end
endtask
initial
begin
initialize();
rst_ip; repeat(10)
write(1'b1, {$random}%8,{$random}% 6544);
#5;
repeat(10)
read(1'b0, {$random}%8); #50;
repeat(10)
write(1'b0, {$random}%8,{$random}% 6544);
#5;
repeat(10)
read(1'b1, {$random}%8); #100 $finish;
end
initial
$monitor("d_tb = %b,clk_tb = %b,rst_tb = %b,we_tb = %b,re_tb= %b,wr_add_tb = %b,rd_add_tb =
%b,d_out_tb =%b",d_tb,clk_tb,rst_tb,we_tb,wr_add_tb,re_tb,rd_add_tb,d_out_tb);
endmodule

3. Waveforms

4. Synthesis circuit
LAB 6

1. write an RTL description for a 101 sequence detector and verify


using test bench(mealy FSM with overlapping)

RTL code for 101 sequence detector by mealy machine with overlapping
RTL code

//FSM seq detector


module seq_det(seq_in,
clock,
reset,
d_out);

//Step1 : Declare the states as parameter "IDLE","STATE1","STATE2","STATE3"


parameter IDLE = 2'b00,
STATE1 = 2'b01,
STATE2 = 2'b10,
STATE3 = 2'b11;

//Step2 : Write down the ports direction


input seq_in, clock, reset;
output d_out;

//Internal registers
reg [1:0]pre_state, next_state;
//Step3 : Write down the sequential logic for present state with active high asychronous
reset
always@(posedge clock)
begin
if(reset)
pre_state <= IDLE;
else
pre_state <= next_state;
end

//Understand the combinational logic for next state


always@(pre_state, seq_in)
begin
case(pre_state)
IDLE :
if(seq_in==1)
next_state=STATE1;
else
next_state=IDLE;
STATE1 :
if(seq_in==0)
next_state=STATE2;
else
next_state=STATE1;
STATE2 :
if(seq_in==1)
next_state=STATE3;
else
next_state=IDLE;
STATE3 :
if(seq_in==1)
next_state=STATE1;
else
next_state=STATE2;

default: next_state=IDLE;

endcase
end

//Step4 : Write down the logic for Moore output d_out


assign d_out = (pre_state == STATE3);

endmodule
1. Testbench code
// Testbech FSM
module seq_det_tb();

//Testbench global variables


reg seq_tb, clock, reset;
wire dout;

//Parameter constant for CYCLE


parameter cycle = 10;

//DUT Instantiation
seq_det SQD(.seq_in(seq_tb),
.clock(clock),
.reset(reset),
.d_out(dout));

//Step1 : Generate clock, using parameter "CYCLE"


initial
begin
clock = 1'b0;
forever #(cycle/2) clock = ~clock;
end

/*Step2 : Write a task named "initialize" to initialize


the input din of sequence detector*/
task initialize;
begin
seq_tb = 0;
end
endtask

//Delay task
task delay(input integer i);
begin
#i;
end
endtask

/*Step3 : Write a task named "RESET" to reset the design,


use delay task for adding delays*/
task RESET;
begin
reset = 1;
delay(10);
reset = 0;
end
endtask

/*Step4 : Write a task named "stimulus" which provides input to


design on negedge of clock*/
task stimulus(input k);
begin
@(negedge clock);
seq_tb = k;
end
endtask

//Process to monitor the changes in the variables


initial
$monitor("Reset=%b, pre_state=%b, Din=%b, Output Dout=%b",
reset,SQD.pre_state,seq_tb,dout);

/*Process to display a string after the sequence is detected and dout is asserted.
SQD.state is used here as a path hierarchy where SQD is the instance name acting
like a handle to access the internal register "state" */
always@(SQD.pre_state or dout)
begin
if(SQD.pre_state==2'b11 && dout==1)
$display("Correct output at state %b", SQD.pre_state);
end

/*Process to generate stimulus by calling the tasks and


passing the sequence in an overlapping mode*/
initial
begin
initialize;
RESET;
stimulus(0);
stimulus(1);
stimulus(0);
stimulus(1);
stimulus(0);
stimulus(1);
stimulus(1);
RESET;
stimulus(1);
stimulus(0);
stimulus(1);
stimulus(1);
delay(10);
$finish;
end

endmodule

2. Waves forms
3. Synthesis circuit

2. Design a synchronous logic control unit for vending machine and verify
using test bench.
The machine can take only 2 types of coins of denomination 1 & 2 in any
order. It delivers only one product that is priced rupees
3 on receiving rupees 3 the product is delivered by asserting on output x=1
which otherwise remains zero. If it gets rupees 4 then the product is
delivered by asserting X and also a coin return mechanism is activated by
output y=1 to return a 1 rupee coin. There are 2 sensors to sense the output
as shown in the following table. The clock speed is much higher than the
human response time i.e. no 2 coins can be deposited in same clock cycle.

I J Coin
0 X No coin dropped
1 0 one Rupee
1 1 Two Rupees

1. RTL code
//RTL

module vending_machine(input [1:0]d_in,input clk,rst,output reg d_out1,output reg d_out2);

parameter s0 = 3'b000,
s1 = 3'b001,
s2 = 3'b010,
s3 = 3'b011,
s4 = 3'b100;

reg [2:0]p_s;
reg [2:0]n_s;

/////present state logic


always@(posedge clk)
begin
if(rst)
p_s <= s0;
else
p_s <= n_s;
end

//////next state logic


always@(p_s,d_in)
begin
case(p_s)
s0 : if(d_in == 2'b10)
n_s = s1;
else if(d_in == 2'b11)
n_s = s2;
else
n_s = s0;
s1 : if(d_in == 2'b10)
n_s = s2;
else if(d_in == 2'b11)
n_s = s3;
else
n_s = s0;
s2 : if(d_in == 2'b10)
n_s = s3;
else if(d_in == 2'b11)
n_s = s4;
else
n_s = s0;
s3 : if(d_in == 2'b0x)
n_s = s0;
else
n_s = s0;
s4 : if(d_in == 2'b0x)
n_s = s0;
else
n_s = s0;
default : n_s = s0;
endcase
end

///////////// output logic


always@(posedge clk)
begin
d_out1 <= 1'b0;
d_out2 <= 1'b0;
case(p_s)
s1 : if(d_in == 2'b11)
begin
d_out1 <= 1'b1;
d_out2 <= 1'b0;
end
s2 : if(d_in == 2'b10)
begin
d_out1 <= 1'b1;
d_out2 <= 1'b0;
end
else if(d_in == 2'b11)
begin
d_out1 <= 1'b1;
d_out2 <= 1'b1;
end
default : begin d_out1 <= 1'b0;
d_out2 <= 1'b0;

end
endcase
end

endmodule

2. Testbench code
//Test bench

module vending_machine_tb;

reg [1:0]d_tb;
reg clk_tb,rst_tb;
wire d_out1_tb;
wire d_out2_tb;

vending_machine DUT(d_tb,clk_tb,rst_tb,d_out1_tb,d_out2_tb);
initial
begin
clk_tb = 1'b0;
forever #10 clk_tb = ~clk_tb;
end

task reset;
begin
@(negedge clk_tb)
rst_tb = 1'b1;
@(negedge clk_tb)
rst_tb = 1'b0;
end
endtask

task delay;
begin
#20;
end
endtask

task in(input [1:0]k);


begin
@(negedge clk_tb)
d_tb = k;
end
endtask

initial
begin
reset;
delay;
in(2'b10);

in(2'b10);
in(2'b11);
in(2'b01);
in(2'b10);
in(2'b11);
in(2'b01);
end

initial
begin
$monitor("d=%b,d_out1=%b,d_out2=%b",d_tb,d_out1_tb,d_out2_tb);
#1000 $stop;
end

endmodule

3. Waveforms
4. Synthesis code

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