Lab Assignment 3

20CP203P-Digital Electronics &Computer Organization Lab

1) Design and implement a Half Adder circuit using Verilog code in

Edaplayground analyze the waveform
Design code:

module halfadder(a,b,s,c);
input a,b;
output s,c;
assign s=a^b;
assign c=a&b;
endmodule

Testbench code:

module tb_halfadder;
reg A,B;
wire S,C;
halfadder a1 (.a(A), .b(B), .s(S), .c(C));

initial
begin
A=0;B=0; #5;
A=0;B=1; #5;
A=1;B=0; #5;
A=1;B=1; #5;
end

initial
begin
$dumpfile("dump.vcd");
$dumpvars(1);
end
endmodule
OUTPUT

Smit Patel D5(G10) 22BCP367

 Lab Assignment 3
20CP203P-Digital Electronics &Computer Organization Lab

2) Design a four-bit combinational circuit for 2’s complement using

exclusive-OR gates and Half Adders. Write Verilog code in
Edaplayground, simulate it, and analyze the waveform.

Design code:

module twos_complement(
input [3:0] A,
output reg [3:0] Twos_compf
);
wire [3:0] inverted_a;
wire carry = 4'b1;
wire [3:0] Twos_comp;

assign inverted_a = ~A;

full_adder
fa0(.a(inverted_a[0]), .b(4'b1), .cin(1'b0), .sum(Twos_comp[0]), .cout(car
ry));
full_adder
fa1(.a(inverted_a[1]), .b(4'b0), .cin(carry), .sum(Twos_comp[1]), .cout(ca
rry));
full_adder
fa2(.a(inverted_a[2]), .b(4'b0), .cin(carry), .sum(Twos_comp[2]), .cout(ca
rry));
full_adder
fa3(.a(inverted_a[3]), .b(4'b0), .cin(carry), .sum(Twos_comp[3]), .cout(ca
rry));

assign Twos_comp=Twos_compf;

endmodule

module full_adder(
input a,b, cin,
output sum, cout
);
wire sum1,carry1,carry2;

half_adder ha1(.a(a), .b(b), .sum(sum1), .carry(carry1));

half_adder ha2(.a(sum1), .b(cin), .sum(sum), .carry(carry2));

Smit Patel D5(G10) 22BCP367

 Lab Assignment 3
20CP203P-Digital Electronics &Computer Organization Lab

assign cout=(carry1|carry2);
endmodule

module half_adder(
input a,b,
output sum, carry
);

assign sum=a^b;
assign carry=a&b;
endmodule

Testbench code:

module tb_twos_complement;

reg [3:0] a;
wire [3:0] twos_comp;

twos_complement twos_comp_inst(.A(a), .Twos_compf(twos_comp));

initial
begin
a=4'b1010; #10;
end

initial
begin
$dumpfile("dump.vcd");
$dumpvars(1);
end

endmodule
OUTPUT

Smit Patel D5(G10) 22BCP367

 Lab Assignment 3
20CP203P-Digital Electronics &Computer Organization Lab

3) Write Verilog code for a Full Adder. Simulate the code in Edaplayground
and observe the results through the waveform.
Design code:

module fulladder(a,b,ci,s,co);
input a,b,ci;
output s,co;
assign s=(a^b^ci);
assign co=(a&b|b&ci|a&ci);
endmodule

Testbench code:

module tb_fulladder;
reg A,B,CI;
wire S,CO;
fulladder a1 (.a(A), .b(B), .ci(CI), .s(S), .co(CO));

initial
begin
A=0; B=0; CI=0; #5;
A=0; B=0; CI=1; #5;
A=0; B=1; CI=0; #5;
A=0; B=1; CI=1; #5;
A=1; B=0; CI=0; #5;
A=1; B=0; CI=1; #5;
A=1; B=1; CI=0; #5;
A=1; B=1; CI=1; #5;

end

initial
begin
$dumpfile("dump.vcd");
$dumpvars(1);
end
endmodule

Smit Patel D5(G10) 22BCP367

 Lab Assignment 3
20CP203P-Digital Electronics &Computer Organization Lab

OUTPUT

Smit Patel D5(G10) 22BCP367

 Lab Assignment 3
20CP203P-Digital Electronics &Computer Organization Lab

4) Write Verilog code for a Full Adder using module instantiation of the
previously designed Half Adder. Simulate the code in Edaplayground and
analyze the waveform.

Design code:

module halfadder(p,q,s,c);
input p,q;
output s,c;
assign s=p^q;
assign c=p&q;
endmodule

module fulladder(a,b,cin,sum,cout);
input a,b,cin;
output sum,cout;
wire s1,c1,c2;
halfadder h1(a,b,s1,c1);
halfadder h2(cin,s1,sum,c2);
or(cout,c1,c2);
endmodule

Testbench code:

module tb_fulladder;
reg A,B,CIN;
wire SUM,COUT;
fulladder a1 (.a(A), .b(B), .cin(CIN), .sum(SUM), .cout(COUT));

initial
begin
A=0; B=0; CIN=0; #5;
A=0; B=0; CIN=1; #5;
A=0; B=1; CIN=0; #5;
A=0; B=1; CIN=1; #5;
A=1; B=0; CIN=0; #5;
A=1; B=0; CIN=1; #5;
A=1; B=1; CIN=0; #5;

Smit Patel D5(G10) 22BCP367

 Lab Assignment 3
20CP203P-Digital Electronics &Computer Organization Lab

A=1; B=1; CIN=1; #5;

end

initial
begin
$dumpfile("dump.vcd");
$dumpvars(1);
end
endmodule

OUTPUT

Smit Patel D5(G10) 22BCP367

 Lab Assignment 3
20CP203P-Digital Electronics &Computer Organization Lab

5) Write Verilog code for a Half Adder using only NAND gates. Simulate
the code in Edaplayground and observe the results in the waveform.

Design code:

module nand_ha(a,b,s,c);
input a,b;
output s,c;
wire p,q,r,t,w;
nand(p,a,a);
nand(q,b,b);
nand(r,a,q);
nand(t,b,p);
nand(s,r,t);
nand(w,a,b);
nand(c,w,w);
endmodule

Testbench code:

module tb_nand_ha;
reg A,B;
wire S,C;
nand_ha a1(.a(A), .b(B), .s(S), .c(C));

initial
begin
A=0; B=0; #5;
A=0; B=1; #5;
A=1; B=0; #5;
A=1; B=1; #5;
end

initial
begin
$dumpfile("dump.vcd");
$dumpvars(1);
end

Smit Patel D5(G10) 22BCP367

 Lab Assignment 3
20CP203P-Digital Electronics &Computer Organization Lab

endmodule

OUTPUT

Smit Patel D5(G10) 22BCP367

 Lab Assignment 3
20CP203P-Digital Electronics &Computer Organization Lab

6) Write Verilog code for a Half Adder using only NOR gates. Simulate the
code in Edaplayground and analyze the waveform.

Design code:

module nor_ha(a,b,s,c);
input a,b;
output s,c;
wire p,q,r,t;
nor(p,a,a);
nor(q,b,b);
nor(r,p,q);
nor(t,a,b);
nor(s,r,t);
nor(c,p,q);
endmodule

Testbench code:

module tb_nor_ha;
reg A,B;
wire S,C;
nor_ha a1 (.a(A), .b(B), .s(S), .c(C));

initial
begin
A=0; B=0; #5;
A=0; B=1; #5;
A=1; B=0; #5;
A=1; B=1; #5;
end

initial
begin
$dumpfile("dump.vcd");
$dumpvars(1);
end
endmodule

Smit Patel D5(G10) 22BCP367

 Lab Assignment 3
20CP203P-Digital Electronics &Computer Organization Lab

OUTPUT

Smit Patel D5(G10) 22BCP367