UNIT-1

Computer architecture refers to those attributes of a system visible to a programmer, or put

another way, those attributes that have a direct impact on the logical execution of a program.

Computer organization refers to the operational units and their interconnection that
realize the architecture specification.

Examples of architecture attributes include the instruction set, the number of bit to represent
various data types (e.g.., numbers, and characters), I/O mechanisms, and technique for
addressing memory.

Organization attributes include those hardware details transparent to the programmer, such as
control signals, interfaces between the computer and peripherals, and the memory technology
used.
As an example, it is an architectural design issue whether a computer will have a multiply
instruction.

Functional unit: -

A computer consists of five functionally independent main parts input, memory, arithmetic logic
unit (ALU), output and control unit.
Input unit: - The source program/high level language program/coded information/simply data is
fed to a computer through input devices keyboard is a most common type. Whenever a key is
pressed, one corresponding word or number is translated into its equivalent binary code over a
cable & fed either to memory or processor. Joysticks, trackballs, mouse, scanners etc are other
input devices.

Memory unit: - Its function into store programs and data. It is basically to two types

1. Primary memory

2. Secondary memory

1. Primary memory: - Is the one exclusively associated with the processor and operates at the
electronics speeds programs must be stored in this memory while they are being executed. The
memory contains a large number of semiconductors storage cells. Each capable of storing one bit
of information. These are processed in a group of fixed site called word. To provide easy access
to a word in memory, a distinct address is associated with each word location. Addresses are
numbers that identify memory location. Number of bits in each word is called word length of the
computer. Programs must reside in the memory during execution. Instructions and data can be
written into the memory or read out under the control of processor. Memory in which any
location can be reached in a short and fixed amount of time after specifying its address is called
random-access memory (RAM). The time required to access one word in called memory access
time. Memory which is only readable by the user and contents of which can’t be altered is called
read only memory (ROM) it contains operating system. Caches are the small fast RAM units,
which are coupled with the processor and are often contained on the same IC chip to achieve
high performance. Although primary storage is essential it tends to be expensive.

2. Secondary memory: - Is used where large amounts of data & programs have to be stored,
particularly information that is accessed infrequently. Examples: - Magnetic disks & tapes,
optical disks (ie CD-ROM’s), floppies etc.,

Arithmetic logic unit (ALU):- Most of the computer operators are executed in ALU of the
processor like addition, subtraction, division, multiplication, etc. the operands are brought into
the ALU from memory and stored in high speed storage elements called register. Then according
to the instructions the operation is performed in the required sequence. The control and the ALU
are may times faster than other devices connected to a computer system. This enables a single
processor to control a number of external devices such as key boards, displays, magnetic and
optical disks, sensors and other mechanical controllers.

Output unit:- These actually are the counterparts of input unit. Its basic function is to send the
processed results to the outside world. Examples:- Printer, speakers, monitor etc.

Control unit:- It effectively is the nerve center that sends signals to other units and senses their
states. The actual timing signals that govern the transfer of data between input unit, processor,
memory and output unit are generated by the control unit.

Interconnection structures
The collection of paths connecting the various modules is called the interconnecting structure.
• All the units must be connected
• Different type of connection for different type of unit
o Memory
o Input/Output
o CPU

• Memory Connection
o Receives and sends data
o Receives addresses (of locations)
o Receives control signals
Read
Write
 Timing
Fig: Memory Module

I/O Connection
o Similar to memory from computer’s viewpoint
o Output
Receive data from computer
Send data to peripheral
o Input
Receive data from peripheral
Send data to computer
o Receive control signals from computer
o Send control signals to peripherals
e.g. spin disk
o Receive addresses from computer
e.g. port number to identify peripheral
o Send interrupt signals (control)
CPU Connection
o Reads instructions and data
o Writes out data (after processing)
o Sends control signals to other units
o Receives (& acts on) interrupts

BUS

A group of lines that serve as a connecting port for several devices is called a bus.

Types of Computer Bus

There are a variety of buses found inside the computer.
Data Bus: The data bus allows data to travel back and forth between the microprocessor (CPU)
and memory (RAM).
Address Bus: The address bus carries information about the location(address) of data in
memory.
Control Bus : The control bus carries the control signals that make sure everything is flowing
smoothly from place to place.

Traditional Bus Architecture:

The traditional bus connection uses three buses local bus , system bus and expansion bus

1. Local bus connects the processor to cache memory and may support one or more local devices

2. The cache memory controller connects the cache to local bus and to the system bus.

3. System bus also connects main memory module

4. Input /output transfer to and from the main memory across the system bus do not interface
with the processor activity because process accesses cache memory.

5. It is possible to connect I/O controllers directly on to the system bus. A more efficient solution
is to make use of one or more expansion buses for this purpose.An expansion bus interface
buffers data transfer between system bus and i/o controller on the expansion bus.

This arrangement allows the system to support a wide variety of i/o devices and at the same time
insulate memory to process or traffic from i/o traffic.
Explain why multibus hierarchies are required?
If large number of devices are connected to the single shared bus , performance will suffer. There
are following problems
1>Bus length is longer. Therefore propagaton time is more. This propagation dealy can affect
performance. When control of the bus passes from one device to another frequently

2>The bus may become bottleneck as aggreagate data transfer demand approaches the capacity
of bus. Because data rate generated by attached deviceslike graphics and video controller are
growing rapidly
3>Only one master bus can operate at a time, other waits. To overcome this problem most
computer system use multiple buses, generally laid out in hierarchy.

BUS ARBRITRATION:

• The device that is allowed to initiate data transfers on the bus at any given time is called
the bus master. In a computer system there may be more than one bus master such as
processor, DMA controller etc.
• They share the system bus. When current master relinquishes control of the bus, another
bus master can acquire the control of the bus.
• Bus arbitration is the process by which the next device to become the bus master is
selected and bus mastership is transferred to it. The selection of bus master is usually
done on the priority basis.
• There are two approaches to bus arbitration: Centralized and distributed.
1. Centralized Arbitration

o In centralized bus arbitration, a single bus arbiter performs the required

arbitration. The bus arbiter may be the processor or a separate controller
connected to the bus.
o There are three different arbitration schemes that use the centralized bus
arbitration approach. There schemes are:
a. Daisy chaining
b. Polling method
c. Independent request
Daisy Chaining

The system connections for Daisy chaining method are shown in fig below.

• It is simple and cheaper method. All masters make use of the same line for bus request.
 • In response to the bus request the controller sends a bus grant if the bus is free.
• The bus grant signal serially propagates through each master until it encounters the first
one that is requesting access to the bus. This master blocks the propagation of the bus
grant signal, activities the busy line and gains control of the bus.
• Therefore any other requesting module will not receive the grant signal and hence cannot
get the bus access.

• b) Polling method
• The system connections for polling method are shown in figure above.
• In this the controller is used to generate the addresses for the master. Number of address
line required depends on the number of master connected in the system.
• For example, if there are 8 masters connected in the system, at least three address lines
are required.
• In response to the bus request controller generates a sequence of master address. When
the requesting master recognizes its address, it activated the busy line ad begins to use the
bus.

c) Independent request

• The figure below shows the system connections for the independent request scheme.
 • In this scheme each master has a separate pair of bus request and bus grant lines and each
pair has a priority assigned to it.
• The built in priority decoder within the controller selects the highest priority request and
asserts the corresponding bus grant signal.

Register Transfer Language(RTL)

A digital computer system exhibits an interconnection of digital modules such as registers,

decoders, arithmetic elements, and Control logic.

These digital modules are interconnected with some common data and control paths to form a
complete digital system.

Moreover, digital modules are best defined by the registers and the operations that are performed
on the data stored in them.

The operations performed on the data stored in registers are called Micro-operations.

The internal hardware organization of a digital system is best defined by specifying:

o The set of registers and the flow of data between them.

o The sequence of micro-operations performed on the data which are stored in the registers.
o The control paths that initiates the sequence of micro-operation

The Register Transfer Language is the symbolic representation of notations used to specify
the sequence of micro-operations.(RTL)
In a computer system, data transfer takes place between processor registers and memory and
between processor registers and input-output systems. These data transfer can be represented by
standard notations given below:

o Notations R0, R1, R2..., and so on represent processor registers.

o The addresses of memory locations are represented by names such as LOC, PLACE,
MEM, etc.
o Input-output registers are represented by names such as Rin DATA IN, DATA OUT and
so on.
o The content of register or memory location is denoted by placing square brackets around
the name of the register or memory location. Eg….R3, R3(IN)=0110

Next Top

Register Transfer

The term Register Transfer refers to the availability of hardware logic circuits that can perform a
given micro-operation and transfer the result of the operation to the same or another register.

Most of the standard notations used for specifying operations on various registers are stated
below.

o The memory address register is designated by MAR. (MDR- memory data register)
o Program Counter PC holds the next instruction's address.
o Instruction Register IR holds the instruction being executed.
o R1 (Processor Register).
o We can also indicate individual bits by placing them in parenthesis. For instance,
PC (8-15), R2 (5), etc.
o Data Transfer from one register to another register is represented in symbolic form by
means of replacement operator. For instance, the following statement denotes a transfer
of the data of register R1 into register R2.

R2 ← R1
o Typically, most of the users want the transfer to occur only in a predetermined control
condition. This can be shown by following if-then statement:
If (P=1) then (R2 ← R1); Here P is a control signal generated in the control section.
 o It is more convenient to specify a control function (P) by separating the control variables
from the register transfer operation. For instance, the following statement defines the data
transfer operation under a specific control function (P).

P: R2 ← R1
Eg….R1 ←R2+R1

The following image shows the block diagram that depicts the transfer of data from R1 to R2.

Here, the letter 'n' indicates the number of bits for the register. The 'n' outputs of the register R1
are connected to the 'n' inputs of register R2.

A load input is activated by the control variable 'P' which is transferred to the register R2.

Bus and Memory Transfers

A digital system composed of many registers, and paths must be provided to transfer information
from one register to another. The number of wires connecting all of the registers will be
excessive if separate lines are used between each register and all other registers in the system.

A bus structure, on the other hand, is more efficient for transferring information between
registers in a multi-register configuration system.

A bus consists of a set of common lines, one for each bit of register, through which binary
information is transferred one at a time. Control signals determine which register is selected by
the bus during a particular register transfer.

The following block diagram shows a Bus system for four registers. It is constructed with
the help of four 4 * 1 Multiplexers each having four data inputs (0 through 3) and two
selection inputs (S1 and S2).
The two selection lines S1 and S2 are connected to the selection inputs of all four multiplexers.
The selection lines choose the four bits of one register and transfer them into the four-line
common bus.

When both of the select lines are at low logic, i.e. S1S0 = 00, the 0 data inputs of all four
multiplexers are selected and applied to the outputs that forms the bus. This, in turn, causes the
bus lines to receive the content of register A since the outputs of this register are connected to the
0 data inputs of the multiplexers.

Similarly, when S1S0 = 01, register B is selected, and the bus lines will receive the content
provided by register B.

The following function table shows the register that is selected by the bus for each of the four
possible binary values of the Selection lines.
Note: The number of multiplexers needed to construct the bus is equal to the number of bits in
each register. The size of each multiplexer must be 'k * 1' since it multiplexes 'k' data lines. For
instance, a common bus for eight registers of 16 bits each requires 16 multiplexers, one for each
line in the bus. Each multiplexer must have eight data input lines and three selection lines to
multiplex one significant bit in the eight registers.

A bus system can also be constructed using three-state gates instead of multiplexers.

The three state gates can be considered as a digital circuit that has three gates, two of which are
signals equivalent to logic 1 and 0 as in a conventional gate. However, the third gate exhibits a
high-impedance state.

The most commonly used three state gates in case of the bus system is a buffer gate.

The graphical symbol of a three-state buffer gate can be represented as:

The following diagram demonstrates the construction of a bus system with three-state buffers.
 o The outputs generated by the four buffers are connected to form a single bus line.
o Only one buffer can be in active state at a given point of time.
o The control inputs to the buffers determine which of the four normal inputs will
communicate with the bus line.
o A 2 * 4 decoder ensures that no more than one control input is active at any given point
of time.

Memory Transfer

Most of the standard notations used for specifying operations on memory transfer are stated
below.

o The transfer of information from a memory unit to the user end is called
a Read operation.
o The transfer of new information to be stored in the memory is called a Write operation.
o A memory word is designated by the letter M.
o We must specify the address of memory word while writing the memory transfer
operations.
o The address register is designated by AR and the data register by DR.
o Thus, a read operation can be stated as:
1. Read: DR ← M [AR]
o The Read statement causes a transfer of information into the data register (DR) from the
memory word (M) selected by the address register (AR).
o And the corresponding write operation can be stated as:

1. Write: M [AR] ← R1
o The Write statement causes a transfer of information from register R1 into the memory
word (M) selected by address register (AR).

General Register organization

Generally CPU has seven general registers. Register organization show how registers are
selected and how data flow between register and ALU. A decoder is used to select a particular
register. The output of each register is connected to two multiplexers to form the two buses A
and B. The selection lines in each multiplexer select the input data for the particular bus.

The A and B buses form the two inputs of an ALU.The operation select lines decide the micro
operation to be performed by ALU. The result of the micro operation is available at the output
bus. The output bus connected to the inputs of all registers, thus by selecting a destination
register it is possible to store the result in it
The control must provide binary selection variables to the following selector inputs:

1. MUX A selector (SELA): to place the content of R2 into bus A.

2. MUX B selector (SELB): to place the content of R3 into bus B.

3. ALU operation selector (OPR): to provide the arithmetic addition A+ B.

4. Decoder destination selector (SELD): to transfer the content of the output bus into R 1.

The four control selection variables are generated in the control unit and must be available at the
beginning of a clock cycle. The data from the two source registers propagate through the gates in
the multiplexers and the ALU, to the output bus, and into the inputs of the destination register, all
during the clock cycle interval.

Then, when the next clock transition occurs, the binary information from the output bus is
transferred into R 1. To achieve a fast response time, the ALU is constructed with high-speed
circuits. The buses are implemented with multiplexers or three-state gates.

Control Word

There are 14 binary selection inputs in the unit, and their combined value specifies a control
word. The 14-bit control word consists of four fields. Three fields contain three bits each, and
 one field has five bits. The three bits of SELA select a source register for the A input of the
ALU. The three bits of SELB select a register for the B input of the ALU. The three bits of
SELD select a destination register using the decoder and its seven load outputs. The five bits of
OPR select one of the operations in the ALU

Combine Values of 14 binary selection i/p in a unit specify a control word

(3+3+5+3)

STACK ORGANIZATION
Stack is a storage structure that stores information in such a way that the last item stored is the
first item retrieved. It is based on the principle of LIFO (Last-in-first-out). The stack in digital
computers is a group of memory locations with a register that holds the address of top of
element. This register that holds the address of top of element of the stack is called Stack
Pointer.

Stack Operations
The two operations of a stack are:
1. Push: Inserts an item on top of stack.
2. Pop: Deletes an item from top of stack.

Implementation of Stack
In digital computers, stack can be implemented in two ways:
1. Register Stack
2. Memory Stack

Register Stack

A stack can be organized as a collection of finite number of registers that are used to store
temporary information during the execution of a program. The stack pointer (SP) is a register
that holds the address of top of element of the stack.
Memory Stack

A stack can be implemented in a random access memory (RAM) attached to a CPU. The
implementation of a stack in the CPU is done by assigning a portion of memory to a stack
operation and using a processor register as a stack pointer. The starting memory location of the
stack is specified by the processor register as stack pointer.
 Addressing Modes

The operation field of an instruction specifies the operation to be performed. This operation must
be executed on some data stored in computer registers or memory words. The way the operands
are chosen during program execution is dependent on the addressing mode of the instruction.
The addressing mode specifies a rule for interpreting or modifying the address field of the
instruction before the operand is actually referenced. Computers use addressing mode techniques
for the purpose of accommodating one or both of the following provisions:

1. To give programming versatility to the user by providing such facilities as pointers to

memory, counters for loop control, indexing of data, and program relocation.

2. To reduce the number of bits in the addressing field of the instruction.

The control unit of a computer is designed to go through an instruction cycle that

is divided into three major phases:

1. Fetch the instruction from memory.

2. Decode the instruction.

3. Execute the instruction.

program counter (PC): PC holds the address of the instruction to be executed next and is
incremented each time an instruction is fetched from memory.

The operation code specifies the operation to be performed. The mode field is used to locate the
operands needed for the operation. There may or may not be an address field in the instruction. If
there is an address field, it may designate a memory address or a processor register.

General Instruction Format

Opcode-Field Address-Field

Instruction format with mode field

 There are two modes that need no address field at all. These are the implied and immediate
modes.

Implied Mode: In this mode the operands are specified implicitly in the definition of the
instruction. For example,the instruction "complement accumulator" is an implied-mode
instruction because the operand in the accumulator register is implied in the definition of the
instruction.

Zero-address instructions in a stack-organized computer are implied-mode instructions since the

operands are implied to be on top of the stack.

Immediate Mode: In this mode the operand is specified in the instruction itself. In other words,
an immediate-mode instruction has an operand field rather than an address field. The operand
field contains the actual operand to be used in conjunction with the operation specified in the
instruction.

Immediate- mode instructions are useful for initializing registers to a constant value

Register Mode: In this mode the operands are in registers that reside within the CPU. The
particular register is selected from a register field in the instruction.

A k-bit field can specify any one of 2' registers.

Register Indirect Mode: In this mode the instruction specifies a register in the CPU whose
contents give the address of the operand in memory. In other words, the selected register
contains the address of the operand rather than the operand itself.

Autoincrement or Autodecrement Mode: This is similar to the register indirect mode except
that the register is incremented or decremented after (or before) its value is used to access
memory. When the address stored in the register refers to a table of data in memory, it is
necessary to increment or decrement the register after every access to the table.

The effective address is defined to be the memory address obtained from the computation
dictated by the given addressing mode.
Direct Address Mode: In this mode the effective address is equal to the address part of the
instruction. The operand resides in memory and its address is given directly by the address field
of the instruction. In a branch-type instruction the address field specifies the actual branch
address.

Indirect Address Mode: In this mode the address field of the instruction gives the address
where the effective address is stored in memory.

effective address = address part of instruction + content of CPU register

Relative Address Mode: In this mode the content of the program counter is added to the
address part of the instruction in order to obtain the effective address.

Indexed Addressing Mode: In this mode the content of an index register is added to the address
part of the instruction to obtain the effective address. The index register is a special CPU register
that contains an index value.

Base Register Addressing Mode: In this mode the content of a base register is added to the
address part of the instruction to obtain the effective address. This is similar to the indexed
addressing mode except that the register is now called a base register instead of an index register.

Address Memory

PC = 200 200 Load to AC Mode

201 Address=500

Ri = 400(Processor register) 202 Next Instruction

XR = 1 00 (Index register)

399 450

AC 400

500 700

600 800

702 900

800 325

Numerical example for addressing modes.

Addressing Mode Effective address Content of AC

Direct address 500 800

Immediate operand 201 500

Indirect address 800 300

Relative address 702 325

Indexed address 600 900

Register 400

Register indirect 400 700

Autoincrement 400 700

Autodecrement 399 450