9) |. SalI t Atetantd Pence | © : CELEBRATING 14 YEARS OF EXCELLENCE IN ViESI TRAINING Advanced ASIC Verification Course We 2K+ ele) Ce eeu} Live Q&A Sessions Cee ee TyMAVEN SILICON MAVEN-SILICON. Maven Silicon isa leading provider of VLSI training for students and professionals. We offer a range of high-quality VLSI traning programs and internships, tought by experienced industry helping engineers to upsklll and advance their careers in the uctor Industry. From digital design and verification to physical design professionals, aimed fast-growing Semicon s along with labs ond overs a wide variety of to ‘and design for testing, Maven Silicon projects through Industry standard EDA tools, Our state-of-the-art training facies, coupled with innovative training methods, provide students with hands-on experience and a the strong foundation in the latest VLS! technologies. Our curriculum is designed to met demands of the industry and Is constantly updated to keep pace with the latest advance- peduling options and customized training ments. In Maven Silicon offers flexible sc programs to accommodate student's busy schedules, With @ commitmentto excellence and @ passion for empowering students and professionals, Maven Silicon is dedicated to providing the highest quality hands-on training to help engineers reach their full potential in the Semiconductor industry, 2 Consultant in the top EDA companies lke Synopsys, Cadence, and Mentor Graphics. Du lutions effectively forthe successful tape-outs of multi-million now more about My vision is to create an excellent learning ecosystem ot superior technical expert, hands-on training experience, fond industry-oriented courses with innovative learning For more than 14 years, Maven Silicon has been a benchmark system in India, offering high-quality ionals, and for the VLSI trainin F VLSI aspirants, profe ‘organizations across the globe, Sivakumar PR ‘ounder and ering and semiconductor industries. He ©, Sivakumar P R, hes 25+ years of exper 1ce in the engin sic design houses and helped them to use the EDA gate designs CEO, visit https://wwlinkedin.com/In/slvapy worked as a ng this tenure, he worked very closely withVEN-SILICON.COM Three reasons to muse with Dynamic VLSI courses designed and delivered by Industry experts nie the B [LSI taining center which provides high-class ind ty carowth inthe e dard VLSI taining. The cou Jeonduetor industry and 1g Methodology and Infrastructure 1 training methodology Is unique. It helps our students to learn even complex technologies ina shor of time and make ‘ther experts. 70% of the course time is dedicated to the labs, min projects, and the finl project. Qur training courses halp you cal skills which are highly «job in the semiconductor indus Hands on Learning Santon Stren TE fom Coverage Driven n(CRODV), Assert ased Verification (ABV) like Systemverilog and Met logieslike UVM on he project life cycle from Verification planning te Verification signoff, making the trainees industry ready EDA Partner Peete et ec ere Toy eee eeMAVEN-SILICON. COURSE CURRICULUM Advanced ASIC Verification Course 14 Modules (08 - Linux Ubuntu | EDA Tools - Synopsys.Siemens, Xilinx, Aldec a I + Components of UNIX system + Direc ory Structure + Utities and Commands * ViEditor sanced Verilog for Verification + Tasks and Functions + Delays ~ Regular, Intra Assignment and Inertial Delays + Race Conditions * File /0 operation + TE Constructs + Self hacking Testbenches + Statement coverage + Branch; + Expression Coverage + Path Coverage foggle Coverage + FSM- State, Transstion coverage Directed Va Random Functional verification p Stimulus Generation + Bus fu Monitors ond reference models Coverage Driven Veri + Verification Planning and mana: ional model + New Datatypes + Tasks and Functions + Interfaces Slocking blocks Object Oriented Programming and Randomization + OOP Basics + Classes - Objects and handles + Polymorphism and inheritance + Randomization + Constraints ‘Threads and Virtual Interfaces + Fotk Join + Fork Join ony + Fork Join none + Event controls Mailboxes and semaphores Virtal Interfaces Transactors Building verification environment + Testeos + Callbacks + Facade Class + Building Reusable Tran + Inserting Callbacks + Registering Callbacks * Ditect Programming i + Functional Coverage overage models + Coverpoints and bins + Gross coverage + Regression testi Environment Configuration Reference Models and Predictor Logics Using Legacy BFMs Scenario Generation Testeases - Random, Directed and Coding styles f ve Verification Plan TB Architecture Coverage Mode! Tracking the simulation process Building regression testsuite Testsuite optimization Introduction to ABV Immediate Assertions Simple Assertions Sequences Sequence Composition Advanced SVA(SystemVerilog Assertions) Features Assertion C erageCOURSE CURRICULUM Advanced ASIC Verification Course 14 Modules. + Introduction to UVM Methodology ‘= RISC-Vinstruction Set Architecture + Overview of Project + UVM TE Architecture *# RISC-V processor 0 + RISC-V ISA Overview + RV921- R and | Type instruction + RV321~ S and B Type Instructo + RV321~ J and U Type Instructions + RV32I - Assembly Programs + Stimulus Modeling + Creating UVCs and Environment + UVM Simulat Phases a Toston Clotsea + RISC-V RVG2I RTL Architecture Design + RISC-V Execution Stages and Flow + RISC-V Register File and fi Instr + TLMOverview + Configuring TB Environment + UVM Sequencers ne Format + Connecting OUT- Virtual interface + RV32I- R and Type ALU Datapath ‘= RV92I- 8 Type ALU Datapath - Load ond Stare + RV32I- Bond U Type ALU Datapath + RV32I- J) Type ALU Datapath ~ JAL ond JALR + Virtual Sequences and Sequencers + Creating TBinfrastructure + Connecting multiple UVC: * Building @ Scoreboard + Introduction to Register Modeling a RIgcry Rvcaie ieee necked eri pemen + PU Performance and RISC-V'5 Stage Pipeline Overview * RISC-V 9 Stage Pipeline - Dato Hazards and Design Approach + RISC-V 5 Stage Pipeline Hazards ond Design Approach + Building reusable environments + Proj jecification Analyse + Understanding the architecture = Module-level implementation and verification (08 - Linux Ubuntu | EDA Tools - Synopsys.Siemens, Xilinx, Aldec Project specification analysis Defining verification plan Creating Testbench architecture Defining Transaction Implementing the transactors - sequencer, driver, monitor & scoreboard Implementing the coverog Building the top-level verification Defining weighted random, cose, and directed Building the functional and code coverage reports ‘Transition from College to Corporate Interpersonal sills ond Presentation Skils Email Etiquette Resume writing Mockup Interviews Technical/HR Interview Skils: Group Discussion cand HR Round Preparation Free Couree Access + Bulding the top-level module «= Introduction to Per + Functions and Statements ‘+ Numbers, Strings, and Quotes + Comments and Loops Verilog HL + Regular Expressions + File Operationshe : 5 7 i A icone et coe ee ee ro Association & Partnerships Synopsys SIEMENS ™Risc @'S4 ALDE!