ELECTRONIC DEVICES | MODULE 4:FIELD EFFECTS TRANSISTOR 18EC33

MODULE 4

FIELD EFFECT TRANSISTORS

4.1 Basic pn JFET Operation
• A simplified cross section of a symmetrical device is shown in Figure 4.1
• The n region between the two p regions is known as the channel
• In this N channel device, majority carrier electrons flow between the source and
drain terminals
• Source - the terminal from which carriers enter the channel from the external circuit
• Drain - the terminal where carriers leave, or are drained from, the device
• Gate - the control terminal
• The two gate terminals shown in Figure 13.2 are tied together to form a single gate
connection
• JFET is a majority-carrier device or unipolar device - majority carrier electrons are
primarily involved in the conduction in this n-channel transistor
• For complementary p-channel JFET
• The p and n regions are reversed from those of the n-channel device.
• Holes will flow in the p-type channel between source and drain
• The source terminal will now be the source of the holes.
• The current direction and voltage polarities in the p-channel JFET are the reverse of
those in the n-channel device.
• The p-channel JFET is generally a lower frequency device than the n-channel JFET
due to the lower hole mobility.

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Working of n-channel pn JFET – Two Scenarios

Scenario 1 – 3 cases (w.r.t Gate voltage)
Case 1 - with zero volts applied to the gate (Figure 4.2a)
1. source is at ground potential
2. a small positive drain voltage is applied
3. drain current ID is produced between the source and drain terminals
4. n channel is essentially a resistance, so the ID versus VDS characteristic, for small VDS
values, is approximately linear
Case 2 - with small Reverse biased voltage applied to the gate (Figure 4.2b)
1. The gate-to-channel pn junction becomes reverse biased
2. The space charge region widens so the channel region becomes narrower and the
resistance of the n channel increases
3. Slope of the ID versus VDS curve, for small VDS , decreases
Case 3 - With large Reverse biased voltage applied to the gate (Figure 4.2c)
1. reverse-biased gate-to-channel space charge region has completely filled the
channel region - condition is known as pinchoff
2. Depletion region isolates the source and drain terminals - drain current at pinchoff is
essentially zero

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Observations so Far –
 The current in the channel is controlled by the gate voltage
 This device is a normally on or depletion mode device, which means that a voltage
must be applied to the gate terminal to turn the device off.
• Scenario 2 – 3 cases (w.r.t Drain voltage)
Let VGS = 0 for all the 3 cases
• Case 1: small drain voltage(Figure 4.3a )
1. replica of Figure 4.3a
• Case 2: drain voltage is increased positively (Figure 4.3b)
1. Gate-to-channel pn junction becomes reverse biased near the drain terminal so that
the space charge region extends further into the channel
2. Effective channel resistance increases as the space charge region widens
3. The slope decreases
Case 3: drain voltage is increased very high (Figure 4.3C)
1. Channel has been pinched off at the drain terminal
2. Further increase in drain voltage will not cause an increase in drain current
3. Drain voltage at pinchoff is referred to as VDS(sat)
4. For VDS ≥ VDS(sat) , the transistor is said to be in the saturation region and the drain
current is independent of VDS

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Observation - The effective channel resistance varies along the channel length
and, since the channel current must be constant, the voltage drop through the
channel becomes dependent on position
• At Pinchoff depicted in figure 4.4– The Current is not zero because
1. The n channel and drain terminal are now separated by a space charge region which
has a length ∆L
2. The electrons move through the n channel from the source and are injected into the
space charge region where, subjected to the E-field force, they are swept through into
the drain contact area
3. assume that ∆L ‹‹ L, then the electric field in the n-channel region remains
unchanged from the VDS(sat) case; the drain current will remain constant as VDS
changes
4. Once charges are in the drain region, the drain current will be independent of VDS -
the device looks like a constant current source

4.2 Equivalent Circuit and Frequency Limitations

• To analyze a transistor circuit, one needs a mathematical model or equivalent circuit
of the transistor - small-signal equivalent circuit
• small-signal equivalent circuit - applies to transistors used in linear amplifier circuits
4.2.1 Small-Signal Equivalent Circuit
• The cross section of an n-channel pn JFET is shown in Figure 4.5 with source and
drain series resistances ( rs , rd)
• substrate may be semi-insulating gallium arsenide or it may be a p type substrate

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• Figure 4.6 shows a small-signal equivalent circuit for the JFET

• 𝑉 - internal gate-to-source voltage that controls the drain current
• 𝑟 & 𝐶 - gate-to-source diffusion resistance and junction capacitance , respectively
• gate-to-source junction is reverse biased for depletion mode devices and has only a
small forward-bias voltage for enhancement mode devices, so that normally rgs is
large
• 𝑟 &𝐶 - gate-to-drain resistance and capacitance, respectively
• 𝑟 - finite drain resistance - a function of the channel length modulation effect
• 𝐶 - drain-to-source parasitic capacitance
• 𝐶 - drain-to-substrate capacitance

• The ideal small-signal equivalent circuit is shown in Figure 4.7a

1. All diffusion resistances are infinite
2. the series resistances are zero
3. At low Frequency, capacitances become open circuits
4. The small-signal drain current is now
𝐼 = 𝑔 𝑉 (4.1)

Which is a function only of the transconductance and the input-signal voltage.

The effect of the source series resistance can be determined using Figure 4.7b.

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We have
𝐼 = 𝑔 𝑉 (4.2)

The relation between 𝑉 & 𝑉 can be found from

𝑉 = 𝑉 + 𝑔 𝑉 𝑟 = (1 + 𝑔 𝑟 )𝑉 (4.3)
Equation (4.2) can then be written as
𝑔
𝐼 = 𝑉 = 𝑔′ 𝑉 (4.4)
1+𝑔 𝑟
The effect of the source resistance is to reduce the effective transconductance or
transistor gain

• gm is a function of the dc gate to source voltage (whose equation is given below), g` m

will also be a function of VGS

(4.5)

• The graph of transconductance versus VGS (a) without and (b) with a source series
resistance is shown below 4.8

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4.2.2 Frequency Limitation Factors and Cutoff Frequency

• There are two frequency limitation factors in a JFET
• Factor 1: channel transit time
1. It is a limiting factor in very high frequency devices
2. For eg : If we assume a channel length of 1 µm and assume carriers are traveling at
their saturation velocity, then the transit time is on the order of

(4.6)

• Factor 2: capacitance charging time

Figure 4.9 is a simplified equivalent circuit that includes the primary capacitances
and ignores the diffusion resistances

• The output current will be the short-circuit current.

• As the frequency of the input-signal voltage Vgs increases, the impedance of Cgd and Cgs
decreases so the current through Cgd will increase. For a constant gmVgs , the Ids current
will then decrease. The output current then becomes a function of frequency.
If the capacitance charging time is the limiting factor, then the cutoff frequency fT is
defined as the frequency at which the magnitude of the input current Ii is equal
to the magnitude of the ideal output current gmVgs of the intrinsic transistor
[Note : Diffusion Capacitance is the capacitance due to transport of charge carriers
between two terminals of a device]
When the output is s circuited,

If we let Cg= Cgs + Cgd then at the cutoff frequency

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Or

The maximum possible transconductance is

and the minimum gate capacitance is

Where a is the maximum space charge width. The maximum cutoff frequency can be
written as

• For gallium arsenide JFETs or MESFETs with very small geometries, the cutoff
frequency is even larger

4.3 MOSFET Two terminal MOS structure

• The heart of the MOSFET is a metal-oxide-semiconductor structure known as an
MOS Capacitor

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• The position of the conduction and valence band is relative to fermi level at the oxide
semiconductor interface is a function of the MOS capacitor voltage.
• Operation and characteristics of the MOSFET are dependent on this inversion and the
creation of an inversion charge density at the semiconductor surface
• Threshold Voltage – applied gate voltage required to create the inversion layer
charge
Two Terminal MOS Structure
• The two terminal MOS Capacitor structure is shown in Fig 4.10

• Metal – aluminum or some other type like high conductivity polycrystalline silicon
deposited on the oxide
• tox – Thickness of the oxide
• €ox – permittivity of the oxide
Fabrication of MOSFET:
 The steps involved in the fabrication process of MOSFET is as shown in the figure
4.11

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4.4 Energy band diagram

• The physics of the MOS structure can be more easily explained with the aid of the
simple parallel-plate capacitor
• Figure 4.12a shows a parallel-plate capacitor with the top plate at a negative
voltage with respect to the bottom plate. An insulator material separates the two
plates
• With this bias, a negative charge exists on the top plate, a positive charge exists
on the bottom plate, and an electric field is induced between the two plates
• The capacitance per unit area for this geometry is

where € - permittivity of the insulator

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d - distance between the two plates

• The magnitude of the charge per unit area on either plate
Q’ = C’ V (4.14)
where the prime indicates charge or capacitance per unit area
• The magnitude of the electric field is

(4.15)

• Figure 4.12b shows a MOS capacitor with a p-type semiconductor substrate. The top
metal gate is at a negative voltage with respect to the semiconductor substrate.
• If the electric field were to penetrate into the semiconductor, the majority carrier
holes would experience a force toward the oxide– semiconductor interface.
• Figure 4.12c shows the equilibrium distribution of charge in the MOS capacitor
with this particular applied voltage
• An accumulation layer of holes at the oxide–semiconductor junction corresponds to
the positive charge on the bottom “plate” of the MOS capacitor.

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• Figure 4.13a shows the same MOS capacitor in which the polarity of the applied
voltage is reversed
• A positive charge now exists on the top metal plate and the induced electric field is in
the opposite direction as shown.
• If the electric field penetrates the semiconductor in this case, majority carrier holes
will experience a force away from the oxide–semiconductor interface which will
give rise to a negative space charge region because of the fixed ionized acceptor
atoms
• Figure 4.13b shows the equilibrium distribution of charge in the MOS capacitor with
this applied voltage

The energy-band diagrams of the MOS capacitor with a p-type substrate for various
gate biases are shown in Figure 10.4 and is explained under 4 cases as below
Case (i) : Ideal Case - zero bias is applied across the MOS device (Figure 4.14a)
The energy bands in the semiconductor are flat indicating no net charge exists in the
semiconductor - This condition is known as flat band
Case (ii) : Negative bias is applied across the MOS device (Figure 4.14b)
• The valence-band edge is closer to the Fermi level at the oxide–semiconductor
interface than in the bulk material, which implies that there is an accumulation of
holes
• The semiconductor surface appears to be more p-type than the bulk material
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Fermi level is a constant in the semiconductor since the MOS system is in thermal
equilibrium and there is no current through the oxide

Case (iii):Moderate Positive bias is applied across the MOS device (Figure 4.14c)
• The conduction- and valence-band edges bend as shown in the figure above
• conduction band and intrinsic Fermi levels move closer to the Fermi level
• induced space charge width is x d
• when more negative voltage is applied to the gate , The conduction and valence
bands are bent even more and the intrinsic Fermi level has moved above the Fermi
level. The valence band at the surface is now close to the Fermi level, whereas the
conduction band is close to the Fermi level in the bulk semiconductor - implies that
the semiconductor surface adjacent to the oxide–semiconductor interface is p
type showing the inversion[Figure 4.15]

Capacitance – Voltage Characteristics

• Information about the MOS device and the oxide–semiconductor interface can be
obtained from the capacitance versus voltage or C–V characteristics of the device.

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• The capacitance of a device is defined as

where dQ - magnitude of the differential change in charge on one plate as a

function of the differential change in voltage dV across the capacitor
• The capacitance is a small-signal or ac parameter and is measured by superimposing
a small ac voltage on an applied dc gate voltage.
• The capacitance, then, is measured as a function of the applied dc gate voltage.

4.5 Ideal Capacitance – Voltage Characteristics

• Initially assume that there is zero charge trapped in the oxide and also that there is
no charge trapped at the oxide–semiconductor interface.
• Three operating conditions of interest in the MOS capacitor which are as follows
1. Accumulation region
2. Depletion region
3. Inversion region
Figure 4.16a shows the energy-band diagram of a MOS capacitor with a p-type
substrate for the case when a negative voltage is applied to the gate, inducing an
accumulation layer of holes in the semiconductor at the oxide–semiconductor
interface. A small differential change in voltage across the MOS structure will cause a
differential change in charge on the metal gate and also in the hole accumulation
charge, as shown in Figure 4.16b. The differential changes in charge density occur at
the edges of the oxide, as in a parallel-plate capacitor. The capacitance C’ per unit
area of the MOS capacitor for this accumulation mode is just the oxide capacitance, or

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• Figure 4.17a shows the energy-band diagram of the MOS device when a small
positive voltage is applied to the gate, inducing a space charge region in the
semiconductor;
• Figure 4.17b shows the charge distribution through the device for this condition.
The oxide capacitance and the capacitance of the depletion region are in series. A
small differential change in voltage across the capacitor will cause a differential
change in the space charge width. The corresponding differential changes in charge
densities are shown in the figure. The total capacitance of the series combination is

• As the space charge width increases, the total capacitance C_(depl) decreases. We had
defined the threshold inversion point to be the condition when the maximum depletion
width is reached, but there is essentially zero inversion charge density.
• This condition will yield a minimum capacitance C _m in , which is given by

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• Figure 4.18a shows the energy-band diagram of this MOS device for the inversion
condition. In the ideal case, a small incremental change in the voltage across the MOS
capacitor will cause a differential change in the inversion layer charge density. The space
charge width does not change. If the inversion charge can respond to the change in
capacitor voltage as indicated in Figure 4.18b, then the capacitance is again just the
oxide capacitance, or

• Figure 4.19 shows the ideal capacitance versus gate voltage, or C–V, characteristics of
the MOS capacitor with a p-type substrate. The three dashed segments correspond to
the three components Cox, C S_D , and C _m in . The solid curve is the ideal net
capacitance of the MOS capacitor. Moderate inversion, which is indicated in the
figure, is the transition region between the point when only the space charge density
changes with gate voltage and when only the inversion charge density changes with
gate voltage. The point on the curve that corresponds to the fl at-band condition is of

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interest. The flat-band condition occurs between the accumulation and depletion
conditions. The capacitance at flat band is given by

We may note that the fl at-band capacitance is a function of oxide thickness as well as
semiconductor doping.

• The same type of ideal C–V characteristics is obtained for a MOS capacitor with an n-
type substrate by changing the sign of the voltage axis. The accumulation condition is
obtained for a positive gate bias and the inversion condition is obtained for a
negative gate bias. This ideal curve is shown in Figure 4.20

4.6 Frequency Effects

• Figure 4.18a shows the MOS capacitor with a p-type substrate and biased in the
inversion condition. We have argued that a differential change in the capacitor
voltage in the ideal case causes a differential change in the inversion layer charge
density. However, we must consider the source of electrons that produces a change
in the inversion charge density.
• There are two sources of electrons that can change the charge density of the
inversion layer. The fi rst source is by diffusion of minority carrier electrons from the
p-type substrate across the space charge region. This diffusion process is the same as
that in a reverse-biased pn junction that generates the ideal reverse saturation
current.
• The second source of electrons is by thermal generation of electron–hole pairs within
the space charge region. This process is again the same as that in a reverse- biased pn
junction generating the reverse-biased generation current. Both of these processes
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generate electrons at a particular rate. The electron concentration in the inversion

layer, then, cannot change instantaneously. If the ac voltage across the MOS capacitor
changes rapidly, the change in the inversion layer charge will not be able to respond.
• The C–V characteristics will then be a function of the frequency of the ac signal used
to measure the capacitance.
• In the limit of a very high frequency, the inversion layer charge will not respond to a
differential change in capacitor voltage. Figure 4.21 shows the charge distribution in
the MOS capacitor with a p-type substrate. At a high-signal frequency, the differential
change in charge occurs at the metal and in the space charge width in the
semiconductor. The capacitance of the MOS capacitor is then C _m in , which we
discussed earlier.
• The high-frequency and low-frequency limits of the C–V characteristics are shown in
Figure 4.22. In general, high frequency corresponds to a value on the order of 1 MHz
and low frequency corresponds to values in the range of 5 to 100 Hz.
• Typically, the high-frequency characteristics of the MOS capacitor are measured.

4.7 Basic MOSFET Operation

• The current in a MOSFET is due to the flow of charge in the inversion layer or
channel region adjacent to the oxide–semiconductor interface.
• The source terminal is the source of carriers that flow through the channel to the
drain terminal

4.8 MOSFET structure

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• There are four basic MOSFET device types

1. n-channel enhancement mode MOSFET
2. n-channel depletion mode MOSFET
3. p-channel enhancement mode MOSFET
4. p-channel depletion mode MOSFET
1. n-channel enhancement mode MOSFET (Figure 4.23)
• At zero gate voltage, the semiconductor substrate is not inverted directly under the
oxide in enhancement mode MOSFET
• A positive gate voltage induces the electron inversion layer, which then “connects”
the n-type source and the n-type drain regions.
• electrons flow from the source to the drain so the conventional current will enter the
drain and leave the source
• conventional circuit symbol for this n-channel enhancement mode device is also
shown in the figure 4.23

2. n-channel depletion mode MOSFET (Figure 4.24)

• An n-channel region (or electron inversion region) exists under the oxide with 0 V
applied to the gate. Therefore VT (threshold voltage) may be negative
• The n-channel shown in the figure can be an electron inversion layer or an
intentionally doped n region

3. p-channel enhancement mode MOSFET(Figure 4.25a)

• a negative gate voltage must be applied to create an inversion layer of holes that will
“connect” the p-type source and drain regions
• Holes flow from the source to the drain, so the conventional current will enter the
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source and leave the drain

4. p-channel depletion mode MOSFET(Figure 4.25b)
• A p-channel region exists even with zero gate voltage

4.9 Current-Voltage Characteristics

For n-channel enhancement mode MOSFET (Figure 4.26a) –
• gate-to source voltage that is less than the threshold voltage and with only a very
small drain-to-source voltage
• The source and substrate, or body, terminals are held at ground potential
• With this bias configuration, there is no electron inversion layer, the drain-to-
substrate pn junction is reverse biased, and the drain current is zero (disregarding
pn junction leakage currents).

For n-channel enhancement mode MOSFET (Figure 4.26b) –

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• The same MOSFET with an applied gate voltage such that V GS ˃ VT

• An electron inversion layer has been created
• when a small drain voltage is applied, the electrons in the inversion layer will flow
from the source to the positive drain terminal
• The conventional current enters the drain terminal and leaves the source terminal
• In this ideal case, there is no current through the oxide to the gate terminal
• For small VDS values, the channel region has the characteristics of a resistor, so
ID = gd VDS (4.23)
where gd - channel conductance in the limit as VDS → 0 and is given by

Where µn is the mobility of the electrons in the inversion layer

| Q’n| is the magnitude of the inversion layer charge per unit area
• The inversion layer charge is a function of the gate voltage. Thus MOS transistor
action is the modulation of the channel conductance by the gate voltage
• The ID versus VDS characteristics, for small values of VDS, are shown in Figure 4.27
1. When VGS˂VT, the drain current is zero
2. As VGS becomes larger than VT, channel inversion charge density increases, which
increases the channel conductance
3. A larger value of gd produces a larger initial slope

• Figure 4.28a shows the basic MOS structure for the case when VGS ˃ VT and the
applied VDS voltage is small

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• The thickness of the inversion channel layer qualitatively indicates the relative
charge density, which is essentially constant along the entire channel length for this
case.
• The corresponding ID versus VDS curve is shown in the figure.

• Figure 4.28b shows the situation when the VDS value increases.
• As the drain voltage increases, the voltage drop across the oxide near the drain
terminal decreases, which means that the induced inversion charge density near the
drain also decreases.
• The incremental conductance of the channel at the drain decreases, which then
means that the slope of the ID versus VDS curve will decrease

• When VDS increases to the point where the potential drop across the oxide at the
drain terminal is equal to VT, the induced inversion charge density is zero at the drain
terminal. This effect is schematically shown in Figure 4.28c.
• At this point, the incremental conductance at the drain is zero, which means that the
slope of the ID versus VDS curve is zero

Where VDS(sat) - drain-to-source voltage producing zero inversion charge density at

the drain terminal

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• When VDS ˃ VDS(sat) the point in the channel at which the inversion charge is just zero
moves toward the source terminal.
• In this case, electrons enter the channel at the source, travel through the channel
toward the drain, and then, at the point where the charge goes to zero, the electrons
are injected into the space charge region where they are swept by the E-field to
the drain contact
• Assumption ∆L (change in channel length) ˂ L (length of the channel), then the drain
current will be a constant
• The region of the ID versus VDS characteristic is referred to as the saturation region
shown in Fig 4.28d

• When VGS changes – As VGS increases, the initial slope of ID versus VDS increases
• The family of curves for this n-channel enhancement mode MOSFET is as shown in
Figure 4.29.

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n-channel depletion mode MOSFET (Figure 4.30) –

• If the n-channel region is actually an induced electron inversion layer created by the
metal– semiconductor work function difference and fixed charge in the oxide, the
current–voltage characteristics are exactly the same as we have discussed, except
that VT is a negative quantity
• In the n-channel region is actually an n-type semiconductor region, a negative gate
voltage will induce a space charge region under the oxide, reducing the thickness of
the n-channel region.
• The reduced thickness decreases the channel conductance, which reduces the drain
Current
• A positive gate voltage will create an electron accumulation layer, which increases
the drain current
• Basic requirement - the channel thickness tc must be less than the maximum induced
space charge width to turn the device off
• ID versus VDS family of curves for an n-channel depletion mode MOSFET is shown in
Figure 4.31

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• In the non saturation region

• In saturation region

Note: The operation of a p-channel device is same as that of the n channel device,
except the charge carrier is the hole and the conventional current direction and
voltage polarities are reversed

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